repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/RIGHT_SHIFTER_32b.vhd | 1 | 13,130 | -------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RIGHT_SHIFTER_32b is
port (
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end RIGHT_SHIFTER_32b;
architecture synthesis of RIGHT_SHIFTER_32b is
SIGNAL n : std_logic_vector(4 downto 0);
begin
n <= INPUT_2(4 downto 0);
process(n,INPUT_1)
begin
case n is
when "00000" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(30 downto 0); -- INPUT_1
when "00001" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 1);
when "00010" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 2);
when "00011" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 3);
when "00100" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 4);
when "00101" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 5);
when "00110" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 6);
when "00111" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(30 downto 7);
when "01000" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 8);
when "01001" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 9);
when "01010" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 10);
when "01011" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 11);
when "01100" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 12);
when "01101" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 13);
when "01110" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 14);
when "01111" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 15);
when "10000" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(30 downto 16);
when "10001" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(30 downto 17);
when "10010" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 18);
when "10011" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 19);
when "10100" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 20);
when "10101" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 21);
when "10110" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 22);
when "10111" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 23);
when "11000" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 24);
when "11001" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 25);
when "11010" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(30 downto 26);
when "11011" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(30 downto 27);
when "11100" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 28);
when "11101" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30 downto 29);
when "11110" => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(30);
when others => OUTPUT_1 <= INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&
INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31)&INPUT_1(31);
end case;
end process;
end synthesis;
| gpl-3.0 | 6e4754903128803993328aef7d6fcf29 | 0.479056 | 3.03654 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_gpio/src/vvc_context.vhd | 1 | 1,400 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_gpio;
use bitvis_vip_gpio.vvc_cmd_pkg.all;
use bitvis_vip_gpio.vvc_methods_pkg.all;
use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;
end context; | mit | e5da26bff561989409ae9a99f66c94a3 | 0.527143 | 5.511811 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_10_dir/exercise5_10.vhd | 1 | 1,600 | --!
--! @file: exercise5_10.vhd
--! @brief: arithmetic circuit with integer
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mini_alu is
generic (N: integer := 3;);
port (
a, b: in integer range -2**(N-1) to 2**(N-1)-1;
cin: in integer range 0 to 1;
opcode: in integer range 0 to 7;
y: out integer range -2**(N-1) to 2**(N-1)-1;
end entity mini_alu;
--------------------------------------
architecture circuit of mini_alu is
signal a_sig, b_sig: signed(N-1 downto 0);
signal a_unsig, b_unsig: unsigned(N-1 downto 0);
signal y_sig: signed(N-1 downto 0);
signal y_unsig: unsigned(N-1 downto 0);
begin
a_sig <= to_signed(a, a_sig'length);
b_sig <= to_signed(b, b_sig'length);
a_unsig <= to_unsigned(a, a_unsig'length);
b_unsig <= to_unsigned(b, b_unsig'length);
-- signed
with opcode(1 downto 0) select
y_sig <= a_sig + b_sig when 0,
a_sig - b_sig when 1.
b_sig - a_sig when 2,
a_sig + b_sig + cin when others;
-- unsigned
with opcode(1 downto 0) select
y_unsig <= a_unsig + b_unsig when 0,
a_unsig - b_unsig when 1.
b_unsig - a_unsig when 2,
a_unsig + b_unsig + cin when others;
-- mux
with opcode(2) select
y <= y_unsig when 0,
y_sig when others;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 7d13702e223698a425a8e4e50161db04 | 0.50875 | 3.44086 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/regfile.vhd | 1 | 2,955 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity regfile is
port
(
regfile_clk: in std_logic;
regfile_rst: in std_logic;
regfile_we: in std_logic;
regfile_waddr: in std_logic_vector(3 downto 0);
regfile_wdata: in std_logic_vector(15 downto 0);
regfile_raddr1: in std_logic_vector(3 downto 0);
regfile_rdata1: out std_logic_vector(15 downto 0);
regfile_raddr2: in std_logic_vector(3 downto 0);
regfile_rdata2: out std_logic_vector(15 downto 0)
);
end regfile;
architecture Behavioral of regfile is
signal r0, r2, r3, r4, r5, r6, r7, r8, r9: std_logic_vector(15 downto 0) := "0000000000000001";
signal r1: std_logic_vector(15 downto 0) := "0000000000000010";
signal r10: std_logic_vector(15 downto 0);
begin
process(regfile_clk, regfile_rst, regfile_we)
begin
if (regfile_rst = '0') then
regfile_rdata1 <= "0000000000000000";
regfile_rdata2 <= "0000000000000000";
else
case regfile_raddr1 is
when "0000" =>
regfile_rdata1 <= r0;
when "0001" =>
regfile_rdata1 <= r1;
when "0010" =>
regfile_rdata1 <= r2;
when "0011" =>
regfile_rdata1 <= r3;
when "0100" =>
regfile_rdata1 <= r4;
when "0101" =>
regfile_rdata1 <= r5;
when "0110" =>
regfile_rdata1 <= r6;
when "0111" =>
regfile_rdata1 <= r7;
when "1000" =>
regfile_rdata1 <= r8;--sp
when "1001" =>
regfile_rdata1 <= r9;--ih
when "1010" =>
regfile_rdata1 <= r10;--t
when others =>
null;
end case;
case regfile_raddr2 is
when "0000" =>
regfile_rdata2 <= r0;
when "0001" =>
regfile_rdata2 <= r1;
when "0010" =>
regfile_rdata2 <= r2;
when "0011" =>
regfile_rdata2 <= r3;
when "0100" =>
regfile_rdata2 <= r4;
when "0101" =>
regfile_rdata2 <= r5;
when "0110" =>
regfile_rdata2 <= r6;
when "0111" =>
regfile_rdata2 <= r7;
when "1000" =>
regfile_rdata2 <= r8;--sp
when "1001" =>
regfile_rdata2 <= r9;--ih
when "1010" =>
regfile_rdata2 <= r10;--t
when others =>
null;
end case;
if(regfile_we='1')then
if (regfile_clk'event and regfile_clk='0') then
case regfile_waddr is
when "0000" =>
r0 <= regfile_wdata;
when "0001" =>
r1 <= regfile_wdata;
when "0010" =>
r2 <= regfile_wdata;
when "0011" =>
r3 <= regfile_wdata;
when "0100" =>
r4 <= regfile_wdata;
when "0101" =>
r5 <= regfile_wdata;
when "0110" =>
r6 <= regfile_wdata;
when "0111" =>
r7 <= regfile_wdata;
when "1000" =>
r8 <= regfile_wdata;--sp
when "1001" =>
r9 <= regfile_wdata;--ih
when "1010" =>
r10 <= regfile_wdata;--t
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end Behavioral; | apache-2.0 | 52275b8c686b5fed737975a2b6ec2535 | 0.564805 | 2.917078 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/example8_4_dir/example8_4.vhd | 1 | 1,616 | --!
--! @file: example8_4.vhd
--! @brief: Shift register with Component and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
--------------------------------------
entity shift_register is
generic (M: positive := 4; -- num. of stages
N: positive := 8); -- bits per stage
port (
clk, load: in std_logic;
x: in std_logic_vector(N-1 downto 0);
d: in twoD(0 to M-1, N-1 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity shift_register;
--------------------------------------
architecture circuit of shift_register is
signal u: twoD(0 to M, N-1 downto 0);
signal v: twoD(0 to M-1, N-1 downto 0);
begin
-- transfer of x -> u and u -> y
gen1: for i in N-1 downto 0 generate
u(0,i) <= x(i); -- mapping input of entity to input of first stage
y(i) <= u(M, i); -- mapping the output of the last stage to the output of entity
end generate gen1;
-- update internal stages
gen2: for i in 0 to M-1 generate
gen3: for j in N-1 downto 0 generate
mux1: mux port map (
a => u(i, j),
b => d(i, j),
sel => load,
x => v(i, j)
);
dff1: flipflop port map (
d => v(i,j),
clk => clk,
q => u(i + 1, j)
);
end generate gen3;
end generate gen2;
end architecture circuit;
| gpl-3.0 | a086f092035bdeba037fb84930fae208 | 0.48948 | 3.672727 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_5_dir/exercise6_5.vhd | 1 | 1,624 | --!
--! @file: exercise6_5.vhd
--! @brief: Shift Register with Load
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity shift_register_load is
--generic declarations
port (
din: in std_logic_vector(0 to 3); -- din
d: in std_logic; -- input
clk: in std_logic; -- clk
load: in std_logic; -- load = 0 normal shift register load = 1 ff are programmed
dout: out std_logic); -- shift register output
end entity shift_register_load;
--------------------------------------
architecture circuit of shift_register_load is
signal mux_out: std_logic_vector(0 to 3);
signal q: std_logic_vector(0 to 2);
begin
-- creating the first mux
mux_out(0) <= d when load = '0' else din(0);
-- creating the other three muxes
gen: for i in 1 to 3 generate
mux_out(i) <= q(i-1) when load = '0' else din(i);
end generate gen;
-- creating the flip flops
proc: process (clk)
variable q_in: std_logic_vector(0 to 2);
begin
if (clk'event and clk = '1') then -- if rising edge
foreach: for i in 0 to 2 -- then assign input to output of each ff
q(i) <= mux_out(i)
end loop label;
dout <= mux_out(3); -- the last input is to the ouput of the register
end if;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 3f6f2ae69fdc995707f6361db5c57b6f | 0.518473 | 3.97066 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/global_signals_and_shared_variables_pkg.vhd | 1 | 2,884 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.protected_types_pkg.all;
package global_signals_and_shared_variables_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array(1 to C_NUM_SYNC_FLAGS) := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status := C_UVVM_STATUS_DEFAULT;
-- Global signals
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
end package global_signals_and_shared_variables_pkg; | mit | 3de668b374f4797cd4f471806a71b1d1 | 0.60957 | 4.478261 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/decode.vhd | 1 | 18,565 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
use mblite.std_pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
msr_interrupt_enable : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if v_reg.msr_interrupt_enable = '1' and decode_i.interrupt = '1' then
v_reg.interrupt := '1';
v_reg.msr_interrupt_enable := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (v_reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.msr_interrupt_enable := '0';
v_reg.interrupt := '0';
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110";
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_wrb.reg_write := '1';
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
if (compare(opcode, "000101") and instruction(1)) = '1' then
v.ctrl_ex.operation := '1';
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
elsif opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- WRITE THE RESULT ALSO TO REGISTER D
if v.reg_a(2) = '1' then
-- Flag writeback if reg_d != 0
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
end if;
if v.reg_a(3) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.reg_a(4);
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v_reg.msr_interrupt_enable := '1';
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.msr_interrupt_enable <= '1';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
| lgpl-3.0 | 20c89c0becbb4a549be359678da204a7 | 0.485214 | 3.537538 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_synth.vhd | 1 | 7,137 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.Font_TB_PKG.ALL;
ENTITY Font_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END Font_tb_synth;
ARCHITECTURE Font_synth_ARCH OF Font_tb_synth IS
COMPONENT Font_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
Font_TB_STIM_GEN_INST:ENTITY work.Font_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: Font_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| mit | 7a20a57c269e3715f3276aace8060884 | 0.556116 | 3.760274 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/dma_engine.vhd | 1 | 11,631 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.conversion.all;
entity dma_engine is
port(
clk : in std_logic; --25 MHz
reset : in std_logic;
start_dma : in std_logic; --enable receive DMA
--
--
--
address : out std_logic_vector(31 downto 0); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
--
--
--
mem_address : in std_logic_vector(31 downto 0); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic
);
end; --entity eth_dma
architecture logic of dma_engine is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal struc_ptr : std_logic_vector(31 downto 0);
SIGNAL dma_type : std_logic_vector( 7 DOWNTO 0);
SIGNAL ptr_src : std_logic_vector(31 downto 0);
SIGNAL ptr_src_2 : std_logic_vector(31 downto 0);
SIGNAL ptr_src_3 : std_logic_vector(31 downto 0);
SIGNAL ptr_dst : std_logic_vector(31 downto 0);
SIGNAL nWords : std_logic_vector(15 downto 0);
TYPE STATE_TYPE IS (waiting, nextS, addr_dma_type, read_dma_type, read_ptr_src, read_ptr_src_2, read_ptr_src_3, read_ptr_dst, read_nb_words, select_type, cpy_init_data, cpy_read_data, cpy_write_data, init_write_data, wait_one_cycle);
SIGNAL dma_state : STATE_TYPE;
CONSTANT INC_1_WORD : UNSIGNED(31 downto 0) := TO_UNSIGNED(4, 32);
begin --architecture
-- mem_address : in std_logic_vector(31 downto 2); --from CPU
-- mem_byte_we : in std_logic_vector(3 downto 0);
-- data_w : in std_logic_vector(31 downto 0);
-- pause_out : out std_logic
-- DMA CLEAR (0x00)
-- DMA COPY (0x01)
-- DMA XOR (0x02)
-- DMA F (0x03)
-- DMA G (0x04)
dma : process(reset, clk)
BEGIN
IF reset = '1' THEN
dma_state <= waiting;
dma_type <= ZERO( 7 downto 0);
ptr_src <= ZERO;
ptr_dst <= ZERO;
nWords <= ZERO(15 downto 0);
pause_out <= '0';
address <= ZERO;
byte_we <= "0000";
data_write <= ZERO;
ELSE
if CLK'event and CLK = '1' then
CASE dma_state IS
WHEN waiting =>
struc_ptr <= data_w(31 DOWNTO 0);
IF start_dma = '1' THEN
-- REPORT "STARTING DMA = " & to_hex_str( data_w );
dma_state <= nextS;
pause_out <= '1';
ELSE
dma_state <= waiting;
pause_out <= '0';
END IF;
address <= data_w(31 DOWNTO 0); -- ON POSITIONNE L'ADRESSE MEMOIRE
WHEN nextS =>
dma_state <= addr_dma_type;
pause_out <= '1';
WHEN addr_dma_type =>
-- REPORT "WRITING STRUCTURE ADDRESS";
pause_out <= '1';
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
byte_we <= "0000"; -- DE LA STRUCTURE CONTENANT LA
dma_state <= read_dma_type; -- REQUETE DMA
WHEN read_dma_type =>
-- REPORT "READING DMA TYPE = " & to_hex_str( data_read );
pause_out <= '1';
dma_type <= data_read( 7 DOWNTO 0); -- ON MEMORISE LE
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000000" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src; -- NEXT STATE
END IF;
WHEN read_ptr_src =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000001" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_2 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_2 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000010" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_3 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_3 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_ptr_dst; -- NEXT STATE
WHEN read_ptr_dst =>
-- REPORT "READING DST POINTER = " & to_hex_str( data_read );
ptr_dst <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_nb_words; -- NEXT STATE
WHEN read_nb_words =>
-- REPORT "READING NB WORDS = " & to_hex_str( data_read );
nWords <= data_read(15 DOWNTO 0); --
byte_we <= "0000"; --
dma_state <= select_type; -- NEXT STATE
WHEN select_type =>
-- REPORT "SELECTING DMA OPERATION";
IF dma_type = "00000000" THEN
dma_state <= init_write_data;
ELSE
dma_state <= cpy_init_data;
END IF;
-----------------------------------------------------------
-- on demande la donnee 0
WHEN cpy_init_data =>
REPORT "PROCESSING cpy_init_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
byte_we <= "0000"; -- TYPE DE LA REQUETE +
dma_state <= cpy_read_data;
-- on demande la donnee 1
WHEN cpy_read_data =>
REPORT "PROCESSING cpy_read_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) );
data_write <= data_read;
byte_we <= "0000";
dma_state <= cpy_write_data;
-- on ecrit la donnee 0
WHEN cpy_write_data =>
REPORT "PROCESSING cpy_write_data to " & to_hex_str( ptr_dst ) & " data_read = " & to_hex_str( data_read );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
-- data_write <= ZERO;
byte_we <= "1111"; -- TYPE DE LA REQUETE +
-- On decompte ...
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= cpy_read_data; -- NEXT STATE
END IF;
-----------------------------------------------------------
WHEN init_write_data =>
-- REPORT "PROCESSING init_write_data " & to_hex_str( ptr_dst ) & " - " & to_hex_str( nWords );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
byte_we <= "1111"; -- TYPE DE LA REQUETE +
pause_out <= '1';
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= init_write_data; -- NEXT STATE
END IF;
WHEN wait_one_cycle =>
-- REPORT "PROCESSING wait_one_cycle";
byte_we <= "0000"; -- TYPE DE LA REQUETE +
pause_out <= '0';
dma_state <= waiting; -- NEXT STATE
END CASE;
END IF;
END IF;
END process;
end; --architecture logic
| gpl-3.0 | a4e952f9ce09d6d9b3e6a6ed450a61e1 | 0.465566 | 3.831028 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/conversion.vhd | 1 | 44,864 | --------------------------------------------------------------------------------
-- File Name: conversions.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was originally written by SEVA Technologies, Inc. and donated
-- to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
-- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int
-- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function
-- int_to_slv
-- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str
-- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0
-- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in
-- function int_to_slv) from > to >=
-- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- integer | to_slv | N/A | N/A | N/A | N/A
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
-- FROM TO: integer
-- -----------------|---------------|
-- std_logic_vector | to_int |
--------------------------------------------------------------------------------
PACKAGE conversion IS
----------------------------------------------------------------------------
-- the conversions in this package are not intended to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
-- <these packages are mutually exclusive>
-- conv_integer(std_logic_vector)
-- <except for this conversion, these packages are unnecessary)
-- to minimize compile problems write:
-- use std_logic_unsigned.conv_integer;
-- use std_logic_signed.conv_integer;
--
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- integer to std_logic_vector
function int_to_slv (x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
-- std_logic_vector to integer
function to_int (x : std_logic_vector)
return integer;
END conversion;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversion IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
function min(x,y: integer) return integer is
begin
if x < y then return x; else return y; end if;
end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
variable slv4_val : slv4;
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
slv4_val := int(i to i+3);
case slv4_val is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
when "LLLL" => r(ptr) := 'L';
when "HHHH" => r(ptr) := 'H';
when "UUUU" => r(ptr) := 'U';
when "XXXX" => r(ptr) := 'X';
when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",decimal,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function int_to_slv(x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : integer := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
if int >= 0 or int = 0 then
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
else
int := 2**(rtn_len - 1) + int;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
r(33-rtn_len) := '1';
return r(33-rtn_len to 32);
end if;
end int_to_slv;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
function to_int(x : std_logic_vector) return integer is
-- assumes x is an signed number
-- more than 32 bits are truncated on left
variable t : std_logic_vector(x'length downto 1) := x;
variable int : std_logic_vector(32 downto 1) := (others => '0');
variable sign : std_logic := '0';
variable size : integer := 0;
variable inv : boolean := false;
variable r : integer := 0;
variable place : positive := 1;
begin
if x'length < 33 then
sign := t(x'length);
for i in t'reverse_range loop
if sign = '1' then
if inv = true then
t(i) := not(t(i));
elsif t(i) = '1' then
inv := true;
end if;
end if;
size := size +1;
end loop;
inv := false;
for i in 1 to size - 1 loop
case t(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
else -- x'length >= 33
int := t(32 downto 1);
sign := t(32);
for i in 1 to 31 loop
if sign = '1' then
if inv = true then
int(i) := not(int(i));
elsif int(i) = '1' then
inv := true;
end if;
end if;
end loop;
inv := false;
for i in 1 to 31 loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
end if;
end to_int;
END conversion;
| gpl-3.0 | 4e19831c28425f6b431db6fe4cc16b3d | 0.442136 | 3.980128 | false | false | false | false |
chriskmanx/qmole | QMOLEDEV/geany-0.21/data/filetypes.vhdl | 1 | 3,274 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# foreground;background;bold;italic
default=0x000000;0xffffff;false;false
comment=0xd00000;0xffffff;false;false
comment_line_bang=0x3f5fbf;0xffffff;false;false;
number=0x007f00;0xffffff;false;false
string=0xff901e;0xffffff;false;false
operator=0x301010;0xffffff;false;false
identifier=0x000000;0xffffff;false;false
stringeol=0x000000;0xe0c0e0;false;false
keyword=0x001a7f;0xffffff;true;false
stdoperator=0x007f7f;0xffffff;false;false
attribute=0x804020;0xffffff;false;false
stdfunction=0x808020;0xffffff;true;false
stdpackage=0x208020;0xffffff;false;false
stdtype=0x208080;0xffffff;false;false
userword=0x804020;0xffffff;true;false
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-3.0 | 7508fc0bbfc1fd5d8325e0480573018c | 0.823458 | 3.802555 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram_xilinx.vhd | 1 | 362,811 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 16);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector( 3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(3 downto 0) is address(16 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(15 downto 0);
--Block Data Out
signal block_do: mem32_vector(15 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(3 downto 0);
begin
block_enable<= "0000000000000001" when (enable='1') and (block_sel="0000") else
"0000000000000010" when (enable='1') and (block_sel="0001") else
"0000000000000100" when (enable='1') and (block_sel="0010") else
"0000000000001000" when (enable='1') and (block_sel="0011") else
"0000000000010000" when (enable='1') and (block_sel="0100") else
"0000000000100000" when (enable='1') and (block_sel="0101") else
"0000000001000000" when (enable='1') and (block_sel="0110") else
"0000000010000000" when (enable='1') and (block_sel="0111") else
"0000000100000000" when (enable='1') and (block_sel="1000") else
"0000001000000000" when (enable='1') and (block_sel="1001") else
"0000010000000000" when (enable='1') and (block_sel="1010") else
"0000100000000000" when (enable='1') and (block_sel="1011") else
"0001000000000000" when (enable='1') and (block_sel="1100") else
"0010000000000000" when (enable='1') and (block_sel="1101") else
"0100000000000000" when (enable='1') and (block_sel="1110") else
"1000000000000000" when (enable='1') and (block_sel="1111") else
"0000000000000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-----------------------------------------------------------------------------
--
-- BLOCKS generation
--
-----------------------------------------------------------------------------
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block8: if (block_count > 8) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 9)
--
-----------------------------------------------------------------------------
block9: if (block_count > 9) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 10)
--
-----------------------------------------------------------------------------
block10: if (block_count > 10) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 11)
--
-----------------------------------------------------------------------------
block11: if (block_count > 11) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 12)
--
-----------------------------------------------------------------------------
block12: if (block_count > 12) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block13: if (block_count > 13) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block14: if (block_count > 14) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 15)
--
-----------------------------------------------------------------------------
block15: if (block_count > 15) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | e74761fe0ef22428c9a0f92dc35d5ab9 | 0.839029 | 7.090861 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_8_dir/exercise6_8.vhd | 1 | 1,472 | --!
--! @file: exercise6_8.vhd
--! @brief: Signal Generator
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity signal_generator is
--generic declarations
port (
clk: in std_logic; -- clk
x, y: out std_logic); --output
end entity signal_generator;
--------------------------------------
architecture circuit of signal_generator is
signal even: std_logic := '0';
begin
proc: process (clk)
begin
if (clk'event and clk = '1') then
if (even = '0') then
x <= clk;
y <= '0';
else
x <= '0';
y <= clk;
end if;
if (even = '0') then
even <= '1';
else
even <= '0';
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
architecture arch of signal_generator is
--signals and declarations
begin
proc: process (clk)
variable a, b: std_logic;
begin
if (clk'event and clk = '1') then
a <= not a;
else if (clk'event and clk = '0') then
b <= not a;
end if;
x <= a and b;
y <= a nor b;
end process proc;
end architecture arch;
--------------------------------------
| gpl-3.0 | d637f73ad23a1c7763939d1fde44d70e | 0.432065 | 4.304094 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/COMPLEX/CPLX_SUB_16b.vhd | 5 | 1,659 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
entity CPL_ADD_16b is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of CPL_ADD_16b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) COMPLEX 16bis ADD RESSOURCE : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(15 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(15 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( SIGNED(INPUT_1(15 downto 0)) + SIGNED(INPUT_2(15 downto 0)) );
rTemp2 := STD_LOGIC_VECTOR( SIGNED(INPUT_1(31 downto 16)) + SIGNED(INPUT_2(31 downto 16)) );
--if( rTemp1(16) = '1' ) then
-- rTemp1(7 downto 0) := "1111111111111111";
--end if;
--if( rTemp2(16) = '1' ) then
-- rTemp2(7 downto 0) := "1111111111111111";
--end if;
OUTPUT_1 <= (rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | e4e9a22ced2cbbc0a56808433d7a4bb2 | 0.517782 | 3.324649 | false | false | false | false |
VLSI-EDA/UVVM_All | xConstrRandFuncCov/src/MessagePkg.vhd | 2 | 5,845 | --
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015: 2015.01 Removed initialized parameter from Get
-- 04/2018: 2018.04 Minor updates to alert message
--
--
-- Copyright (c) 2010 - 2018 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; | mit | 2405f9703c41d5dd2e1d58748e76fd3c | 0.553807 | 5.021478 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/mem.vhd | 1 | 4,548 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
use mblite.std_pkg.all;
entity mem is port
(
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end mem;
architecture arch of mem is
signal r, rin : mem_out_type;
signal mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
-- connect pipline signals
mem_o.ctrl_wrb <= r.ctrl_wrb;
mem_o.ctrl_mem_wrb <= r.ctrl_mem_wrb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_o.dat_o <= mem_result;
dmem_o.sel_o <= decode_mem_store(mem_i.alu_result(1 downto 0), mem_i.ctrl_mem.transfer_size);
dmem_o.we_o <= mem_i.ctrl_mem.mem_write;
dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 downto 0);
dmem_o.ena_o <= mem_i.ctrl_mem.mem_read or mem_i.ctrl_mem.mem_write;
mem_comb: process(mem_i, mem_i.ctrl_wrb, mem_i.ctrl_mem, r, r.ctrl_wrb, r.ctrl_mem_wrb)
variable v : mem_out_type;
variable intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v.ctrl_wrb := mem_i.ctrl_wrb;
if mem_i.branch = '1' then
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
else
v.alu_result := mem_i.alu_result;
end if;
-- Forward memory result
if CFG_MEM_FWD_WRB = true and ( r.ctrl_mem_wrb.mem_read and compare(mem_i.ctrl_wrb.reg_d, r.ctrl_wrb.reg_d)) = '1' then
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wrb.transfer_size, r.alu_result(1 downto 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
else
mem_result <= mem_i.dat_d;
end if;
v.ctrl_mem_wrb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wrb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
end process;
mem_seq: process(clk_i)
procedure proc_mem_reset is
begin
r.alu_result <= (others => '0');
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.ctrl_mem_wrb.mem_read <= '0';
r.ctrl_mem_wrb.transfer_size <= WORD;
end procedure proc_mem_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_mem_reset;
elsif ena_i = '1' then
r <= rin;
end if;
end if;
end process;
end arch;
| lgpl-3.0 | 98c091817a3d0084c093b53acd807e6d | 0.570361 | 3.60095 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/coproc_3.vhd | 5 | 1,408 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_3 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_3 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 | 8986918d269870471adcf463ad9a7352 | 0.508523 | 3.705263 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/example10_4_dir/reg_mux.vhd | 1 | 794 | library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity reg_mux is
--generic declarations
port (
a, b, c, d: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0) ;
clk: in std_logic;
x, y: out std_logic_vector(3 downto 0));
end entity reg_mux;
--------------------------------------
architecture circuit of reg_mux is
signal mux: std_logic_vector(3 downto 0);
begin
-- mutiplexer
mux <= a when sel = "00" else
b when sel = "01" else
c when sel = "10" else
d;
x <= mux;
-- register
proc: process (clk)
begin
if (clk'event and clk = '1') then
y <= mux;
end if;
end process proc;
end architecture circuit;
| gpl-3.0 | 19a815d78231852746a5cb240b3a00ea | 0.501259 | 3.817308 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/vga_bitmap_640x480.vhd | 2 | 11,684 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.CONSTANTS.all;
entity VGA_bitmap_640x480 is
generic(grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
endcalcul : in std_logic;
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 307199) of std_logic_vector(bit_per_pixel - 1 downto 0);
signal screen : GRAM; -- the memory representation of the image
signal ADDR : unsigned(18 downto 0);
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
begin
ADDRmanagement : process(clk,reset, data_write, endcalcul)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR < 307199 then
ADDR<=ADDR+1;
else
ADDR<=(others=>'0');
end if;
end if;
end if;
end if;
end process;
-- This process performs data access (read and write) to the memory
memory_management : process(clk)
begin
if clk'event and clk='1' then
next_pixel <= screen(pix_read_addr);
data_out <= screen(to_integer(ADDR));
if data_write = '1' then
screen(to_integer(ADDR)) <= data_in;
end if;
end if;
end process;
pixel_read_addr : process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
when others => NULL;
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 4a3858e537c8a99c4c5f701c58f73e71 | 0.486563 | 3.626319 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_5.vhd | 4 | 2,143 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity function_5 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_5 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data1 := UNSIGNED( INPUT_1(7 downto 0) );
data2 := UNSIGNED( INPUT_1(15 downto 8) );
data3 := UNSIGNED( INPUT_1(23 downto 16) );
data4 := UNSIGNED( INPUT_1(31 downto 24) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff1 := data1 - mini; -- 8
diff2 := data2 - mini; -- 8
diff3 := data3 - mini; -- 8
diff4 := data4 - mini; -- 8
mult1 := diff1 * beta; -- 24
mult2 := diff2 * beta; -- 24
mult3 := diff3 * beta; -- 24
mult4 := diff4 * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
OUTPUT_1(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
OUTPUT_1(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
OUTPUT_1(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
--OUTPUT_1 <= INPUT_1;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | 85296fb01a3895c6b84f7983d15fb788 | 0.569295 | 3.322481 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_IOPORT_2.vhd | 2 | 3,058 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--use ims.conversion.all;
entity RESOURCE_CUSTOM_6 is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in async32_in_type;
outp : out async32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_6 is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal wBuffer : std_logic_vector(1 downto 0);
signal rBuffer : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_6 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-- type async32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- signed : std_logic;
-- write_data : std_logic;
-- read_data : std_logic;
-- end record;
-- type async32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
-- end record;
-------------------------------------------------------------------------
reg : process(clk)
variable vready : std_logic;
variable vnready : std_logic;
begin
vready := '0';
vnready := '0';
if rising_edge(clk) then
if (rst = '0') then
--assert false report "STATE XXX => RESET";
--elsif (inp.flush = '1') then
--assert false report "STATE XXX => (inp.flush = '1')";
--state <= "000";
elsif (holdn = '0') then
--assert false report "STATE XXX => (holdn = '1')";
--state <= state;
else
rBuffer <= rBuffer(0) & inp.read_data;
wBuffer <= wBuffer(0) & inp.write_data;
if( wBuffer(0) = '1' ) then
--printmsg("(IOs) DATA ARE SENDED TO THE INTERFACE (1)");
--printmsg("(IOs) - COMPUTATION INPUT_A IS (" & to_int_str(inp.op1(31 downto 0),6) & " )");
--printmsg("(IOs) - COMPUTATION INPUT_B IS (" & to_int_str(inp.op2(31 downto 0),6) & " )");
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
end if;
if( rBuffer(1) = '1' ) then
--printmsg("(IOs) DATA READ FROM THE INTERFACE");
--printmsg("(IOs) - COMPUTATION INPUT_A IS (" & to_int_str(A,6) & " )");
--printmsg("(IOs) - COMPUTATION INPUT_B IS (" & to_int_str(B,6) & " )");
A <= "00000000000000000000000000000000";
end if;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
-------------------------------------------------------------------------
outp.result <= A;
outp.icc <= "0000";
end;
| gpl-3.0 | f8cbf4cf3a4ab2216b3ba5c98deaf0af | 0.520929 | 3.263607 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/coproc_4.vhd | 1 | 3,806 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
--clock_vga : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0);
--VGA_hs : out std_logic; -- horisontal vga syncr.
-- VGA_vs : out std_logic; -- vertical vga syncr.
--iter : out std_logic_vector(3 downto 0) -- red output
data_write :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0)
-- VGA_green : out std_logic_vector(3 downto 0); -- green output
-- VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal tmp_addr : std_logic_vector(16 downto 0);
signal pixel : std_logic_vector(11 downto 0);
--signal tmp_out : std_logic_vector(10 downto 0);
signal counter : integer range 0 to 76799:= 0;
begin
--tmp_addr <= INPUT_1(31 downto 13);
--pixel <= INPUT_1(7 downto 0);
--
process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSE
IF INPUT_1_valid = '1' THEN
IF counter < 76799 THEN
counter <= counter + 1;
ELSE
counter <= 0;
END IF;
END IF;
END IF;
END IF;
end process;
--
--
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- tmp_addr <= (others => '1');
-- pixel <= (others => '0');
-- data_write <= '0';
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- tmp_addr <= INPUT_1(31 downto 13);
-- pixel <= INPUT_1(7 downto 0);
-- data_write <= '1';
-- else
-- data_write <= '0';
-- END IF;
-- END IF;
-- END IF;
-- end process;
--
tmp_addr <= std_logic_vector(to_signed(counter, 17));
--
data_write <=INPUT_1_valid;
data_out <=INPUT_1(11 downto 0);
ADDR <= tmp_addr;
OUTPUT_1 <= "000000000000000"&tmp_addr;
-- process (clock)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
---- assert INPUT_1_valid /= '1' severity failure;
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-------------------------------------------------------------------------
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
-------------------------------------------------------------------------
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-- -------------------------------------------------------------------------
--
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 | 8e793771f1d80ed3c4793670229af7cc | 0.496322 | 3.006319 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/pulse_filter.vhd | 1 | 2,970 | ----------------------------------------------------------------------------
-- debouncer.vhd -- Signal Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals. It is designed to
-- independently debounce a variable number of signals, the number of which
-- are set using the PORT_WIDTH generic. Debouncing is done by only
-- registering a change in a button state if it remains constant for
-- the number of clocks determined by the DEBNC_CLOCKS generic.
--
-- Generic Descriptions:
--
-- PORT_WIDTH - The number of signals to debounce. determines the width
-- of the SIGNAL_I and SIGNAL_O std_logic_vectors
-- DEBNC_CLOCKS - The number of clocks (CLK_I) to wait before registering
-- a change.
--
-- Port Descriptions:
--
-- SIGNAL_I - The input signals. A vector of width equal to PORT_WIDTH
-- CLK_I - Input clock
-- SIGNAL_O - The debounced signals. A vector of width equal to PORT_WIDTH
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
-- 08/29/2013(SamB): Improved reuseability by using generics
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.all;
entity pulse_filter is
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16);
Port (
SIGNAL_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC
);
end pulse_filter;
architecture Behavioral of pulse_filter is
constant CNTR_WIDTH : integer := natural(ceil(LOG2(real(DEBNC_CLOCKS))));
constant CNTR_MAX : std_logic_vector((CNTR_WIDTH - 1) downto 0) := std_logic_vector(to_unsigned((DEBNC_CLOCKS - 1), CNTR_WIDTH));
signal sig_cntrs_ary : std_logic_vector((CNTR_WIDTH - 1) downto 0) := (others=>'0');
signal sig_out_reg : std_logic := '0';
begin
dprocess : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (sig_cntrs_ary = CNTR_MAX) then
sig_out_reg <= not(sig_out_reg);
end if;
end if;
end process;
cprocess : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if ((sig_out_reg = '1') xor (SIGNAL_I = '1')) then
if (sig_cntrs_ary = CNTR_MAX) then
sig_cntrs_ary <= (others => '0');
else
sig_cntrs_ary <= sig_cntrs_ary + 1;
end if;
else
sig_cntrs_ary <= (others => '0');
end if;
end if;
end process;
SIGNAL_O <= sig_out_reg;
end Behavioral;
| gpl-3.0 | f5ec9a4f2748da0fa05a07c331282ee9 | 0.527946 | 4.013514 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_axilite/src/vvc_methods_pkg.vhd | 1 | 17,285 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axilite_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the AXILITE VVC
--===============================================================================================
constant C_VVC_NAME : string := "AXILITE_VVC";
signal AXILITE_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AXILITE_VVCT;
alias t_bfm_config is t_axilite_bfm_config;
type t_executor_result is record
cmd_idx : natural; -- from UVVM handshake mechanism
data : std_logic_vector(127 downto 0);
value_is_new : boolean; -- turn true/false for put/fetch
fetch_is_accepted : boolean;
end record;
type t_executor_result_array is array (natural range <>) of t_executor_result;
-- Type found in UVVM-Util types_pkg
constant C_AXILITE_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_axilite_bfm_config; -- Configuration for AXI4-Lite BFM. See quick reference for AXI4-Lite BFM
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AXILITE_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AXILITE_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AXILITE_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'),
msg => (others => ' ')
);
shared variable shared_axilite_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_AXILITE_VVC_CONFIG_DEFAULT);
shared variable shared_axilite_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_axilite_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axilite_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX)
& ", " & to_string(byte_enable, BIN, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_normalised_byte_ena : std_logic_vector(shared_vvc_cmd.byte_enable'length-1 downto 0) :=
normalize_and_check(byte_enable, shared_vvc_cmd.byte_enable, ALLOW_WIDER_NARROWER, "byte_enable", "shared_vvc_cmd.byte_enable", proc_call & " called with to wide byte_enable. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.byte_enable := v_normalised_byte_ena;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure axilite_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure axilite_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ);
shared_vvc_cmd.operation := READ;
shared_vvc_cmd.addr := v_normalised_addr;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure axilite_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
end package body vvc_methods_pkg;
| mit | 412efa051a5b7881bb564c5168b651f5 | 0.586983 | 4.092093 | false | true | false | false |
MForever78/CPUFly | ipcore_dir/Ram/example_design/Ram_exdes ([email protected] 2015-09-19-17-37-53).vhd | 1 | 4,746 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Ram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Ram_exdes;
ARCHITECTURE xilinx OF Ram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Ram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Ram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 36c0bb303edef15e4889e947fd56a0cf | 0.546144 | 4.585507 | false | false | false | false |
ryos36/polyphony-tutorial | Life/life_show_tb.vhdl | 1 | 2,604 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use iEEE.std_logic_arith.all;
use iEEE.std_logic_unsigned."-";
use iEEE.std_logic_unsigned."+";
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity life_show_tb is
end life_show_tb;
architecture sim of life_show_tb is
----------------------------------------------------------------
component space_is_the_place
port(
clk : in std_logic;
clk_for_life : out std_logic;
data_src : out std_logic_vector(2 downto 0);
mark_src : out std_logic;
data_result : in std_logic;
mark_result : in std_logic
);
end component;
----------------------------------------------------------------
component pattern_detector
port(
clk : in std_logic;
din : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(2 downto 0);
mark_src : out std_logic
);
end component;
----------------------------------------------------------------
component life
port(
clk : in std_logic;
din : in std_logic_vector(2 downto 0);
mark_in : in std_logic;
dout : out std_logic;
mark_out : out std_logic
);
end component;
----------------------------------------------------------------
signal clk : std_logic;
signal clk_for_life : std_logic;
signal data_src : std_logic_vector(2 downto 0);
signal delayed_data_src : std_logic_vector(2 downto 0);
signal mark_src : std_logic;
signal data_result : std_logic;
signal mark_result : std_logic;
constant clk_period : time := 10 ns;
begin
-------------------------------------------------------------------
space_is_the_place0 : space_is_the_place
port map (
clk => clk,
clk_for_life => clk_for_life,
data_src => data_src,
--mark_src => mark_src,
data_result => data_result,
mark_result => mark_result
);
-------------------------------------------------------------------
pattern_detector0 : pattern_detector
port map (
clk => clk_for_life,
din => data_src,
dout => delayed_data_src,
mark_src => mark_src
);
-------------------------------------------------------------------
life0 : life
port map (
clk => clk_for_life,
din => delayed_data_src,
mark_in => mark_src,
dout => data_result,
mark_out => mark_result
);
-------------------------------------------------------------------
clk_producer: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
end sim;
| mit | a22cf95ca5b6d3f97ad6ea0e7dcbbb6a | 0.481183 | 3.904048 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_6_dir/exercise8_6.vhd | 1 | 1,182 | --!
--! @file: exercise8_6.vhd
--! @brief: synchronous counter with component and genrate
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.pkg_sync_counter.all;
--------------------------------------
entity 32_sync_counter is
generic (N: integer := 32);
port (
a, b, clk: in std_logic;
q: out std_logic_vector(N-1 downto 0));
end entity sync_counter;
--------------------------------------
architecture circuit of 32_sync_counter is
signal q_and: std_logic_vector(N-1 downto 0);
signal q_temp: std_logic_vector(N-1 downto 0);
begin
sync0: sync_counter port map (
a => a,
b => b,
clk => clk,
andq => q_and(0),
q => q_temp(0)
);
gen1: for i in 1 to N-1 generate
sync: sync_counter port map (
a => and_q(i-1),
b => q_temp(i-1),
clk => clk,
andq => q_and(i),
q => q_temp(i),
);
end generate gen1;
q <= q_temp(i);
end architecture circuit;
--------------------------------------
| gpl-3.0 | 160b37258a59fa803e7a30110cb2c1c6 | 0.481387 | 3.560241 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/coproc_1.vhd | 1 | 3,734 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
signal R0, R1, R2, R3, R4, R5 : std_logic_vector(31 downto 0);
signal Temp01, Temp23, Temp45 : signed(63 downto 0);
signal mul01, mul23, mul45 : std_logic_vector(31 downto 0);
signal reg_mul01, reg_mul23, reg_mul45 : std_logic_vector(31 downto 0);
signal sum1 : signed(32 downto 0);
signal out_tmp : signed(33 downto 0);
signal counter : integer range 0 to 1:= 0;
signal pipe_enable : std_logic;
attribute RAM_STYLE : string;
attribute RAM_STYLE of R0: signal is "DISTRIBUTED";
attribute RAM_STYLE of R1: signal is "DISTRIBUTED";
attribute RAM_STYLE of R2: signal is "DISTRIBUTED";
attribute RAM_STYLE of R3: signal is "DISTRIBUTED";
attribute RAM_STYLE of R4: signal is "DISTRIBUTED";
attribute RAM_STYLE of R5: signal is "DISTRIBUTED";
attribute RAM_STYLE of reg_mul01: signal is "DISTRIBUTED";
attribute RAM_STYLE of reg_mul23: signal is "DISTRIBUTED";
attribute RAM_STYLE of reg_mul45: signal is "DISTRIBUTED";
begin
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
R0 <= (others => '0');
R1 <= (others => '0');
R2 <= (others => '0');
R3 <= (others => '0');
R4 <= (others => '0');
R5 <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
R5 <= R4;
R4 <= R3;
R3 <= R2;
R2 <= R1;
R1 <= R0;
R0 <= INPUT_1;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
Temp01 <= (signed(R0) * signed(R1));
mul01 <= std_logic_vector(Temp01(42 downto 11));
Temp23 <= (signed(R2) * signed(R3));
mul23 <= std_logic_vector(Temp23(42 downto 11));
Temp45 <= (signed(R4) * signed(R5));
mul45 <= std_logic_vector(Temp45(42 downto 11));
register_mult : process(clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
reg_mul01 <= (others => '0');
reg_mul23 <= (others => '0');
reg_mul45 <= (others => '0');
ELSIF pipe_enable = '1' THEN
reg_mul01 <= mul01;
reg_mul23 <= mul23;
reg_mul45 <= mul45;
END IF;
END IF;
end process;
sum1 <= signed(reg_mul01(31)®_mul01) + signed(reg_mul23(31)®_mul23); -- 33 bits
out_tmp <= sum1(32)&sum1 + signed(reg_mul45(31)®_mul45(31)®_mul45); -- 34 bits
pipe_ctrl: process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSIF INPUT_1_valid = '0' THEN
IF counter = 1 THEN
counter <= 1;
ELSE
counter <= counter + 1;
END IF;
ELSE
counter <= 0;
END IF;
END IF;
end process;
pipe_enable <= '0' when counter = 3 else '1';
output_reg: process(clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
OUTPUT_1 <= (others => '0');
ELSE
OUTPUT_1 <= std_logic_vector(out_tmp(31 downto 0));
END IF;
END IF;
end process;
end; --architecture logic | gpl-3.0 | d7fcb7d902643f34ef64ac90910985a9 | 0.585163 | 3.0682 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_14_dir/exercise5_14.vhd | 1 | 1,365 | --!
--! @file: exercise5_14.vhd
--! @brief: Recommended Unsigned Adder/Substracter
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity unsigned_adder_substracter is
generic (N: integer := 5;);
port (
a, b: in std_logic_vector(N-1 downto 0); -- operands
cin: in std_logic; -- cin
sum, sub: out std_logic_vector(N downto 0)); -- result of sum of sub with their respectives cout
end entity unsigned_adder_substracter;
--------------------------------------
architecture circuit of unsigned_adder_substracter is
signal a_un: unsigned(N-1 downto 0);
signal b_un: unsigned(N-1 downto 0);
signal sum_un: unsigned(N downto 0);
signal sub_un: unsigned(N downto 0);
begin
--------------------------------------
a_un <= unsigned(a);
b_un <= unsigned(b);
--------------------------------------
sum_un <= ('0' & a_un) + ('0' & b_un) + ('0' & cin);
sub_un <= ('0' & a_un) - ('0' & b_un) + ('0' & cin);
--------------------------------------
sum <= std_logic_vector(sum_un);
sub <= std_logic_vector(sub_un);
--------------------------------------
end architecture circuit;
--------------------------------------
| gpl-3.0 | 494c5d883a823766211e3e0f80787345 | 0.462271 | 3.922414 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/build_dir/generated/ram_image.vhd | 1 | 362,811 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 03);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector( 3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(3 downto 0) is address(16 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(15 downto 0);
--Block Data Out
signal block_do: mem32_vector(15 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(3 downto 0);
begin
block_enable<= "0000000000000001" when (enable='1') and (block_sel="0000") else
"0000000000000010" when (enable='1') and (block_sel="0001") else
"0000000000000100" when (enable='1') and (block_sel="0010") else
"0000000000001000" when (enable='1') and (block_sel="0011") else
"0000000000010000" when (enable='1') and (block_sel="0100") else
"0000000000100000" when (enable='1') and (block_sel="0101") else
"0000000001000000" when (enable='1') and (block_sel="0110") else
"0000000010000000" when (enable='1') and (block_sel="0111") else
"0000000100000000" when (enable='1') and (block_sel="1000") else
"0000001000000000" when (enable='1') and (block_sel="1001") else
"0000010000000000" when (enable='1') and (block_sel="1010") else
"0000100000000000" when (enable='1') and (block_sel="1011") else
"0001000000000000" when (enable='1') and (block_sel="1100") else
"0010000000000000" when (enable='1') and (block_sel="1101") else
"0100000000000000" when (enable='1') and (block_sel="1110") else
"1000000000000000" when (enable='1') and (block_sel="1111") else
"0000000000000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-----------------------------------------------------------------------------
--
-- BLOCKS generation
--
-----------------------------------------------------------------------------
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"8c8c8c3403acacacacacacacacacacacac08000c241400ac273c243c243c273c",
INIT_01 => X"3c240c3c260caf0cafafafafafafafaf3c24af3c2734038c8c8c8c8c8c8c8c8c",
INIT_02 => X"8c36020c260c240c3c020c260c8c36020c260c240c3c260c260c8e260c3c0c3c",
INIT_03 => X"0c3c020c270c8c36020c260c240c3c020c240c8c36020c260c240c3c020c3c0c",
INIT_04 => X"020c36260c240c3c020c000c8c36020c260c240c3c020c000c8c36020c260c24",
INIT_05 => X"0c030c020c020c020c020c000c8e243c0014008e0014008e0226020c263c0c8e",
INIT_06 => X"0080ac001030008c3c241000800003ac001030008c3c0008ae020c020c020c02",
INIT_07 => X"ac24001030008c3c00030014ac24001030008c3c2424102c3000242400032414",
INIT_08 => X"64762d2028662d2028662d2079652d00292079652d0d6e656365205000080014",
INIT_09 => X"984500002064702067692d002064752067612d2974632d2974632d2064762d20",
INIT_0A => X"c81a8df5f8c42476d0bd84a8b16130ba50fbc4c2f90fcd230800a941581f94dc",
INIT_0B => X"0b7ee457b6b6af8c1565b7f0ed85de4078f97f898d9ad44258d7d3b9c682adc2",
INIT_0C => X"ac373024844fc3d60e7ea85ed9e011caee81d3b13e2bc5473f1247314a8f8284",
INIT_0D => X"af8a2e4a8d6be3ac12ffb717218d6a91fe6a28c51b5deaca9912e75582185a8f",
INIT_0E => X"80f6ab5e0b2f4885362e2e8c8c4ce7679e4e9df8f39db657b9fe47f1f606c685",
INIT_0F => X"42368df4d83e95b24163ab1b7125795700cf6eacd963f881df4f5d2c3946ccae",
INIT_10 => X"454c467b252bb8bdac97bde56a809470b6b772f29ab9d371b409f56cd26f2c5b",
INIT_11 => X"b9aed638e6acd74523257f694a1a10e177d0c06f8d12b243077d17664d419cdf",
INIT_12 => X"c4ce3ca13e2d54b204c300b9aa1d3fef6e606b2f3a29a172ec027a5efd28b262",
INIT_13 => X"11100da1fbab8d51aa9dbd512cad86f056d227c9ec84e1609f53b6a66541d6cb",
INIT_14 => X"837538676d43b101a0a0b7f5fe9514a40345fbf2d4e5d3b2deac7b4291843290",
INIT_15 => X"04dc19e162c9e42b2dcf1acd850153167cd7fbed62e717e8af2ed4bce03d4373",
INIT_16 => X"deb1b597c7e4ed350e92f7edb7dca6cfcaf872fa48d739c8adfa5726158d4656",
INIT_17 => X"24682ec7d2e0afd47feec635b1f062407f66db4e31b34d6e8f0917a26d42dc8f",
INIT_18 => X"b34267a233f1266a1317d9e9029e08209703758626800616f1aacba58d562a0a",
INIT_19 => X"d6b5ac7cac764644095b3e0fa8d4ed1a1fccaa7966629dfcef47d0a9a452d9c0",
INIT_1A => X"b181835217e9fb925ea72b142117a964f74dc972d5046e6e1083be5c15563bc4",
INIT_1B => X"3cc8bf23dcbc303214617743748aa72a27351dc0372bc8f35f9fc6a2381ba0ad",
INIT_1C => X"139bf3eaf4f2fe60898af2eba0bea5d5d8bcb51c163846db9eb5eae967c338af",
INIT_1D => X"907522d7c8c98968533e1b630f23e8996c6dcc5ead3ac0ac27c7523744c50bdd",
INIT_1E => X"2a146ca3b9616350be5fb692a0b96fefcf40e54a8ec8ed9d08e135df83a66d06",
INIT_1F => X"72a0a98fde8e08b27fa873acbff15f111cb54c020dc4abff6d419510ca8d9a78",
INIT_20 => X"cf8e93b4c8064b904d3d1c1192a9baee48cfa9f55fd4ed3fb5c5956571fc507c",
INIT_21 => X"58837daf9c58c53f6e7039a6e5b62e66559a0b4b2bd41027dd1b9e222db76675",
INIT_22 => X"da26a53b7d154e6ff47fb8d576675d0874872806372fc23b786f4d701fe3078f",
INIT_23 => X"c43f70579a6759914f4e2060b9f4fd78466b65f0ab66cd7b91bfd056d5b51b95",
INIT_24 => X"933235a6f255b2544e477465cdd091434869be5041a2b681432b152a5994e619",
INIT_25 => X"b24c65f3db0c13c43709ef99ada733273c086e9355b8f05a11a4060078104ead",
INIT_26 => X"6f183a449e43eec1094abb693b99817c957fe4d577f4afcc796d6b0c7c92ab2c",
INIT_27 => X"14e29253e7c57d26b356666fed0d12a6885745da4e3eb9f2e8412f8750eea410",
INIT_28 => X"2f26c028f45e348220d779b9ced47d4aabde0e3f300f2bcbc5a0aa27ea8a1d48",
INIT_29 => X"123fcf66661386f67a01af7c92bcf9b062bbd4ca8fa3d29309bd268d04144534",
INIT_2A => X"16bd2f4833f88765e065af5a6aa9eadaab7abb7b7833d8879747c002e009b5da",
INIT_2B => X"f0579f00568d30384972ead0ff61fc0cffdaf5aad0ea88626389c81192cc7b3c",
INIT_2C => X"0746b55ea410ada7b19adc28015e5e37e2c75826887e84c34d27a706ef7c3d1a",
INIT_2D => X"fd0e61f18f3983c1f7496d4c3c1b79aab5a93bf05cb74e14d3812edc7bb432b8",
INIT_2E => X"aac9cc6a2112b89e8cf54f4aef89b9ca1da0555528c8fbc466bf87be116c17ff",
INIT_2F => X"16344368aa57794a4339cebda6748efdeec7ef91117bf997e1f38332ef2fca1f",
INIT_30 => X"e1cf04640b1b7c2746003bf198a4159340c8d6da523d95123985922e07245eec",
INIT_31 => X"7cea9eaa70c84a9690f63b54ba8063a4b4f6cc83ad3a969cef0a7add5a1219e4",
INIT_32 => X"4e204f150b713f5e666897063737cea8f20c4c791b01cc07be645035fe9d4420",
INIT_33 => X"65cb55288de236f649da69d9bc660ae312e277295141c6f5a6085bcd1be90e78",
INIT_34 => X"a9075673c9d0ec2fadb3057ec78bcec1d756ec5d98b8caabf99c515022967b88",
INIT_35 => X"7be1eda8afe0072d10e71608355e35e553a9c4822586032715eb0102e6682180",
INIT_36 => X"9e801426b6b5d4b2ce18b72e75c92cd36760a7be31ad9bed79b9c98375cc16b6",
INIT_37 => X"96cc3fad8c7eca20b19abc0dc35235baf477501fe6a20bbdc7f884a8106df4fa",
INIT_38 => X"2d2e25caa1672ba0bc867a438c6cb05c4b23fbf8b0298f92adab24ba6b10ae1d",
INIT_39 => X"7622a3e2cce4c1492eef724dd880d7a002949448fddc0a35d5a02d35fdfaf96b",
INIT_3A => X"00d0bf25003ed8786d6c12ff83a9def1151d2c2fd4d201c351925d3cd7225da0",
INIT_3B => X"c0d0d6ee4982ce6c5a88e642cd047ea3d444c341b05c1304d64f263ad895d648",
INIT_3C => X"9fa13d50fadb836aad9797c66433acf30dfcf3c87bd07234823d6b6d9997ac55",
INIT_3D => X"454363dbf491482e361639b8aef66fc25032d718aa3a2f2bb9895d55d9922004",
INIT_3E => X"13a0f42035d61e058864de303e9c278c36e693edcfaa2c946e94f71567fc5b25",
INIT_3F => X"f428bacb9c45a95236d821c1cf65cb0ab8b5bcea9794ecfd8938c02c0bcab6bc"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"92919002e09f9d9c9e9796959493929190000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"128400042400b000b2b3b4b5b6b7bebf1184b104bda2e09f9d9c9e9796959493",
INIT_02 => X"4402a0000400840004800034004402a000040084000424005500044400100004",
INIT_03 => X"00048000de004402a0000400840004800011004402a000040084000480001e00",
INIT_04 => X"a000100400840004800000004402a0000400840004800000004402a000040084",
INIT_05 => X"00c00080004000a000600000007284040040000200510002c013800016100004",
INIT_06 => X"00854500606300430284a0008500e0440060630043020000f280004000a000c0",
INIT_07 => X"47a500606300430200e0a4a647a50060630043024747604342a4060500e084a0",
INIT_08 => X"286120202975202029752020286d20002020286d200a6773657269430000a4a6",
INIT_09 => X"696700002061756f207420002061746920642020656f2020656f202028612020",
INIT_0A => X"3e70dc21740e549bcdab5e580525a3310d66c9332e76e71b547ce3f2ba294a51",
INIT_0B => X"f705f1b10fa85c89be757c05d1fbaafbfe02dbec3c323bec5c8f6bea7e3efc41",
INIT_0C => X"1a0b7dba22bb1548e333af1bacaa0911643b795e5a14641c1e1f6448cbca3ae9",
INIT_0D => X"d4084efd154fe4e2b3365c3bb5be55aa21ac6cfa4ebc3d7938984eb51bf8f87f",
INIT_0E => X"f13e86200bf407fb8520304a1cde76ad7fa3afc4e5092d4cf3aca80ebc9a548a",
INIT_0F => X"0825e99b443299fb3a84b3514c6adad0e64978bcbe94f610a0f7d914a39933d9",
INIT_10 => X"e4227c7c668c85178086add357897c44803f5a6587d96466e8d8fad0d2605ee9",
INIT_11 => X"8295f496d177f8e5024512ed6724c735b689ef2d11b8079327ff2fb4bcaf0bda",
INIT_12 => X"d9c9019145d9fe189a228b4cd3ed6a4c286e80c9cfcb37b2cab4a6ac68cdae6c",
INIT_13 => X"b202a4c78cf9327ee9bf9bfe618164ea4f75ce71493e65cd7269627c87152f01",
INIT_14 => X"1a56de708a63c6af2e8ec57dd6e501d5ab9b0dbc030ad49f5b996710f001ec72",
INIT_15 => X"46f36aac1e3b24eb1a1c81a4abc7e513edbcdd6c55614bd2d2e3a116fd0d0121",
INIT_16 => X"fa0d9cf20f864cd5789b5d0d0d03b54d0a60db119ec7f8ba2ac03a1feb0d2647",
INIT_17 => X"0d5a7b4a73d14a1e199cdc80cf2e2821b675764e32315413fbe22a09fd50b5d8",
INIT_18 => X"7fe249202fee3b5533e107a84dffc8165661d280b5c824c402b63db5025bed9c",
INIT_19 => X"b62b67027feebc758a8aa9e52745ae5c25e8964bfef41aa2c8a81841981169e3",
INIT_1A => X"54082f6969181957d691795cca39e48f286874767487e14d11021e5be7abf51b",
INIT_1B => X"4fff76e603e6d067821d689dc7cf9d61637ad3c4f3997d4df347c0844305d175",
INIT_1C => X"41c9e2d08774953db60d3166edea9cb596b2793762325dd19df44e1530cdc60d",
INIT_1D => X"fd90b5c965073d4fab5e8df1d02a43143aaff5f255a36a3516be6b2bbeab01d5",
INIT_1E => X"9ffc9ce11953e3edb495ebad25abcab0114973dca4311da362dce271ab42642b",
INIT_1F => X"bbd466c811c3ef264d640e1a85df5a1a7c6811d31e052e9b9a2315cceade9f23",
INIT_20 => X"a3274670abe96413b7ae4d13ffdbf431871b60c4d36890796b3fb107885ae7fd",
INIT_21 => X"e4a13d63038cfd8ec5215bb374897538c423fd4510028e7967ff7a92f814e33b",
INIT_22 => X"dcd2df707e26ec7e12d6f8b0b7c5bc7506e2378ca34e8845446a2d894cc725a8",
INIT_23 => X"27d35db05bd7f2d30e9dc6dbb5b29ac3f3b34edaef8ca517105a6b1f24a18410",
INIT_24 => X"6a74778d3c6579a3d3fc6f2dcc33cdf1898a081fdbf41b5221e991cf4c80fac8",
INIT_25 => X"2c7b853695213ed6f72cc6dc2fc9f65f51b8be784019f7564bbb9500bb51d685",
INIT_26 => X"c0db2c3a8d85e57e9569e0efe2b4085f6c441116e8ec2d2d2f68488090d38cfd",
INIT_27 => X"579deaf914148c82e206aa901f4ebd6d92e6e47d202b5200796aa87979616c91",
INIT_28 => X"6ed65dfcc386eabf51fc9a0e6e14414944fbde9d930590edcc60d5c0914ad87c",
INIT_29 => X"88b76f1bfe790a9d5e221e4fd45867c285d8a590dab22c314aa8fe65a681b2bd",
INIT_2A => X"7658642225ff527c967fc06798d6c44d8714d557b0c7b52dd9c9446442febd2c",
INIT_2B => X"fd93b810a1698fb38c1d3ed9d7f395ee795e3e7b0ee65bb9919bd8664141f130",
INIT_2C => X"d8f975794a5ecf86390f9d9a14108b68d662d9c2795a422b2cf6b738e869b19b",
INIT_2D => X"e4ca4a2a61834fff4887759d4c3ea904c2f3c8663374f8b55d9201142bd734d3",
INIT_2E => X"116f8e1a4f0e87780f951e58f012bd8f737a1eda24d64fb705db2e429362a902",
INIT_2F => X"df479b84b091d86d229a2218368deea2bb9ec34d0f149017e2c8aa00861ef01e",
INIT_30 => X"7f035e9c3e69032152532e5ebb110220887073577fcc330f0d433bc11c41a902",
INIT_31 => X"3022294b6e60a9ee3a4f114ebc4f281c8ae61a63a1727478ed65a037fca18518",
INIT_32 => X"926c0c050312ca78b99f777c6a003a244d659cec8820f5652ba77d14987cfbc2",
INIT_33 => X"b49992da9d20620d5c04f243ce4c60147f1cb583b645e0a628d03e83b69f31a2",
INIT_34 => X"697a259f5e184dbde6f68903950f55fd80843439df634a1be9eb823bde2a60c2",
INIT_35 => X"31b7b04a2de05af20d4cfe979e704cb89c3090aa65cebafb53dce34ce0f19f86",
INIT_36 => X"bce7664f5f6cb347d2bd55d84697725ac7f2aba1f6e6b68acc03b539b4aa1888",
INIT_37 => X"16241d2277a2ff5882ca8d65e5c32663f27378cadee860648ceb09867555450e",
INIT_38 => X"ed66ba4a0c9f2a1701a4feb3080b7ff4a72ea1fb01e993f20dfa8c1453d73f47",
INIT_39 => X"e0c14984a848ebb616e08f089f63256f0e8a164d6f549335fe7ba0c4723e2647",
INIT_3A => X"61bbc307c54e3150be1affa0b3a5e2714b678b5ac6f8f4e7b33428bc179ddd8c",
INIT_3B => X"e8db6ce27577f153a361587541acfa2784e8829c170d8721e4efb1c93e3d3a36",
INIT_3C => X"39e36732b97e27edd42704b39971b7ec64ac21874f751ac47c67f599d11b66af",
INIT_3D => X"1630e104771184e592f3997d917259ea29bec0768cb0e309129447ff107ad895",
INIT_3E => X"2ea008381b1d44384851fff9ee397fbda8f5375d096faf70da3568e9f0d97f0c",
INIT_3F => X"1677c392c36e4fcf7926f227532fc01e58d6435a1ddeec854c0d4539341df4d8"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000ff18004400450004008400",
INIT_01 => X"0004000004000000000000000000000000040000ff0000000000000000000000",
INIT_02 => X"0000200000000400002000040000002000000004000004000400000400300030",
INIT_03 => X"0000200004000000200000000400002000000000002000000004000020000000",
INIT_04 => X"2000000000040000200000000000200000000400002000000000002000000004",
INIT_05 => X"0020002000200020002000000000040000ff000000ff0000b800200000300000",
INIT_06 => X"00000000ff000000200000000010000000ff0000002000000020002000200020",
INIT_07 => X"00ff00ff00000020000010ff00ff00ff00000020000000000010ff00100000ff",
INIT_08 => X"296c6928206c6f28206c692829706f003d2829706900007420666e49000010ff",
INIT_09 => X"4823000020747475616977002074206e6169722872756f2872756928296c6f28",
INIT_0A => X"d4ddf0bd861d869ee08ca85aa389d9e4d75d07d7722543e92762e11ed77c585c",
INIT_0B => X"bf5d5035403c26e9a80fc7c13fa5c326bb48a41b8fcc067c4ea4774a2a5f23f8",
INIT_0C => X"011ea557010101d4c5e77021115b597006df2f23827bfdee9e5d96027f700aea",
INIT_0D => X"1b2cb5b531ff0afcc9502909e3ecaa59fad4fd4b826e1a5ce8f6d32a773470bd",
INIT_0E => X"5d4aaca8283b23ec85e88ad33dde6e64d44d8222e843c29dab5af0ae1de8131a",
INIT_0F => X"8d8ec346ea6f163ae48b6bcf51b39ecd7eefa285c104b127d5945a67d258fb68",
INIT_10 => X"bcfc32971d53767f0872ef60ed67dfe213b42828aeabaf4abc37d07e8a9d81bb",
INIT_11 => X"8f4e09a71b6558d56886e761805e2213b006bbd38ed76fbf3bc3fe0b270660da",
INIT_12 => X"beaa01a95d8fdba535edbc257c3c1820c225de1162881fc4489d837c92fd7cca",
INIT_13 => X"006374237579d58cfe5da5e253eb312c9dec9828251f8ef405ba6966fa81e804",
INIT_14 => X"1a3cad683685e6745396a27ad7a52836d60c02e186cf5e6bfe26df4fd65f3d98",
INIT_15 => X"f396b95db6461344b7cafc5abd3453bf4a7e629b4e842c6130745c9832410997",
INIT_16 => X"807f9039de350d485ba4e70e02bc5c104e77d762b99c91912684f5305acb5858",
INIT_17 => X"a8ae2dad2fe087cc5c563fc892d0825cf6baffe64b14527d3f2534652f936b85",
INIT_18 => X"62fea5a9784ceb192eca94cd449576c20d99ee5548d8f7a07e4a94538bdcfa86",
INIT_19 => X"cfcb4857f0ada7a6582e57787d926cf88d5ebcce05d0ee16b1e3c17d3bdb5fbc",
INIT_1A => X"e57a9fe05bd096cd153b97df73bfbb3311a02781801be556c7c7b75466e498c4",
INIT_1B => X"f3e659f97d685edd54d7e23b2ddf45c8e2cf41bb7edfdc5b31254a632fc2c45b",
INIT_1C => X"71cca7aa0e1498d06590a18ba70c99116bf1e5d55c2298cfe8fe4ade07ad39e3",
INIT_1D => X"0e8e45952736a214ea422b625a2d5e774be0faa125b49e2527dcc136b1ab9cb8",
INIT_1E => X"043be49eacf219abfdbf74d699f3953c4676c0b19fb566914a891d9f0a7d2979",
INIT_1F => X"b1c5452a9116762aa8e0ed54022a9eb72d761779676460d192537081203a319a",
INIT_20 => X"7cdb8372fcab643b7dd1d6280e2cea994c1c960964cbcebe77140de4a8106ed2",
INIT_21 => X"e9d349a8a3f1137f9716c283d95c1dbc0fdbd9be88d92e28acec604ac8f91f8a",
INIT_22 => X"2f19c3a51b869eb6bb3145c3d87dec7b17818ab4de5e933eaebbe0588aec4687",
INIT_23 => X"b8b7c3ff5805f81cc9b1208a4ad22e6200401751a14b90df2ec4d58e8b92fc38",
INIT_24 => X"767e10b0a5f4f704c9b791e3fbebd82f83828fb2fa50e99dbd64797af5a00ec1",
INIT_25 => X"73a1fb4a9f687c2863013eb3a7ac378bb602c58a5ee3afc3f95547ed751c7d25",
INIT_26 => X"95cfc3821866b6b81635d7a7a6fd0f40ac9621dde88ad88c32a3156c2c58d4e6",
INIT_27 => X"891bab2c9fcb646d484fb01c9463942c68b5f388825735d70239d10c58e0aaf0",
INIT_28 => X"716b07039e65914ba33f5979fb67d4c9272322c362129143c65e7d51f90a5527",
INIT_29 => X"f031213bde159a4c94b839b949fec5a8f004f150ccc6f13e4047657ecd1408ac",
INIT_2A => X"97dac2ee740099b9ec47a22aaccbe46154cebb48993f9a1d3e3a038f8648960b",
INIT_2B => X"649fda4b370023d1d44d5ac8738ed97b160b67ff33bb5beaefa9764226e6e601",
INIT_2C => X"7e9825fd373625355d2950a8644eb320e1497e287eda507d60f178da4d3d7ced",
INIT_2D => X"b8179bcb29df79465e40ce6af7f45ee76243371115f3258129df7657dd331666",
INIT_2E => X"93ea0a7667e06787bab50a7747cb36359f536489ba8afee9817e077fb8531a77",
INIT_2F => X"3132309ae88ac53cd0b0b029a67e2cb9e6995adde51aa99a920f273e79baa863",
INIT_30 => X"62442de1f5ce64db1274762ad21cb79fb4ed0e96a63f69b2cfd568d5e10460a5",
INIT_31 => X"8e52a13c4bf8d126922a5e355dbeb6cedaad52b29fa1b76b31c0dd9603b288f6",
INIT_32 => X"c8412157ea5b5f3370556b876ccc45372dc864b9ab3dcf08fbe02b39f1ffa1df",
INIT_33 => X"ae680a050b883710cf10e2183326cc205ac649a056d166e567c136b3f045af1c",
INIT_34 => X"c92dcab52d85e8785fff1a19dbf15852df5128eee1578d30929a2a8c6f38ef70",
INIT_35 => X"c7415173632cb4130f2cf437601c4e75296d8a7bfacdf8011bafb6ece6e90b77",
INIT_36 => X"547c875e7406606a0631e73e4ca2a07d1722a01f564ace81e6d96a8cd54b14b0",
INIT_37 => X"863424dc9eb1c3bc58840647fb4527e971efa0fbc9c1729cab52c1c79c69c3cb",
INIT_38 => X"8b71ed9c60dbca4b1928efb0261b6df94091c5efd71c1178ccd654271e7270cb",
INIT_39 => X"c3a577602cbf26382548ed06b6d49afbffc27623a6ab9c0140e9bc783d85d7de",
INIT_3A => X"c2d5422d6dac4b6f306491e0e6b51473bda35278b5cea813db8b2c496f36204e",
INIT_3B => X"74aa330cc47fc86e8cbd92f33f5738aa8dc3126f811442afc894a6eb9459f1df",
INIT_3C => X"954a4ceda4fe3b1fcb1904d0a1468bb952b49951bfbbb751a9c6f580d9795a3f",
INIT_3D => X"06b40dcca9f3696641f2420b4c4855713776bae78a2a063cf40bed705985384b",
INIT_3E => X"2d2a07c8c3edafb4f84dc536b28f89920cd83032852125b7c32d2ca1b50a1bb4",
INIT_3F => X"327381592f40e723d5abf98f91d6d46f72cf8a8bb522d3a73d4890eafbf5593a"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"08040000082c2824201c1814100c0804000e002b04fd2a00e8000000f400f001",
INIT_01 => X"002cd30028d310d3181c2024282c303400101400c800082c2824201c1814100c",
INIT_02 => X"002021d320e454d30021d328e4001021d310e444d30028d33ce4003cd300e400",
INIT_03 => X"d30021d3d4e4004021d340e474d30021d301e4003021d330e464d30021d300e4",
INIT_04 => X"21d37070e4a4d30021d300e4006021d360e494d30021d300e4005021d350e484",
INIT_05 => X"e421d321d321e421d321e400d300b40000f9000000fd0040218021d39000e400",
INIT_06 => X"00000000fb02002000010c000021080000fb0200200000a80021d321e421d321",
INIT_07 => X"00fc00fb02002000000806f200fc00fb0200200030570e0a0f06fc1c210801f6",
INIT_08 => X"20695f00206c5f00206c5f0020745f00200020745f0000697461746500f606e6",
INIT_09 => X"73c60000286120746e6e7200286120706e6e6500286e5f00286e5f0020695f00",
INIT_0A => X"a1e9873d418211b4c6b2d4e9175d5a58b7329a9f635a8de8f8c246fbabcdecff",
INIT_0B => X"00efb3eb9599bbf961d8943ce6293afa431a5c1854affbb02a3896dc970167e1",
INIT_0C => X"1ce1f59b196f5c4750cd3b10f2d4dc9e2470634bc573c57ba823bd47d00be5a1",
INIT_0D => X"b270a98249329ef0af94d3047370a21a2b8605cb775f344de032e8ca13a42923",
INIT_0E => X"ec05c3bab9ec04b26c23f6c4ec3247d42d84cd3306429bd78e5b4418d50a4829",
INIT_0F => X"f5cfe5bcee579031945348257e7e691a2369fa44b40105a8f25e34d3e350b767",
INIT_10 => X"66fcbbc0f10cf1e4ec95ac51594ea5de29628a7075a89882d4355485b2aa53e2",
INIT_11 => X"caaa1fc1a5099d0ad839ec96d883e4c163d44f8d346d1fac16af3a6983626361",
INIT_12 => X"152affc6a3cde4d1d456007999d219d7da035ec361082ac299a8f27aba169049",
INIT_13 => X"edf43c5b6a7cbd4e8c0d67c3fdebff7e76a73a4bcfaba67181fc9e136102ee43",
INIT_14 => X"2b890c971fc9b9022d21163ef6f2d6980ebfbea7d161988e1750cf8b004df316",
INIT_15 => X"065868fba8794c66ee53884ddde220efdef7c233d1d5359892cfa4c28bd8071b",
INIT_16 => X"5aa753eb98ea9c705687cd4722a05b31a72204087316f64eab543b6cb2d20e2b",
INIT_17 => X"7b31c0e91f7c4f6db0d762f93725716b4d715bce23639a47b7a3a55a5dc2dbb0",
INIT_18 => X"f8a081026ef01d57a6095e8ab5ca7143fde0db301297954cd45752dedbbcca36",
INIT_19 => X"878cea1539ba6aa42c718d3f86466d8fcb152d4815499004fd4b229fb9b6e347",
INIT_1A => X"9757d1dd8e8ddfb7de8a5ee894cc3a1d832aa1db8a603bcd77a8e590901c6164",
INIT_1B => X"60d960d7aac401006b5be48753e06634ef28cc2202e6650c9e9615bc619bae39",
INIT_1C => X"7e788200abf76f13decf5a3cffcd835cbfc836d81860b76e5cd132996a8ddded",
INIT_1D => X"a5ef785afa92f21593a3af3c5501bf3b8436bb3773f2a9abfb2238ef11efbfde",
INIT_1E => X"acad2b8c2f871ed1384d89081c75f27674706c5afa82aa9f2b8dcf3833355540",
INIT_1F => X"eee23023960d2b7b00a83d9aac44f91b8bb1cfbae647ef7d10ca62d58cc4ce69",
INIT_20 => X"58cd8b0bad377b4727b952b0e27d8b6e181b983930a13c5a65fe6b96746cdc15",
INIT_21 => X"d9018600d10d90539ac2b2ef1b6d4ca75ea06c56723962cb1232404628e21697",
INIT_22 => X"47e552b6b28fcd9a1b3d1ae44e083c2b8a1c2de0b18bd141f8f2aaa77a9a3159",
INIT_23 => X"965163a9b1e15fb3b4d63520d1be6477c42aaccefc243dfcd87df51d513bd698",
INIT_24 => X"65011744845498ee4f90165d031a7184522ff339a4762a13bc9f6c135baf7bc1",
INIT_25 => X"dbd6ee53997eefee831198c4c9b1b1273d28ecb7a633bbc45f68fc2b7ea2b837",
INIT_26 => X"3a997e9e9bcd6ac29610572a349932f8413d916d22c24e6e3e3fac56b0bbc722",
INIT_27 => X"0a7ddff892acae350624fac8c736ceff77a4584d66df855ee83ee35a514f45c8",
INIT_28 => X"1fa1f7a1237ec4e1e9676e44d4d2931c77353a7efea40158e2b8c63cdbf8ca14",
INIT_29 => X"79f4f3a309e44f8a5368f7d2bd0e443795136637aeefb734674f61419021d2af",
INIT_2A => X"a5eb36fa5602434bac9930dc3a064b45405d0e1fe2b3a6e366a286604d9184f0",
INIT_2B => X"81316edfe49e99e8d7cf74af59d72f6a8eb4d3720881b8e3186ee502a889073a",
INIT_2C => X"624bdb232048e07b3aca90cb4873d287fdd655316ae394bca943552642888e92",
INIT_2D => X"ce0c1d2aea8274403cd32f4d52d4dbf6c6a060a8ed43132c183a23c87148e363",
INIT_2E => X"ff01946de9ab4f5e4c24341f5550f11d7c02a56e00b03a54db76c908fff5408d",
INIT_2F => X"e9562273dee782b2b204e1e18d74c0acbdd4bc9d2edf266941b995a476e131ce",
INIT_30 => X"23e60cb1c082ed85623ba1f6d21f613173529e1a50e3a0e5b15d5b3f5ae08fcd",
INIT_31 => X"3eb33188c34b60aec8feb35c8624bd0ffe9a66000eb2e1f086f38a2aff402982",
INIT_32 => X"90596a9ffe5398ae05a323e814d2a04828cc0eb26b63c5d595b763a9cab71258",
INIT_33 => X"ad12f652a318523daa1a140ccf16b3b0be47efc24ae3b8f248f7232d1b9ba2cc",
INIT_34 => X"77a52392522d20311172ee174a3327e146e8d3723de73c4bf8de3fd06e2e0e14",
INIT_35 => X"6f4c7abd8bc0c0c847517382bc2da93bb6f9258a6d1813a19aca426af53496be",
INIT_36 => X"412e410a0ea92e884821dcfbd02604e07adc58a631e46b26f6c285b241b7f87d",
INIT_37 => X"870f95f06cdd40e32e1950ef499bb8378134b14537bfd03f32db44ca2d8ba52e",
INIT_38 => X"5a6178ae9a2b0094960bae951fd2cce675b81f1e0c0b940c530fdee13c250a3c",
INIT_39 => X"30570ebe965a0aa9168d833f2797ad34d203b3299e9fd52892a16870f22f536c",
INIT_3A => X"2c0e6e50a8f748b201b2d4db62f90e28f36b1b0f7c9c309eea3e9da6a57def05",
INIT_3B => X"02f0caf71408602b823d64f2753864bf1ee358da144c6f163f6fe33dddeddc43",
INIT_3C => X"d0cbdeda057662eeeb801a8e0a8908ca5b0962bb578f3b6dba99fa2a91a75ce3",
INIT_3D => X"1b0ac33787119575fdab11d87269640153f959f3e29c8739811b27142d7106f1",
INIT_3E => X"5db02d527a4da7f7c2d92e5622709728014d8dea7426825e1afbdd8957117e70",
INIT_3F => X"961b6806c86cad66ac3f349868f43c4cae71fa251608a390458e8a3317e211ad"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"dbd11e5c48496182ebc5b24cec0e78fe314e4ad620fde0ab13a65165d89606e2",
INIT_01 => X"2e71cac237369e89e2229c5a72b891dd0271af6102a88599c583e28f0ba46488",
INIT_02 => X"8b7aedd2ef62afc04ebb3461b0e25f9dcd42ae0cacb6eede76319398325cd132",
INIT_03 => X"7cc95d359b2badf79f538db123c30dc7ee76515bcd68cdfb5d977007b77d115a",
INIT_04 => X"beaf0d0dbfdd9edaedc5cd50925e0e418eb239330857aa562f52498dda4fd64c",
INIT_05 => X"86bc0cf436a2abfb9b6dba922b142a6e7ec8e3dd1d16232fd117aaf04db58201",
INIT_06 => X"6d95ebf2099c247375040da59ffda2ba31788249e0d1f8be5dea6451a429508a",
INIT_07 => X"4bed80bf368af7b34b805112f49d30a296f625b0eec81a6d9e638bd7ea56349e",
INIT_08 => X"58e6bd1f1be376c8e34cf8c4c57b8b87742bc0f6944964cf6c351dfef39689e0",
INIT_09 => X"e5a830c53ea9f3e4d97534114e80d1c4a5f888500a1d5a4d9c80213323628a2e",
INIT_0A => X"228e3110a62ee0e4a27ed83c06bb929d4306012dff7e265c8c404e533aac9405",
INIT_0B => X"5028fb55dd99c1f2bc45b9302c962beca4d714e931ed9ba62b533bd21681754c",
INIT_0C => X"b0c276787856372d2092dd79f26b4a48393e7cfba2fb2c85475a7116babd82ba",
INIT_0D => X"a8ce162c7818f3b83f2c5d5c74fcccfdea87531e6123b0b8115a4b6759fe0f6c",
INIT_0E => X"3cda0bbebe3d52e04d82cc46e8a233579b4139ff2a58bbdc0f27adfe5a9ac9fa",
INIT_0F => X"96d87e1a7d13051b30b3c55eff01f1bbd4370fc88451120a81f8b3a04ffe220b",
INIT_10 => X"8fc466e25174a234f3ab4ce57d97468cfab16e8ce00081f171f87e00edc94e49",
INIT_11 => X"2242be95a63ed7a352f62c59663e5b6c7272065eab8f4c366ae2ce21d809a6a9",
INIT_12 => X"0a796bb79f7cd08dcf1ef0d43b7ad77dc803dbd6143e833ae2ab47c0e8b2254a",
INIT_13 => X"506fc622592eeb7da641f3e3880845717f85850fe512f4165c9af5e6d6a12622",
INIT_14 => X"bbc63f363ff4ef7a33176668492fad02becc1b6dc0503354942613fae3b2f4eb",
INIT_15 => X"1b438429852523c08217802f021fb2a6db20814be247b28ba86cf1240bfa7db1",
INIT_16 => X"0ed43a4407c37812223877d5095f1ac24788d819a4658d0c3bc656801d8b8ab8",
INIT_17 => X"174203c653cc064f31fd41a23a6e05a69cfe7031425f49a2cbbed04d925fe453",
INIT_18 => X"4e91fb871c5b250ed98f5f59eef582e2dad3aeae2f249764d498b8354ab4ef20",
INIT_19 => X"4bd51cd4858ca7c240e555863888a2a1846a807f989d97332355e99fc29f0aa1",
INIT_1A => X"b24aff37e76e4b2345205a2472500f44a9250b5d67f8d1cf10afb612df53b730",
INIT_1B => X"de283effaab979cf4dfbdd2361384eda77ea659d42d1c107d383aac2bdb12709",
INIT_1C => X"c8c68faab2e48a4f2c0fdf31baeb45256c641a4070318661fb1503fc87388e54",
INIT_1D => X"f17c3069b0c45d756a1167143dd4a25785c881d33ec75333418353c2c9da4af6",
INIT_1E => X"d1bf781d4fce8b9eb51dea3e5930f645e717bf963024b4d52a00acd4efff0585",
INIT_1F => X"6df4186f7ed3f860bb93631586f423eb075852427f00e44bb8832ba983ae494d",
INIT_20 => X"ccc32598bb092c2103d7de9e50e436cb6861cd93299543402582e6b301377a70",
INIT_21 => X"2fbb8783b0ea8affdff9bf1e03b464ee3f9c1fece98ca74309cff919ed3b9271",
INIT_22 => X"eb2bb3819d97c203892362425dc04d721669afb01c0b2e5a0ba3f3d31ae6d397",
INIT_23 => X"c8750545e82dbe9cb9125204f7e890749f6751d6e9e4eb0944d8c8a308a0f5b3",
INIT_24 => X"5f6e6207233b3b42e6abb51b4b316b62390e40d8634db631e797d3b8aef2003a",
INIT_25 => X"6422b286a00817b1ba6d44f420765f3bdd84119d86f314361841b291f0e526d4",
INIT_26 => X"756b74716d97d571df404fc40cfb58f4ddb7cc5d743a0bc685b53c7313127e94",
INIT_27 => X"08e9e931f579213b56065e6b39a6eb01cd94be02cd245a41033c76bc183965ae",
INIT_28 => X"0c4185cc6ba5d05b0e2e7b6abe552562cfaa66fb096f50145eb40c0ff2f826ea",
INIT_29 => X"b15a22a27d5e0b68ece1a4d628634e27a762e8c188a38342fa5dd489064bfe4a",
INIT_2A => X"6a577faed46c19b0fd44638e9a4b691a3826685c39c178ba20035f1bc054f46f",
INIT_2B => X"2c38284b806c3d8a55ac01a771d514e67bfda6b2c723a092b87f1e7397fee0e5",
INIT_2C => X"fbc5f5400b4df45aaa7c3b6fb28532330e5dc6b891331106f0d8b9041dec02ff",
INIT_2D => X"7200028ae693b8439a34e12321f69ab812e88f54eeb1769b368e3437267d1815",
INIT_2E => X"ac4cefa94b0e122ffee2a40103a65845a9e1c7f0cac8944e695da16463cded40",
INIT_2F => X"a2934be1dfcb709809fac4b3b9464d35f8488319c04fbbb36093214ee0c1a52f",
INIT_30 => X"ad19ea7d2384020657699d702efc313cc527a969979d26e6fca71952bd1ebfe1",
INIT_31 => X"ed3669444aa61cd2ba400e413a56a02cc4399f549e7d642ce0b9572781ceb134",
INIT_32 => X"3935b09363e059c16326f5a2915fa1ed660072cc68af99c6d777ed2b79b05ea5",
INIT_33 => X"2f6dc885e4aa9650d2912d00c9637f3b4d6627f39f00b912e588b2d1c5f5c2dc",
INIT_34 => X"d64460a6f1d08f2dab29f05e5923b470a7059191271fa0dd53fd7e1ebef4d925",
INIT_35 => X"5901383e03d81bdab3ec5345cf937c750649130de1c199af7b20b84becfd1988",
INIT_36 => X"10751f6ac90fdac53428146f9da376d8ff23a987abe26beccaf5eb42d23fea5f",
INIT_37 => X"7723acb0cdd44f0f214ba14ecc5f14baf55f2231202af47ac986a58c92d06608",
INIT_38 => X"a2e6f931ff19b15e0bbe9d4def02163b60b9385e69789f8fb85756a84b326afe",
INIT_39 => X"845d6607491d60e027bc8f3c9648f91339abb831569bfbc5cfc60dc4d21a8f26",
INIT_3A => X"9eb515a35c0bbbf5adf56571bcf764ec2448ea56402f0ad417ad89d8be499e6a",
INIT_3B => X"735a55c5fcd79cb8f959ccb63d25c980bbd8df648950c01c98a6b6d8c425d7fc",
INIT_3C => X"a57867efb3e651647656c5cda1067457c709a893a444b99181f7ddb3c6c980a2",
INIT_3D => X"d3683b50c0fb09a0a003abb1ba2f7b41ab868063f098538f5144e9123855f177",
INIT_3E => X"1ed1871e4024ac806f310c8e39cbf6828fbd5e7d9b377a4035a0ab9ff6034084",
INIT_3F => X"be061cdad4429397b83db65f4e9518bda97e8984df8ea4189a6cbff81d01d8e7"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0856ba6bb5552f8c37b51d08ef7b1832841a45773c4bad06903026bdfecad267",
INIT_01 => X"dfa502ee8c5dcaf2b94ecc05280154b106ae8827b4977793fb14778a4a378695",
INIT_02 => X"1ee69df8f2537a046364cd05c872f41dcdc80ad2be8032dc36b6f10622d23e95",
INIT_03 => X"e7f663a9cf28553fbe3f91550a43c4b4946384aa5bccbbe11a32e8756228f377",
INIT_04 => X"4ef1be5bc97e374aab432bff29e17a32c63aa025e0eb01e6e5b6ad8579d1887e",
INIT_05 => X"c99e8898a98304890ef22a176397b6ea1f2ed309ebe2d6ca945671281bbd27d3",
INIT_06 => X"6e6d3171d20138271225f62d6b337ab16f076949d80923c8162dd668445130ed",
INIT_07 => X"60c1a6f72c4b4169a654715ce4b1486903941377c2296976df112fcd0fa62140",
INIT_08 => X"56ba46ca2a3208098bbb289e7e702e2116de17298e95bd8150c2cb32ff003bcf",
INIT_09 => X"58b1cb3fc129d443f098c427aa8080a809b5cd7412590785bb5fb1c4bfb2fcad",
INIT_0A => X"a6907ba17da3ebec59643b4de6304a8e1e155d137529c4ae6ee4c7b99f18b3da",
INIT_0B => X"10eeb7275fa05a854c18f98c0de3460b723e74c3291c6bcfd06a595985dac56c",
INIT_0C => X"151c9b959272830d3d8f0f2ff6523524868fbc9dad2f6baa5244a6528023df61",
INIT_0D => X"a0f7638d4317e082185f3b30dd7826ae74c64f1809953687e2eda21a7dff8787",
INIT_0E => X"253bcc125b88e551a39186b40ac7bd0643a09fa665bed11ef536b7b0dd6a53d2",
INIT_0F => X"0ef5a0d9692c367a444516286a87dabb19c7b39cebee4634bfe51c7ee47db2a6",
INIT_10 => X"bb4021425e5f5fa537d93fc3d9488a610cfa6a66a1efdfad98fdded911a7e984",
INIT_11 => X"fbe44c903206c2f9ef0063060114b07ce5247b02d6fbdcb19ba2643b8be1ab22",
INIT_12 => X"3e9bc8c2b43db5c4240c581ff212731d97dd755360307351d486952324e7bdc1",
INIT_13 => X"a3b1496fdb7d794454aa4f8c6cd63bbb6bbfcc18976a3ac8a0820d36fc49bcb4",
INIT_14 => X"e6de90c303fb2e98408a3601d4de331d8fa39c72a6fdf09374fdb057bf1571dc",
INIT_15 => X"59cf40133498bc100fca854d73edb15abe935ae5e330437b2e140b87330c2d20",
INIT_16 => X"03552c77b32a10c9497bed2e312212079151a49913ebd6fe90859d804bee8fe9",
INIT_17 => X"0fbfe90448617fdd93da40abe72176d24b96b999ac7a8dbd460f5552a47352de",
INIT_18 => X"f06370b9e954a6b844d262083494f94aff32b5ae151664b96b2f05fa679fd7d2",
INIT_19 => X"2363ba83a10a7760e437f4fddf18cc42b6ad68a6cdc41e7663978a05674a9645",
INIT_1A => X"ea913c25d1faba19d077e6f227bb17e17883ce6f581ac49c5e3fb67af32432be",
INIT_1B => X"3f7f44125346e787eac5c0e096515e8c3ae7a136f7d3c59406782f7c4e0c785e",
INIT_1C => X"2b4c24b42ea6b054e33030b2406a55cc8ba3efffe0e4b71c1ed583004e4aa430",
INIT_1D => X"de6d910a4a2998b5793ca5bca01023a772fafc0d26f0c1dbb0345c32b4232edf",
INIT_1E => X"62c3be637b97a024b305ed1a81bb86145e2d35dd99264d38cff2857bf7d8dea4",
INIT_1F => X"73db40cbc062738c225bcd168e3094a727275c8d4c6862408ff48c4c4a66c359",
INIT_20 => X"408123a3cb39673823ac63457e947a9ce5a52187fe64aaac3029063afee69052",
INIT_21 => X"1fde04a8e3bce15d99f7abb105bd8c5801fd5d63d271acd8a5d8e7a1e0349f7d",
INIT_22 => X"5787df85afe368e8294a104f0baf1f2823165c0f0c0feb317bbe53b5c219c3a6",
INIT_23 => X"ebfed0b071e642f6497a5132e7542ae868a91b31c7fb77f21e97b459fc58f0e9",
INIT_24 => X"12ae40f3f7c9a98ddc4428398e58bfe62146e63c3ddd3e3f915636ab943b2792",
INIT_25 => X"365f54e235423c868fab3f34f3ec016ff4548bb2b35edee4cfe7ee070525b5aa",
INIT_26 => X"655c73b5b917db9cd1827e0fd5652e24ac5fb67ec29d888b711e8e37d13e63f1",
INIT_27 => X"043fd962fc489ffdab91cbd71e11fbe8763aee9aa82572fbab9cd01c2f93e22e",
INIT_28 => X"a35408d8ed692f24db6fea8dddf9f4b49691b13067b3483ccd2873b0e729a2a9",
INIT_29 => X"f9a2f96a935bf6d13c2545e0e1ad0270025c36a5b6f518b42e1cb4147972e6d6",
INIT_2A => X"d33f0283ca5d0a4682e57b980180ac32b6353e01400da4e56a0c536b5377f4e5",
INIT_2B => X"1e42a7050b33c19cd99a4f369e8520054cdbb29a2175c765212ebd72cd801c62",
INIT_2C => X"3178e81c8785f07bea3afa1bd3d319459adde910420348415f99c7c6d92bcd5b",
INIT_2D => X"365b5fed15aa7b0ed6a178029d065807d5af8a9e4575a62a52ac0d9c583d2fea",
INIT_2E => X"e0507f15da504ac1d01a907a641340e428c91f6a3596b5435b24f0eee03ea738",
INIT_2F => X"a243a66ad76e781e54c9c586458be04778e045f4b9521faf87065a0f8a425776",
INIT_30 => X"f081f947b0627082207199b41de2c5bc775d97aa98e2b5c8382600f715ed13ee",
INIT_31 => X"6f8dc699394797658b0b5cc9aca8c5d7bdee32fe84460615cc201f21b590e7fa",
INIT_32 => X"46de4b76eb179b0f7f599bdc0c094ce5c55441d30a212f7d6e1e61439aafcc28",
INIT_33 => X"fc345ba6e9955ceef3494fad2952255b95da82f47f42db7e029b50d2f67958a1",
INIT_34 => X"c0375f204a559b03421b7668c01f70962e61786a145015f518f53407543e63de",
INIT_35 => X"6891659cf594693bca6a9cf4b1d5b45fd1566ecd6acdc0548169bb5664f5a21f",
INIT_36 => X"f0b36d699dda61709315ee8c3cbd98dc836e5701d1c8a9db8c668763ab3644aa",
INIT_37 => X"6cdcef5bf0cc500ce14358741bfd5af67b2c7e38ce3da719a9fe4aa396cca2b8",
INIT_38 => X"9082d3a7038e0c5af1359be31b293f3be3300934d527d605b7809c1726b69589",
INIT_39 => X"0e17f5c4c78ee85cc6f269600a2d94bfb30d607284e26234f3867b839834af2e",
INIT_3A => X"155a4baa8ec2903968fb6aae0cc4730f26305f3892c8490373ae145ae9cec90b",
INIT_3B => X"1e3a45b4db67daef4c0482fcbba00b420684a542c721c60a6e8bf07343e54761",
INIT_3C => X"c60f1735e5ab1aff54fdebe7b8d2cdcdcffc86196b99be5b1cbffc0a4c77a498",
INIT_3D => X"ea967971fe9f37c5904ae59681cc9742d10fe9e5118294a1e3fd3a8e0aac215a",
INIT_3E => X"989a96855bfbc079c31cd1ddf180311671eaaa0226b81c0238104d036322c63d",
INIT_3F => X"c3d64fba616098ea720284bcea3764507464ee2ac6f9c9cd531e2a18435ee840"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"cf50aa921f817fcb70c5f23e74519438303efedac87df0bcf8873dfa57d647bf",
INIT_01 => X"4fcc34e797a13268bb62dd54479c8166fa8a322105cee22705cd55bdf0519753",
INIT_02 => X"18bb159d6f5c763c9aab92447a92f99f75dc7e7679251515bb76baceb643eac0",
INIT_03 => X"914baced867a606d4fea4893cac54400d0dcd6ba3bbd5e0c57bfc2ecdec23ceb",
INIT_04 => X"f19cbff910a732971cfda3dbece89165feb6fd668d4582dd49e9e06801f90f8a",
INIT_05 => X"2b8abc1a7fc812be9d8ba9d504772400caa28c2b24e30d6ff198b51a061460cc",
INIT_06 => X"501c6a8ce505446dc26b8f044e46e481020905edc52e6108e5ffbf5ebb7b9fb1",
INIT_07 => X"9016b65b3ae67b66edf07580751af9ca949245d9ba2409c3d600dbf8fbd39b0f",
INIT_08 => X"6d314bdbd90a11481c64fae3797f1dfd0c0be315099a5963e9697e45a87e7e7b",
INIT_09 => X"6dd5bdc7f9fd0133c3d19170b4f5273027e137c73d7530124805801b2750aae3",
INIT_0A => X"2c7416a75be063c9db647d550ecc49d70be6d530436505802528c96fbde386b6",
INIT_0B => X"14a02cf183f2df57ebe5836769416d1a23377862fd41d50c38dd50eebe7c07b4",
INIT_0C => X"0ab0b7f552da284c1824d364810405bcf8cc249e50091f084c2d5b74edae517b",
INIT_0D => X"cc00b4cb3654dcefe46fb7c06325fcf9f403e0d79c280e49876bf9367802d7fa",
INIT_0E => X"31a7fff73d7d39095edc6d95a18ef1643ce2ce408534f403dfec2bb8f63ef774",
INIT_0F => X"9452528ddb8a6d42bd4657b2a241baf6434ba29010d047d4d900231c450aae6f",
INIT_10 => X"506094bf008335759dbddefc98335648fb04655f1bff047614afb4b2274e4b87",
INIT_11 => X"af3107ac9c83339f2c963b345f3476191b962211729eab0c17c1cd24ef2440d6",
INIT_12 => X"f634bb7b52e5cb5258d37f833abf30ee4efe19d2d32978ba4f9ab6140b8b887e",
INIT_13 => X"e145a8df3dd18f9a584f7e7def1c13a6a8908851ca93932d28c404c775629ce1",
INIT_14 => X"c8fe035a62afcb676cfa8e5d2a90b4b3b86cdd86738d837fa4ba3cd7957cf495",
INIT_15 => X"ea5f490671060734a3289bf344bda058d13d12227df18097e6243c7162c7e069",
INIT_16 => X"9681cce0dc1c78b045b39b5fdf374dd241f35d288e13325f86d8989dbb8dd8ce",
INIT_17 => X"e9a0c4c4fd49af7ba00c600bbb980680527e057ca3516543d0f2850a34edb328",
INIT_18 => X"73d65acb0a543270f433f1a62bcd96caf4c5f132eaea31dae8e9338b572a8e1c",
INIT_19 => X"76a13f060b4060d81879dc222765408f0bcf119425b48e4964c22e21f8f896d1",
INIT_1A => X"8fa85cf3ccb31b17f06bd42863ef986056563284cc575bb771f7f735daf0b8ed",
INIT_1B => X"03b5e90f56bca10f03b0a70bfa0b8b9ef418e74208a9761ea6efe218d5995ac2",
INIT_1C => X"ecfb0fcd25fb81b370da47bde7cc5efbb8f969af30311a75e551f7655cf08c2c",
INIT_1D => X"d4b63232979b3dbe45a99790966b31cfbf4a99cd720518ccd280d1a80b04e20d",
INIT_1E => X"0460340e65bcc26af2153f0605e644ed9cb113618d6499887616e55714435994",
INIT_1F => X"e01fc7d11577609fde1c99b29da69a50a52302f81d33194422e1c66eeca37ec7",
INIT_20 => X"8f8efa889c56b64618032036973803e3d13a884205c2141de2a146654c016491",
INIT_21 => X"aac620d0d7748b873dc9eefcce5229d10eebaf0e25634d36f1fdf1ccd9e35602",
INIT_22 => X"9dcaea4d47de0eb87d6de650946758e900de6ba38edf4496a3d2cdda04d64c93",
INIT_23 => X"eaa5ad3904a881a41c96dcc08b9915951b3c019d6689a106dc51c66be2527438",
INIT_24 => X"d19b1664149e909ddc9cb21eea1a553948094e69939e5fa5348ccb00f6f82259",
INIT_25 => X"5d900bb1a59da4cfa45d36d3074f200458700ce8fb38725484993ca5007206ca",
INIT_26 => X"5f52293af44aaceb07d479496e6b065c4c307f27c1abce9c66f7e058069f0bc3",
INIT_27 => X"ebb7c5b47bef60b14862a8af62043b3342346d4295c8d9d9ae56fc67fd72a9cd",
INIT_28 => X"a45477d2a0d9ca5f42da1ecb65185af6956ee4f3a1468d80f0631651645f90f3",
INIT_29 => X"82c9046520940c6f239e33fdec5472a5adf4020d70efe8cab8e3b782b5bda032",
INIT_2A => X"71b7d43dc8527176ff8391f9662a6e2d961ab65c63f6192c6b4bfc642b1dd3ff",
INIT_2B => X"1ea348261e04aef63eb9269048abe45be3110946d175fed12f1cb8fb8d7a30d4",
INIT_2C => X"f8049dd205868dbc822c476c8a4f1f115df3f0b97e91722e630fb11f9374d440",
INIT_2D => X"b8157375e8a6f411cf17b1552dc0352bfe8a1ae4f182e82be9deb362eccb9b2d",
INIT_2E => X"92988a12fedcf893300d5ea50bbc13962239f0cc537ae121a03c9945f00f360c",
INIT_2F => X"c8442a63e531e7c4ae2546da942ef69d783066b0f806c172c2203085c2a8d505",
INIT_30 => X"56b0a4cdee9aa47d509917474fee5b84094cfce37f06b26c3f224d81d27828f0",
INIT_31 => X"632e7ee9fbbb4f1e6ceffa917d22fb766e4d6e89fa87b0e3bfae901f3fe031df",
INIT_32 => X"231793d6acc170fceccd197e8a1a9ec5a55f03d1f3e36cf449a76b87f299fb8e",
INIT_33 => X"a815ec0c9e35518ca312897b3545300f4360294f931df23e4915f8bb98533bda",
INIT_34 => X"b407ab8261b64c4b07435cd7417264802bc1feefa48488e94e51afebf4a289af",
INIT_35 => X"763f8717e6fc9c4d9bcf6688df697320d1ea5241678b7f0b4d6374dc5c73ab8b",
INIT_36 => X"4e1e8d729686a8a014df6488e64918e9830288e4216fc5e5cf9f2e2685b9f3d6",
INIT_37 => X"dea20ff006703916c56bd571eca68b5c6733a64094be89a44cd9b4a74003ac87",
INIT_38 => X"215aea37771ad6ab4d56a545aa616dcbb7af8216286d63086678f3ec81365e8b",
INIT_39 => X"70a0b2024fb77c23825f02a30ccc2dc9d15a1750cdfade8124198270687e28b8",
INIT_3A => X"a139eb4661fc25b7c97c1f45d02335c2b26eb3a73754f1788eb0954e8634b27d",
INIT_3B => X"da109edc3b2609ba75645df4fe8da692d47d199ff31d27539b64ce299793f402",
INIT_3C => X"cf2ef95c79f5a930e847c57fb93b2148ac1bedf90ab6681db0d70c9280bec83c",
INIT_3D => X"a9e7d6415ff939f492fdf6a342b3969cfd26db57870776a2a95f69fd23927e1a",
INIT_3E => X"5317dc9fa147b8e971422ee56aec85d04232e5d6883b3b3e404ba2a2b4fbb44f",
INIT_3F => X"c4c5595ec673265d5550cb0e8d35be8265a85567ade53d47ec2e292a9012b214"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"893f86facc6cd7e4bbad38153917fd56825ceeffdd7074dfffa0e4f1f22596d6",
INIT_01 => X"56089c14847f8931e2c7199f8c9ee88c43907d6f022ce82ba0af40673f751120",
INIT_02 => X"036bc0fc263884954003bbb97816f00c5de977c06ebe3901a8ab54eed8669634",
INIT_03 => X"abf70c54d2b00b7a20ab87f3b826dd87daa290f8c4ae3594374cd92f2dbbe912",
INIT_04 => X"2485956aa31735ad2910b5d766f4034eb9871b4394d10e3af66cc40b2692c1ab",
INIT_05 => X"88a7c77c8def6ce4bcbe6dd5bfd1a7460221fba93d9f48cba01d6b46bc51b4c9",
INIT_06 => X"1fa1793b4a113035ed0c5b419bbe029ff532e760a2cc4b1ab7e45a6f6893857f",
INIT_07 => X"2baa8b40c203920fca516e137f571025d581e4f39a3b77183841f205d48c73e8",
INIT_08 => X"db5ca9425b969e483c786049a22d2151ad78eb348ce9cc912b7186715d1f80a9",
INIT_09 => X"59d4f58e9de69df71d80875b45405a0563232e592432b7c3693c7fe7507b1d84",
INIT_0A => X"1e9ab7dbb660151d13a931ade9e9a6d2efb5c5416885d84227b75164405e5ad8",
INIT_0B => X"fa2a66d36383a1b7e7caf6663ccce537aa1b54a4bde872bb56b2bdc027ab9cf0",
INIT_0C => X"4021244f0f303ca83961739ca4b54765f0cd8c6556ca4aacc9f26a7aafec4457",
INIT_0D => X"a5d753922fe9184ee61d1d7f92a3aefb4d6434a42bc9f965fadfa98c2f7dd94a",
INIT_0E => X"410fb2fb2f4a0f74af7beac2779b709672409dc84c1435d5b9cf0f199a304bc6",
INIT_0F => X"b0b9a11dc821688a79d50e8606be38cb6dd8d7b801a1bca436bf106a31bc6de2",
INIT_10 => X"a22d3dc8c501951686d7c0b7219b09f57e785b41c949d9ce77221e27d0530be9",
INIT_11 => X"6031b5ad0999f4ccb1fea8654f3b5d90463643f73e3a11fa479b14caa4846a45",
INIT_12 => X"b8609f2a9115f4975d2da587359704549e7137acc0a657977f852387edbed5ac",
INIT_13 => X"6cb42fa79510ae8e73ef0e790c370428740ab35f2cee06554631425568aec7b1",
INIT_14 => X"fb1f669f6dd496301dabfe8535f23200803f23ef6dcb10ed4105010ea2ddb3de",
INIT_15 => X"29fea68e7d9f415245b4627e74e466ebb340c373f346765cad4b11690d02fe19",
INIT_16 => X"5dbec858c423b51f797db3cea35df5203bfd6853fe0b964c95ac4ad13b02d70a",
INIT_17 => X"91349a02fa2b57209787ba3c731a459e75bdeed8f141e856d89ecd91a1830115",
INIT_18 => X"ad6feb9e03bbcfa88bcd373a8e60e9d605c46dfe1aac1aeb0c98d4a84bbef485",
INIT_19 => X"a571300ab1452402ad5794691d348c4df359093e7d08ca094fced7c952cbd9e9",
INIT_1A => X"72b4a89f69123494134431dd350a05aa41f1d2129d65a7d59f9ab1e72111d6f0",
INIT_1B => X"0c7ef9f47dde5baf59c658c5cdac98b2458bc733f8978ec191fff334fe9f1901",
INIT_1C => X"18af571ea590389b4d4f87c36ba3162fd32e7f24f60b63055c6dc50e2a3b819d",
INIT_1D => X"1403044637bfa53a1755f0fc42d7caa1d9275a4ba4ef8160884063e5d56f4980",
INIT_1E => X"d71c90b074394a003ebc0c07367dec3cd2134a2a30976267a7feb79c957eb401",
INIT_1F => X"8267f21cefc0f5849b5d0a1b7cde0eeb80be500bcbddd82f18405137804514e9",
INIT_20 => X"1d0848ecc0659cce58946e84ce798275f894623e2f6b0ea4b52895ccfc1f8207",
INIT_21 => X"3605a5401fb3cf45cf5189ec5e6d8ca07a9de4f51477110c100a4d44791d12bb",
INIT_22 => X"af029b0bf274f7147b8b0d5e64e141e6bc7ced10b7ceed5c1cecac6dcac863ac",
INIT_23 => X"e739598c1709f1c06c70c99cae2640599272b9a68026d5867fdea30ca7fb9876",
INIT_24 => X"94613add05e66a1a83b98fc403532149d8d13a0d8daf25d34c7f25e66d0fe615",
INIT_25 => X"ce4837c1f4efe46d8f0e1be1f30794a9ff9e60f351d5ad7874ca4b2d5e4302d1",
INIT_26 => X"801f146f959e39590def2d649cff620f51ecdd177fbdceada41ee2107356dd37",
INIT_27 => X"27509cebe347221d8c7673ef2d2a7b596854f61bda2b128738a29eada3b89394",
INIT_28 => X"099e699f9997d824abb8b550a9dbdd383ab56f411545846c261e41b200c1baff",
INIT_29 => X"12fcc6c900acc655d973fc95c17ce2e932d9f9becd061d5e40908364ffc4d097",
INIT_2A => X"72b8b9085e4a5326cae5a455eb00aaaa1a37a33977374060dd90909857d592fb",
INIT_2B => X"48f3e0bdcde212a1ff71655bf8ed85683d85da23f992c22b743f5749181de280",
INIT_2C => X"be82f97195327e327c5ab49a9af27168380752e90953742136a06028626be13e",
INIT_2D => X"62349c9f48c0837ccbcbafaaa2b044049abc172d912daf4327f7d6525802be4b",
INIT_2E => X"34a7defaba8057855deb9e54012123cf0256c59583caedd632c68f5941443e8e",
INIT_2F => X"8a1e4b1d62317074784c8c9f9b6b89d05726443967faffd2c82a2a1bbcbb8921",
INIT_30 => X"3d70a4480c0964d53ad1db1dd9daa98a4b39ed3e4c8d36b04554c0da73587a82",
INIT_31 => X"6483876b461bab912028e9cbc97a67a4e822807d8db6773da23f924e4404dcb5",
INIT_32 => X"c310ca2deaa531aed609fb6d4ce694917cb160d0ba68c40684ec4ef67878d034",
INIT_33 => X"8ff1816c89dc31cec751487a241cd4ed7bc8d2cab8c7959daacf2b915564aa92",
INIT_34 => X"cd8d81c2c0b05357108e5ef426c4d4923f749f70f7fe8b74e42750a4eb8d3022",
INIT_35 => X"f037f26361d3088abf1e5d6d2b195473762e04c9ed0aaa1d6cfd71db5d623e30",
INIT_36 => X"90f0d7f4db32383cf17af2c4204412c718bf9237649e70f5a151cd482af6801d",
INIT_37 => X"d26b876e041f49885d027266a0f0c31ee46eeb3ca644f30a6eddb88458df7588",
INIT_38 => X"beb6d70dc2e281c73b5264b84065f178b97510c582c6d1088d7d5a7e2ab186c6",
INIT_39 => X"d6a8d227006d3e28265ce686b02cf3623cf0f5578965c200e06cb83317cb58cf",
INIT_3A => X"6971daedfb2201b1ffdd5d201e5cddf03b6d50878d11915b0bdb4c522ed438a2",
INIT_3B => X"7c4b3880a9a210120ef088ab134e274de5ba9c12cb54ccfec4586fae93532588",
INIT_3C => X"dce7316bc48598125808a6b4dd19447394a453b04d99c2f7ae480ece745f3829",
INIT_3D => X"d84b80e784484725ebc894bb5aa1eef26aaff528b77a4cfdfc8e8bf593d92d93",
INIT_3E => X"b0087005fde632e01e09ee3e839538382894999f291ba170d5dd4d48b9480981",
INIT_3F => X"26c41f508b5ee33bcfd7da144fa8ae5da486c45c7e25c81397ed34143cdac0c9"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"49e06a8ec69cc4f866e57feabc835e432e39ad635779304e727238df6a0c8248",
INIT_01 => X"0d69d71b33670f658708214a33ef6a674b537647511f0cb53fa2b7252f707349",
INIT_02 => X"77f3f2a7d027d5b64ea0891883f129116b778a307dfe52668e684ac7e613a9e1",
INIT_03 => X"1cac969510f82cd2d38cb8a0a722df2a4c0a1155bb4b2a3b22bd4b7a1bb12971",
INIT_04 => X"f9eb0192f7b6dff76e568644945f5b045287ebcf0eb59bc8a2abf74c18f7b358",
INIT_05 => X"07620b9d6df735378c90506b24de194d7008fd94b351b9778315fe0d65c9ec58",
INIT_06 => X"b392040879de38525d82d092dc23f93073690861e2c48a5fa6c98c0ea4a0c5d8",
INIT_07 => X"6dd14d870e5245e969673b7b940a9f69081a07b49e8eb77f3b4d3bd7054b92b0",
INIT_08 => X"e2b051f85357f83167a6a56051966972207cf714d9cdf07fa38ef554ddb1f0f1",
INIT_09 => X"5faf5886072567248bc9d6759a72c812942ae2c1667522a3aaf2e3de03944683",
INIT_0A => X"00000000000000000000000000000000000000000000000000000000000068c8",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"1e3e27d6914f869f4efdbc5fbd128c607e137581009bcf14a50267d4a7d0d521",
INIT_01 => X"cfc002e58bc1671d5bff199b70bbfc545ff88b812bccea0cbf10a0b0f1decff8",
INIT_02 => X"792b20da3dbd91bfd590b3683624e22926078f51a3ccaea0d2a7ffc8b6b84790",
INIT_03 => X"ec081549c746059d78bc48be0c7482b9d1f8e452922748c662fd6da2c4f536b3",
INIT_04 => X"ea9e3c73fab0ce0e4ab7a1d3e0f996b70c445c4147d1cf68346d2ff67ab570ef",
INIT_05 => X"002379dd09194bbafe8ad8abf7bbb102552f9860ab6e10088922a4b3ac91c3c4",
INIT_06 => X"e9227025f9a05cc73e1aaaef0d88f6451f6f94d628aa2c94684a874c100eb9e6",
INIT_07 => X"bf7233be058db2d120a327564751238bcccdc141ce07bab726810f5ec4e6bc67",
INIT_08 => X"e57f8f5eb8368f84e31ec0170f06df25e28084734e3ba7f109fdf70b88ca6e87",
INIT_09 => X"d583c2c59b05ebb2fa2c70aa9afb332bc3a6819ea545a9c4d96557abdb2c94c3",
INIT_0A => X"00000000000000000000000000000000000000000000000000000000000005dc",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"2398c774ff1b729734f25cf562c950b1816c6a735405900609f01c216cd1ddd7",
INIT_01 => X"d1226faaaf608494be60eceb159ad8bf9dbf27bbaed351049a1d0baf5b30cda7",
INIT_02 => X"045d1e5a5853b5a1071881ceb810241458989a541a86ce9ecdd2d0075edcd178",
INIT_03 => X"d6e2a0224de71dfdc8da5ef29dfbdc767c8948adf3fa63f7749a1ba5caac62a1",
INIT_04 => X"f05319e385eeac0a1f28f08cac74fc05e0087ba44bacc0ce7ecad9d0985a7bfc",
INIT_05 => X"af7ba66a8be8894607d48023ec7f165d60f77fb4e3b12d630c6c64ec0e81b855",
INIT_06 => X"c2777182401a17e7e1775c68319ed038420fc3ed62f756db01199ef40beab720",
INIT_07 => X"3a55a21506e47720e776c8cfe1a4b59bcbbb46a396315e73a09859d6de6ed3ad",
INIT_08 => X"2272744b6bd1fe582648ef47ea4723116e65e52654fed2e8785fbb182d84fb0c",
INIT_09 => X"c1edb1eae6ce99ae6c81687d51cca6dbaec572b86d76faa3234b84a9f497194c",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000003b28",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"9fa5e906d0863b1e11626224e63430533438574f5631753decd9d62b8cbf5828",
INIT_01 => X"1461de174292e9450bd8ab106bed322ef1a9c053a27b5b45afeeadae3e8c0baa",
INIT_02 => X"5446e2cc0e348b8330861035ec99e26d975e11a6b13a6139c55ac7cf54b74bcb",
INIT_03 => X"c2e741ab9897c5c182aabb791646ae08ab5d7db2028583f3bd4232775d6cd75c",
INIT_04 => X"5648b756f216df1a1fd5400fef106d7c33484a5d1a96af390aa7b2c2737c636f",
INIT_05 => X"25ce0ca17af6280f9262cd9b6e5d9318f382ffe7e10ab95831ee6a4d64a3bd80",
INIT_06 => X"688f948e7684716aae133994d40654d85594f9a18835aeb40485d6e8b9b0a1b1",
INIT_07 => X"fdff8bc7cf80d8da5a4ed756afe7718834ab643e2db35783484d786ed5c9efe0",
INIT_08 => X"a572de3caaddbf8a10c914071267ef510743e581f9ac7fbbce17aeaf20b5d8e2",
INIT_09 => X"ae856b1ca490f7a3f04910f1a60e575769661e34a362fb68ea3ac99c43a4c9c4",
INIT_0A => X"000000000000000000000000000000000000000000000000000000000000d808",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block8: if (block_count > 8) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 9)
--
-----------------------------------------------------------------------------
block9: if (block_count > 9) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 10)
--
-----------------------------------------------------------------------------
block10: if (block_count > 10) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 11)
--
-----------------------------------------------------------------------------
block11: if (block_count > 11) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 12)
--
-----------------------------------------------------------------------------
block12: if (block_count > 12) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block13: if (block_count > 13) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block14: if (block_count > 14) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 15)
--
-----------------------------------------------------------------------------
block15: if (block_count > 15) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | 4808e63803decdeb02f2da0dc36c25a6 | 0.839029 | 5.247332 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/GRAPHLAB/SEQ_SUM_8d_8b_6c.vhd | 1 | 24,059 | -- This SEQ_SUM_8d_8b_6c file has been generated by the GraphLab tool
-- using the hls_GeneratedMooreArchitecture developped by Bertrand LE GAL
-- and Willy AUBRY for High-Level Synthesis design flow.
-- * Time and Date : 10:59 10/03/2011
-- * Module name :
-- * Module version : 0
-- * Module command :
-- * Author name :
-- * E-Mail :
-- * Company :
-- * Copyright :
-- * Design function :
--
--
-- Correspondence concerning GraphLab software and its modules
-- should be addressed as follows:
-- Bertrand LE GAL ([email protected])
-- Maitre de Conferences - ENSEIRB
-- Laboratoire IMS - ENSEIRB - UMR 5818
-- Universite de Bordeaux 1
-- 351, cours de la Liberation
-- F-33405 TALENCE Cedex
-- FRANCE
--
-- Or directly using its website :
-- http://uuu.enseirb.fr/~legal/wp_graphlab
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
library work;
use work.all;
ENTITY SEQ_SUM_8d_8b_6c IS
PORT (
rst : IN STD_LOGIC;
clock : IN STD_LOGIC;
start : IN STD_LOGIC;
flush : IN STD_LOGIC;
holdn : IN STD_LOGIC;
INPUT_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ready : OUT STD_LOGIC;
nready : OUT STD_LOGIC;
icc : OUT STD_LOGIC_vector(3 downto 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SEQ_SUM_8d_8b_6c;
ARCHITECTURE SEQ_SUM_8d_8b_6c_arch OF SEQ_SUM_8d_8b_6c IS
COMPONENT ADD_DYNAMIC
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : POSITIVE := 16;
INPUT_2_WIDTH : POSITIVE := 16;
OUTPUT_1_WIDTH : POSITIVE := 16
);
PORT(
INPUT_1 : IN STD_LOGIC_VECTOR(INPUT_1_WIDTH -1 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(INPUT_2_WIDTH -1 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
TYPE StateType IS (E0, E1, E2, E3, E4, E5, E6, E7, E8, E9);
SIGNAL CurrentState_GLOBAL : StateType;
--
-- DEFINITION DES REGISTRES
--
SIGNAL OPR_ADD_1_INPUT_1_REGISTER_0001 : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0002 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0003 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0004 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0005 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0006 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0007 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0008 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORT_9_REGISTER_0009 : STD_LOGIC_VECTOR(10 DOWNTO 0);
--
-- DEFINITION DES ENTREES DES REGISTRES (UTILISE POUR LES MULTIPLEXEURS)
--
SIGNAL OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORT_9_REGISTER_0009_INPUT : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_1 : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_OUTPUT_1 : STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
---------------------------------------------------------
-- Cluster name : OPR_ADD_1
-- * The cluster contains 1 possible execution paths
-- => The mode 1 required computation(s) : True (E1/E10=>10 states)
--
---------------------------------------------------------
PROC_ASYNC_OPR_ADD_1_INPUT_1 : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_INPUT_1_REGISTER_0001)
BEGIN
CASE CurrentState_GLOBAL IS
-- MODE=1 CYCLE=2 OFFSET=0 => 2
WHEN E2 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 5 / mode = 1 / cycle = 2)
-- MODE=1 CYCLE=3 OFFSET=0 => 3
WHEN E3 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 8 / mode = 1 / cycle = 3)
-- MODE=1 CYCLE=4 OFFSET=0 => 4
WHEN E4 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 11 / mode = 1 / cycle = 4)
-- MODE=1 CYCLE=5 OFFSET=0 => 5
WHEN E5 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 14 / mode = 1 / cycle = 5)
-- MODE=1 CYCLE=6 OFFSET=0 => 6
WHEN E6 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 17 / mode = 1 / cycle = 6)
-- MODE=1 CYCLE=7 OFFSET=0 => 7
WHEN E7 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 20 / mode = 1 / cycle = 7)
-- MODE=1 CYCLE=8 OFFSET=0 => 8
WHEN E8 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 23 / mode = 1 / cycle = 8)
WHEN OTHERS => OPR_ADD_1_INPUT_1 <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_ASYNC_OPR_ADD_1_INPUT_1;
---------------------------------------------------------
-- Cluster name : OPR_ADD_1
-- * The cluster contains 1 possible execution paths
-- => The mode 1 required computation(s) : True (E1/E10=>10 states)
--
---------------------------------------------------------
PROC_ASYNC_OPR_ADD_1_INPUT_2 : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_INPUT_2_REGISTER_0002, OPR_ADD_1_INPUT_2_REGISTER_0003, OPR_ADD_1_INPUT_2_REGISTER_0004, OPR_ADD_1_INPUT_2_REGISTER_0005, OPR_ADD_1_INPUT_2_REGISTER_0006, OPR_ADD_1_INPUT_2_REGISTER_0007, OPR_ADD_1_INPUT_2_REGISTER_0008)
BEGIN
CASE CurrentState_GLOBAL IS
-- MODE=1 CYCLE=2 OFFSET=0 => 2
WHEN E2 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0002; -- (+ / 5 / mode = 1 / cycle = 2)
-- MODE=1 CYCLE=3 OFFSET=0 => 3
WHEN E3 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0003; -- (+ / 8 / mode = 1 / cycle = 3)
-- MODE=1 CYCLE=4 OFFSET=0 => 4
WHEN E4 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- (+ / 11 / mode = 1 / cycle = 4)
-- MODE=1 CYCLE=5 OFFSET=0 => 5
WHEN E5 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- (+ / 14 / mode = 1 / cycle = 5)
-- MODE=1 CYCLE=6 OFFSET=0 => 6
WHEN E6 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- (+ / 17 / mode = 1 / cycle = 6)
-- MODE=1 CYCLE=7 OFFSET=0 => 7
WHEN E7 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- (+ / 20 / mode = 1 / cycle = 7)
-- MODE=1 CYCLE=8 OFFSET=0 => 8
WHEN E8 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- (+ / 23 / mode = 1 / cycle = 8)
WHEN OTHERS => OPR_ADD_1_INPUT_2 <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_ASYNC_OPR_ADD_1_INPUT_2;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_1_REGISTER_0001
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_1_REGISTER_0001 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (a)
WHEN E2 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp0)
WHEN E3 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp1)
WHEN E4 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp2)
WHEN E5 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp3)
WHEN E6 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp4)
WHEN E7 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp5)
WHEN OTHERS => OPR_ADD_1_INPUT_1_REGISTER_0001 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_1_REGISTER_0001;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0002
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0002 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0002 <= OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT; -- mode (1) :: Affectation d'une valeur (b)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0002 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0002;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0003
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0003 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0003 <= OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT; -- mode (1) :: Affectation d'une valeur (c)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0003 <= OPR_ADD_1_INPUT_2_REGISTER_0003; -- mode (1) :: Maintient d'une valeur (c)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0003 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0003;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0004
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0004 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT; -- mode (1) :: Affectation d'une valeur (d)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- mode (1) :: Maintient d'une valeur (d)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- mode (1) :: Maintient d'une valeur (d)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0004 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0004;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0005
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0005 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT; -- mode (1) :: Affectation d'une valeur (e)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0005 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0005;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0006
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0006 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT; -- mode (1) :: Affectation d'une valeur (f)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0006 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0006;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0007
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0007 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT; -- mode (1) :: Affectation d'une valeur (g)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E6 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0007 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0007;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0008
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0008 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT; -- mode (1) :: Affectation d'une valeur (h)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E6 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E7 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0008 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0008;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO PORT_9_REGISTER_0009
--
PROC_REGISTER_CONTROL_PORT_9_REGISTER_0009 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E8 => PORT_9_REGISTER_0009 <= PORT_9_REGISTER_0009_INPUT; -- mode (1) :: Affectation d'une valeur (z)
WHEN E9 => PORT_9_REGISTER_0009 <= PORT_9_REGISTER_0009; -- mode (1) :: Maintient d'une valeur (z)
WHEN OTHERS => PORT_9_REGISTER_0009 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_PORT_9_REGISTER_0009;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OUTPUT_1(31 downto 0)
--
PROCESS (PORT_9_REGISTER_0009)
BEGIN
OUTPUT_1(31 downto 0) <= STD_LOGIC_VECTOR( RESIZE( UNSIGNED(PORT_9_REGISTER_0009), 32) );
END PROCESS;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(7 downto 0), OPR_ADD_1_OUTPUT_1)
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= STD_LOGIC_VECTOR( RESIZE( UNSIGNED(INPUT_1(7 downto 0)), 11) );
WHEN E2 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E3 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E4 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E5 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E6 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E7 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN OTHERS => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(15 downto 8))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT <= INPUT_1(15 downto 8);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(23 downto 16))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT <= INPUT_1(23 downto 16);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(31 downto 24))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT <= INPUT_1(31 downto 24);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(7 downto 0))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT <= INPUT_2(7 downto 0);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(15 downto 8))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT <= INPUT_2(15 downto 8);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(23 downto 16))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT <= INPUT_2(23 downto 16);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(31 downto 24))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT <= INPUT_2(31 downto 24);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO PORT_9_REGISTER_0009_INPUT
--
PROC_MULTIPLEXER_PORT_9_REGISTER_0009_INPUT : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_OUTPUT_1)
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E8 => PORT_9_REGISTER_0009_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN OTHERS => PORT_9_REGISTER_0009_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_PORT_9_REGISTER_0009_INPUT;
--process(start)
--BEGIN
-- if (start = '1') then
-- REPORT "(GL) THE START SIGNAL IS UP !!!";
-- else
-- REPORT "(GL) THE START SIGNAL IS DOWN !!!";
-- end if;
--END PROCESS;
---------------------------------------------------------
PROC_CONTROLER_FSM : PROCESS (clock, rst)
variable sready : std_logic;
variable snready : std_logic;
BEGIN
sready := '0';
snready := '0';
IF rst = '0' THEN
CurrentState_GLOBAL <= E0;
ready <= sready;
nready <= snready;
--printmsg("(GL) THE DESIGN IS PROCESSING RESET !");
ELSIF clock'event and clock = '1' THEN
--if (start = '1') then
-- printmsg("(GL) THE START SIGNAL IS UP (3) !!!");
--end if;
IF( flush = '1' ) THEN
CurrentState_GLOBAL <= E0;
--printmsg("(GL) THE DESIGN IS PROCESSING FLUSH !");
ELSIF (holdn = '0') AND (CurrentState_GLOBAL /= E0) THEN
CurrentState_GLOBAL <= CurrentState_GLOBAL;
--printmsg("(GL) THE DESIGN IS PROCESSING HOLDN !");
ELSE
CASE CurrentState_GLOBAL IS
WHEN E0 =>
IF( start = '1' ) THEN
CurrentState_GLOBAL <= E1;
--REPORT "(GL) THE DESIGN IS STARTING !";
ELSE
CurrentState_GLOBAL <= E0;
--REPORT "(GL) THE DESIGN IS WAITING !";
END IF;
WHEN E1 => CurrentState_GLOBAL <= E2 ;
WHEN E2 => CurrentState_GLOBAL <= E3 ;
WHEN E3 => CurrentState_GLOBAL <= E4 ;
WHEN E4 => CurrentState_GLOBAL <= E5 ;
WHEN E5 => CurrentState_GLOBAL <= E6 ;
WHEN E6 => CurrentState_GLOBAL <= E7 ;
WHEN E7 => CurrentState_GLOBAL <= E8 ;
WHEN E8 => CurrentState_GLOBAL <= E9 ;
snready := '1'; -- LE CALCUL PRESQUE FINI...
--printmsg("(GL) SENDING THE READY SIGNAL !");
WHEN E9 =>
--printmsg("(GL) THE COMPUTATION IS FINISHED !");
CurrentState_GLOBAL <= E0 ;
WHEN OTHERS =>
CurrentState_GLOBAL <= E0;
END CASE;
END IF;
ready <= sready;
nready <= snready;
END IF;
END PROCESS PROC_CONTROLER_FSM;
---------------------------------------------------------
icc <= "0000";
OPR_ADD_1 : ADD_DYNAMIC
GENERIC MAP(
C_SIGNED => 0,
INPUT_1_WIDTH => 11,
INPUT_2_WIDTH => 8,
OUTPUT_1_WIDTH => 11
)
PORT MAP(
STD_LOGIC_VECTOR(OPR_ADD_1_INPUT_1),
STD_LOGIC_VECTOR(OPR_ADD_1_INPUT_2),
OPR_ADD_1_OUTPUT_1
);
END SEQ_SUM_8d_8b_6c_arch;
| gpl-3.0 | 50bd2e8772016205dc84261eeefae0ef | 0.61158 | 3.113225 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/bus_mux.vhd | 1 | 5,288 | ---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
function chr_one_zero(int: std_logic) return character is
variable c: character;
begin
case int is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
return c;
end chr_one_zero;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function bin_char(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
variable bitv : std_logic;
begin
r := 1;
for i in slv'range loop
bitv := slv(i);
result(r) := chr_one_zero( bitv );
r := r + 1;
end loop;
return result;
end bin_char;
begin
--
-- Determine value of a_bus
--
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--
-- Determine value of b_bus
--
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
-- BEGIN ENABLE_(BLTZ,BLTZAL)
when BRANCH_LTZ =>
take_branch <= reg_source(31);
-- END ENABLE_(BLTZ,BLTZAL)
-- BEGIN ENABLE_(BLEZ)
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
-- END ENABLE_(BLEZ)
when BRANCH_EQ =>
take_branch <= is_equal;
-- BEGIN ENABLE_(BNE)
when BRANCH_NE =>
take_branch <= not is_equal;
-- END ENABLE_(BNE)
-- BEGIN ENABLE_(BGEZ,BGEZAL)
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
-- END ENABLE_(BGEZ,BGEZAL)
-- DIFFICILE A SUPPRIMER...
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
| gpl-3.0 | 9b6622fc5a61f1911f076606d25f27f2 | 0.560136 | 3.206792 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_pkg.vhd | 1 | 6,103 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Instruction_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Instruction_Memory_TB_PKG;
PACKAGE BODY Instruction_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Instruction_Memory_TB_PKG;
| mit | c1432ed7c6ad4eaee7adb730d470dc12 | 0.579551 | 4.432099 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_wb.vhd | 1 | 1,248 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:52 05/21/2017
-- Design Name:
-- Module Name: mux_pc1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_wb is
Port(
regsrc : in STD_LOGIC_VECTOR(1 downto 0);
input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0)
);
end mux_wb;
architecture Behavioral of mux_wb is
begin
process(regsrc)
begin
case regsrc is
when "00"=>output<=input1;
when "01"=>output<=input2;
when others => null;
end case;
end process;
end Behavioral;
| apache-2.0 | aabd26fd0d7ee01a6c0c604f823e9053 | 0.592949 | 3.670588 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/alu.vhd | 1 | 1,228 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
port
(
alu_input1: in std_logic_vector(15 downto 0);
alu_input2: in std_logic_vector(15 downto 0);
alu_output: out std_logic_vector(15 downto 0);
alu_operator: in std_logic_vector(2 downto 0)
);
end alu;
architecture Behavioral of alu is
begin
process(alu_operator, alu_input1, alu_input2)
variable a :std_logic_vector(15 downto 0);
begin
case alu_operator is
when "000" =>
alu_output <= alu_input1 + alu_input2;
when "001" =>
alu_output <= alu_input1 - alu_input2;
when "010" =>
alu_output <= alu_input1 and alu_input2;
when "011" =>
alu_output <= alu_input1 or alu_input2;
when "100" =>
a := alu_input1 xor alu_input2;
if(a="0000000000000000")then
alu_output<="0000000000000000";
else
alu_output<="0000000000000001";
end if;
when "101" =>
alu_output <= to_stdlogicvector(to_bitvector(alu_input1) sll conv_integer(alu_input2));
when "110" =>
alu_output <= to_stdlogicvector(to_bitvector(alu_input1) sra conv_integer(alu_input2));
when others =>
alu_output <= "0000000000000000";
end case;
end process;
end Behavioral;
| apache-2.0 | 1e4078358476837fd2cf8c031cec9015 | 0.677524 | 2.889412 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/simulation/pcie_out.vhd | 1 | 1,010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity PCIE_OUT is
port(
clk : IN std_logic;
fifo_in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_write_en : IN std_logic;
fifo_full : OUT std_logic;
fifo_valid : OUT std_logic
);
end;
architecture logic of PCIE_OUT is
begin
PROCESS
file ram_valid_file : TEXT open WRITE_MODE is "pcie_out.txt";
variable LineValid : string(1 to 32);
BEGIN
while( true ) LOOP
wait UNTIL rising_edge( clk );
if fifo_write_en = '1' then
LineValid := str( fifo_in_data );
print(ram_valid_file, LineValid);
end if;
end LOOP;
END PROCESS;
fifo_valid <= '0';
fifo_full <= '0';
fifo_compteur <= (OTHERS => '0');
end; --architecture logic
| gpl-3.0 | bb80a21ed5dbf482fbc8e532159c90ef | 0.563366 | 3.15625 | false | false | false | false |
idpromnut/tek7854mpu | debugger/debug_hdl/netgen/synthesis/toplevel_synthesis.vhd | 1 | 152,840 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: toplevel_synthesis.vhd
-- /___/ /\ Timestamp: Sun Mar 27 23:04:04 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm toplevel -w -dir netgen/synthesis -ofmt vhdl -sim toplevel.ngc toplevel_synthesis.vhd
-- Device : xc6slx9-2-tqg144
-- Input file : toplevel.ngc
-- Output file : /home/chris/Documents/tek7854mpu/debugger/debug_hdl/netgen/synthesis/toplevel_synthesis.vhd
-- # of Entities : 1
-- Design Name : toplevel
-- Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity toplevel is
port (
clk : in STD_LOGIC := 'X';
mojo_tx : out STD_LOGIC;
idpromnut_tx : out STD_LOGIC;
led0 : out STD_LOGIC;
led1 : out STD_LOGIC;
led2 : out STD_LOGIC;
led3 : out STD_LOGIC;
led4 : out STD_LOGIC;
led5 : out STD_LOGIC;
led6 : out STD_LOGIC;
led7 : out STD_LOGIC
);
end toplevel;
architecture Structure of toplevel is
signal clk_BUFGP_0 : STD_LOGIC;
signal transmitter_tx_out_1 : STD_LOGIC;
signal transmitter_ready_2 : STD_LOGIC;
signal ser_ready_last_3 : STD_LOGIC;
signal ser_ready_ser_ready_last_AND_7_o : STD_LOGIC;
signal Q_n0018 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal Mram_n0015_7_0_Q : STD_LOGIC;
signal Mram_n0015_7_0_1 : STD_LOGIC;
signal Mram_n0015_7_0_2 : STD_LOGIC;
signal Mram_n0015_7_0_3 : STD_LOGIC;
signal Mram_n0015_7_0_4 : STD_LOGIC;
signal Mram_n0015_7_0_5 : STD_LOGIC;
signal Mram_n0015_7_0_6 : STD_LOGIC;
signal Mram_n0015_7_0_7 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1 : STD_LOGIC;
signal transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q : STD_LOGIC;
signal transmitter_state_FSM_FFd2_204 : STD_LOGIC;
signal transmitter_state_FSM_FFd1_In : STD_LOGIC;
signal transmitter_state_FSM_FFd2_In : STD_LOGIC;
signal transmitter_n0071_inv : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_4_o : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o : STD_LOGIC;
signal transmitter_state_1_PWR_5_o_Mux_20_o : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q : STD_LOGIC;
signal transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q : STD_LOGIC;
signal transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q : STD_LOGIC;
signal transmitter_baud_clk_edge_342 : STD_LOGIC;
signal transmitter_state_1_GND_5_o_Mux_21_o : STD_LOGIC;
signal transmitter_state_FSM_FFd1_344 : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q : STD_LOGIC;
signal transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q : STD_LOGIC;
signal Q_n00181_352 : STD_LOGIC;
signal Q_n00182_353 : STD_LOGIC;
signal Q_n00183_354 : STD_LOGIC;
signal Q_n00184_355 : STD_LOGIC;
signal Q_n00185_356 : STD_LOGIC;
signal Q_n00186_357 : STD_LOGIC;
signal N3 : STD_LOGIC;
signal N5 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367 : STD_LOGIC;
signal transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368 : STD_LOGIC;
signal Mcount_rom_addr_cy_1_rt_380 : STD_LOGIC;
signal Mcount_rom_addr_cy_2_rt_381 : STD_LOGIC;
signal Mcount_rom_addr_cy_3_rt_382 : STD_LOGIC;
signal Mcount_rom_addr_cy_4_rt_383 : STD_LOGIC;
signal Mcount_rom_addr_cy_5_rt_384 : STD_LOGIC;
signal Mcount_rom_addr_cy_6_rt_385 : STD_LOGIC;
signal Mcount_rom_addr_cy_7_rt_386 : STD_LOGIC;
signal Mcount_rom_addr_cy_8_rt_387 : STD_LOGIC;
signal Mcount_rom_addr_cy_9_rt_388 : STD_LOGIC;
signal Mcount_rom_addr_cy_10_rt_389 : STD_LOGIC;
signal Mcount_rom_addr_cy_11_rt_390 : STD_LOGIC;
signal Mcount_rom_addr_cy_12_rt_391 : STD_LOGIC;
signal Mcount_rom_addr_cy_13_rt_392 : STD_LOGIC;
signal Mcount_rom_addr_cy_14_rt_393 : STD_LOGIC;
signal Mcount_rom_addr_cy_15_rt_394 : STD_LOGIC;
signal Mcount_rom_addr_cy_16_rt_395 : STD_LOGIC;
signal Mcount_rom_addr_cy_17_rt_396 : STD_LOGIC;
signal Mcount_rom_addr_cy_18_rt_397 : STD_LOGIC;
signal Mcount_rom_addr_cy_19_rt_398 : STD_LOGIC;
signal Mcount_rom_addr_cy_20_rt_399 : STD_LOGIC;
signal Mcount_rom_addr_cy_21_rt_400 : STD_LOGIC;
signal Mcount_rom_addr_cy_22_rt_401 : STD_LOGIC;
signal Mcount_rom_addr_cy_23_rt_402 : STD_LOGIC;
signal Mcount_rom_addr_cy_24_rt_403 : STD_LOGIC;
signal Mcount_rom_addr_cy_25_rt_404 : STD_LOGIC;
signal Mcount_rom_addr_cy_26_rt_405 : STD_LOGIC;
signal Mcount_rom_addr_cy_27_rt_406 : STD_LOGIC;
signal Mcount_rom_addr_cy_28_rt_407 : STD_LOGIC;
signal Mcount_rom_addr_cy_29_rt_408 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_29_rt_409 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_28_rt_410 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_27_rt_411 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_26_rt_412 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_25_rt_413 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_24_rt_414 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_23_rt_415 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_22_rt_416 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_21_rt_417 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_20_rt_418 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_19_rt_419 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_18_rt_420 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_17_rt_421 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_16_rt_422 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_15_rt_423 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_14_rt_424 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_13_rt_425 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_12_rt_426 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_11_rt_427 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_10_rt_428 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_9_rt_429 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_8_rt_430 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_7_rt_431 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_6_rt_432 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_5_rt_433 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_4_rt_434 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_3_rt_435 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_2_rt_436 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_cy_1_rt_437 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466 : STD_LOGIC;
signal Mcount_rom_addr_xor_30_rt_467 : STD_LOGIC;
signal transmitter_Mcount_baud_divider_xor_30_rt_468 : STD_LOGIC;
signal transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal transmitter_baud_divider_30_rstpot_473 : STD_LOGIC;
signal transmitter_baud_divider_29_rstpot_474 : STD_LOGIC;
signal transmitter_baud_divider_28_rstpot_475 : STD_LOGIC;
signal transmitter_baud_divider_27_rstpot_476 : STD_LOGIC;
signal transmitter_baud_divider_26_rstpot_477 : STD_LOGIC;
signal transmitter_baud_divider_25_rstpot_478 : STD_LOGIC;
signal transmitter_baud_divider_24_rstpot_479 : STD_LOGIC;
signal transmitter_baud_divider_23_rstpot_480 : STD_LOGIC;
signal transmitter_baud_divider_22_rstpot_481 : STD_LOGIC;
signal transmitter_baud_divider_21_rstpot_482 : STD_LOGIC;
signal transmitter_baud_divider_20_rstpot_483 : STD_LOGIC;
signal transmitter_baud_divider_19_rstpot_484 : STD_LOGIC;
signal transmitter_baud_divider_18_rstpot_485 : STD_LOGIC;
signal transmitter_baud_divider_17_rstpot_486 : STD_LOGIC;
signal transmitter_baud_divider_16_rstpot_487 : STD_LOGIC;
signal transmitter_baud_divider_15_rstpot_488 : STD_LOGIC;
signal transmitter_baud_divider_14_rstpot_489 : STD_LOGIC;
signal transmitter_baud_divider_13_rstpot_490 : STD_LOGIC;
signal transmitter_baud_divider_12_rstpot_491 : STD_LOGIC;
signal transmitter_baud_divider_11_rstpot_492 : STD_LOGIC;
signal transmitter_baud_divider_10_rstpot_493 : STD_LOGIC;
signal transmitter_baud_divider_9_rstpot_494 : STD_LOGIC;
signal transmitter_baud_divider_8_rstpot_495 : STD_LOGIC;
signal transmitter_baud_divider_7_rstpot_496 : STD_LOGIC;
signal transmitter_baud_divider_6_rstpot_497 : STD_LOGIC;
signal transmitter_baud_divider_5_rstpot_498 : STD_LOGIC;
signal transmitter_baud_divider_4_rstpot_499 : STD_LOGIC;
signal transmitter_baud_divider_3_rstpot_500 : STD_LOGIC;
signal transmitter_baud_divider_2_rstpot_501 : STD_LOGIC;
signal transmitter_baud_divider_1_rstpot_502 : STD_LOGIC;
signal transmitter_baud_divider_0_rstpot_503 : STD_LOGIC;
signal transmitter_baud_clk_edge_1_504 : STD_LOGIC;
signal transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505 : STD_LOGIC;
signal transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506 : STD_LOGIC;
signal rom_addr : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Mcount_rom_addr_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Mcount_rom_addr_cy : STD_LOGIC_VECTOR ( 29 downto 0 );
signal transmitter_Mcount_baud_divider_cy : STD_LOGIC_VECTOR ( 29 downto 0 );
signal transmitter_Mcount_baud_divider_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal transmitter_Result : STD_LOGIC_VECTOR ( 30 downto 0 );
signal transmitter_data_shift_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal transmitter_baud_divider : STD_LOGIC_VECTOR ( 30 downto 0 );
signal transmitter_bits_transmitted : STD_LOGIC_VECTOR ( 30 downto 0 );
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => Mram_n0015_7_0_7
);
ser_ready_last : FD
port map (
C => clk_BUFGP_0,
D => transmitter_ready_2,
Q => ser_ready_last_3
);
rom_addr_0 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(0),
R => Q_n0018,
Q => rom_addr(0)
);
rom_addr_1 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(1),
R => Q_n0018,
Q => rom_addr(1)
);
rom_addr_2 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(2),
R => Q_n0018,
Q => rom_addr(2)
);
rom_addr_3 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(3),
R => Q_n0018,
Q => rom_addr(3)
);
rom_addr_4 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(4),
R => Q_n0018,
Q => rom_addr(4)
);
rom_addr_5 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(5),
R => Q_n0018,
Q => rom_addr(5)
);
rom_addr_6 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(6),
R => Q_n0018,
Q => rom_addr(6)
);
rom_addr_7 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(7),
R => Q_n0018,
Q => rom_addr(7)
);
rom_addr_8 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(8),
R => Q_n0018,
Q => rom_addr(8)
);
rom_addr_9 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(9),
R => Q_n0018,
Q => rom_addr(9)
);
rom_addr_10 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(10),
R => Q_n0018,
Q => rom_addr(10)
);
rom_addr_11 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(11),
R => Q_n0018,
Q => rom_addr(11)
);
rom_addr_12 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(12),
R => Q_n0018,
Q => rom_addr(12)
);
rom_addr_13 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(13),
R => Q_n0018,
Q => rom_addr(13)
);
rom_addr_14 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(14),
R => Q_n0018,
Q => rom_addr(14)
);
rom_addr_15 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(15),
R => Q_n0018,
Q => rom_addr(15)
);
rom_addr_16 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(16),
R => Q_n0018,
Q => rom_addr(16)
);
rom_addr_17 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(17),
R => Q_n0018,
Q => rom_addr(17)
);
rom_addr_18 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(18),
R => Q_n0018,
Q => rom_addr(18)
);
rom_addr_19 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(19),
R => Q_n0018,
Q => rom_addr(19)
);
rom_addr_20 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(20),
R => Q_n0018,
Q => rom_addr(20)
);
rom_addr_21 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(21),
R => Q_n0018,
Q => rom_addr(21)
);
rom_addr_22 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(22),
R => Q_n0018,
Q => rom_addr(22)
);
rom_addr_23 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(23),
R => Q_n0018,
Q => rom_addr(23)
);
rom_addr_24 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(24),
R => Q_n0018,
Q => rom_addr(24)
);
rom_addr_25 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(25),
R => Q_n0018,
Q => rom_addr(25)
);
rom_addr_26 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(26),
R => Q_n0018,
Q => rom_addr(26)
);
rom_addr_27 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(27),
R => Q_n0018,
Q => rom_addr(27)
);
rom_addr_28 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(28),
R => Q_n0018,
Q => rom_addr(28)
);
rom_addr_29 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(29),
R => Q_n0018,
Q => rom_addr(29)
);
rom_addr_30 : FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => ser_ready_ser_ready_last_AND_7_o,
D => Result(30),
R => Q_n0018,
Q => rom_addr(30)
);
Mcount_rom_addr_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => Mcount_rom_addr_lut(0),
O => Mcount_rom_addr_cy(0)
);
Mcount_rom_addr_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => Mcount_rom_addr_lut(0),
O => Result(0)
);
Mcount_rom_addr_cy_1_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(0),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_1_rt_380,
O => Mcount_rom_addr_cy(1)
);
Mcount_rom_addr_xor_1_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(0),
LI => Mcount_rom_addr_cy_1_rt_380,
O => Result(1)
);
Mcount_rom_addr_cy_2_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(1),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_2_rt_381,
O => Mcount_rom_addr_cy(2)
);
Mcount_rom_addr_xor_2_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(1),
LI => Mcount_rom_addr_cy_2_rt_381,
O => Result(2)
);
Mcount_rom_addr_cy_3_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(2),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_3_rt_382,
O => Mcount_rom_addr_cy(3)
);
Mcount_rom_addr_xor_3_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(2),
LI => Mcount_rom_addr_cy_3_rt_382,
O => Result(3)
);
Mcount_rom_addr_cy_4_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(3),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_4_rt_383,
O => Mcount_rom_addr_cy(4)
);
Mcount_rom_addr_xor_4_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(3),
LI => Mcount_rom_addr_cy_4_rt_383,
O => Result(4)
);
Mcount_rom_addr_cy_5_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(4),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_5_rt_384,
O => Mcount_rom_addr_cy(5)
);
Mcount_rom_addr_xor_5_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(4),
LI => Mcount_rom_addr_cy_5_rt_384,
O => Result(5)
);
Mcount_rom_addr_cy_6_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(5),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_6_rt_385,
O => Mcount_rom_addr_cy(6)
);
Mcount_rom_addr_xor_6_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(5),
LI => Mcount_rom_addr_cy_6_rt_385,
O => Result(6)
);
Mcount_rom_addr_cy_7_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(6),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_7_rt_386,
O => Mcount_rom_addr_cy(7)
);
Mcount_rom_addr_xor_7_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(6),
LI => Mcount_rom_addr_cy_7_rt_386,
O => Result(7)
);
Mcount_rom_addr_cy_8_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(7),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_8_rt_387,
O => Mcount_rom_addr_cy(8)
);
Mcount_rom_addr_xor_8_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(7),
LI => Mcount_rom_addr_cy_8_rt_387,
O => Result(8)
);
Mcount_rom_addr_cy_9_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(8),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_9_rt_388,
O => Mcount_rom_addr_cy(9)
);
Mcount_rom_addr_xor_9_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(8),
LI => Mcount_rom_addr_cy_9_rt_388,
O => Result(9)
);
Mcount_rom_addr_cy_10_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(9),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_10_rt_389,
O => Mcount_rom_addr_cy(10)
);
Mcount_rom_addr_xor_10_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(9),
LI => Mcount_rom_addr_cy_10_rt_389,
O => Result(10)
);
Mcount_rom_addr_cy_11_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(10),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_11_rt_390,
O => Mcount_rom_addr_cy(11)
);
Mcount_rom_addr_xor_11_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(10),
LI => Mcount_rom_addr_cy_11_rt_390,
O => Result(11)
);
Mcount_rom_addr_cy_12_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(11),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_12_rt_391,
O => Mcount_rom_addr_cy(12)
);
Mcount_rom_addr_xor_12_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(11),
LI => Mcount_rom_addr_cy_12_rt_391,
O => Result(12)
);
Mcount_rom_addr_cy_13_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(12),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_13_rt_392,
O => Mcount_rom_addr_cy(13)
);
Mcount_rom_addr_xor_13_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(12),
LI => Mcount_rom_addr_cy_13_rt_392,
O => Result(13)
);
Mcount_rom_addr_cy_14_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(13),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_14_rt_393,
O => Mcount_rom_addr_cy(14)
);
Mcount_rom_addr_xor_14_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(13),
LI => Mcount_rom_addr_cy_14_rt_393,
O => Result(14)
);
Mcount_rom_addr_cy_15_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(14),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_15_rt_394,
O => Mcount_rom_addr_cy(15)
);
Mcount_rom_addr_xor_15_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(14),
LI => Mcount_rom_addr_cy_15_rt_394,
O => Result(15)
);
Mcount_rom_addr_cy_16_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(15),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_16_rt_395,
O => Mcount_rom_addr_cy(16)
);
Mcount_rom_addr_xor_16_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(15),
LI => Mcount_rom_addr_cy_16_rt_395,
O => Result(16)
);
Mcount_rom_addr_cy_17_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(16),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_17_rt_396,
O => Mcount_rom_addr_cy(17)
);
Mcount_rom_addr_xor_17_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(16),
LI => Mcount_rom_addr_cy_17_rt_396,
O => Result(17)
);
Mcount_rom_addr_cy_18_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(17),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_18_rt_397,
O => Mcount_rom_addr_cy(18)
);
Mcount_rom_addr_xor_18_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(17),
LI => Mcount_rom_addr_cy_18_rt_397,
O => Result(18)
);
Mcount_rom_addr_cy_19_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(18),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_19_rt_398,
O => Mcount_rom_addr_cy(19)
);
Mcount_rom_addr_xor_19_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(18),
LI => Mcount_rom_addr_cy_19_rt_398,
O => Result(19)
);
Mcount_rom_addr_cy_20_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(19),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_20_rt_399,
O => Mcount_rom_addr_cy(20)
);
Mcount_rom_addr_xor_20_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(19),
LI => Mcount_rom_addr_cy_20_rt_399,
O => Result(20)
);
Mcount_rom_addr_cy_21_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(20),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_21_rt_400,
O => Mcount_rom_addr_cy(21)
);
Mcount_rom_addr_xor_21_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(20),
LI => Mcount_rom_addr_cy_21_rt_400,
O => Result(21)
);
Mcount_rom_addr_cy_22_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(21),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_22_rt_401,
O => Mcount_rom_addr_cy(22)
);
Mcount_rom_addr_xor_22_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(21),
LI => Mcount_rom_addr_cy_22_rt_401,
O => Result(22)
);
Mcount_rom_addr_cy_23_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(22),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_23_rt_402,
O => Mcount_rom_addr_cy(23)
);
Mcount_rom_addr_xor_23_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(22),
LI => Mcount_rom_addr_cy_23_rt_402,
O => Result(23)
);
Mcount_rom_addr_cy_24_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(23),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_24_rt_403,
O => Mcount_rom_addr_cy(24)
);
Mcount_rom_addr_xor_24_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(23),
LI => Mcount_rom_addr_cy_24_rt_403,
O => Result(24)
);
Mcount_rom_addr_cy_25_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(24),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_25_rt_404,
O => Mcount_rom_addr_cy(25)
);
Mcount_rom_addr_xor_25_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(24),
LI => Mcount_rom_addr_cy_25_rt_404,
O => Result(25)
);
Mcount_rom_addr_cy_26_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(25),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_26_rt_405,
O => Mcount_rom_addr_cy(26)
);
Mcount_rom_addr_xor_26_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(25),
LI => Mcount_rom_addr_cy_26_rt_405,
O => Result(26)
);
Mcount_rom_addr_cy_27_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(26),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_27_rt_406,
O => Mcount_rom_addr_cy(27)
);
Mcount_rom_addr_xor_27_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(26),
LI => Mcount_rom_addr_cy_27_rt_406,
O => Result(27)
);
Mcount_rom_addr_cy_28_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(27),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_28_rt_407,
O => Mcount_rom_addr_cy(28)
);
Mcount_rom_addr_xor_28_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(27),
LI => Mcount_rom_addr_cy_28_rt_407,
O => Result(28)
);
Mcount_rom_addr_cy_29_Q : MUXCY
port map (
CI => Mcount_rom_addr_cy(28),
DI => Mram_n0015_7_0_7,
S => Mcount_rom_addr_cy_29_rt_408,
O => Mcount_rom_addr_cy(29)
);
Mcount_rom_addr_xor_29_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(28),
LI => Mcount_rom_addr_cy_29_rt_408,
O => Result(29)
);
Mcount_rom_addr_xor_30_Q : XORCY
port map (
CI => Mcount_rom_addr_cy(29),
LI => Mcount_rom_addr_xor_30_rt_467,
O => Result(30)
);
transmitter_Mcount_baud_divider_xor_30_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(29),
LI => transmitter_Mcount_baud_divider_xor_30_rt_468,
O => transmitter_Result(30)
);
transmitter_Mcount_baud_divider_xor_29_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(28),
LI => transmitter_Mcount_baud_divider_cy_29_rt_409,
O => transmitter_Result(29)
);
transmitter_Mcount_baud_divider_cy_29_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(28),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_29_rt_409,
O => transmitter_Mcount_baud_divider_cy(29)
);
transmitter_Mcount_baud_divider_xor_28_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(27),
LI => transmitter_Mcount_baud_divider_cy_28_rt_410,
O => transmitter_Result(28)
);
transmitter_Mcount_baud_divider_cy_28_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(27),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_28_rt_410,
O => transmitter_Mcount_baud_divider_cy(28)
);
transmitter_Mcount_baud_divider_xor_27_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(26),
LI => transmitter_Mcount_baud_divider_cy_27_rt_411,
O => transmitter_Result(27)
);
transmitter_Mcount_baud_divider_cy_27_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(26),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_27_rt_411,
O => transmitter_Mcount_baud_divider_cy(27)
);
transmitter_Mcount_baud_divider_xor_26_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(25),
LI => transmitter_Mcount_baud_divider_cy_26_rt_412,
O => transmitter_Result(26)
);
transmitter_Mcount_baud_divider_cy_26_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(25),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_26_rt_412,
O => transmitter_Mcount_baud_divider_cy(26)
);
transmitter_Mcount_baud_divider_xor_25_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(24),
LI => transmitter_Mcount_baud_divider_cy_25_rt_413,
O => transmitter_Result(25)
);
transmitter_Mcount_baud_divider_cy_25_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(24),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_25_rt_413,
O => transmitter_Mcount_baud_divider_cy(25)
);
transmitter_Mcount_baud_divider_xor_24_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(23),
LI => transmitter_Mcount_baud_divider_cy_24_rt_414,
O => transmitter_Result(24)
);
transmitter_Mcount_baud_divider_cy_24_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(23),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_24_rt_414,
O => transmitter_Mcount_baud_divider_cy(24)
);
transmitter_Mcount_baud_divider_xor_23_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(22),
LI => transmitter_Mcount_baud_divider_cy_23_rt_415,
O => transmitter_Result(23)
);
transmitter_Mcount_baud_divider_cy_23_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(22),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_23_rt_415,
O => transmitter_Mcount_baud_divider_cy(23)
);
transmitter_Mcount_baud_divider_xor_22_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(21),
LI => transmitter_Mcount_baud_divider_cy_22_rt_416,
O => transmitter_Result(22)
);
transmitter_Mcount_baud_divider_cy_22_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(21),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_22_rt_416,
O => transmitter_Mcount_baud_divider_cy(22)
);
transmitter_Mcount_baud_divider_xor_21_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(20),
LI => transmitter_Mcount_baud_divider_cy_21_rt_417,
O => transmitter_Result(21)
);
transmitter_Mcount_baud_divider_cy_21_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(20),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_21_rt_417,
O => transmitter_Mcount_baud_divider_cy(21)
);
transmitter_Mcount_baud_divider_xor_20_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(19),
LI => transmitter_Mcount_baud_divider_cy_20_rt_418,
O => transmitter_Result(20)
);
transmitter_Mcount_baud_divider_cy_20_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(19),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_20_rt_418,
O => transmitter_Mcount_baud_divider_cy(20)
);
transmitter_Mcount_baud_divider_xor_19_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(18),
LI => transmitter_Mcount_baud_divider_cy_19_rt_419,
O => transmitter_Result(19)
);
transmitter_Mcount_baud_divider_cy_19_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(18),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_19_rt_419,
O => transmitter_Mcount_baud_divider_cy(19)
);
transmitter_Mcount_baud_divider_xor_18_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(17),
LI => transmitter_Mcount_baud_divider_cy_18_rt_420,
O => transmitter_Result(18)
);
transmitter_Mcount_baud_divider_cy_18_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(17),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_18_rt_420,
O => transmitter_Mcount_baud_divider_cy(18)
);
transmitter_Mcount_baud_divider_xor_17_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(16),
LI => transmitter_Mcount_baud_divider_cy_17_rt_421,
O => transmitter_Result(17)
);
transmitter_Mcount_baud_divider_cy_17_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(16),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_17_rt_421,
O => transmitter_Mcount_baud_divider_cy(17)
);
transmitter_Mcount_baud_divider_xor_16_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(15),
LI => transmitter_Mcount_baud_divider_cy_16_rt_422,
O => transmitter_Result(16)
);
transmitter_Mcount_baud_divider_cy_16_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(15),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_16_rt_422,
O => transmitter_Mcount_baud_divider_cy(16)
);
transmitter_Mcount_baud_divider_xor_15_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(14),
LI => transmitter_Mcount_baud_divider_cy_15_rt_423,
O => transmitter_Result(15)
);
transmitter_Mcount_baud_divider_cy_15_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(14),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_15_rt_423,
O => transmitter_Mcount_baud_divider_cy(15)
);
transmitter_Mcount_baud_divider_xor_14_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(13),
LI => transmitter_Mcount_baud_divider_cy_14_rt_424,
O => transmitter_Result(14)
);
transmitter_Mcount_baud_divider_cy_14_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(13),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_14_rt_424,
O => transmitter_Mcount_baud_divider_cy(14)
);
transmitter_Mcount_baud_divider_xor_13_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(12),
LI => transmitter_Mcount_baud_divider_cy_13_rt_425,
O => transmitter_Result(13)
);
transmitter_Mcount_baud_divider_cy_13_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(12),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_13_rt_425,
O => transmitter_Mcount_baud_divider_cy(13)
);
transmitter_Mcount_baud_divider_xor_12_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(11),
LI => transmitter_Mcount_baud_divider_cy_12_rt_426,
O => transmitter_Result(12)
);
transmitter_Mcount_baud_divider_cy_12_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(11),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_12_rt_426,
O => transmitter_Mcount_baud_divider_cy(12)
);
transmitter_Mcount_baud_divider_xor_11_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(10),
LI => transmitter_Mcount_baud_divider_cy_11_rt_427,
O => transmitter_Result(11)
);
transmitter_Mcount_baud_divider_cy_11_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(10),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_11_rt_427,
O => transmitter_Mcount_baud_divider_cy(11)
);
transmitter_Mcount_baud_divider_xor_10_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(9),
LI => transmitter_Mcount_baud_divider_cy_10_rt_428,
O => transmitter_Result(10)
);
transmitter_Mcount_baud_divider_cy_10_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(9),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_10_rt_428,
O => transmitter_Mcount_baud_divider_cy(10)
);
transmitter_Mcount_baud_divider_xor_9_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(8),
LI => transmitter_Mcount_baud_divider_cy_9_rt_429,
O => transmitter_Result(9)
);
transmitter_Mcount_baud_divider_cy_9_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(8),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_9_rt_429,
O => transmitter_Mcount_baud_divider_cy(9)
);
transmitter_Mcount_baud_divider_xor_8_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(7),
LI => transmitter_Mcount_baud_divider_cy_8_rt_430,
O => transmitter_Result(8)
);
transmitter_Mcount_baud_divider_cy_8_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(7),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_8_rt_430,
O => transmitter_Mcount_baud_divider_cy(8)
);
transmitter_Mcount_baud_divider_xor_7_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(6),
LI => transmitter_Mcount_baud_divider_cy_7_rt_431,
O => transmitter_Result(7)
);
transmitter_Mcount_baud_divider_cy_7_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(6),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_7_rt_431,
O => transmitter_Mcount_baud_divider_cy(7)
);
transmitter_Mcount_baud_divider_xor_6_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(5),
LI => transmitter_Mcount_baud_divider_cy_6_rt_432,
O => transmitter_Result(6)
);
transmitter_Mcount_baud_divider_cy_6_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(5),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_6_rt_432,
O => transmitter_Mcount_baud_divider_cy(6)
);
transmitter_Mcount_baud_divider_xor_5_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(4),
LI => transmitter_Mcount_baud_divider_cy_5_rt_433,
O => transmitter_Result(5)
);
transmitter_Mcount_baud_divider_cy_5_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(4),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_5_rt_433,
O => transmitter_Mcount_baud_divider_cy(5)
);
transmitter_Mcount_baud_divider_xor_4_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(3),
LI => transmitter_Mcount_baud_divider_cy_4_rt_434,
O => transmitter_Result(4)
);
transmitter_Mcount_baud_divider_cy_4_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(3),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_4_rt_434,
O => transmitter_Mcount_baud_divider_cy(4)
);
transmitter_Mcount_baud_divider_xor_3_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(2),
LI => transmitter_Mcount_baud_divider_cy_3_rt_435,
O => transmitter_Result(3)
);
transmitter_Mcount_baud_divider_cy_3_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(2),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_3_rt_435,
O => transmitter_Mcount_baud_divider_cy(3)
);
transmitter_Mcount_baud_divider_xor_2_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(1),
LI => transmitter_Mcount_baud_divider_cy_2_rt_436,
O => transmitter_Result(2)
);
transmitter_Mcount_baud_divider_cy_2_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(1),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_2_rt_436,
O => transmitter_Mcount_baud_divider_cy(2)
);
transmitter_Mcount_baud_divider_xor_1_Q : XORCY
port map (
CI => transmitter_Mcount_baud_divider_cy(0),
LI => transmitter_Mcount_baud_divider_cy_1_rt_437,
O => transmitter_Result(1)
);
transmitter_Mcount_baud_divider_cy_1_Q : MUXCY
port map (
CI => transmitter_Mcount_baud_divider_cy(0),
DI => Mram_n0015_7_0_7,
S => transmitter_Mcount_baud_divider_cy_1_rt_437,
O => transmitter_Mcount_baud_divider_cy(1)
);
transmitter_Mcount_baud_divider_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => transmitter_Mcount_baud_divider_lut(0),
O => transmitter_Result(0)
);
transmitter_Mcount_baud_divider_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => transmitter_Mcount_baud_divider_lut(0),
O => transmitter_Mcount_baud_divider_cy(0)
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_29_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_Q_142
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_28_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_Q_143
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_27_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_Q_144
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_26_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_Q_145
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_25_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_Q_146
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_24_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_Q_147
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_23_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_Q_148
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_22_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_Q_149
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_21_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_Q_150
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_20_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_Q_151
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_19_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_Q_152
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_18_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_Q_153
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_17_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_Q_154
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_16_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_Q_155
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_15_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_Q_156
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_14_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_Q_157
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_13_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_Q_158
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_12_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_Q_159
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_11_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_Q_160
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_10_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_Q_161
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_9_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_Q_162
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_8_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_Q_163
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_7_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_Q_164
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_6_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_Q_165
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_5_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_Q_166
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_4_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_Q_167
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_3_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_Q_168
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_2_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_Q_169
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_1_Q : XORCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q : MUXCY
port map (
CI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171,
DI => Mram_n0015_7_0_7,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_Q_170
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_0_Q : XORCY
port map (
CI => Mram_n0015_7_0_7,
LI => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q,
O => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q : MUXCY
port map (
CI => Mram_n0015_7_0_7,
DI => N0,
S => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q,
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_0_Q_171
);
transmitter_state_FSM_FFd1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_FSM_FFd1_In,
Q => transmitter_state_FSM_FFd1_344
);
transmitter_state_FSM_FFd2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_FSM_FFd2_In,
Q => transmitter_state_FSM_FFd2_204
);
transmitter_bits_transmitted_30 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q,
Q => transmitter_bits_transmitted(30)
);
transmitter_bits_transmitted_29 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q,
Q => transmitter_bits_transmitted(29)
);
transmitter_bits_transmitted_28 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q,
Q => transmitter_bits_transmitted(28)
);
transmitter_bits_transmitted_27 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q,
Q => transmitter_bits_transmitted(27)
);
transmitter_bits_transmitted_26 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q,
Q => transmitter_bits_transmitted(26)
);
transmitter_bits_transmitted_25 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q,
Q => transmitter_bits_transmitted(25)
);
transmitter_bits_transmitted_24 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q,
Q => transmitter_bits_transmitted(24)
);
transmitter_bits_transmitted_23 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q,
Q => transmitter_bits_transmitted(23)
);
transmitter_bits_transmitted_22 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q,
Q => transmitter_bits_transmitted(22)
);
transmitter_bits_transmitted_21 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q,
Q => transmitter_bits_transmitted(21)
);
transmitter_bits_transmitted_20 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q,
Q => transmitter_bits_transmitted(20)
);
transmitter_bits_transmitted_19 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q,
Q => transmitter_bits_transmitted(19)
);
transmitter_bits_transmitted_18 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q,
Q => transmitter_bits_transmitted(18)
);
transmitter_bits_transmitted_17 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q,
Q => transmitter_bits_transmitted(17)
);
transmitter_bits_transmitted_16 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q,
Q => transmitter_bits_transmitted(16)
);
transmitter_bits_transmitted_15 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q,
Q => transmitter_bits_transmitted(15)
);
transmitter_bits_transmitted_14 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q,
Q => transmitter_bits_transmitted(14)
);
transmitter_bits_transmitted_13 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q,
Q => transmitter_bits_transmitted(13)
);
transmitter_bits_transmitted_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q,
Q => transmitter_bits_transmitted(12)
);
transmitter_bits_transmitted_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q,
Q => transmitter_bits_transmitted(11)
);
transmitter_bits_transmitted_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q,
Q => transmitter_bits_transmitted(10)
);
transmitter_bits_transmitted_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q,
Q => transmitter_bits_transmitted(9)
);
transmitter_bits_transmitted_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q,
Q => transmitter_bits_transmitted(8)
);
transmitter_bits_transmitted_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q,
Q => transmitter_bits_transmitted(7)
);
transmitter_bits_transmitted_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q,
Q => transmitter_bits_transmitted(6)
);
transmitter_bits_transmitted_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q,
Q => transmitter_bits_transmitted(5)
);
transmitter_bits_transmitted_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q,
Q => transmitter_bits_transmitted(4)
);
transmitter_bits_transmitted_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q,
Q => transmitter_bits_transmitted(3)
);
transmitter_bits_transmitted_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q,
Q => transmitter_bits_transmitted(2)
);
transmitter_bits_transmitted_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q,
Q => transmitter_bits_transmitted(1)
);
transmitter_bits_transmitted_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q,
Q => transmitter_bits_transmitted(0)
);
transmitter_ready : FD
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_GND_5_o_Mux_21_o,
Q => transmitter_ready_2
);
transmitter_data_shift_reg_6 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q,
Q => transmitter_data_shift_reg(6)
);
transmitter_data_shift_reg_5 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q,
Q => transmitter_data_shift_reg(5)
);
transmitter_data_shift_reg_4 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q,
Q => transmitter_data_shift_reg(4)
);
transmitter_data_shift_reg_3 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q,
Q => transmitter_data_shift_reg(3)
);
transmitter_data_shift_reg_2 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q,
Q => transmitter_data_shift_reg(2)
);
transmitter_data_shift_reg_1 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q,
Q => transmitter_data_shift_reg(1)
);
transmitter_data_shift_reg_0 : FDE
port map (
C => clk_BUFGP_0,
CE => transmitter_n0071_inv,
D => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q,
Q => transmitter_data_shift_reg(0)
);
transmitter_tx_out : FD
port map (
C => clk_BUFGP_0,
D => transmitter_state_1_PWR_5_o_Mux_20_o,
Q => transmitter_tx_out_1
);
transmitter_baud_clk_edge : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_GND_5_o_baud_divider_30_equal_4_o,
Q => transmitter_baud_clk_edge_342
);
ser_ready_ser_ready_last_AND_7_o1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_ready_2,
I1 => ser_ready_last_3,
O => ser_ready_ser_ready_last_AND_7_o
);
Mram_n0015_7_0_111 : LUT5
generic map(
INIT => X"CC72B557"
)
port map (
I0 => rom_addr(0),
I1 => rom_addr(1),
I2 => rom_addr(2),
I3 => rom_addr(4),
I4 => rom_addr(3),
O => Mram_n0015_7_0_1
);
Mram_n0015_7_0_31 : LUT5
generic map(
INIT => X"A9A089D5"
)
port map (
I0 => rom_addr(4),
I1 => rom_addr(3),
I2 => rom_addr(0),
I3 => rom_addr(1),
I4 => rom_addr(2),
O => Mram_n0015_7_0_3
);
Mram_n0015_7_0_21 : LUT5
generic map(
INIT => X"6236FF3F"
)
port map (
I0 => rom_addr(4),
I1 => rom_addr(1),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(3),
O => Mram_n0015_7_0_2
);
Mram_n0015_7_0_51 : LUT5
generic map(
INIT => X"1D101018"
)
port map (
I0 => rom_addr(2),
I1 => rom_addr(3),
I2 => rom_addr(4),
I3 => rom_addr(0),
I4 => rom_addr(1),
O => Mram_n0015_7_0_5
);
Mram_n0015_7_0_41 : LUT5
generic map(
INIT => X"222402C4"
)
port map (
I0 => rom_addr(2),
I1 => rom_addr(4),
I2 => rom_addr(1),
I3 => rom_addr(3),
I4 => rom_addr(0),
O => Mram_n0015_7_0_4
);
Mram_n0015_7_0_11 : LUT5
generic map(
INIT => X"3435791A"
)
port map (
I0 => rom_addr(3),
I1 => rom_addr(1),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(4),
O => Mram_n0015_7_0_Q
);
Mram_n0015_7_0_61 : LUT5
generic map(
INIT => X"1617FF13"
)
port map (
I0 => rom_addr(1),
I1 => rom_addr(4),
I2 => rom_addr(0),
I3 => rom_addr(2),
I4 => rom_addr(3),
O => Mram_n0015_7_0_6
);
transmitter_mux12 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(1),
I3 => transmitter_data_shift_reg(0),
I4 => Mram_n0015_7_0_Q,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_0_Q
);
transmitter_mux111 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(2),
I3 => transmitter_data_shift_reg(1),
I4 => Mram_n0015_7_0_1,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_1_Q
);
transmitter_mux311 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(4),
I3 => transmitter_data_shift_reg(3),
I4 => Mram_n0015_7_0_3,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_3_Q
);
transmitter_mux411 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(5),
I3 => transmitter_data_shift_reg(4),
I4 => Mram_n0015_7_0_4,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_4_Q
);
transmitter_mux211 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(3),
I3 => transmitter_data_shift_reg(2),
I4 => Mram_n0015_7_0_2,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_2_Q
);
transmitter_mux611 : LUT4
generic map(
INIT => X"7520"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(6),
I3 => Mram_n0015_7_0_6,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_6_Q
);
transmitter_mux511 : LUT5
generic map(
INIT => X"F7D5A280"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_data_shift_reg(6),
I3 => transmitter_data_shift_reg(5),
I4 => Mram_n0015_7_0_5,
O => transmitter_state_1_data_shift_reg_7_wide_mux_18_OUT_5_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT110 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(0),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_0_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_0_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT210 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(10),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_10_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_10_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT32 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(11),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_11_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_11_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT41 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(12),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_12_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_12_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT51 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(13),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_13_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_13_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT61 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(14),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_14_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_14_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT71 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(15),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_15_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_15_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT81 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(16),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_16_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_16_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT91 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(17),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_17_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_17_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT101 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(18),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_18_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_18_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(19),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_19_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_19_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT121 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(1),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_1_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_1_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT131 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(20),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_20_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_20_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT141 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(21),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_21_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_21_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT151 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(22),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_22_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_22_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT161 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(23),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_23_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_23_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT171 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(24),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_24_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_24_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT181 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(25),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_25_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_25_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT191 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(26),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_26_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_26_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT201 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(27),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_27_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_27_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT211 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(28),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_28_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_28_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT221 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(29),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_29_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_29_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT231 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(2),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_2_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_2_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT241 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(30),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_30_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_30_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT251 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(3),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_3_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_3_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT261 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(4),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_4_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_4_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT271 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(5),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_5_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_5_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT281 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(6),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_6_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_6_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT291 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(7),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_7_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_7_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT301 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(8),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_8_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_8_Q
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT311 : LUT5
generic map(
INIT => X"FF202020"
)
port map (
I0 => transmitter_bits_transmitted(9),
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_bits_transmitted_30_GND_5_o_add_14_OUT_9_Q,
I4 => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505,
O => transmitter_state_1_bits_transmitted_30_wide_mux_19_OUT_9_Q
);
transmitter_state_1_PWR_5_o_Mux_20_o1 : LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_data_shift_reg(0),
I2 => transmitter_state_FSM_FFd1_344,
O => transmitter_state_1_PWR_5_o_Mux_20_o
);
transmitter_state_state_1_GND_5_o_Mux_21_o1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_state_FSM_FFd1_344,
O => transmitter_state_1_GND_5_o_Mux_21_o
);
transmitter_n0071_inv1 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_state_FSM_FFd1_344,
O => transmitter_n0071_inv
);
Q_n00181 : LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => ser_ready_last_3,
I1 => transmitter_ready_2,
I2 => rom_addr(3),
I3 => rom_addr(4),
I4 => rom_addr(1),
I5 => rom_addr(0),
O => Q_n00181_352
);
Q_n00182 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(8),
I1 => rom_addr(9),
I2 => rom_addr(7),
I3 => rom_addr(6),
I4 => rom_addr(5),
I5 => rom_addr(30),
O => Q_n00182_353
);
Q_n00183 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(25),
I1 => rom_addr(26),
I2 => rom_addr(27),
I3 => rom_addr(28),
I4 => rom_addr(29),
I5 => rom_addr(2),
O => Q_n00183_354
);
Q_n00184 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(23),
I1 => rom_addr(24),
I2 => rom_addr(22),
I3 => rom_addr(21),
I4 => rom_addr(20),
I5 => rom_addr(19),
O => Q_n00184_355
);
Q_n00185 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => rom_addr(17),
I1 => rom_addr(18),
I2 => rom_addr(16),
I3 => rom_addr(15),
I4 => rom_addr(14),
I5 => rom_addr(13),
O => Q_n00185_356
);
Q_n00186 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => rom_addr(11),
I1 => rom_addr(12),
I2 => rom_addr(10),
O => Q_n00186_357
);
Q_n00187 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => Q_n00186_357,
I1 => Q_n00185_356,
I2 => Q_n00184_355,
I3 => Q_n00182_353,
I4 => Q_n00183_354,
I5 => Q_n00181_352,
O => Q_n0018
);
transmitter_GND_5_o_baud_divider_30_equal_4_o_30_SW0 : LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => transmitter_baud_divider(9),
I1 => transmitter_baud_divider(5),
I2 => transmitter_baud_divider(2),
I3 => transmitter_baud_divider(11),
O => N3
);
transmitter_GND_5_o_baud_divider_30_equal_4_o_30_Q : LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N3,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_4_o
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_SW0 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => transmitter_baud_divider(9),
I1 => transmitter_baud_divider(5),
I2 => transmitter_baud_divider(2),
I3 => transmitter_baud_divider(11),
O => N5
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q : LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N5,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11 : LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => transmitter_baud_divider(3),
I1 => transmitter_baud_divider(0),
I2 => transmitter_baud_divider(30),
I3 => transmitter_baud_divider(1),
I4 => transmitter_baud_divider(7),
I5 => transmitter_baud_divider(8),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_baud_divider(14),
I1 => transmitter_baud_divider(13),
I2 => transmitter_baud_divider(15),
I3 => transmitter_baud_divider(17),
I4 => transmitter_baud_divider(16),
I5 => transmitter_baud_divider(18),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_baud_divider(20),
I1 => transmitter_baud_divider(19),
I2 => transmitter_baud_divider(21),
I3 => transmitter_baud_divider(22),
I4 => transmitter_baud_divider(24),
I5 => transmitter_baud_divider(23),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14 : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transmitter_baud_divider(26),
I1 => transmitter_baud_divider(25),
I2 => transmitter_baud_divider(27),
I3 => transmitter_baud_divider(28),
I4 => transmitter_baud_divider(29),
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_15 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_14_363,
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_13_362,
I2 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_12_361,
I3 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_11_360,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(3),
I1 => transmitter_bits_transmitted(30),
I2 => transmitter_bits_transmitted(4),
I3 => transmitter_bits_transmitted(5),
I4 => transmitter_bits_transmitted(6),
I5 => transmitter_bits_transmitted(7),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(9),
I1 => transmitter_bits_transmitted(8),
I2 => transmitter_bits_transmitted(10),
I3 => transmitter_bits_transmitted(11),
I4 => transmitter_bits_transmitted(12),
I5 => transmitter_bits_transmitted(13),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(14),
I1 => transmitter_bits_transmitted(15),
I2 => transmitter_bits_transmitted(16),
I3 => transmitter_bits_transmitted(17),
I4 => transmitter_bits_transmitted(18),
I5 => transmitter_bits_transmitted(19),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => transmitter_bits_transmitted(21),
I1 => transmitter_bits_transmitted(20),
I2 => transmitter_bits_transmitted(22),
I3 => transmitter_bits_transmitted(23),
I4 => transmitter_bits_transmitted(24),
I5 => transmitter_bits_transmitted(25),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => transmitter_bits_transmitted(27),
I1 => transmitter_bits_transmitted(26),
I2 => transmitter_bits_transmitted(28),
I3 => transmitter_bits_transmitted(29),
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_16 : LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_15_368,
I1 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_14_367,
I2 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_11_364,
I3 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_13_366,
I4 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_12_365,
O => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1
);
mojo_tx_OBUF : OBUF
port map (
I => transmitter_tx_out_1,
O => mojo_tx
);
idpromnut_tx_OBUF : OBUF
port map (
I => transmitter_tx_out_1,
O => idpromnut_tx
);
led0_OBUF : OBUF
port map (
I => Mram_n0015_7_0_Q,
O => led0
);
led1_OBUF : OBUF
port map (
I => Mram_n0015_7_0_1,
O => led1
);
led2_OBUF : OBUF
port map (
I => Mram_n0015_7_0_2,
O => led2
);
led3_OBUF : OBUF
port map (
I => Mram_n0015_7_0_3,
O => led3
);
led4_OBUF : OBUF
port map (
I => Mram_n0015_7_0_4,
O => led4
);
led5_OBUF : OBUF
port map (
I => Mram_n0015_7_0_5,
O => led5
);
led6_OBUF : OBUF
port map (
I => Mram_n0015_7_0_6,
O => led6
);
led7_OBUF : OBUF
port map (
I => Mram_n0015_7_0_7,
O => led7
);
Mcount_rom_addr_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(1),
O => Mcount_rom_addr_cy_1_rt_380
);
Mcount_rom_addr_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(2),
O => Mcount_rom_addr_cy_2_rt_381
);
Mcount_rom_addr_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(3),
O => Mcount_rom_addr_cy_3_rt_382
);
Mcount_rom_addr_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(4),
O => Mcount_rom_addr_cy_4_rt_383
);
Mcount_rom_addr_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(5),
O => Mcount_rom_addr_cy_5_rt_384
);
Mcount_rom_addr_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(6),
O => Mcount_rom_addr_cy_6_rt_385
);
Mcount_rom_addr_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(7),
O => Mcount_rom_addr_cy_7_rt_386
);
Mcount_rom_addr_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(8),
O => Mcount_rom_addr_cy_8_rt_387
);
Mcount_rom_addr_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(9),
O => Mcount_rom_addr_cy_9_rt_388
);
Mcount_rom_addr_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(10),
O => Mcount_rom_addr_cy_10_rt_389
);
Mcount_rom_addr_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(11),
O => Mcount_rom_addr_cy_11_rt_390
);
Mcount_rom_addr_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(12),
O => Mcount_rom_addr_cy_12_rt_391
);
Mcount_rom_addr_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(13),
O => Mcount_rom_addr_cy_13_rt_392
);
Mcount_rom_addr_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(14),
O => Mcount_rom_addr_cy_14_rt_393
);
Mcount_rom_addr_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(15),
O => Mcount_rom_addr_cy_15_rt_394
);
Mcount_rom_addr_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(16),
O => Mcount_rom_addr_cy_16_rt_395
);
Mcount_rom_addr_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(17),
O => Mcount_rom_addr_cy_17_rt_396
);
Mcount_rom_addr_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(18),
O => Mcount_rom_addr_cy_18_rt_397
);
Mcount_rom_addr_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(19),
O => Mcount_rom_addr_cy_19_rt_398
);
Mcount_rom_addr_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(20),
O => Mcount_rom_addr_cy_20_rt_399
);
Mcount_rom_addr_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(21),
O => Mcount_rom_addr_cy_21_rt_400
);
Mcount_rom_addr_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(22),
O => Mcount_rom_addr_cy_22_rt_401
);
Mcount_rom_addr_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(23),
O => Mcount_rom_addr_cy_23_rt_402
);
Mcount_rom_addr_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(24),
O => Mcount_rom_addr_cy_24_rt_403
);
Mcount_rom_addr_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(25),
O => Mcount_rom_addr_cy_25_rt_404
);
Mcount_rom_addr_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(26),
O => Mcount_rom_addr_cy_26_rt_405
);
Mcount_rom_addr_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(27),
O => Mcount_rom_addr_cy_27_rt_406
);
Mcount_rom_addr_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(28),
O => Mcount_rom_addr_cy_28_rt_407
);
Mcount_rom_addr_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(29),
O => Mcount_rom_addr_cy_29_rt_408
);
transmitter_Mcount_baud_divider_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(29),
O => transmitter_Mcount_baud_divider_cy_29_rt_409
);
transmitter_Mcount_baud_divider_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(28),
O => transmitter_Mcount_baud_divider_cy_28_rt_410
);
transmitter_Mcount_baud_divider_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(27),
O => transmitter_Mcount_baud_divider_cy_27_rt_411
);
transmitter_Mcount_baud_divider_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(26),
O => transmitter_Mcount_baud_divider_cy_26_rt_412
);
transmitter_Mcount_baud_divider_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(25),
O => transmitter_Mcount_baud_divider_cy_25_rt_413
);
transmitter_Mcount_baud_divider_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(24),
O => transmitter_Mcount_baud_divider_cy_24_rt_414
);
transmitter_Mcount_baud_divider_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(23),
O => transmitter_Mcount_baud_divider_cy_23_rt_415
);
transmitter_Mcount_baud_divider_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(22),
O => transmitter_Mcount_baud_divider_cy_22_rt_416
);
transmitter_Mcount_baud_divider_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(21),
O => transmitter_Mcount_baud_divider_cy_21_rt_417
);
transmitter_Mcount_baud_divider_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(20),
O => transmitter_Mcount_baud_divider_cy_20_rt_418
);
transmitter_Mcount_baud_divider_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(19),
O => transmitter_Mcount_baud_divider_cy_19_rt_419
);
transmitter_Mcount_baud_divider_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(18),
O => transmitter_Mcount_baud_divider_cy_18_rt_420
);
transmitter_Mcount_baud_divider_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(17),
O => transmitter_Mcount_baud_divider_cy_17_rt_421
);
transmitter_Mcount_baud_divider_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(16),
O => transmitter_Mcount_baud_divider_cy_16_rt_422
);
transmitter_Mcount_baud_divider_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(15),
O => transmitter_Mcount_baud_divider_cy_15_rt_423
);
transmitter_Mcount_baud_divider_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(14),
O => transmitter_Mcount_baud_divider_cy_14_rt_424
);
transmitter_Mcount_baud_divider_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(13),
O => transmitter_Mcount_baud_divider_cy_13_rt_425
);
transmitter_Mcount_baud_divider_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(12),
O => transmitter_Mcount_baud_divider_cy_12_rt_426
);
transmitter_Mcount_baud_divider_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(11),
O => transmitter_Mcount_baud_divider_cy_11_rt_427
);
transmitter_Mcount_baud_divider_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(10),
O => transmitter_Mcount_baud_divider_cy_10_rt_428
);
transmitter_Mcount_baud_divider_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(9),
O => transmitter_Mcount_baud_divider_cy_9_rt_429
);
transmitter_Mcount_baud_divider_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(8),
O => transmitter_Mcount_baud_divider_cy_8_rt_430
);
transmitter_Mcount_baud_divider_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(7),
O => transmitter_Mcount_baud_divider_cy_7_rt_431
);
transmitter_Mcount_baud_divider_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(6),
O => transmitter_Mcount_baud_divider_cy_6_rt_432
);
transmitter_Mcount_baud_divider_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(5),
O => transmitter_Mcount_baud_divider_cy_5_rt_433
);
transmitter_Mcount_baud_divider_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(4),
O => transmitter_Mcount_baud_divider_cy_4_rt_434
);
transmitter_Mcount_baud_divider_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(3),
O => transmitter_Mcount_baud_divider_cy_3_rt_435
);
transmitter_Mcount_baud_divider_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(2),
O => transmitter_Mcount_baud_divider_cy_2_rt_436
);
transmitter_Mcount_baud_divider_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(1),
O => transmitter_Mcount_baud_divider_cy_1_rt_437
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(29),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_29_rt_438
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(28),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_28_rt_439
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(27),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_27_rt_440
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(26),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_26_rt_441
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(25),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_25_rt_442
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(24),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_24_rt_443
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(23),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_23_rt_444
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(22),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_22_rt_445
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(21),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_21_rt_446
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(20),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_20_rt_447
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(19),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_19_rt_448
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(18),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_18_rt_449
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(17),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_17_rt_450
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(16),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_16_rt_451
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(15),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_15_rt_452
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(14),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_14_rt_453
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(13),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_13_rt_454
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(12),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_12_rt_455
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(11),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_11_rt_456
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(10),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_10_rt_457
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(9),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_9_rt_458
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(8),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_8_rt_459
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(7),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_7_rt_460
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(6),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_6_rt_461
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(5),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_5_rt_462
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(4),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_4_rt_463
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(3),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_3_rt_464
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(2),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_2_rt_465
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(1),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_cy_1_rt_466
);
Mcount_rom_addr_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rom_addr(30),
O => Mcount_rom_addr_xor_30_rt_467
);
transmitter_Mcount_baud_divider_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_baud_divider(30),
O => transmitter_Mcount_baud_divider_xor_30_rt_468
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_bits_transmitted(30),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_xor_30_rt_469
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_SW0 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => transmitter_baud_clk_edge_1_504,
I1 => transmitter_state_FSM_FFd1_344,
O => N7
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111 : LUT6
generic map(
INIT => X"1555555455555555"
)
port map (
I0 => N7,
I1 => transmitter_bits_transmitted(0),
I2 => transmitter_bits_transmitted(2),
I3 => transmitter_bits_transmitted(1),
I4 => transmitter_state_FSM_FFd2_204,
I5 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
O => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT111_110
);
transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_2_SW0 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => transmitter_bits_transmitted(1),
I1 => transmitter_bits_transmitted(2),
O => N9
);
transmitter_state_FSM_FFd1_In1 : LUT6
generic map(
INIT => X"EEEEEEEEAAAAAA2A"
)
port map (
I0 => transmitter_state_FSM_FFd1_344,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
I3 => transmitter_bits_transmitted(0),
I4 => N9,
I5 => transmitter_state_FSM_FFd2_204,
O => transmitter_state_FSM_FFd1_In
);
transmitter_GND_5_o_bits_transmitted_30_equal_8_o_30_1_SW0 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => transmitter_bits_transmitted(0),
I1 => transmitter_bits_transmitted(1),
I2 => transmitter_bits_transmitted(2),
O => N11
);
transmitter_state_FSM_FFd2_In1 : LUT6
generic map(
INIT => X"2EAEAEAE2AAAAAAA"
)
port map (
I0 => transmitter_state_FSM_FFd2_204,
I1 => transmitter_baud_clk_edge_342,
I2 => transmitter_state_FSM_FFd1_344,
I3 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
I4 => N11,
I5 => transmitter_ready_2,
O => transmitter_state_FSM_FFd2_In
);
transmitter_baud_divider_30_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(30),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_30_rstpot_473
);
transmitter_baud_divider_30 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_30_rstpot_473,
Q => transmitter_baud_divider(30)
);
transmitter_baud_divider_29_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(29),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_29_rstpot_474
);
transmitter_baud_divider_29 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_29_rstpot_474,
Q => transmitter_baud_divider(29)
);
transmitter_baud_divider_28_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(28),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_28_rstpot_475
);
transmitter_baud_divider_28 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_28_rstpot_475,
Q => transmitter_baud_divider(28)
);
transmitter_baud_divider_27_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(27),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_27_rstpot_476
);
transmitter_baud_divider_27 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_27_rstpot_476,
Q => transmitter_baud_divider(27)
);
transmitter_baud_divider_26_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(26),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_26_rstpot_477
);
transmitter_baud_divider_26 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_26_rstpot_477,
Q => transmitter_baud_divider(26)
);
transmitter_baud_divider_25_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(25),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_25_rstpot_478
);
transmitter_baud_divider_25 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_25_rstpot_478,
Q => transmitter_baud_divider(25)
);
transmitter_baud_divider_24_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(24),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_24_rstpot_479
);
transmitter_baud_divider_24 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_24_rstpot_479,
Q => transmitter_baud_divider(24)
);
transmitter_baud_divider_23_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(23),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_23_rstpot_480
);
transmitter_baud_divider_23 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_23_rstpot_480,
Q => transmitter_baud_divider(23)
);
transmitter_baud_divider_22_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(22),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_22_rstpot_481
);
transmitter_baud_divider_22 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_22_rstpot_481,
Q => transmitter_baud_divider(22)
);
transmitter_baud_divider_21_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(21),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_21_rstpot_482
);
transmitter_baud_divider_21 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_21_rstpot_482,
Q => transmitter_baud_divider(21)
);
transmitter_baud_divider_20_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(20),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_20_rstpot_483
);
transmitter_baud_divider_20 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_20_rstpot_483,
Q => transmitter_baud_divider(20)
);
transmitter_baud_divider_19_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(19),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_19_rstpot_484
);
transmitter_baud_divider_19 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_19_rstpot_484,
Q => transmitter_baud_divider(19)
);
transmitter_baud_divider_18_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(18),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_18_rstpot_485
);
transmitter_baud_divider_18 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_18_rstpot_485,
Q => transmitter_baud_divider(18)
);
transmitter_baud_divider_17_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(17),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_17_rstpot_486
);
transmitter_baud_divider_17 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_17_rstpot_486,
Q => transmitter_baud_divider(17)
);
transmitter_baud_divider_16_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(16),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_16_rstpot_487
);
transmitter_baud_divider_16 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_16_rstpot_487,
Q => transmitter_baud_divider(16)
);
transmitter_baud_divider_15_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(15),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o,
O => transmitter_baud_divider_15_rstpot_488
);
transmitter_baud_divider_15 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_15_rstpot_488,
Q => transmitter_baud_divider(15)
);
transmitter_baud_divider_14_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(14),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_14_rstpot_489
);
transmitter_baud_divider_14 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_14_rstpot_489,
Q => transmitter_baud_divider(14)
);
transmitter_baud_divider_13_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(13),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_13_rstpot_490
);
transmitter_baud_divider_13 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_13_rstpot_490,
Q => transmitter_baud_divider(13)
);
transmitter_baud_divider_12_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(12),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_12_rstpot_491
);
transmitter_baud_divider_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_12_rstpot_491,
Q => transmitter_baud_divider(12)
);
transmitter_baud_divider_11_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(11),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_11_rstpot_492
);
transmitter_baud_divider_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_11_rstpot_492,
Q => transmitter_baud_divider(11)
);
transmitter_baud_divider_10_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(10),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_10_rstpot_493
);
transmitter_baud_divider_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_10_rstpot_493,
Q => transmitter_baud_divider(10)
);
transmitter_baud_divider_9_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(9),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_9_rstpot_494
);
transmitter_baud_divider_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_9_rstpot_494,
Q => transmitter_baud_divider(9)
);
transmitter_baud_divider_8_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(8),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_8_rstpot_495
);
transmitter_baud_divider_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_8_rstpot_495,
Q => transmitter_baud_divider(8)
);
transmitter_baud_divider_7_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(7),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_7_rstpot_496
);
transmitter_baud_divider_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_7_rstpot_496,
Q => transmitter_baud_divider(7)
);
transmitter_baud_divider_6_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(6),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_6_rstpot_497
);
transmitter_baud_divider_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_6_rstpot_497,
Q => transmitter_baud_divider(6)
);
transmitter_baud_divider_5_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(5),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_5_rstpot_498
);
transmitter_baud_divider_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_5_rstpot_498,
Q => transmitter_baud_divider(5)
);
transmitter_baud_divider_4_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(4),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_4_rstpot_499
);
transmitter_baud_divider_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_4_rstpot_499,
Q => transmitter_baud_divider(4)
);
transmitter_baud_divider_3_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(3),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_3_rstpot_500
);
transmitter_baud_divider_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_3_rstpot_500,
Q => transmitter_baud_divider(3)
);
transmitter_baud_divider_2_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(2),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_2_rstpot_501
);
transmitter_baud_divider_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_2_rstpot_501,
Q => transmitter_baud_divider(2)
);
transmitter_baud_divider_1_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(1),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_1_rstpot_502
);
transmitter_baud_divider_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_1_rstpot_502,
Q => transmitter_baud_divider(1)
);
transmitter_baud_divider_0_rstpot : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transmitter_Result(0),
I1 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506,
O => transmitter_baud_divider_0_rstpot_503
);
transmitter_baud_divider_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_baud_divider_0_rstpot_503,
Q => transmitter_baud_divider(0)
);
transmitter_baud_clk_edge_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
D => transmitter_GND_5_o_baud_divider_30_equal_4_o,
Q => transmitter_baud_clk_edge_1_504
);
transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_1 : LUT6
generic map(
INIT => X"1555555455555555"
)
port map (
I0 => N7,
I1 => transmitter_bits_transmitted(0),
I2 => transmitter_bits_transmitted(2),
I3 => transmitter_bits_transmitted(1),
I4 => transmitter_state_FSM_FFd2_204,
I5 => transmitter_GND_5_o_bits_transmitted_30_equal_14_o_30_1,
O => transmitter_Mmux_state_1_bits_transmitted_30_wide_mux_19_OUT1111_505
);
transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1 : LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => transmitter_baud_divider(10),
I1 => transmitter_baud_divider(12),
I2 => transmitter_baud_divider(4),
I3 => transmitter_baud_divider(6),
I4 => N5,
I5 => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_1_108,
O => transmitter_GND_5_o_baud_divider_30_equal_1_o_30_Q_506
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_0
);
Mcount_rom_addr_lut_0_INV_0 : INV
port map (
I => rom_addr(0),
O => Mcount_rom_addr_lut(0)
);
transmitter_Mcount_baud_divider_lut_0_INV_0 : INV
port map (
I => transmitter_baud_divider(0),
O => transmitter_Mcount_baud_divider_lut(0)
);
transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_INV_0 : INV
port map (
I => transmitter_bits_transmitted(0),
O => transmitter_Madd_bits_transmitted_30_GND_5_o_add_14_OUT_lut_0_Q
);
end Structure;
| mit | 40dfa4b69e7652ec57d17d819627c358 | 0.608754 | 2.868619 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_FIFO_576s.vhd | 1 | 2,947 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_FIFO_576s is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
SOFT_RST : in STD_LOGIC;
LIMIT_WE : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture aQ16_8_FIFO_576s of Q16_8_FIFO_576s is
type ram_type is array (0 to 576-1) of STD_LOGIC_VECTOR (15 downto 0);
signal RAM : ram_type;
SIGNAL READ_C : UNSIGNED(9 downto 0);
SIGNAL WRITE_C : UNSIGNED(9 downto 0);
BEGIN
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(9 downto 0);
begin
if reset = '0' then
WRITE_C <= TO_UNSIGNED(0, 10);
elsif clock'event and clock = '1' then
if soft_rst = '1' then
WRITE_C <= TO_UNSIGNED(0, 10);
elsif write_en = '1' AND holdn = '1' then
TEMP := WRITE_C + TO_UNSIGNED(1, 10);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 10);
END IF;
WRITE_C <= TEMP;
else
WRITE_C <= WRITE_C;
end if;
end if;
end process;
--
-- COMPTEUR EN CHARGE DE LA GENERATION DE L'ADRESSE DES DONNEES
-- A LIRE DANS LA MEMOIRE (ACCES LINAIRE DE 0 => 575)
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(9 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 10);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
-- synthesis translate_off
-- printmsg("(Q16_8_RAM_576s) ===> READING (" & to_int_str( STD_LOGIC_VECTOR( RAM( to_integer(TEMP) ) ), 6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(TEMP),6) );
-- synthesis translate_on
TEMP := TEMP + TO_UNSIGNED(1, 10);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 10);
END IF;
end if;
READ_C <= TEMP;
OUTPUT_1 <= STD_LOGIC_VECTOR(RESIZE( SIGNED(RAM( to_integer(TEMP) )), 32));
end if;
end process;
--
--
--
process(clock)
VARIABLE AR : INTEGER RANGE 0 to 575;
VARIABLE AW : INTEGER RANGE 0 to 575;
begin
if clock'event and clock = '1' then
--AR := to_integer( READ_C );
if WRITE_EN = '1' AND holdn = '1' then
AW := to_integer( WRITE_C );
RAM( AW ) <= INPUT_1(15 downto 0);
-- synthesis translate_off
-- printmsg("(Q16_8_RAM_576s) ===> WRITING (" & to_int_str( STD_LOGIC_VECTOR(INPUT_1(15 downto 0)),6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(WRITE_C),6) );
-- synthesis translate_on
end if;
end if;
end process;
END aQ16_8_RAM_576s; | gpl-3.0 | 33408df59492b712940f4a0f3398f170 | 0.557516 | 2.938185 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_OPR_VtoC_RAM.vhd | 1 | 46,921 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_opr_VtoC_RAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_opr_VtoC_RAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
type rom_type is array (0 to 1824-1) of UNSIGNED (10 downto 0);
signal RAM : ram_type;
constant ROM : rom_type:= (
TO_UNSIGNED( 114, 11), TO_UNSIGNED( 174, 11), TO_UNSIGNED( 342, 11), TO_UNSIGNED( 444, 11), TO_UNSIGNED( 636, 11), TO_UNSIGNED( 930, 11), TO_UNSIGNED( 810, 11), TO_UNSIGNED(1026, 11),
TO_UNSIGNED(1152, 11), TO_UNSIGNED(1467, 11), TO_UNSIGNED(1600, 11), TO_UNSIGNED(1719, 11), TO_UNSIGNED( 18, 11), TO_UNSIGNED(1027, 11), TO_UNSIGNED(1502, 11), TO_UNSIGNED( 24, 11),
TO_UNSIGNED(1032, 11), TO_UNSIGNED(1509, 11), TO_UNSIGNED( 30, 11), TO_UNSIGNED(1038, 11), TO_UNSIGNED(1516, 11), TO_UNSIGNED( 36, 11), TO_UNSIGNED(1044, 11), TO_UNSIGNED(1523, 11),
TO_UNSIGNED( 42, 11), TO_UNSIGNED(1050, 11), TO_UNSIGNED(1530, 11), TO_UNSIGNED( 48, 11), TO_UNSIGNED(1056, 11), TO_UNSIGNED(1537, 11), TO_UNSIGNED( 54, 11), TO_UNSIGNED(1062, 11),
TO_UNSIGNED(1544, 11), TO_UNSIGNED( 60, 11), TO_UNSIGNED(1068, 11), TO_UNSIGNED(1551, 11), TO_UNSIGNED( 66, 11), TO_UNSIGNED(1074, 11), TO_UNSIGNED(1558, 11), TO_UNSIGNED( 72, 11),
TO_UNSIGNED(1080, 11), TO_UNSIGNED(1565, 11), TO_UNSIGNED( 78, 11), TO_UNSIGNED(1086, 11), TO_UNSIGNED(1572, 11), TO_UNSIGNED( 84, 11), TO_UNSIGNED(1092, 11), TO_UNSIGNED(1579, 11),
TO_UNSIGNED( 90, 11), TO_UNSIGNED(1098, 11), TO_UNSIGNED(1586, 11), TO_UNSIGNED( 96, 11), TO_UNSIGNED(1104, 11), TO_UNSIGNED(1593, 11), TO_UNSIGNED( 102, 11), TO_UNSIGNED(1110, 11),
TO_UNSIGNED(1601, 11), TO_UNSIGNED( 108, 11), TO_UNSIGNED(1116, 11), TO_UNSIGNED(1607, 11), TO_UNSIGNED( 115, 11), TO_UNSIGNED(1122, 11), TO_UNSIGNED(1614, 11), TO_UNSIGNED( 120, 11),
TO_UNSIGNED(1128, 11), TO_UNSIGNED(1621, 11), TO_UNSIGNED( 126, 11), TO_UNSIGNED(1134, 11), TO_UNSIGNED(1628, 11), TO_UNSIGNED( 132, 11), TO_UNSIGNED(1140, 11), TO_UNSIGNED(1635, 11),
TO_UNSIGNED( 138, 11), TO_UNSIGNED(1146, 11), TO_UNSIGNED(1642, 11), TO_UNSIGNED( 0, 11), TO_UNSIGNED(1008, 11), TO_UNSIGNED(1649, 11), TO_UNSIGNED( 798, 11), TO_UNSIGNED(1063, 11),
TO_UNSIGNED(1159, 11), TO_UNSIGNED(1369, 11), TO_UNSIGNED(1622, 11), TO_UNSIGNED(1720, 11), TO_UNSIGNED( 6, 11), TO_UNSIGNED(1160, 11), TO_UNSIGNED( 12, 11), TO_UNSIGNED(1166, 11),
TO_UNSIGNED( 19, 11), TO_UNSIGNED(1173, 11), TO_UNSIGNED( 25, 11), TO_UNSIGNED(1180, 11), TO_UNSIGNED( 31, 11), TO_UNSIGNED(1187, 11), TO_UNSIGNED( 37, 11), TO_UNSIGNED(1194, 11),
TO_UNSIGNED( 43, 11), TO_UNSIGNED(1201, 11), TO_UNSIGNED( 49, 11), TO_UNSIGNED(1208, 11), TO_UNSIGNED( 55, 11), TO_UNSIGNED(1215, 11), TO_UNSIGNED( 61, 11), TO_UNSIGNED(1222, 11),
TO_UNSIGNED( 67, 11), TO_UNSIGNED(1229, 11), TO_UNSIGNED( 73, 11), TO_UNSIGNED(1236, 11), TO_UNSIGNED( 79, 11), TO_UNSIGNED(1243, 11), TO_UNSIGNED( 85, 11), TO_UNSIGNED(1250, 11),
TO_UNSIGNED( 91, 11), TO_UNSIGNED(1257, 11), TO_UNSIGNED( 97, 11), TO_UNSIGNED(1264, 11), TO_UNSIGNED( 103, 11), TO_UNSIGNED(1271, 11), TO_UNSIGNED( 109, 11), TO_UNSIGNED(1278, 11),
TO_UNSIGNED( 116, 11), TO_UNSIGNED(1285, 11), TO_UNSIGNED( 121, 11), TO_UNSIGNED(1292, 11), TO_UNSIGNED( 127, 11), TO_UNSIGNED(1299, 11), TO_UNSIGNED( 133, 11), TO_UNSIGNED(1306, 11),
TO_UNSIGNED( 139, 11), TO_UNSIGNED(1313, 11), TO_UNSIGNED( 792, 11), TO_UNSIGNED(1057, 11), TO_UNSIGNED(1153, 11), TO_UNSIGNED(1362, 11), TO_UNSIGNED(1615, 11), TO_UNSIGNED(1712, 11),
TO_UNSIGNED( 822, 11), TO_UNSIGNED(1039, 11), TO_UNSIGNED(1167, 11), TO_UNSIGNED(1481, 11), TO_UNSIGNED(1616, 11), TO_UNSIGNED(1733, 11), TO_UNSIGNED(1168, 11), TO_UNSIGNED(1334, 11),
TO_UNSIGNED(1174, 11), TO_UNSIGNED(1341, 11), TO_UNSIGNED(1181, 11), TO_UNSIGNED(1348, 11), TO_UNSIGNED(1188, 11), TO_UNSIGNED(1355, 11), TO_UNSIGNED(1195, 11), TO_UNSIGNED(1363, 11),
TO_UNSIGNED(1202, 11), TO_UNSIGNED(1370, 11), TO_UNSIGNED(1209, 11), TO_UNSIGNED(1376, 11), TO_UNSIGNED(1216, 11), TO_UNSIGNED(1383, 11), TO_UNSIGNED(1223, 11), TO_UNSIGNED(1390, 11),
TO_UNSIGNED(1230, 11), TO_UNSIGNED(1397, 11), TO_UNSIGNED(1237, 11), TO_UNSIGNED(1404, 11), TO_UNSIGNED(1244, 11), TO_UNSIGNED(1411, 11), TO_UNSIGNED(1251, 11), TO_UNSIGNED(1418, 11),
TO_UNSIGNED(1258, 11), TO_UNSIGNED(1425, 11), TO_UNSIGNED(1265, 11), TO_UNSIGNED(1432, 11), TO_UNSIGNED(1272, 11), TO_UNSIGNED(1439, 11), TO_UNSIGNED(1279, 11), TO_UNSIGNED(1446, 11),
TO_UNSIGNED(1286, 11), TO_UNSIGNED(1453, 11), TO_UNSIGNED(1293, 11), TO_UNSIGNED(1460, 11), TO_UNSIGNED(1300, 11), TO_UNSIGNED(1468, 11), TO_UNSIGNED(1307, 11), TO_UNSIGNED(1474, 11),
TO_UNSIGNED(1314, 11), TO_UNSIGNED(1482, 11), TO_UNSIGNED( 144, 11), TO_UNSIGNED(1320, 11), TO_UNSIGNED( 150, 11), TO_UNSIGNED(1327, 11), TO_UNSIGNED( 156, 11), TO_UNSIGNED(1335, 11),
TO_UNSIGNED( 162, 11), TO_UNSIGNED(1342, 11), TO_UNSIGNED( 168, 11), TO_UNSIGNED(1349, 11), TO_UNSIGNED( 175, 11), TO_UNSIGNED(1356, 11), TO_UNSIGNED( 180, 11), TO_UNSIGNED(1364, 11),
TO_UNSIGNED( 186, 11), TO_UNSIGNED(1371, 11), TO_UNSIGNED( 192, 11), TO_UNSIGNED(1377, 11), TO_UNSIGNED( 198, 11), TO_UNSIGNED(1384, 11), TO_UNSIGNED( 204, 11), TO_UNSIGNED(1391, 11),
TO_UNSIGNED( 210, 11), TO_UNSIGNED(1398, 11), TO_UNSIGNED( 216, 11), TO_UNSIGNED(1405, 11), TO_UNSIGNED( 222, 11), TO_UNSIGNED(1412, 11), TO_UNSIGNED( 228, 11), TO_UNSIGNED(1419, 11),
TO_UNSIGNED( 234, 11), TO_UNSIGNED(1426, 11), TO_UNSIGNED( 240, 11), TO_UNSIGNED(1433, 11), TO_UNSIGNED( 246, 11), TO_UNSIGNED(1440, 11), TO_UNSIGNED( 252, 11), TO_UNSIGNED(1447, 11),
TO_UNSIGNED( 258, 11), TO_UNSIGNED(1454, 11), TO_UNSIGNED( 264, 11), TO_UNSIGNED(1461, 11), TO_UNSIGNED( 270, 11), TO_UNSIGNED(1469, 11), TO_UNSIGNED( 276, 11), TO_UNSIGNED(1475, 11),
TO_UNSIGNED( 282, 11), TO_UNSIGNED(1483, 11), TO_UNSIGNED( 145, 11), TO_UNSIGNED( 288, 11), TO_UNSIGNED( 151, 11), TO_UNSIGNED( 294, 11), TO_UNSIGNED( 157, 11), TO_UNSIGNED( 300, 11),
TO_UNSIGNED( 163, 11), TO_UNSIGNED( 306, 11), TO_UNSIGNED( 169, 11), TO_UNSIGNED( 312, 11), TO_UNSIGNED( 176, 11), TO_UNSIGNED( 318, 11), TO_UNSIGNED( 181, 11), TO_UNSIGNED( 324, 11),
TO_UNSIGNED( 187, 11), TO_UNSIGNED( 330, 11), TO_UNSIGNED( 193, 11), TO_UNSIGNED( 336, 11), TO_UNSIGNED( 199, 11), TO_UNSIGNED( 343, 11), TO_UNSIGNED( 205, 11), TO_UNSIGNED( 348, 11),
TO_UNSIGNED( 211, 11), TO_UNSIGNED( 354, 11), TO_UNSIGNED( 217, 11), TO_UNSIGNED( 360, 11), TO_UNSIGNED( 223, 11), TO_UNSIGNED( 366, 11), TO_UNSIGNED( 229, 11), TO_UNSIGNED( 372, 11),
TO_UNSIGNED( 235, 11), TO_UNSIGNED( 378, 11), TO_UNSIGNED( 241, 11), TO_UNSIGNED( 384, 11), TO_UNSIGNED( 247, 11), TO_UNSIGNED( 390, 11), TO_UNSIGNED( 253, 11), TO_UNSIGNED( 396, 11),
TO_UNSIGNED( 259, 11), TO_UNSIGNED( 402, 11), TO_UNSIGNED( 265, 11), TO_UNSIGNED( 408, 11), TO_UNSIGNED( 271, 11), TO_UNSIGNED( 414, 11), TO_UNSIGNED( 277, 11), TO_UNSIGNED( 420, 11),
TO_UNSIGNED( 283, 11), TO_UNSIGNED( 426, 11), TO_UNSIGNED( 289, 11), TO_UNSIGNED(1488, 11), TO_UNSIGNED( 295, 11), TO_UNSIGNED(1495, 11), TO_UNSIGNED( 301, 11), TO_UNSIGNED(1503, 11),
TO_UNSIGNED( 307, 11), TO_UNSIGNED(1510, 11), TO_UNSIGNED( 313, 11), TO_UNSIGNED(1517, 11), TO_UNSIGNED( 319, 11), TO_UNSIGNED(1524, 11), TO_UNSIGNED( 325, 11), TO_UNSIGNED(1531, 11),
TO_UNSIGNED( 331, 11), TO_UNSIGNED(1538, 11), TO_UNSIGNED( 337, 11), TO_UNSIGNED(1545, 11), TO_UNSIGNED( 344, 11), TO_UNSIGNED(1552, 11), TO_UNSIGNED( 349, 11), TO_UNSIGNED(1559, 11),
TO_UNSIGNED( 355, 11), TO_UNSIGNED(1566, 11), TO_UNSIGNED( 361, 11), TO_UNSIGNED(1573, 11), TO_UNSIGNED( 367, 11), TO_UNSIGNED(1580, 11), TO_UNSIGNED( 373, 11), TO_UNSIGNED(1587, 11),
TO_UNSIGNED( 379, 11), TO_UNSIGNED(1594, 11), TO_UNSIGNED( 385, 11), TO_UNSIGNED(1602, 11), TO_UNSIGNED( 391, 11), TO_UNSIGNED(1608, 11), TO_UNSIGNED( 397, 11), TO_UNSIGNED(1617, 11),
TO_UNSIGNED( 403, 11), TO_UNSIGNED(1623, 11), TO_UNSIGNED( 409, 11), TO_UNSIGNED(1629, 11), TO_UNSIGNED( 415, 11), TO_UNSIGNED(1636, 11), TO_UNSIGNED( 421, 11), TO_UNSIGNED(1643, 11),
TO_UNSIGNED( 427, 11), TO_UNSIGNED(1650, 11), TO_UNSIGNED( 432, 11), TO_UNSIGNED(1489, 11), TO_UNSIGNED( 438, 11), TO_UNSIGNED(1496, 11), TO_UNSIGNED( 445, 11), TO_UNSIGNED(1504, 11),
TO_UNSIGNED( 450, 11), TO_UNSIGNED(1511, 11), TO_UNSIGNED( 456, 11), TO_UNSIGNED(1518, 11), TO_UNSIGNED( 462, 11), TO_UNSIGNED(1525, 11), TO_UNSIGNED( 468, 11), TO_UNSIGNED(1532, 11),
TO_UNSIGNED( 474, 11), TO_UNSIGNED(1539, 11), TO_UNSIGNED( 480, 11), TO_UNSIGNED(1546, 11), TO_UNSIGNED( 486, 11), TO_UNSIGNED(1553, 11), TO_UNSIGNED( 492, 11), TO_UNSIGNED(1560, 11),
TO_UNSIGNED( 498, 11), TO_UNSIGNED(1567, 11), TO_UNSIGNED( 504, 11), TO_UNSIGNED(1574, 11), TO_UNSIGNED( 510, 11), TO_UNSIGNED(1581, 11), TO_UNSIGNED( 516, 11), TO_UNSIGNED(1588, 11),
TO_UNSIGNED( 522, 11), TO_UNSIGNED(1595, 11), TO_UNSIGNED( 528, 11), TO_UNSIGNED(1603, 11), TO_UNSIGNED( 534, 11), TO_UNSIGNED(1609, 11), TO_UNSIGNED( 540, 11), TO_UNSIGNED(1618, 11),
TO_UNSIGNED( 546, 11), TO_UNSIGNED(1624, 11), TO_UNSIGNED( 552, 11), TO_UNSIGNED(1630, 11), TO_UNSIGNED( 558, 11), TO_UNSIGNED(1637, 11), TO_UNSIGNED( 564, 11), TO_UNSIGNED(1644, 11),
TO_UNSIGNED( 570, 11), TO_UNSIGNED(1651, 11), TO_UNSIGNED( 433, 11), TO_UNSIGNED( 576, 11), TO_UNSIGNED( 439, 11), TO_UNSIGNED( 582, 11), TO_UNSIGNED( 446, 11), TO_UNSIGNED( 588, 11),
TO_UNSIGNED( 451, 11), TO_UNSIGNED( 594, 11), TO_UNSIGNED( 457, 11), TO_UNSIGNED( 600, 11), TO_UNSIGNED( 463, 11), TO_UNSIGNED( 606, 11), TO_UNSIGNED( 469, 11), TO_UNSIGNED( 612, 11),
TO_UNSIGNED( 475, 11), TO_UNSIGNED( 618, 11), TO_UNSIGNED( 481, 11), TO_UNSIGNED( 624, 11), TO_UNSIGNED( 487, 11), TO_UNSIGNED( 630, 11), TO_UNSIGNED( 493, 11), TO_UNSIGNED( 637, 11),
TO_UNSIGNED( 499, 11), TO_UNSIGNED( 642, 11), TO_UNSIGNED( 505, 11), TO_UNSIGNED( 648, 11), TO_UNSIGNED( 511, 11), TO_UNSIGNED( 654, 11), TO_UNSIGNED( 517, 11), TO_UNSIGNED( 660, 11),
TO_UNSIGNED( 523, 11), TO_UNSIGNED( 666, 11), TO_UNSIGNED( 529, 11), TO_UNSIGNED( 672, 11), TO_UNSIGNED( 535, 11), TO_UNSIGNED( 678, 11), TO_UNSIGNED( 541, 11), TO_UNSIGNED( 684, 11),
TO_UNSIGNED( 547, 11), TO_UNSIGNED( 690, 11), TO_UNSIGNED( 553, 11), TO_UNSIGNED( 696, 11), TO_UNSIGNED( 559, 11), TO_UNSIGNED( 702, 11), TO_UNSIGNED( 565, 11), TO_UNSIGNED( 708, 11),
TO_UNSIGNED( 571, 11), TO_UNSIGNED( 714, 11), TO_UNSIGNED( 577, 11), TO_UNSIGNED(1656, 11), TO_UNSIGNED( 583, 11), TO_UNSIGNED(1663, 11), TO_UNSIGNED( 589, 11), TO_UNSIGNED(1670, 11),
TO_UNSIGNED( 595, 11), TO_UNSIGNED(1677, 11), TO_UNSIGNED( 601, 11), TO_UNSIGNED(1684, 11), TO_UNSIGNED( 607, 11), TO_UNSIGNED(1691, 11), TO_UNSIGNED( 613, 11), TO_UNSIGNED(1698, 11),
TO_UNSIGNED( 619, 11), TO_UNSIGNED(1705, 11), TO_UNSIGNED( 625, 11), TO_UNSIGNED(1713, 11), TO_UNSIGNED( 631, 11), TO_UNSIGNED(1721, 11), TO_UNSIGNED( 638, 11), TO_UNSIGNED(1726, 11),
TO_UNSIGNED( 643, 11), TO_UNSIGNED(1734, 11), TO_UNSIGNED( 649, 11), TO_UNSIGNED(1740, 11), TO_UNSIGNED( 655, 11), TO_UNSIGNED(1747, 11), TO_UNSIGNED( 661, 11), TO_UNSIGNED(1754, 11),
TO_UNSIGNED( 667, 11), TO_UNSIGNED(1761, 11), TO_UNSIGNED( 673, 11), TO_UNSIGNED(1768, 11), TO_UNSIGNED( 679, 11), TO_UNSIGNED(1775, 11), TO_UNSIGNED( 685, 11), TO_UNSIGNED(1782, 11),
TO_UNSIGNED( 691, 11), TO_UNSIGNED(1789, 11), TO_UNSIGNED( 697, 11), TO_UNSIGNED(1796, 11), TO_UNSIGNED( 703, 11), TO_UNSIGNED(1803, 11), TO_UNSIGNED( 709, 11), TO_UNSIGNED(1810, 11),
TO_UNSIGNED( 715, 11), TO_UNSIGNED(1817, 11), TO_UNSIGNED( 720, 11), TO_UNSIGNED(1657, 11), TO_UNSIGNED( 726, 11), TO_UNSIGNED(1664, 11), TO_UNSIGNED( 732, 11), TO_UNSIGNED(1671, 11),
TO_UNSIGNED( 738, 11), TO_UNSIGNED(1678, 11), TO_UNSIGNED( 744, 11), TO_UNSIGNED(1685, 11), TO_UNSIGNED( 750, 11), TO_UNSIGNED(1692, 11), TO_UNSIGNED( 756, 11), TO_UNSIGNED(1699, 11),
TO_UNSIGNED( 762, 11), TO_UNSIGNED(1706, 11), TO_UNSIGNED( 768, 11), TO_UNSIGNED(1714, 11), TO_UNSIGNED( 774, 11), TO_UNSIGNED(1722, 11), TO_UNSIGNED( 780, 11), TO_UNSIGNED(1727, 11),
TO_UNSIGNED( 786, 11), TO_UNSIGNED(1735, 11), TO_UNSIGNED( 793, 11), TO_UNSIGNED(1741, 11), TO_UNSIGNED( 799, 11), TO_UNSIGNED(1748, 11), TO_UNSIGNED( 804, 11), TO_UNSIGNED(1755, 11),
TO_UNSIGNED( 811, 11), TO_UNSIGNED(1762, 11), TO_UNSIGNED( 816, 11), TO_UNSIGNED(1769, 11), TO_UNSIGNED( 823, 11), TO_UNSIGNED(1776, 11), TO_UNSIGNED( 828, 11), TO_UNSIGNED(1783, 11),
TO_UNSIGNED( 834, 11), TO_UNSIGNED(1790, 11), TO_UNSIGNED( 840, 11), TO_UNSIGNED(1797, 11), TO_UNSIGNED( 846, 11), TO_UNSIGNED(1804, 11), TO_UNSIGNED( 852, 11), TO_UNSIGNED(1811, 11),
TO_UNSIGNED( 858, 11), TO_UNSIGNED(1818, 11), TO_UNSIGNED( 721, 11), TO_UNSIGNED( 864, 11), TO_UNSIGNED( 727, 11), TO_UNSIGNED( 870, 11), TO_UNSIGNED( 733, 11), TO_UNSIGNED( 876, 11),
TO_UNSIGNED( 739, 11), TO_UNSIGNED( 882, 11), TO_UNSIGNED( 745, 11), TO_UNSIGNED( 888, 11), TO_UNSIGNED( 751, 11), TO_UNSIGNED( 894, 11), TO_UNSIGNED( 757, 11), TO_UNSIGNED( 900, 11),
TO_UNSIGNED( 763, 11), TO_UNSIGNED( 906, 11), TO_UNSIGNED( 769, 11), TO_UNSIGNED( 912, 11), TO_UNSIGNED( 775, 11), TO_UNSIGNED( 918, 11), TO_UNSIGNED( 781, 11), TO_UNSIGNED( 924, 11),
TO_UNSIGNED( 787, 11), TO_UNSIGNED( 931, 11), TO_UNSIGNED( 794, 11), TO_UNSIGNED( 936, 11), TO_UNSIGNED( 800, 11), TO_UNSIGNED( 942, 11), TO_UNSIGNED( 805, 11), TO_UNSIGNED( 948, 11),
TO_UNSIGNED( 812, 11), TO_UNSIGNED( 954, 11), TO_UNSIGNED( 817, 11), TO_UNSIGNED( 960, 11), TO_UNSIGNED( 824, 11), TO_UNSIGNED( 966, 11), TO_UNSIGNED( 829, 11), TO_UNSIGNED( 972, 11),
TO_UNSIGNED( 835, 11), TO_UNSIGNED( 978, 11), TO_UNSIGNED( 841, 11), TO_UNSIGNED( 984, 11), TO_UNSIGNED( 847, 11), TO_UNSIGNED( 990, 11), TO_UNSIGNED( 853, 11), TO_UNSIGNED( 996, 11),
TO_UNSIGNED( 859, 11), TO_UNSIGNED(1002, 11), TO_UNSIGNED( 865, 11), TO_UNSIGNED(1009, 11), TO_UNSIGNED( 871, 11), TO_UNSIGNED(1014, 11), TO_UNSIGNED( 877, 11), TO_UNSIGNED(1020, 11),
TO_UNSIGNED( 883, 11), TO_UNSIGNED(1028, 11), TO_UNSIGNED( 889, 11), TO_UNSIGNED(1033, 11), TO_UNSIGNED( 895, 11), TO_UNSIGNED(1040, 11), TO_UNSIGNED( 901, 11), TO_UNSIGNED(1045, 11),
TO_UNSIGNED( 907, 11), TO_UNSIGNED(1051, 11), TO_UNSIGNED( 913, 11), TO_UNSIGNED(1058, 11), TO_UNSIGNED( 919, 11), TO_UNSIGNED(1064, 11), TO_UNSIGNED( 925, 11), TO_UNSIGNED(1069, 11),
TO_UNSIGNED( 932, 11), TO_UNSIGNED(1075, 11), TO_UNSIGNED( 937, 11), TO_UNSIGNED(1081, 11), TO_UNSIGNED( 943, 11), TO_UNSIGNED(1087, 11), TO_UNSIGNED( 949, 11), TO_UNSIGNED(1093, 11),
TO_UNSIGNED( 955, 11), TO_UNSIGNED(1099, 11), TO_UNSIGNED( 961, 11), TO_UNSIGNED(1105, 11), TO_UNSIGNED( 967, 11), TO_UNSIGNED(1111, 11), TO_UNSIGNED( 973, 11), TO_UNSIGNED(1117, 11),
TO_UNSIGNED( 979, 11), TO_UNSIGNED(1123, 11), TO_UNSIGNED( 985, 11), TO_UNSIGNED(1129, 11), TO_UNSIGNED( 991, 11), TO_UNSIGNED(1135, 11), TO_UNSIGNED( 997, 11), TO_UNSIGNED(1141, 11),
TO_UNSIGNED(1003, 11), TO_UNSIGNED(1147, 11), TO_UNSIGNED( 1, 11), TO_UNSIGNED( 596, 11), TO_UNSIGNED(1203, 11), TO_UNSIGNED( 7, 11), TO_UNSIGNED( 602, 11), TO_UNSIGNED(1210, 11),
TO_UNSIGNED( 13, 11), TO_UNSIGNED( 608, 11), TO_UNSIGNED(1217, 11), TO_UNSIGNED( 20, 11), TO_UNSIGNED( 614, 11), TO_UNSIGNED(1224, 11), TO_UNSIGNED( 26, 11), TO_UNSIGNED( 620, 11),
TO_UNSIGNED(1231, 11), TO_UNSIGNED( 32, 11), TO_UNSIGNED( 626, 11), TO_UNSIGNED(1238, 11), TO_UNSIGNED( 38, 11), TO_UNSIGNED( 632, 11), TO_UNSIGNED(1245, 11), TO_UNSIGNED( 44, 11),
TO_UNSIGNED( 639, 11), TO_UNSIGNED(1252, 11), TO_UNSIGNED( 50, 11), TO_UNSIGNED( 644, 11), TO_UNSIGNED(1259, 11), TO_UNSIGNED( 56, 11), TO_UNSIGNED( 650, 11), TO_UNSIGNED(1266, 11),
TO_UNSIGNED( 62, 11), TO_UNSIGNED( 656, 11), TO_UNSIGNED(1273, 11), TO_UNSIGNED( 68, 11), TO_UNSIGNED( 662, 11), TO_UNSIGNED(1280, 11), TO_UNSIGNED( 74, 11), TO_UNSIGNED( 668, 11),
TO_UNSIGNED(1287, 11), TO_UNSIGNED( 80, 11), TO_UNSIGNED( 674, 11), TO_UNSIGNED(1294, 11), TO_UNSIGNED( 86, 11), TO_UNSIGNED( 680, 11), TO_UNSIGNED(1301, 11), TO_UNSIGNED( 92, 11),
TO_UNSIGNED( 686, 11), TO_UNSIGNED(1308, 11), TO_UNSIGNED( 98, 11), TO_UNSIGNED( 692, 11), TO_UNSIGNED(1315, 11), TO_UNSIGNED( 104, 11), TO_UNSIGNED( 698, 11), TO_UNSIGNED(1154, 11),
TO_UNSIGNED( 110, 11), TO_UNSIGNED( 704, 11), TO_UNSIGNED(1161, 11), TO_UNSIGNED( 117, 11), TO_UNSIGNED( 710, 11), TO_UNSIGNED(1169, 11), TO_UNSIGNED( 122, 11), TO_UNSIGNED( 716, 11),
TO_UNSIGNED(1175, 11), TO_UNSIGNED( 128, 11), TO_UNSIGNED( 578, 11), TO_UNSIGNED(1182, 11), TO_UNSIGNED( 134, 11), TO_UNSIGNED( 584, 11), TO_UNSIGNED(1189, 11), TO_UNSIGNED( 140, 11),
TO_UNSIGNED( 590, 11), TO_UNSIGNED(1196, 11), TO_UNSIGNED( 105, 11), TO_UNSIGNED( 206, 11), TO_UNSIGNED( 338, 11), TO_UNSIGNED( 566, 11), TO_UNSIGNED( 681, 11), TO_UNSIGNED( 866, 11),
TO_UNSIGNED( 111, 11), TO_UNSIGNED( 212, 11), TO_UNSIGNED( 345, 11), TO_UNSIGNED( 572, 11), TO_UNSIGNED( 687, 11), TO_UNSIGNED( 872, 11), TO_UNSIGNED( 118, 11), TO_UNSIGNED( 218, 11),
TO_UNSIGNED( 350, 11), TO_UNSIGNED( 434, 11), TO_UNSIGNED( 693, 11), TO_UNSIGNED( 878, 11), TO_UNSIGNED( 123, 11), TO_UNSIGNED( 224, 11), TO_UNSIGNED( 356, 11), TO_UNSIGNED( 440, 11),
TO_UNSIGNED( 699, 11), TO_UNSIGNED( 884, 11), TO_UNSIGNED( 129, 11), TO_UNSIGNED( 230, 11), TO_UNSIGNED( 362, 11), TO_UNSIGNED( 447, 11), TO_UNSIGNED( 705, 11), TO_UNSIGNED( 890, 11),
TO_UNSIGNED( 135, 11), TO_UNSIGNED( 236, 11), TO_UNSIGNED( 368, 11), TO_UNSIGNED( 452, 11), TO_UNSIGNED( 711, 11), TO_UNSIGNED( 896, 11), TO_UNSIGNED( 141, 11), TO_UNSIGNED( 242, 11),
TO_UNSIGNED( 374, 11), TO_UNSIGNED( 458, 11), TO_UNSIGNED( 717, 11), TO_UNSIGNED( 902, 11), TO_UNSIGNED( 2, 11), TO_UNSIGNED( 248, 11), TO_UNSIGNED( 380, 11), TO_UNSIGNED( 464, 11),
TO_UNSIGNED( 579, 11), TO_UNSIGNED( 908, 11), TO_UNSIGNED( 8, 11), TO_UNSIGNED( 254, 11), TO_UNSIGNED( 386, 11), TO_UNSIGNED( 470, 11), TO_UNSIGNED( 585, 11), TO_UNSIGNED( 914, 11),
TO_UNSIGNED( 14, 11), TO_UNSIGNED( 260, 11), TO_UNSIGNED( 392, 11), TO_UNSIGNED( 476, 11), TO_UNSIGNED( 591, 11), TO_UNSIGNED( 920, 11), TO_UNSIGNED( 21, 11), TO_UNSIGNED( 266, 11),
TO_UNSIGNED( 398, 11), TO_UNSIGNED( 482, 11), TO_UNSIGNED( 597, 11), TO_UNSIGNED( 926, 11), TO_UNSIGNED( 27, 11), TO_UNSIGNED( 272, 11), TO_UNSIGNED( 404, 11), TO_UNSIGNED( 488, 11),
TO_UNSIGNED( 603, 11), TO_UNSIGNED( 933, 11), TO_UNSIGNED( 33, 11), TO_UNSIGNED( 278, 11), TO_UNSIGNED( 410, 11), TO_UNSIGNED( 494, 11), TO_UNSIGNED( 609, 11), TO_UNSIGNED( 938, 11),
TO_UNSIGNED( 39, 11), TO_UNSIGNED( 284, 11), TO_UNSIGNED( 416, 11), TO_UNSIGNED( 500, 11), TO_UNSIGNED( 615, 11), TO_UNSIGNED( 944, 11), TO_UNSIGNED( 45, 11), TO_UNSIGNED( 146, 11),
TO_UNSIGNED( 422, 11), TO_UNSIGNED( 506, 11), TO_UNSIGNED( 621, 11), TO_UNSIGNED( 950, 11), TO_UNSIGNED( 51, 11), TO_UNSIGNED( 152, 11), TO_UNSIGNED( 428, 11), TO_UNSIGNED( 512, 11),
TO_UNSIGNED( 627, 11), TO_UNSIGNED( 956, 11), TO_UNSIGNED( 57, 11), TO_UNSIGNED( 158, 11), TO_UNSIGNED( 290, 11), TO_UNSIGNED( 518, 11), TO_UNSIGNED( 633, 11), TO_UNSIGNED( 962, 11),
TO_UNSIGNED( 63, 11), TO_UNSIGNED( 164, 11), TO_UNSIGNED( 296, 11), TO_UNSIGNED( 524, 11), TO_UNSIGNED( 640, 11), TO_UNSIGNED( 968, 11), TO_UNSIGNED( 69, 11), TO_UNSIGNED( 170, 11),
TO_UNSIGNED( 302, 11), TO_UNSIGNED( 530, 11), TO_UNSIGNED( 645, 11), TO_UNSIGNED( 974, 11), TO_UNSIGNED( 75, 11), TO_UNSIGNED( 177, 11), TO_UNSIGNED( 308, 11), TO_UNSIGNED( 536, 11),
TO_UNSIGNED( 651, 11), TO_UNSIGNED( 980, 11), TO_UNSIGNED( 81, 11), TO_UNSIGNED( 182, 11), TO_UNSIGNED( 314, 11), TO_UNSIGNED( 542, 11), TO_UNSIGNED( 657, 11), TO_UNSIGNED( 986, 11),
TO_UNSIGNED( 87, 11), TO_UNSIGNED( 188, 11), TO_UNSIGNED( 320, 11), TO_UNSIGNED( 548, 11), TO_UNSIGNED( 663, 11), TO_UNSIGNED( 992, 11), TO_UNSIGNED( 93, 11), TO_UNSIGNED( 194, 11),
TO_UNSIGNED( 326, 11), TO_UNSIGNED( 554, 11), TO_UNSIGNED( 669, 11), TO_UNSIGNED( 998, 11), TO_UNSIGNED( 99, 11), TO_UNSIGNED( 200, 11), TO_UNSIGNED( 332, 11), TO_UNSIGNED( 560, 11),
TO_UNSIGNED( 675, 11), TO_UNSIGNED(1004, 11), TO_UNSIGNED( 477, 11), TO_UNSIGNED( 927, 11), TO_UNSIGNED(1321, 11), TO_UNSIGNED( 483, 11), TO_UNSIGNED( 934, 11), TO_UNSIGNED(1328, 11),
TO_UNSIGNED( 489, 11), TO_UNSIGNED( 939, 11), TO_UNSIGNED(1336, 11), TO_UNSIGNED( 495, 11), TO_UNSIGNED( 945, 11), TO_UNSIGNED(1343, 11), TO_UNSIGNED( 501, 11), TO_UNSIGNED( 951, 11),
TO_UNSIGNED(1350, 11), TO_UNSIGNED( 507, 11), TO_UNSIGNED( 957, 11), TO_UNSIGNED(1357, 11), TO_UNSIGNED( 513, 11), TO_UNSIGNED( 963, 11), TO_UNSIGNED(1365, 11), TO_UNSIGNED( 519, 11),
TO_UNSIGNED( 969, 11), TO_UNSIGNED(1372, 11), TO_UNSIGNED( 525, 11), TO_UNSIGNED( 975, 11), TO_UNSIGNED(1378, 11), TO_UNSIGNED( 531, 11), TO_UNSIGNED( 981, 11), TO_UNSIGNED(1385, 11),
TO_UNSIGNED( 537, 11), TO_UNSIGNED( 987, 11), TO_UNSIGNED(1392, 11), TO_UNSIGNED( 543, 11), TO_UNSIGNED( 993, 11), TO_UNSIGNED(1399, 11), TO_UNSIGNED( 549, 11), TO_UNSIGNED( 999, 11),
TO_UNSIGNED(1406, 11), TO_UNSIGNED( 555, 11), TO_UNSIGNED(1005, 11), TO_UNSIGNED(1413, 11), TO_UNSIGNED( 561, 11), TO_UNSIGNED( 867, 11), TO_UNSIGNED(1420, 11), TO_UNSIGNED( 567, 11),
TO_UNSIGNED( 873, 11), TO_UNSIGNED(1427, 11), TO_UNSIGNED( 573, 11), TO_UNSIGNED( 879, 11), TO_UNSIGNED(1434, 11), TO_UNSIGNED( 435, 11), TO_UNSIGNED( 885, 11), TO_UNSIGNED(1441, 11),
TO_UNSIGNED( 441, 11), TO_UNSIGNED( 891, 11), TO_UNSIGNED(1448, 11), TO_UNSIGNED( 448, 11), TO_UNSIGNED( 897, 11), TO_UNSIGNED(1455, 11), TO_UNSIGNED( 453, 11), TO_UNSIGNED( 903, 11),
TO_UNSIGNED(1462, 11), TO_UNSIGNED( 459, 11), TO_UNSIGNED( 909, 11), TO_UNSIGNED(1470, 11), TO_UNSIGNED( 465, 11), TO_UNSIGNED( 915, 11), TO_UNSIGNED(1476, 11), TO_UNSIGNED( 471, 11),
TO_UNSIGNED( 921, 11), TO_UNSIGNED(1484, 11), TO_UNSIGNED( 147, 11), TO_UNSIGNED(1124, 11), TO_UNSIGNED(1742, 11), TO_UNSIGNED( 153, 11), TO_UNSIGNED(1130, 11), TO_UNSIGNED(1749, 11),
TO_UNSIGNED( 159, 11), TO_UNSIGNED(1136, 11), TO_UNSIGNED(1756, 11), TO_UNSIGNED( 165, 11), TO_UNSIGNED(1142, 11), TO_UNSIGNED(1763, 11), TO_UNSIGNED( 171, 11), TO_UNSIGNED(1148, 11),
TO_UNSIGNED(1770, 11), TO_UNSIGNED( 178, 11), TO_UNSIGNED(1010, 11), TO_UNSIGNED(1777, 11), TO_UNSIGNED( 183, 11), TO_UNSIGNED(1015, 11), TO_UNSIGNED(1784, 11), TO_UNSIGNED( 189, 11),
TO_UNSIGNED(1021, 11), TO_UNSIGNED(1791, 11), TO_UNSIGNED( 195, 11), TO_UNSIGNED(1029, 11), TO_UNSIGNED(1798, 11), TO_UNSIGNED( 201, 11), TO_UNSIGNED(1034, 11), TO_UNSIGNED(1805, 11),
TO_UNSIGNED( 207, 11), TO_UNSIGNED(1041, 11), TO_UNSIGNED(1812, 11), TO_UNSIGNED( 213, 11), TO_UNSIGNED(1046, 11), TO_UNSIGNED(1819, 11), TO_UNSIGNED( 219, 11), TO_UNSIGNED(1052, 11),
TO_UNSIGNED(1658, 11), TO_UNSIGNED( 225, 11), TO_UNSIGNED(1059, 11), TO_UNSIGNED(1665, 11), TO_UNSIGNED( 231, 11), TO_UNSIGNED(1065, 11), TO_UNSIGNED(1672, 11), TO_UNSIGNED( 237, 11),
TO_UNSIGNED(1070, 11), TO_UNSIGNED(1679, 11), TO_UNSIGNED( 243, 11), TO_UNSIGNED(1076, 11), TO_UNSIGNED(1686, 11), TO_UNSIGNED( 249, 11), TO_UNSIGNED(1082, 11), TO_UNSIGNED(1693, 11),
TO_UNSIGNED( 255, 11), TO_UNSIGNED(1088, 11), TO_UNSIGNED(1700, 11), TO_UNSIGNED( 261, 11), TO_UNSIGNED(1094, 11), TO_UNSIGNED(1707, 11), TO_UNSIGNED( 267, 11), TO_UNSIGNED(1100, 11),
TO_UNSIGNED(1715, 11), TO_UNSIGNED( 273, 11), TO_UNSIGNED(1106, 11), TO_UNSIGNED(1723, 11), TO_UNSIGNED( 279, 11), TO_UNSIGNED(1112, 11), TO_UNSIGNED(1728, 11), TO_UNSIGNED( 285, 11),
TO_UNSIGNED(1118, 11), TO_UNSIGNED(1736, 11), TO_UNSIGNED( 782, 11), TO_UNSIGNED(1030, 11), TO_UNSIGNED(1267, 11), TO_UNSIGNED(1373, 11), TO_UNSIGNED(1638, 11), TO_UNSIGNED(1778, 11),
TO_UNSIGNED( 788, 11), TO_UNSIGNED(1035, 11), TO_UNSIGNED(1274, 11), TO_UNSIGNED(1379, 11), TO_UNSIGNED(1645, 11), TO_UNSIGNED(1785, 11), TO_UNSIGNED( 795, 11), TO_UNSIGNED(1042, 11),
TO_UNSIGNED(1281, 11), TO_UNSIGNED(1386, 11), TO_UNSIGNED(1652, 11), TO_UNSIGNED(1792, 11), TO_UNSIGNED( 801, 11), TO_UNSIGNED(1047, 11), TO_UNSIGNED(1288, 11), TO_UNSIGNED(1393, 11),
TO_UNSIGNED(1490, 11), TO_UNSIGNED(1799, 11), TO_UNSIGNED( 806, 11), TO_UNSIGNED(1053, 11), TO_UNSIGNED(1295, 11), TO_UNSIGNED(1400, 11), TO_UNSIGNED(1497, 11), TO_UNSIGNED(1806, 11),
TO_UNSIGNED( 813, 11), TO_UNSIGNED(1060, 11), TO_UNSIGNED(1302, 11), TO_UNSIGNED(1407, 11), TO_UNSIGNED(1505, 11), TO_UNSIGNED(1813, 11), TO_UNSIGNED( 818, 11), TO_UNSIGNED(1066, 11),
TO_UNSIGNED(1309, 11), TO_UNSIGNED(1414, 11), TO_UNSIGNED(1512, 11), TO_UNSIGNED(1820, 11), TO_UNSIGNED( 825, 11), TO_UNSIGNED(1071, 11), TO_UNSIGNED(1316, 11), TO_UNSIGNED(1421, 11),
TO_UNSIGNED(1519, 11), TO_UNSIGNED(1659, 11), TO_UNSIGNED( 830, 11), TO_UNSIGNED(1077, 11), TO_UNSIGNED(1155, 11), TO_UNSIGNED(1428, 11), TO_UNSIGNED(1526, 11), TO_UNSIGNED(1666, 11),
TO_UNSIGNED( 836, 11), TO_UNSIGNED(1083, 11), TO_UNSIGNED(1162, 11), TO_UNSIGNED(1435, 11), TO_UNSIGNED(1533, 11), TO_UNSIGNED(1673, 11), TO_UNSIGNED( 842, 11), TO_UNSIGNED(1089, 11),
TO_UNSIGNED(1170, 11), TO_UNSIGNED(1442, 11), TO_UNSIGNED(1540, 11), TO_UNSIGNED(1680, 11), TO_UNSIGNED( 848, 11), TO_UNSIGNED(1095, 11), TO_UNSIGNED(1176, 11), TO_UNSIGNED(1449, 11),
TO_UNSIGNED(1547, 11), TO_UNSIGNED(1687, 11), TO_UNSIGNED( 854, 11), TO_UNSIGNED(1101, 11), TO_UNSIGNED(1183, 11), TO_UNSIGNED(1456, 11), TO_UNSIGNED(1554, 11), TO_UNSIGNED(1694, 11),
TO_UNSIGNED( 860, 11), TO_UNSIGNED(1107, 11), TO_UNSIGNED(1190, 11), TO_UNSIGNED(1463, 11), TO_UNSIGNED(1561, 11), TO_UNSIGNED(1701, 11), TO_UNSIGNED( 722, 11), TO_UNSIGNED(1113, 11),
TO_UNSIGNED(1197, 11), TO_UNSIGNED(1471, 11), TO_UNSIGNED(1568, 11), TO_UNSIGNED(1708, 11), TO_UNSIGNED( 728, 11), TO_UNSIGNED(1119, 11), TO_UNSIGNED(1204, 11), TO_UNSIGNED(1477, 11),
TO_UNSIGNED(1575, 11), TO_UNSIGNED(1716, 11), TO_UNSIGNED( 734, 11), TO_UNSIGNED(1125, 11), TO_UNSIGNED(1211, 11), TO_UNSIGNED(1485, 11), TO_UNSIGNED(1582, 11), TO_UNSIGNED(1724, 11),
TO_UNSIGNED( 740, 11), TO_UNSIGNED(1131, 11), TO_UNSIGNED(1218, 11), TO_UNSIGNED(1322, 11), TO_UNSIGNED(1589, 11), TO_UNSIGNED(1729, 11), TO_UNSIGNED( 746, 11), TO_UNSIGNED(1137, 11),
TO_UNSIGNED(1225, 11), TO_UNSIGNED(1329, 11), TO_UNSIGNED(1596, 11), TO_UNSIGNED(1737, 11), TO_UNSIGNED( 752, 11), TO_UNSIGNED(1143, 11), TO_UNSIGNED(1232, 11), TO_UNSIGNED(1337, 11),
TO_UNSIGNED(1604, 11), TO_UNSIGNED(1743, 11), TO_UNSIGNED( 758, 11), TO_UNSIGNED(1149, 11), TO_UNSIGNED(1239, 11), TO_UNSIGNED(1344, 11), TO_UNSIGNED(1610, 11), TO_UNSIGNED(1750, 11),
TO_UNSIGNED( 764, 11), TO_UNSIGNED(1011, 11), TO_UNSIGNED(1246, 11), TO_UNSIGNED(1351, 11), TO_UNSIGNED(1619, 11), TO_UNSIGNED(1757, 11), TO_UNSIGNED( 770, 11), TO_UNSIGNED(1016, 11),
TO_UNSIGNED(1253, 11), TO_UNSIGNED(1358, 11), TO_UNSIGNED(1625, 11), TO_UNSIGNED(1764, 11), TO_UNSIGNED( 776, 11), TO_UNSIGNED(1022, 11), TO_UNSIGNED(1260, 11), TO_UNSIGNED(1366, 11),
TO_UNSIGNED(1631, 11), TO_UNSIGNED(1771, 11), TO_UNSIGNED(1450, 11), TO_UNSIGNED(1491, 11), TO_UNSIGNED(1725, 11), TO_UNSIGNED(1457, 11), TO_UNSIGNED(1498, 11), TO_UNSIGNED(1730, 11),
TO_UNSIGNED(1464, 11), TO_UNSIGNED(1506, 11), TO_UNSIGNED(1738, 11), TO_UNSIGNED(1472, 11), TO_UNSIGNED(1513, 11), TO_UNSIGNED(1744, 11), TO_UNSIGNED(1478, 11), TO_UNSIGNED(1520, 11),
TO_UNSIGNED(1751, 11), TO_UNSIGNED(1486, 11), TO_UNSIGNED(1527, 11), TO_UNSIGNED(1758, 11), TO_UNSIGNED(1323, 11), TO_UNSIGNED(1534, 11), TO_UNSIGNED(1765, 11), TO_UNSIGNED(1330, 11),
TO_UNSIGNED(1541, 11), TO_UNSIGNED(1772, 11), TO_UNSIGNED(1338, 11), TO_UNSIGNED(1548, 11), TO_UNSIGNED(1779, 11), TO_UNSIGNED(1345, 11), TO_UNSIGNED(1555, 11), TO_UNSIGNED(1786, 11),
TO_UNSIGNED(1352, 11), TO_UNSIGNED(1562, 11), TO_UNSIGNED(1793, 11), TO_UNSIGNED(1359, 11), TO_UNSIGNED(1569, 11), TO_UNSIGNED(1800, 11), TO_UNSIGNED(1367, 11), TO_UNSIGNED(1576, 11),
TO_UNSIGNED(1807, 11), TO_UNSIGNED(1374, 11), TO_UNSIGNED(1583, 11), TO_UNSIGNED(1814, 11), TO_UNSIGNED(1380, 11), TO_UNSIGNED(1590, 11), TO_UNSIGNED(1821, 11), TO_UNSIGNED(1387, 11),
TO_UNSIGNED(1597, 11), TO_UNSIGNED(1660, 11), TO_UNSIGNED(1394, 11), TO_UNSIGNED(1605, 11), TO_UNSIGNED(1667, 11), TO_UNSIGNED(1401, 11), TO_UNSIGNED(1611, 11), TO_UNSIGNED(1674, 11),
TO_UNSIGNED(1408, 11), TO_UNSIGNED(1620, 11), TO_UNSIGNED(1681, 11), TO_UNSIGNED(1415, 11), TO_UNSIGNED(1626, 11), TO_UNSIGNED(1688, 11), TO_UNSIGNED(1422, 11), TO_UNSIGNED(1632, 11),
TO_UNSIGNED(1695, 11), TO_UNSIGNED(1429, 11), TO_UNSIGNED(1639, 11), TO_UNSIGNED(1702, 11), TO_UNSIGNED(1436, 11), TO_UNSIGNED(1646, 11), TO_UNSIGNED(1709, 11), TO_UNSIGNED(1443, 11),
TO_UNSIGNED(1653, 11), TO_UNSIGNED(1717, 11), TO_UNSIGNED( 303, 11), TO_UNSIGNED( 610, 11), TO_UNSIGNED(1156, 11), TO_UNSIGNED( 417, 11), TO_UNSIGNED( 580, 11), TO_UNSIGNED(1289, 11),
TO_UNSIGNED( 423, 11), TO_UNSIGNED( 586, 11), TO_UNSIGNED(1296, 11), TO_UNSIGNED( 429, 11), TO_UNSIGNED( 592, 11), TO_UNSIGNED(1303, 11), TO_UNSIGNED( 291, 11), TO_UNSIGNED( 598, 11),
TO_UNSIGNED(1310, 11), TO_UNSIGNED( 297, 11), TO_UNSIGNED( 604, 11), TO_UNSIGNED(1317, 11), TO_UNSIGNED( 315, 11), TO_UNSIGNED( 622, 11), TO_UNSIGNED(1171, 11), TO_UNSIGNED( 309, 11),
TO_UNSIGNED( 616, 11), TO_UNSIGNED(1163, 11), TO_UNSIGNED( 339, 11), TO_UNSIGNED( 646, 11), TO_UNSIGNED(1198, 11), TO_UNSIGNED( 321, 11), TO_UNSIGNED( 628, 11), TO_UNSIGNED(1177, 11),
TO_UNSIGNED( 327, 11), TO_UNSIGNED( 634, 11), TO_UNSIGNED(1184, 11), TO_UNSIGNED( 333, 11), TO_UNSIGNED( 641, 11), TO_UNSIGNED(1191, 11), TO_UNSIGNED( 363, 11), TO_UNSIGNED( 670, 11),
TO_UNSIGNED(1226, 11), TO_UNSIGNED( 346, 11), TO_UNSIGNED( 652, 11), TO_UNSIGNED(1205, 11), TO_UNSIGNED( 351, 11), TO_UNSIGNED( 658, 11), TO_UNSIGNED(1212, 11), TO_UNSIGNED( 357, 11),
TO_UNSIGNED( 664, 11), TO_UNSIGNED(1219, 11), TO_UNSIGNED( 375, 11), TO_UNSIGNED( 682, 11), TO_UNSIGNED(1240, 11), TO_UNSIGNED( 381, 11), TO_UNSIGNED( 688, 11), TO_UNSIGNED(1247, 11),
TO_UNSIGNED( 387, 11), TO_UNSIGNED( 694, 11), TO_UNSIGNED(1254, 11), TO_UNSIGNED( 369, 11), TO_UNSIGNED( 676, 11), TO_UNSIGNED(1233, 11), TO_UNSIGNED( 399, 11), TO_UNSIGNED( 706, 11),
TO_UNSIGNED(1268, 11), TO_UNSIGNED( 393, 11), TO_UNSIGNED( 700, 11), TO_UNSIGNED(1261, 11), TO_UNSIGNED( 411, 11), TO_UNSIGNED( 718, 11), TO_UNSIGNED(1282, 11), TO_UNSIGNED( 405, 11),
TO_UNSIGNED( 712, 11), TO_UNSIGNED(1275, 11), TO_UNSIGNED( 826, 11), TO_UNSIGNED(1090, 11), TO_UNSIGNED(1192, 11), TO_UNSIGNED(1402, 11), TO_UNSIGNED(1654, 11), TO_UNSIGNED(1752, 11),
TO_UNSIGNED( 807, 11), TO_UNSIGNED(1072, 11), TO_UNSIGNED(1172, 11), TO_UNSIGNED(1381, 11), TO_UNSIGNED(1633, 11), TO_UNSIGNED(1731, 11), TO_UNSIGNED( 814, 11), TO_UNSIGNED(1078, 11),
TO_UNSIGNED(1178, 11), TO_UNSIGNED(1388, 11), TO_UNSIGNED(1640, 11), TO_UNSIGNED(1739, 11), TO_UNSIGNED( 819, 11), TO_UNSIGNED(1084, 11), TO_UNSIGNED(1185, 11), TO_UNSIGNED(1395, 11),
TO_UNSIGNED(1647, 11), TO_UNSIGNED(1745, 11), TO_UNSIGNED( 837, 11), TO_UNSIGNED(1102, 11), TO_UNSIGNED(1206, 11), TO_UNSIGNED(1416, 11), TO_UNSIGNED(1499, 11), TO_UNSIGNED(1766, 11),
TO_UNSIGNED( 831, 11), TO_UNSIGNED(1096, 11), TO_UNSIGNED(1199, 11), TO_UNSIGNED(1409, 11), TO_UNSIGNED(1492, 11), TO_UNSIGNED(1759, 11), TO_UNSIGNED( 849, 11), TO_UNSIGNED(1114, 11),
TO_UNSIGNED(1220, 11), TO_UNSIGNED(1430, 11), TO_UNSIGNED(1514, 11), TO_UNSIGNED(1780, 11), TO_UNSIGNED( 843, 11), TO_UNSIGNED(1108, 11), TO_UNSIGNED(1213, 11), TO_UNSIGNED(1423, 11),
TO_UNSIGNED(1507, 11), TO_UNSIGNED(1773, 11), TO_UNSIGNED( 855, 11), TO_UNSIGNED(1120, 11), TO_UNSIGNED(1227, 11), TO_UNSIGNED(1437, 11), TO_UNSIGNED(1521, 11), TO_UNSIGNED(1787, 11),
TO_UNSIGNED( 861, 11), TO_UNSIGNED(1126, 11), TO_UNSIGNED(1234, 11), TO_UNSIGNED(1444, 11), TO_UNSIGNED(1528, 11), TO_UNSIGNED(1794, 11), TO_UNSIGNED( 729, 11), TO_UNSIGNED(1138, 11),
TO_UNSIGNED(1248, 11), TO_UNSIGNED(1458, 11), TO_UNSIGNED(1542, 11), TO_UNSIGNED(1808, 11), TO_UNSIGNED( 723, 11), TO_UNSIGNED(1132, 11), TO_UNSIGNED(1241, 11), TO_UNSIGNED(1451, 11),
TO_UNSIGNED(1535, 11), TO_UNSIGNED(1801, 11), TO_UNSIGNED( 747, 11), TO_UNSIGNED(1012, 11), TO_UNSIGNED(1269, 11), TO_UNSIGNED(1479, 11), TO_UNSIGNED(1563, 11), TO_UNSIGNED(1661, 11),
TO_UNSIGNED( 753, 11), TO_UNSIGNED(1017, 11), TO_UNSIGNED(1276, 11), TO_UNSIGNED(1487, 11), TO_UNSIGNED(1570, 11), TO_UNSIGNED(1668, 11), TO_UNSIGNED( 735, 11), TO_UNSIGNED(1144, 11),
TO_UNSIGNED(1255, 11), TO_UNSIGNED(1465, 11), TO_UNSIGNED(1549, 11), TO_UNSIGNED(1815, 11), TO_UNSIGNED( 741, 11), TO_UNSIGNED(1150, 11), TO_UNSIGNED(1262, 11), TO_UNSIGNED(1473, 11),
TO_UNSIGNED(1556, 11), TO_UNSIGNED(1822, 11), TO_UNSIGNED( 771, 11), TO_UNSIGNED(1036, 11), TO_UNSIGNED(1297, 11), TO_UNSIGNED(1339, 11), TO_UNSIGNED(1591, 11), TO_UNSIGNED(1689, 11),
TO_UNSIGNED( 759, 11), TO_UNSIGNED(1023, 11), TO_UNSIGNED(1283, 11), TO_UNSIGNED(1324, 11), TO_UNSIGNED(1577, 11), TO_UNSIGNED(1675, 11), TO_UNSIGNED( 765, 11), TO_UNSIGNED(1031, 11),
TO_UNSIGNED(1290, 11), TO_UNSIGNED(1331, 11), TO_UNSIGNED(1584, 11), TO_UNSIGNED(1682, 11), TO_UNSIGNED( 783, 11), TO_UNSIGNED(1048, 11), TO_UNSIGNED(1311, 11), TO_UNSIGNED(1353, 11),
TO_UNSIGNED(1606, 11), TO_UNSIGNED(1703, 11), TO_UNSIGNED( 789, 11), TO_UNSIGNED(1054, 11), TO_UNSIGNED(1318, 11), TO_UNSIGNED(1360, 11), TO_UNSIGNED(1612, 11), TO_UNSIGNED(1710, 11),
TO_UNSIGNED( 777, 11), TO_UNSIGNED(1043, 11), TO_UNSIGNED(1304, 11), TO_UNSIGNED(1346, 11), TO_UNSIGNED(1598, 11), TO_UNSIGNED(1696, 11), TO_UNSIGNED( 82, 11), TO_UNSIGNED( 244, 11),
TO_UNSIGNED( 922, 11), TO_UNSIGNED( 88, 11), TO_UNSIGNED( 250, 11), TO_UNSIGNED( 928, 11), TO_UNSIGNED( 94, 11), TO_UNSIGNED( 256, 11), TO_UNSIGNED( 935, 11), TO_UNSIGNED( 119, 11),
TO_UNSIGNED( 280, 11), TO_UNSIGNED( 958, 11), TO_UNSIGNED( 124, 11), TO_UNSIGNED( 286, 11), TO_UNSIGNED( 964, 11), TO_UNSIGNED( 100, 11), TO_UNSIGNED( 262, 11), TO_UNSIGNED( 940, 11),
TO_UNSIGNED( 106, 11), TO_UNSIGNED( 268, 11), TO_UNSIGNED( 946, 11), TO_UNSIGNED( 112, 11), TO_UNSIGNED( 274, 11), TO_UNSIGNED( 952, 11), TO_UNSIGNED( 142, 11), TO_UNSIGNED( 160, 11),
TO_UNSIGNED( 982, 11), TO_UNSIGNED( 3, 11), TO_UNSIGNED( 166, 11), TO_UNSIGNED( 988, 11), TO_UNSIGNED( 9, 11), TO_UNSIGNED( 172, 11), TO_UNSIGNED( 994, 11), TO_UNSIGNED( 136, 11),
TO_UNSIGNED( 154, 11), TO_UNSIGNED( 976, 11), TO_UNSIGNED( 130, 11), TO_UNSIGNED( 148, 11), TO_UNSIGNED( 970, 11), TO_UNSIGNED( 15, 11), TO_UNSIGNED( 179, 11), TO_UNSIGNED(1000, 11),
TO_UNSIGNED( 22, 11), TO_UNSIGNED( 184, 11), TO_UNSIGNED(1006, 11), TO_UNSIGNED( 28, 11), TO_UNSIGNED( 190, 11), TO_UNSIGNED( 868, 11), TO_UNSIGNED( 34, 11), TO_UNSIGNED( 196, 11),
TO_UNSIGNED( 874, 11), TO_UNSIGNED( 40, 11), TO_UNSIGNED( 202, 11), TO_UNSIGNED( 880, 11), TO_UNSIGNED( 46, 11), TO_UNSIGNED( 208, 11), TO_UNSIGNED( 886, 11), TO_UNSIGNED( 52, 11),
TO_UNSIGNED( 214, 11), TO_UNSIGNED( 892, 11), TO_UNSIGNED( 64, 11), TO_UNSIGNED( 226, 11), TO_UNSIGNED( 904, 11), TO_UNSIGNED( 58, 11), TO_UNSIGNED( 220, 11), TO_UNSIGNED( 898, 11),
TO_UNSIGNED( 131, 11), TO_UNSIGNED( 191, 11), TO_UNSIGNED( 358, 11), TO_UNSIGNED( 460, 11), TO_UNSIGNED( 653, 11), TO_UNSIGNED( 947, 11), TO_UNSIGNED( 137, 11), TO_UNSIGNED( 197, 11),
TO_UNSIGNED( 364, 11), TO_UNSIGNED( 466, 11), TO_UNSIGNED( 659, 11), TO_UNSIGNED( 953, 11), TO_UNSIGNED( 125, 11), TO_UNSIGNED( 185, 11), TO_UNSIGNED( 352, 11), TO_UNSIGNED( 454, 11),
TO_UNSIGNED( 647, 11), TO_UNSIGNED( 941, 11), TO_UNSIGNED( 400, 11), TO_UNSIGNED( 461, 11), TO_UNSIGNED( 827, 11), TO_UNSIGNED( 70, 11), TO_UNSIGNED( 232, 11), TO_UNSIGNED( 910, 11),
TO_UNSIGNED( 16, 11), TO_UNSIGNED( 221, 11), TO_UNSIGNED( 388, 11), TO_UNSIGNED( 490, 11), TO_UNSIGNED( 683, 11), TO_UNSIGNED( 977, 11), TO_UNSIGNED( 143, 11), TO_UNSIGNED( 203, 11),
TO_UNSIGNED( 370, 11), TO_UNSIGNED( 472, 11), TO_UNSIGNED( 665, 11), TO_UNSIGNED( 959, 11), TO_UNSIGNED( 4, 11), TO_UNSIGNED( 209, 11), TO_UNSIGNED( 376, 11), TO_UNSIGNED( 478, 11),
TO_UNSIGNED( 671, 11), TO_UNSIGNED( 965, 11), TO_UNSIGNED( 10, 11), TO_UNSIGNED( 215, 11), TO_UNSIGNED( 382, 11), TO_UNSIGNED( 484, 11), TO_UNSIGNED( 677, 11), TO_UNSIGNED( 971, 11),
TO_UNSIGNED( 23, 11), TO_UNSIGNED( 227, 11), TO_UNSIGNED( 394, 11), TO_UNSIGNED( 496, 11), TO_UNSIGNED( 689, 11), TO_UNSIGNED( 983, 11), TO_UNSIGNED( 35, 11), TO_UNSIGNED( 238, 11),
TO_UNSIGNED( 406, 11), TO_UNSIGNED( 508, 11), TO_UNSIGNED( 701, 11), TO_UNSIGNED( 995, 11), TO_UNSIGNED( 29, 11), TO_UNSIGNED( 233, 11), TO_UNSIGNED( 401, 11), TO_UNSIGNED( 502, 11),
TO_UNSIGNED( 695, 11), TO_UNSIGNED( 989, 11), TO_UNSIGNED( 53, 11), TO_UNSIGNED( 257, 11), TO_UNSIGNED( 424, 11), TO_UNSIGNED( 526, 11), TO_UNSIGNED( 719, 11), TO_UNSIGNED( 869, 11),
TO_UNSIGNED( 59, 11), TO_UNSIGNED( 263, 11), TO_UNSIGNED( 430, 11), TO_UNSIGNED( 532, 11), TO_UNSIGNED( 581, 11), TO_UNSIGNED( 875, 11), TO_UNSIGNED( 41, 11), TO_UNSIGNED( 245, 11),
TO_UNSIGNED( 412, 11), TO_UNSIGNED( 514, 11), TO_UNSIGNED( 707, 11), TO_UNSIGNED(1001, 11), TO_UNSIGNED( 47, 11), TO_UNSIGNED( 251, 11), TO_UNSIGNED( 418, 11), TO_UNSIGNED( 520, 11),
TO_UNSIGNED( 713, 11), TO_UNSIGNED(1007, 11), TO_UNSIGNED( 65, 11), TO_UNSIGNED( 269, 11), TO_UNSIGNED( 292, 11), TO_UNSIGNED( 538, 11), TO_UNSIGNED( 587, 11), TO_UNSIGNED( 881, 11),
TO_UNSIGNED( 71, 11), TO_UNSIGNED( 275, 11), TO_UNSIGNED( 298, 11), TO_UNSIGNED( 544, 11), TO_UNSIGNED( 593, 11), TO_UNSIGNED( 887, 11), TO_UNSIGNED( 83, 11), TO_UNSIGNED( 287, 11),
TO_UNSIGNED( 310, 11), TO_UNSIGNED( 556, 11), TO_UNSIGNED( 605, 11), TO_UNSIGNED( 899, 11), TO_UNSIGNED( 76, 11), TO_UNSIGNED( 281, 11), TO_UNSIGNED( 304, 11), TO_UNSIGNED( 550, 11),
TO_UNSIGNED( 599, 11), TO_UNSIGNED( 893, 11), TO_UNSIGNED( 95, 11), TO_UNSIGNED( 155, 11), TO_UNSIGNED( 322, 11), TO_UNSIGNED( 568, 11), TO_UNSIGNED( 617, 11), TO_UNSIGNED( 911, 11),
TO_UNSIGNED( 89, 11), TO_UNSIGNED( 149, 11), TO_UNSIGNED( 316, 11), TO_UNSIGNED( 562, 11), TO_UNSIGNED( 611, 11), TO_UNSIGNED( 905, 11), TO_UNSIGNED( 113, 11), TO_UNSIGNED( 173, 11),
TO_UNSIGNED( 340, 11), TO_UNSIGNED( 442, 11), TO_UNSIGNED( 635, 11), TO_UNSIGNED( 929, 11), TO_UNSIGNED( 101, 11), TO_UNSIGNED( 161, 11), TO_UNSIGNED( 328, 11), TO_UNSIGNED( 574, 11),
TO_UNSIGNED( 623, 11), TO_UNSIGNED( 916, 11), TO_UNSIGNED( 107, 11), TO_UNSIGNED( 167, 11), TO_UNSIGNED( 334, 11), TO_UNSIGNED( 436, 11), TO_UNSIGNED( 629, 11), TO_UNSIGNED( 923, 11),
TO_UNSIGNED( 407, 11), TO_UNSIGNED( 467, 11), TO_UNSIGNED( 832, 11), TO_UNSIGNED( 413, 11), TO_UNSIGNED( 473, 11), TO_UNSIGNED( 838, 11), TO_UNSIGNED( 11, 11), TO_UNSIGNED(1018, 11),
TO_UNSIGNED(1493, 11), TO_UNSIGNED( 77, 11), TO_UNSIGNED( 239, 11), TO_UNSIGNED( 917, 11), TO_UNSIGNED( 419, 11), TO_UNSIGNED( 479, 11), TO_UNSIGNED( 844, 11), TO_UNSIGNED( 425, 11),
TO_UNSIGNED( 485, 11), TO_UNSIGNED( 850, 11), TO_UNSIGNED( 431, 11), TO_UNSIGNED( 491, 11), TO_UNSIGNED( 856, 11), TO_UNSIGNED( 299, 11), TO_UNSIGNED( 503, 11), TO_UNSIGNED( 724, 11),
TO_UNSIGNED( 305, 11), TO_UNSIGNED( 509, 11), TO_UNSIGNED( 730, 11), TO_UNSIGNED( 293, 11), TO_UNSIGNED( 497, 11), TO_UNSIGNED( 862, 11), TO_UNSIGNED( 317, 11), TO_UNSIGNED( 521, 11),
TO_UNSIGNED( 742, 11), TO_UNSIGNED( 311, 11), TO_UNSIGNED( 515, 11), TO_UNSIGNED( 736, 11), TO_UNSIGNED( 323, 11), TO_UNSIGNED( 527, 11), TO_UNSIGNED( 748, 11), TO_UNSIGNED( 335, 11),
TO_UNSIGNED( 539, 11), TO_UNSIGNED( 760, 11), TO_UNSIGNED( 329, 11), TO_UNSIGNED( 533, 11), TO_UNSIGNED( 754, 11), TO_UNSIGNED( 341, 11), TO_UNSIGNED( 545, 11), TO_UNSIGNED( 766, 11),
TO_UNSIGNED( 347, 11), TO_UNSIGNED( 551, 11), TO_UNSIGNED( 772, 11), TO_UNSIGNED( 353, 11), TO_UNSIGNED( 557, 11), TO_UNSIGNED( 778, 11), TO_UNSIGNED( 359, 11), TO_UNSIGNED( 563, 11),
TO_UNSIGNED( 784, 11), TO_UNSIGNED( 365, 11), TO_UNSIGNED( 569, 11), TO_UNSIGNED( 790, 11), TO_UNSIGNED( 377, 11), TO_UNSIGNED( 437, 11), TO_UNSIGNED( 802, 11), TO_UNSIGNED( 371, 11),
TO_UNSIGNED( 575, 11), TO_UNSIGNED( 796, 11), TO_UNSIGNED( 383, 11), TO_UNSIGNED( 443, 11), TO_UNSIGNED( 808, 11), TO_UNSIGNED( 389, 11), TO_UNSIGNED( 449, 11), TO_UNSIGNED( 815, 11),
TO_UNSIGNED( 395, 11), TO_UNSIGNED( 455, 11), TO_UNSIGNED( 820, 11), TO_UNSIGNED( 5, 11), TO_UNSIGNED(1157, 11), TO_UNSIGNED(1158, 11), TO_UNSIGNED(1325, 11), TO_UNSIGNED( 833, 11),
TO_UNSIGNED(1049, 11), TO_UNSIGNED(1179, 11), TO_UNSIGNED(1326, 11), TO_UNSIGNED(1627, 11), TO_UNSIGNED(1746, 11), TO_UNSIGNED( 857, 11), TO_UNSIGNED(1073, 11), TO_UNSIGNED(1207, 11),
TO_UNSIGNED(1354, 11), TO_UNSIGNED(1655, 11), TO_UNSIGNED(1774, 11), TO_UNSIGNED( 845, 11), TO_UNSIGNED(1061, 11), TO_UNSIGNED(1193, 11), TO_UNSIGNED(1340, 11), TO_UNSIGNED(1641, 11),
TO_UNSIGNED(1760, 11), TO_UNSIGNED( 851, 11), TO_UNSIGNED(1067, 11), TO_UNSIGNED(1200, 11), TO_UNSIGNED(1347, 11), TO_UNSIGNED(1648, 11), TO_UNSIGNED(1767, 11), TO_UNSIGNED( 839, 11),
TO_UNSIGNED(1055, 11), TO_UNSIGNED(1186, 11), TO_UNSIGNED(1332, 11), TO_UNSIGNED(1634, 11), TO_UNSIGNED(1753, 11), TO_UNSIGNED( 863, 11), TO_UNSIGNED(1079, 11), TO_UNSIGNED(1214, 11),
TO_UNSIGNED(1361, 11), TO_UNSIGNED(1494, 11), TO_UNSIGNED(1781, 11), TO_UNSIGNED( 731, 11), TO_UNSIGNED(1091, 11), TO_UNSIGNED(1228, 11), TO_UNSIGNED(1375, 11), TO_UNSIGNED(1508, 11),
TO_UNSIGNED(1795, 11), TO_UNSIGNED( 725, 11), TO_UNSIGNED(1085, 11), TO_UNSIGNED(1221, 11), TO_UNSIGNED(1368, 11), TO_UNSIGNED(1500, 11), TO_UNSIGNED(1788, 11), TO_UNSIGNED( 737, 11),
TO_UNSIGNED(1097, 11), TO_UNSIGNED(1235, 11), TO_UNSIGNED(1382, 11), TO_UNSIGNED(1515, 11), TO_UNSIGNED(1802, 11), TO_UNSIGNED( 755, 11), TO_UNSIGNED(1115, 11), TO_UNSIGNED(1256, 11),
TO_UNSIGNED(1403, 11), TO_UNSIGNED(1536, 11), TO_UNSIGNED(1823, 11), TO_UNSIGNED( 761, 11), TO_UNSIGNED(1121, 11), TO_UNSIGNED(1263, 11), TO_UNSIGNED(1410, 11), TO_UNSIGNED(1543, 11),
TO_UNSIGNED(1662, 11), TO_UNSIGNED( 767, 11), TO_UNSIGNED(1127, 11), TO_UNSIGNED(1270, 11), TO_UNSIGNED(1417, 11), TO_UNSIGNED(1550, 11), TO_UNSIGNED(1669, 11), TO_UNSIGNED( 773, 11),
TO_UNSIGNED(1133, 11), TO_UNSIGNED(1277, 11), TO_UNSIGNED(1424, 11), TO_UNSIGNED(1557, 11), TO_UNSIGNED(1676, 11), TO_UNSIGNED( 779, 11), TO_UNSIGNED(1139, 11), TO_UNSIGNED(1284, 11),
TO_UNSIGNED(1431, 11), TO_UNSIGNED(1564, 11), TO_UNSIGNED(1683, 11), TO_UNSIGNED( 743, 11), TO_UNSIGNED(1103, 11), TO_UNSIGNED(1242, 11), TO_UNSIGNED(1389, 11), TO_UNSIGNED(1522, 11),
TO_UNSIGNED(1809, 11), TO_UNSIGNED( 749, 11), TO_UNSIGNED(1109, 11), TO_UNSIGNED(1249, 11), TO_UNSIGNED(1396, 11), TO_UNSIGNED(1529, 11), TO_UNSIGNED(1816, 11), TO_UNSIGNED( 809, 11),
TO_UNSIGNED(1024, 11), TO_UNSIGNED(1319, 11), TO_UNSIGNED(1466, 11), TO_UNSIGNED(1599, 11), TO_UNSIGNED(1718, 11), TO_UNSIGNED( 791, 11), TO_UNSIGNED(1151, 11), TO_UNSIGNED(1298, 11),
TO_UNSIGNED(1445, 11), TO_UNSIGNED(1578, 11), TO_UNSIGNED(1697, 11), TO_UNSIGNED( 797, 11), TO_UNSIGNED(1013, 11), TO_UNSIGNED(1305, 11), TO_UNSIGNED(1452, 11), TO_UNSIGNED(1585, 11),
TO_UNSIGNED(1704, 11), TO_UNSIGNED( 785, 11), TO_UNSIGNED(1145, 11), TO_UNSIGNED(1291, 11), TO_UNSIGNED(1438, 11), TO_UNSIGNED(1571, 11), TO_UNSIGNED(1690, 11), TO_UNSIGNED( 803, 11),
TO_UNSIGNED(1019, 11), TO_UNSIGNED(1312, 11), TO_UNSIGNED(1459, 11), TO_UNSIGNED(1592, 11), TO_UNSIGNED(1711, 11), TO_UNSIGNED( 821, 11), TO_UNSIGNED(1037, 11), TO_UNSIGNED(1164, 11),
TO_UNSIGNED(1480, 11), TO_UNSIGNED(1613, 11), TO_UNSIGNED(1732, 11), TO_UNSIGNED( 17, 11), TO_UNSIGNED(1025, 11), TO_UNSIGNED(1501, 11), TO_UNSIGNED(1165, 11), TO_UNSIGNED(1333, 11)
);
SIGNAL READ_C : UNSIGNED(10 downto 0);
SIGNAL WRITE_C : UNSIGNED(10 downto 0);
SIGNAL ROM_ADR : UNSIGNED(10 downto 0);
SIGNAL OUT_BIS : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL WE_BIS : STD_LOGIC;
SIGNAL HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
--WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
--WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
-- COMPTEUR EMPLOYE POUR L'ECRITURE DES DONNEES
--
PROCESS(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
BEGIN
IF reset = '0' THEN
WRITE_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' THEN
IF WRITE_EN = '1' AND HOLDN = '1' THEN
TEMP := WRITE_C + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
WE_BIS <= '1';
WRITE_C <= TEMP;
ELSE
WE_BIS <= '0';
WRITE_C <= WRITE_C;
END IF;
OP1 := SIGNED( INPUT_2(31) & INPUT_2(31 downto 16) ); -- ON RECUPERE LA VALEUR QUI EST DANS LES MSB
OP2 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) ); -- ON RECUPERE LA SOMME DANS LES LSBs
OP3 := OP2 - OP1;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
IN_BIS <= STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
IN_BIS <= STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
IN_BIS <= STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END if;
END PROCESS;
--
-- COMPTEUR EMPLOYE POUR LA LECTURE DES DONNEES
--
-- process(clock, reset)
-- VARIABLE TEMP : UNSIGNED(10 downto 0);
-- begin
-- if reset = '0' then
-- READ_C <= TO_UNSIGNED(0, 11);
-- elsif clock'event and clock = '1' then
-- if read_en = '1' AND holdn = '1' then
-- TEMP := READ_C + TO_UNSIGNED(1, 11);
-- IF TEMP = 1824 THEN
-- TEMP := TO_UNSIGNED(0, 11);
-- END IF;
-- READ_C <= TEMP;
-- else
-- READ_C <= READ_C;
-- end if;
-- end if;
-- end process;
process(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
end if;
READ_C <= TEMP;
TMP := RAM( to_integer( TEMP ) );
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE( SIGNED(TMP), 32) ) ;
end if;
end process;
--
--
--
process(clock)
VARIABLE ADR : INTEGER RANGE 0 to 1823;
VARIABLE POS : INTEGER RANGE 0 to 1823;
begin
if clock'event and clock = '1' then
ADR := to_integer( WRITE_C );
ROM_ADR <= ROM( ADR );
end if;
end process;
--
--
--
process(clock)
begin
if clock'event and clock = '1' then
if WE_BIS = '1' then
RAM( to_integer( ROM_ADR ) ) <= IN_BIS;
end if;
--OUT_BIS <= RAM( to_integer(READ_C) );
end if;
end process;
--OUTPUT_1 <= "0000000000000000" & OUT_BIS;
END cRAM;
| gpl-3.0 | 2cf1e5617481e491264635014b46d0ea | 0.648857 | 2.825715 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/cpu_top.vhd | 1 | 20,301 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cpu_top is
Port
(
port_clk_50: in std_logic; --50MHz clock
port_clk_key: in std_logic; --One-Step clk key
port_switch: in std_logic_vector(15 downto 0); --On-board switch
port_rst: in std_logic; --Reset key
port_mem1_oe: out std_logic; --Memory#1 signal
port_mem1_we: out std_logic;
port_mem1_en: out std_logic;
port_mem1_addr: out std_logic_vector(17 downto 0);
port_mem1_data: inout std_logic_vector(15 downto 0);
port_mem2_oe: out std_logic; --Memory#1 signal
port_mem2_we: out std_logic;
port_mem2_en: out std_logic;
port_mem2_addr: out std_logic_vector(17 downto 0);
port_mem2_data: inout std_logic_vector(15 downto 0);
port_com_data_ready: in std_logic; --COM signal
port_com_rdn: out std_logic;
port_com_tbre: inout std_logic;
port_com_tsre: inout std_logic;
port_com_wrn: out std_logic;
port_led: out std_logic_vector(15 downto 0) --On-board LED
);
end cpu_top;
architecture Behavioral of cpu_top is
component clkkey is
port
(
clkkey_port_clk: in std_logic;
clkkey_clk: out std_logic
);
end component;
signal internal_debug_clk: std_logic;
component switch is
port
(
switch_port_switch: in std_logic_vector(15 downto 0);
switch_switch: out std_logic_vector(15 downto 0)
);
end component;
signal internal_switch: std_logic_vector(15 downto 0);
signal internal_debug: std_logic_vector(15 downto 0) := "0000000000000000";
component mux_wb is
Port(
regsrc : in STD_LOGIC_VECTOR(1 downto 0);
input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component mcmgmt is
port
(
mcmgmt_clk: in std_logic;
mcmgmt_rst: in std_logic;
mcmgmt_port_mem1_oe: out std_logic;
mcmgmt_port_mem1_we: out std_logic;
mcmgmt_port_mem1_en: out std_logic;
mcmgmt_port_mem1_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem1_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_mem2_oe: out std_logic;
mcmgmt_port_mem2_we: out std_logic;
mcmgmt_port_mem2_en: out std_logic;
mcmgmt_port_mem2_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem2_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_com_data_ready: in std_logic;
mcmgmt_port_com_rdn: out std_logic;
mcmgmt_port_com_tbre: inout std_logic;
mcmgmt_port_com_tsre: inout std_logic;
mcmgmt_port_com_wrn: out std_logic;
mcmgmt_addr: in std_logic_vector(19 downto 0);
mcmgmt_idata: in std_logic_vector(15 downto 0);
mcmgmt_odata: out std_logic_vector(15 downto 0);
mcmgmt_rw: in std_logic;
mcmgmt_by_byte: in std_logic;
mcmgmt_byte_select: in std_logic;
mcmgmt_free: out std_logic;
mcmgmt_int: out std_logic;
mcmgmt_debug_status: out std_logic_vector(4 downto 0)
);
end component;
signal internal_mcmgmt_data: std_logic_vector(15 downto 0);
signal internal_mcmgmt_free: std_logic;
signal internal_mcmgmt_debug_status: std_logic_vector(4 downto 0);
signal internal_mcmgmt_ins: std_logic_vector(15 downto 0);
component alu is
port
(
alu_input1: in std_logic_vector(15 downto 0);
alu_input2: in std_logic_vector(15 downto 0);
alu_output: out std_logic_vector(15 downto 0);
alu_operator: in std_logic_vector(2 downto 0)
);
end component;
signal alu_src_data1:std_logic_vector(15 downto 0);
signal alu_src_data2:std_logic_vector(15 downto 0);
signal alu_result:std_logic_vector(15 downto 0);
signal alu_idex_op:std_logic_vector(2 downto 0);
component add_pc is --PC×Ô¼ÓÆ÷
Port (
input1 : in STD_LOGIC_VECTOR(15 downto 0);
input2 : in STD_LOGIC_VECTOR(15 downto 0);
output : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
signal pc_output: STD_LOGIC_VECTOR(15 downto 0);
signal pc_add2: STD_LOGIC_VECTOR(15 downto 0);
component pc is
Port (
pc_in: in std_logic_vector(15 downto 0);
pc_out: out std_logic_vector(15 downto 0);
pc_clk: in std_logic;
pc_rst: in std_logic
);
end component;
signal pc_input:STD_LOGIC_VECTOR(15 downto 0):="0000000000000001";
component mux_pc is
Port(
pcsrc : in STD_LOGIC_VECTOR (2 downto 0);
input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
input3 : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal pc_src_op: STD_LOGIC_VECTOR (2 downto 0);
signal pc_reg: STD_LOGIC_VECTOR (15 downto 0);
--******************¼Ä´æÆ÷¶Ñ
component regfile is
port
(
regfile_clk: in std_logic;
regfile_rst: in std_logic;
regfile_we: in std_logic;
regfile_waddr: in std_logic_vector(3 downto 0);
regfile_wdata: in std_logic_vector(15 downto 0);
regfile_raddr1: in std_logic_vector(3 downto 0);
regfile_rdata1: out std_logic_vector(15 downto 0);
regfile_raddr2: in std_logic_vector(3 downto 0);
regfile_rdata2: out std_logic_vector(15 downto 0)
);
end component;
signal regfile_port_we:std_logic;
signal regfile_port_waddr: std_logic_vector(3 downto 0);
signal regfile_port_wdata: std_logic_vector(15 downto 0);
signal regfile_port_raddr1: std_logic_vector(3 downto 0);
signal regfile_port_rdata1: std_logic_vector(15 downto 0);
signal regfile_port_raddr2: std_logic_vector(3 downto 0);
signal regfile_port_rdata2: std_logic_vector(15 downto 0);
--******************
component mux_reg1 is
Port ( alusrca : in STD_LOGIC_VECTOR (1 downto 0);
muxreg1 : in STD_LOGIC_VECTOR (15 downto 0);
mux_PC : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataA : out STD_LOGIC_VECTOR (15 downto 0)
);
end component ;
component mux_reg2 is
Port ( alusrcb : in STD_LOGIC_VECTOR (1 downto 0);
muxreg2 : in STD_LOGIC_VECTOR (15 downto 0);
mux_imm : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataB : out STD_LOGIC_VECTOR (15 downto 0)
);
end component ;
component mux_result is
Port ( alusrc : in STD_LOGIC_VECTOR (1 downto 0);
mux_alures : in STD_LOGIC_VECTOR (15 downto 0);
mux_menres : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataC : out STD_LOGIC_VECTOR (15 downto 0));
end component ;
signal ex_mux_result:std_logic_vector(15 downto 0);
--¶à·ѡÔñÆ÷
component decoder is
Port ( reg1 : out STD_LOGIC_VECTOR (3 downto 0);--¶Á³öµÄ¼Ä´æÆ÷
reg2 : out STD_LOGIC_VECTOR (3 downto 0);--¶Á³öµÄ¼Ä´æÆ÷
reg3 : out STD_LOGIC_VECTOR (3 downto 0);--д»ØµÄ¼Ä´æÆ÷
imm : out STD_LOGIC_VECTOR (15 downto 0);--À©Õ¹ºóµÄÁ¢¼´Êý
imm1 : out STD_LOGIC_VECTOR (15 downto 0);--À©Õ¹ºóµÄÁ¢¼´Êý
rw : out std_logic;--ÄÚ´æ¶Áд
we : out std_logic;
muxop1 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷1
muxop2 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷2
muxop3 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷3
muxop4 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷4
muxpc : out std_logic_vector(2 downto 0);--¶à·ѡÔñÆ÷pc
aluop : out std_logic_vector(2 downto 0);--alu²Ù×÷Êý
instruction : in STD_LOGIC_VECTOR (15 downto 0)--Ö¸Áî
);
end component;
signal id_mux_reg1:std_logic_vector(1 downto 0);
signal id_mux_reg2:std_logic_vector(1 downto 0);
signal id_mux_imm:std_logic_vector(15 downto 0);
signal id_mux:std_logic_vector(1 downto 0);
--******************IF_ID
component if_id_segment_regfile is
port
(
if_id_segment_regfile_clk: in std_logic;
if_id_segment_regfile_write_in: in std_logic;
if_id_segment_regfile_instruction_in: in std_logic_vector(15 downto 0);
if_id_segment_regfile_instruction_out: out std_logic_vector(15 downto 0);
--id_ex_segment_regfiel_we_result_in: in std_logic_vector (1 downto 0);
-- id_ex_segment_regfiel_we_result_out: out std_logic_vector (1 downto 0);
if_id_segment_regfile_pc_in: in std_logic_vector(15 downto 0);
if_id_segment_regfile_pc_out: out std_logic_vector(15 downto 0)
);
end component;
signal if_id_regfile_instruction: std_logic_vector(15 downto 0);
signal if_id_pc: std_logic_vector(15 downto 0);
--****************id_ex
component id_ex_segment_regfile is
port
(
id_ex_segment_regfile_clk : in std_logic;
id_ex_segment_regfile_write_in : in std_logic;
id_ex_segment_regfile_rdata1_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata2_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata1_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata2_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_pc_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_pc_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_alu_op_in : in std_logic_vector (2 downto 0);
id_ex_segment_regfile_alu_op_out : out std_logic_vector (2 downto 0);
id_ex_segment_regfile_reg_rx_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_reg_rx_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_mem_we_in : in std_logic;
id_ex_segment_regfile_mem_we_out : out std_logic;
id_ex_segment_regfile_pc_src_in : in std_logic_vector (2 downto 0);
id_ex_segment_regfile_pC_src_out : out std_logic_vector (2 downto 0);
id_ex_segment_regfile_reg_ry_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_reg_ry_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_src_result_in : in std_logic_vector (1 downto 0);
id_ex_segment_regfile_src_result_out : out std_logic_vector (1 downto 0);
id_ex_segment_regfile_reg_we_in : in std_logic;
id_ex_segment_regfile_reg_we_out : out std_logic;
id_ex_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
id_ex_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
id_ex_segment_regfile_imm_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_imm_out : out std_logic_vector (15 downto 0));
end component;
signal id_ex_pc: std_logic_vector(15 downto 0);
signal id_ex_regfile_alu_op: std_logic_vector(2 downto 0);
signal id_ex_regfile_reg_rx: std_logic_vector(15 downto 0);
signal id_ex_regfile_mem_we: std_logic;
signal regfile_mem_we: std_logic;
signal id_ex_regfile_pc_src: std_logic_vector(2 downto 0);
signal id_ex_regfile_reg_ry: std_logic_vector(15 downto 0);
signal regfile_reg_ry: std_logic_vector(15 downto 0);
signal id_ex_regfile_src_result: std_logic_vector(1 downto 0);
signal regfile_src_result: std_logic_vector(1 downto 0);
signal id_ex_regfile_reg_we: std_logic;
signal regfile_reg_we: std_logic;
signal id_ex_regfile_imm:std_logic_vector(15 downto 0);
signal regfile_imm:std_logic_vector(15 downto 0);
signal regfile_port_rdataA : std_logic_vector (15 downto 0);
signal regfile_port_rdataB : std_logic_vector (15 downto 0);
signal id_ex_regfile_we_result: std_logic_vector(1 downto 0);
--****************ex_mem
component ex_mem_segment_regfile is
port
(
ex_mem_segment_regfile_clk: in std_logic;
ex_mem_segment_regfile_write_in: in std_logic;
ex_mem_segment_regfile_alu_result_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_alu_result_out: out std_logic_vector(15 downto 0);
ex_mem_segment_regfile_mem_we_in: in std_logic;
ex_mem_segment_regfile_mem_we_out: out std_logic;
ex_mem_segment_regfile_reg_ry_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_reg_ry_out: out std_logic_vector(15 downto 0);
ex_mem_segment_regfile_src_result_in: in std_logic_vector(1 downto 0);
ex_mem_segment_regfile_src_result_out: out std_logic_vector(1 downto 0);
ex_mem_segment_regfile_reg_we_in: in std_logic;
ex_mem_segment_regfile_reg_we_out: out std_logic;
ex_mem_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
ex_mem_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
ex_mem_segment_regfile_imm_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_imm_out: out std_logic_vector(15 downto 0)
);
end component;
signal ex_mem_regfile_alu_result: std_logic_vector(15 downto 0);
signal ex_mem_regfile_mem_we: std_logic;
signal ex_mem_regfile_reg_ry: std_logic_vector(15 downto 0);
signal ex_mem_regfile_src_result : std_logic_vector(1 downto 0);
signal ex_mem_regfile_reg_we: std_logic;
signal ex_mem_regfile_imm: std_logic_vector(15 downto 0);
signal ex_mem_regfile_we_result : std_logic_vector(1 downto 0);
--**********************mem_we
component mem_we_segment_regfile is
port
(
mem_we_segment_regfile_clk: in std_logic;
mem_we_segment_regfile_write_in: in std_logic;
mem_we_segment_regfile_result_in: in std_logic_vector(15 downto 0);
mem_we_segment_regfile_result_out: out std_logic_vector(15 downto 0);
mem_we_segment_regfile_reg_we_in: in std_logic;
mem_we_segment_regfile_reg_we_out: out std_logic;
mem_we_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
mem_we_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
mem_we_segment_regfile_imm_in: in std_logic_vector(15 downto 0);
mem_we_segment_regfile_imm_out: out std_logic_vector(15 downto 0)
);
end component;
signal mem_we_regfile_result: std_logic_vector(15 downto 0);
signal mem_we_regfile_imm: std_logic_vector(15 downto 0);
signal mem_we_regfile_we_result : std_logic_vector(1 downto 0);
--*****************************
begin
clkkey1: clkkey port map
(
clkkey_port_clk => port_clk_key,
clkkey_clk => internal_debug_clk
);
switch1: switch port map
(
switch_port_switch => port_switch,
switch_switch => internal_switch
);
alu1: alu port map(
alu_input1 => alu_src_data1,
alu_input2 => alu_src_data2,
alu_output => port_led,
alu_operator => alu_idex_op
);
addpc1:add_pc port map(
input1 => pc_output,
input2 => "0000000000000010",
output => pc_add2
);
pc1: pc port map(
pc_in => pc_input,
pc_out => pc_output,
pc_clk => port_clk_key,
pc_rst => port_rst
);
mux_pc1:mux_pc port map(
pcsrc => pc_src_op,
input1 => pc_add2,
input2 => regfile_port_rdata1,
input3 => alu_result,
output=> pc_input
);
mux_wb1:mux_wb port map(
regsrc=>mem_we_regfile_we_result,
input1=>mem_we_regfile_result,
input2=> mem_we_regfile_imm,
output=> regfile_port_wdata
);
mcmgmt1: mcmgmt port map
(
mcmgmt_clk => port_clk_key,
mcmgmt_rst => port_rst,
mcmgmt_port_mem1_oe => port_mem1_oe,
mcmgmt_port_mem1_we => port_mem1_we,
mcmgmt_port_mem1_en => port_mem1_en,
mcmgmt_port_mem1_addr => port_mem1_addr,
mcmgmt_port_mem1_data => port_mem1_data,
mcmgmt_port_mem2_oe => port_mem2_oe,
mcmgmt_port_mem2_we => port_mem2_we,
mcmgmt_port_mem2_en => port_mem2_en,
mcmgmt_port_mem2_addr => port_mem2_addr,
mcmgmt_port_mem2_data => port_mem2_data,
mcmgmt_port_com_data_ready => port_com_data_ready,
mcmgmt_port_com_rdn => port_com_rdn,
mcmgmt_port_com_tbre => port_com_tbre,
mcmgmt_port_com_tsre => port_com_tsre,
mcmgmt_port_com_wrn => port_com_wrn,
mcmgmt_addr => "00000000000000000000",
mcmgmt_idata => "1111111111111111",
mcmgmt_odata =>internal_mcmgmt_ins,
mcmgmt_rw => '1',
mcmgmt_by_byte => '1',
mcmgmt_byte_select => '1',
mcmgmt_free => internal_mcmgmt_free,
mcmgmt_int => open,
mcmgmt_debug_status => internal_mcmgmt_debug_status
);
internal_debug <= internal_mcmgmt_debug_status & "01010101011";
--************
regfile1: regfile port map
(
regfile_clk=>port_clk_key,
regfile_rst=>port_rst,
regfile_we=>regfile_port_we,
regfile_waddr=> regfile_port_waddr,
regfile_wdata=> regfile_port_wdata,
regfile_raddr1=>regfile_port_raddr1,
regfile_rdata1=> regfile_port_rdata1,
regfile_raddr2=> regfile_port_raddr2,
regfile_rdata2=>regfile_port_rdata2
);
--************
mux_reg11: mux_reg1 port map(
alusrca=>id_mux_reg1,
muxreg1=>regfile_port_rdata1,
mux_PC=>pc_add2,
mux_dataA=>regfile_port_rdataA
);
mux_reg21: mux_reg2 port map(
alusrcb=>id_mux_reg2,
muxreg2=>regfile_port_rdata2,
mux_imm=>id_mux_imm,
mux_dataB=>regfile_port_rdataB
);
mux_result1: mux_result port map(
alusrc=>ex_mem_regfile_src_result,
mux_alures=>ex_mem_regfile_alu_result,
mux_menres=>internal_mcmgmt_data,
mux_dataC=>ex_mux_result
);
--************
decoder1: decoder port map(
instruction =>if_id_regfile_instruction,
imm1=>id_ex_regfile_imm,
rw=>id_ex_regfile_mem_we,
we=>id_ex_regfile_reg_we,
aluop=>id_ex_regfile_alu_op,
muxpc=>id_ex_regfile_pc_src,
muxop3=>id_ex_regfile_src_result,
muxop4=>id_mux,
reg1=>regfile_port_raddr1,
reg2=>regfile_port_raddr2,
reg3=>regfile_port_waddr,
imm=>id_mux_imm,
muxop2=>id_mux_reg2,
muxop1=>id_mux_reg1
);
--****************if_id
if_id_segment_regfile1: if_id_segment_regfile port map
(
if_id_segment_regfile_clk=>port_clk_key,
if_id_segment_regfile_write_in=>'1',
if_id_segment_regfile_instruction_in=>port_switch,
if_id_segment_regfile_instruction_out=> if_id_regfile_instruction,
if_id_segment_regfile_pc_in=>pc_output,
if_id_segment_regfile_pc_out=>if_id_pc
);
--************id_ex
id_ex_segment_regfile1: id_ex_segment_regfile port map
(
id_ex_segment_regfile_clk=>port_clk_key,
id_ex_segment_regfile_write_in =>'1',
id_ex_segment_regfile_rdata1_in =>regfile_port_rdataA,
id_ex_segment_regfile_rdata2_in => regfile_port_rdataB,
id_ex_segment_regfile_rdata1_out =>alu_src_data1,
id_ex_segment_regfile_rdata2_out => alu_src_data2,
id_ex_segment_regfile_pc_in => if_id_pc,
id_ex_segment_regfile_pc_out =>id_ex_pc,
id_ex_segment_regfile_alu_op_in =>id_ex_regfile_alu_op,
id_ex_segment_regfile_alu_op_out =>alu_idex_op,
id_ex_segment_regfile_reg_rx_in => id_ex_regfile_reg_rx,
id_ex_segment_regfile_reg_rx_out =>pc_reg,
id_ex_segment_regfile_mem_we_in => id_ex_regfile_mem_we,
id_ex_segment_regfile_mem_we_out => regfile_mem_we,
id_ex_segment_regfile_pc_src_in=>id_ex_regfile_pc_src,
id_ex_segment_regfile_pc_src_out=>pc_src_op,
id_ex_segment_regfile_reg_ry_in =>id_ex_regfile_reg_ry,
id_ex_segment_regfile_reg_ry_out =>regfile_reg_ry,
id_ex_segment_regfile_src_result_in =>id_ex_regfile_src_result,
id_ex_segment_regfile_src_result_out =>regfile_src_result,
id_ex_segment_regfile_reg_we_in =>id_ex_regfile_reg_we,
id_ex_segment_regfile_reg_we_out =>regfile_reg_we,
id_ex_segment_regfile_we_result_in=> id_mux,
id_ex_segment_regfile_we_result_out=>id_ex_regfile_we_result,
id_ex_segment_regfile_imm_in =>id_ex_regfile_imm,
id_ex_segment_regfile_imm_out =>regfile_imm
);
--***************ex_mem
ex_mem_segment_regfile1: ex_mem_segment_regfile port map
(
ex_mem_segment_regfile_clk => port_clk_key,
ex_mem_segment_regfile_write_in=> '1',
ex_mem_segment_regfile_alu_result_in=>alu_result,
ex_mem_segment_regfile_alu_result_out=>ex_mem_regfile_alu_result,
ex_mem_segment_regfile_mem_we_in=>regfile_mem_we,
ex_mem_segment_regfile_mem_we_out=>ex_mem_regfile_mem_we,
ex_mem_segment_regfile_reg_ry_in=>regfile_reg_ry,
ex_mem_segment_regfile_reg_ry_out=>ex_mem_regfile_reg_ry,
ex_mem_segment_regfile_src_result_in=>regfile_src_result,
ex_mem_segment_regfile_src_result_out=> ex_mem_regfile_src_result,
ex_mem_segment_regfile_reg_we_in=>regfile_reg_we,
ex_mem_segment_regfile_reg_we_out=>ex_mem_regfile_reg_we,
ex_mem_segment_regfile_we_result_in=>id_ex_regfile_we_result,
ex_mem_segment_regfile_we_result_out=>ex_mem_regfile_we_result,
ex_mem_segment_regfile_imm_in=>regfile_imm,
ex_mem_segment_regfile_imm_out=>ex_mem_regfile_imm
);
--****************mem-we
mem_we_segment_regfile1: mem_we_segment_regfile port map
(
mem_we_segment_regfile_clk=>port_clk_key,
mem_we_segment_regfile_write_in => '1',
mem_we_segment_regfile_result_in => ex_mux_result,
mem_we_segment_regfile_result_out=>mem_we_regfile_result,
mem_we_segment_regfile_reg_we_in=>ex_mem_regfile_reg_we,
mem_we_segment_regfile_reg_we_out=>regfile_port_we,
mem_we_segment_regfile_we_result_in=>ex_mem_regfile_we_result,
mem_we_segment_regfile_we_result_out=>mem_we_regfile_we_result,
mem_we_segment_regfile_imm_in=>ex_mem_regfile_imm,
mem_we_segment_regfile_imm_out=>mem_we_regfile_imm
);
end Behavioral;
| apache-2.0 | f805e6bad58fc6f3a70ed3b6862bab93 | 0.683365 | 2.775256 | false | false | false | false |
siam28/neppielight | spiout.vhd | 2 | 2,125 | ----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 21:43:14 02/02/2015
-- Design Name: SPI driver for WS2801 led strings
-- Module Name: spiout - Behavioral
-- Project Name: Neppielight
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spiout is
Port ( clk50 : in STD_LOGIC;
data : in std_logic_vector(0 to 24*25-1); -- MSB first
MOSI : out STD_LOGIC;
SCK : out STD_LOGIC);
end spiout;
architecture Behavioral of spiout is
signal sck_counter : std_logic_vector(15 downto 0);
signal sck_s : std_logic;
signal sck_enable : std_logic := '1';
signal wrcnt: std_logic_vector(9 downto 0) := (others => '0');
begin
process(clk50,sck_counter,sck_enable)
begin
if (rising_edge(clk50)) then
sck_counter <= sck_counter + 1;
end if;
sck_s <= sck_counter(11);
end process;
process(sck_s, sck_enable)
begin
-- Assert MOSI on the falling edge
-- So it can be sampled by the WS2801 on the rising edge.
if (falling_edge(sck_s)) then
if wrcnt <= 599 then
MOSI <= data(to_integer(unsigned(wrcnt)));
wrcnt <= (wrcnt + 1);
sck_enable <= '1'; -- this will let the clock go high on the next rising edge.
elsif wrcnt = 600 then
MOSI <= '0';
sck_enable <= '0';
wrcnt <= (wrcnt + 1);
elsif wrcnt = 640 then
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (others =>'0');
else
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (wrcnt + 1);
end if;
end if;
if sck_enable = '1' then
SCK <= sck_s;
else
SCK <= '0';
end if;
end process;
end Behavioral;
| gpl-2.0 | 90246aee062afaefa37db930c3ae96ff | 0.575529 | 3.432956 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/MAXIMUM_MINIMUM_32b.vhd | 1 | 1,788 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:19:12 02/17/2011
-- Design Name:
-- Module Name: MINIMUM_MAXIMUM_32b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MINIMUM_MAXIMUM_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR( 1 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end MINIMUM_MAXIMUM_32b;
architecture rtl of MINIMUM_MAXIMUM_32b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
wait for 1 ns;
REPORT "(IMS) MINIMUM RESOURCE : ALLOCATION OK !";
wait;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2, FONCTION)
variable decision : std_logic;
begin
if( SIGNED(INPUT_1) < SIGNED(INPUT_2) ) then
decision := '1';
else
decision := '0';
end if;
-- SI LE BIT DE POIDS FAIBLE = 1 CE SIGNIFIE QUE L'ON
-- VEUT CALCULER LE MINIMUM DES 2 NOMBRES
decision := decision xor FONCTION(1);
if( decision = '1' ) then
OUTPUT_1 <= INPUT_1;
else
OUTPUT_1 <= INPUT_2;
end if;
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | f134c88c760586f01789365ec1f013a2 | 0.474832 | 3.90393 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_uart/src/uart_bfm_pkg.vhd | 1 | 26,302 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: This BFM is only intended as a simplified UART BFM to be used as a test
-- vehicle for presenting UVVM functionality.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library STD;
use std.textio.all;
--=================================================================================================
package uart_bfm_pkg is
--===============================================================================================
-- Types and constants for UART BFMs
--===============================================================================================
constant C_SCOPE : string := "UART BFM";
-- Configuration record to be assigned in the test harness.
type t_parity is (
PARITY_NONE,
PARITY_ODD,
PARITY_EVEN
);
type t_stop_bits is (
STOP_BITS_ONE,
STOP_BITS_ONE_AND_HALF,
STOP_BITS_TWO
);
constant C_DATA_MAX_LENGTH : natural := 8;
constant C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR : string := "; ";
type uart_expect_received_data_array is array (natural range<>) of std_logic_vector(C_DATA_MAX_LENGTH-1 downto 0);
type t_uart_bfm_config is
record
bit_time : time; -- The time it takes to transfer one bit
num_data_bits : natural range 7 to 8; -- Number of data bits to send per transmission
idle_state : std_logic; -- Bit value when line is idle
num_stop_bits : t_stop_bits; -- Number of stop-bits to use per transmission {STOP_BITS_ONE, STOP_BITS_ONE_AND_HALF, STOP_BITS_TWO}
parity : t_parity; -- Transmission parity bit {PARITY_NONE, PARITY_ODD, PARITY_EVEN}
timeout : time; -- The maximum time to pass before the expected data must be received. Exceeding this limit results in an alert with severity ‘alert_level’.
timeout_severity : t_alert_level; -- The above timeout will have this severity
num_bytes_to_log_before_expected_data : natural; -- Maximum number of bytes to save ahead of the expected data in the receive buffer. The bytes in the receive buffer will be logged.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the UART BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the UART BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the UART BFM
id_for_bfm_poll_summary : t_msg_id; -- The message ID used for logging polling summary in the UART BFM
end record;
constant C_UART_BFM_CONFIG_DEFAULT : t_uart_bfm_config := (
bit_time => -1 ns,
num_data_bits => 8,
idle_state => '1',
num_stop_bits => STOP_BITS_ONE,
parity => PARITY_ODD,
timeout => 0 ns, -- will default never time out
timeout_severity => error,
num_bytes_to_log_before_expected_data => 10,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
id_for_bfm_poll_summary => ID_BFM_POLL_SUMMARY
);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
------------------------------------------
-- uart_transmit
------------------------------------------
-- - This procedure transmits data 'data_value' to the UART DUT
-- - The TX configuration can be set in the config parameter
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- uart_receive
------------------------------------------
-- - This procedure reads data from the UART DUT and returns it in 'data_value'
-- - The RX configuration can be set in the config parameter
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
);
------------------------------------------
-- uart_expect
------------------------------------------
-- - This procedure reads data from the UART DUT and compares it to the data in
-- 'data_exp'.
-- - If the read data is inconsistent with the 'data_exp' data, a new read will
-- be performed, and the new read data will be compared with 'data_exp'.
-- This process will continue untill one of the following conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_receptions'
-- c) The time spent reading is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_receptions' is set to 0, it will be interpreted as no limitation on number of reads
-- - The RX configuration can be set in the config parameter
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- odd_parity
------------------------------------------
-- - This function checks if the data parity is odd or even
-- - If the number of '1' in the 'data' input is odd, '1' will be returned
-- - If the number of '1' in the 'data' input is even, '0' will be returned
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body uart_bfm_pkg is
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic is
begin
return xnor(data);
end odd_parity;
---------------------------------------------------------------------------------
-- uart_transmit
---------------------------------------------------------------------------------
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_transmit";
constant proc_call : string := proc_name & "(" & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- check if tx line was idle when trying to transmit data
check_value(tx, config.idle_state, FAILURE, proc_call & " Bus was active when trying to send data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
tx <= not config.idle_state;
wait for config.bit_time;
for j in data_value'low to data_value'high loop
tx <= data_value(j);
wait for config.bit_time;
end loop;
-- parity?
if (config.parity = PARITY_ODD) then
tx <= odd_parity(data_value);
wait for config.bit_time;
elsif(config.parity = PARITY_EVEN) then
tx <= not odd_parity(data_value);
wait for config.bit_time;
end if;
-- stop bits
tx <= config.idle_state;
wait for config.bit_time;
if (config.num_stop_bits = STOP_BITS_ONE_AND_HALF) then
wait for config.bit_time/2;
elsif(config.num_stop_bits = STOP_BITS_TWO) then
wait for config.bit_time;
end if;
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- uart_receive
---------------------------------------------------------------------------------
-- Perform a receive operation
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
) is
constant start_time : time := now;
-- local_proc_* used if uart_receive is called directly from sequencer or VVC
constant local_proc_name : string := "uart_receive";
constant local_proc_call : string := local_proc_name & "()";
-- Helper variables
variable v_transfer_time : time;
variable v_proc_call : line; -- Current proc_call, external or internal
variable v_remaining_time : time; -- temp variable to calculate the remaining time before timeout
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_terminated : boolean := false;
variable v_timeout : boolean := false;
begin
-- check whether config.bit_time was set properly
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
data_value := (data_value'range => 'X');
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If timeout enabled, check that timeout is longer than transfer time
if config.timeout /= 0 ns then
v_transfer_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_transfer_time := v_transfer_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
check_value(v_transfer_time < config.timeout, TB_ERROR, "Length of timeout is shorter than or equal length of transfer time.", C_SCOPE, ID_NEVER, msg_id_panel);
end if;
if ext_proc_call = "" then
-- called from sequencer/VVC, show 'uart_receive()...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like uart_expect, log 'uart_expect() while executing uart_receive()...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name & ". ");
end if;
-- check if bus is in idle state
check_value(rx, config.idle_state, FAILURE, v_proc_call.all & "Bus was active when trying to receive data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait until the start bit is sent on the bus, configured timeout occures or procedure get terminate signal
if config.timeout = 0 ns then
wait until (rx = not config.idle_state) or (terminate_loop = '1');
else
wait until (rx = not config.idle_state) or (terminate_loop = '1') for config.timeout;
end if;
if terminate_loop = '1' then
if ext_proc_call = "" then
log(ID_TERMINATE_CMD, v_proc_call.all & "=> terminated." & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- termination handled in calling procedure
end if;
v_terminated := true;
end if;
-- if configured timeout, check if there is enough time remaining to receive the byte
if config.timeout /= 0 ns and not v_terminated then
v_remaining_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_remaining_time := v_remaining_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if now + v_remaining_time > start_time + config.timeout then
-- wait until timeout
wait for ((start_time + config.timeout) - now);
if ext_proc_call = "" then
alert(config.timeout_severity, v_proc_call.all & "=> timeout. " & add_msg_delimiter(msg),scope);
else
-- timeout handled in upper module
end if;
v_timeout := true;
end if;
end if;
if not v_terminated and not v_timeout then
-- enter the middle of the bit period
wait for config.bit_time/2;
check_value(rx , not config.idle_state, FAILURE, v_proc_call.all & " Start bit was not stable during receiving. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait for data bit
wait for config.bit_time;
-- sample the data bits
for i in 0 to config.num_data_bits-1 loop
v_data_value(i) := rx;
-- wait for middle of the next bit
wait for config.bit_time;
end loop;
-- check parity, if enabled
if config.parity = PARITY_ODD then
if rx /= odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
elsif config.parity = PARITY_EVEN then
if rx /= not odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
end if;
-- check the stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect stop bit received. " & add_msg_delimiter(msg),scope);
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for config.bit_time/2 + config.bit_time/4; -- middle of the last half. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second half stop bit received. " & add_msg_delimiter(msg),scope);
end if;
elsif config.num_stop_bits = STOP_BITS_TWO then
wait for config.bit_time; -- middle of the last bit. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second stop bit received. " & add_msg_delimiter(msg),scope);
end if;
end if;
-- return the received data
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. uart_expect)
end if;
end if;
end procedure;
----------------------------------------------------------------------------------------
-- uart_expect
----------------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1; -- 0 = any occurrence before timeout
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant start_time : time := now;
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_num_of_occurrences : natural := 0;
variable v_check_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_timeout_ok : boolean;
variable v_config : t_uart_bfm_config := config;
variable v_received_data_fifo : uart_expect_received_data_array(0 to v_config.num_bytes_to_log_before_expected_data-1) := (others => (others =>'0'));
variable v_received_data_fifo_write_idx : natural := 0;
variable v_received_output_line : line;
variable v_internal_timeout : time;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- if timeout = -1 function was called without parameter
if timeout = -1 ns then
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
assert (v_internal_timeout >= 0 ns) report "configured negative timeout(not allowed). " & add_msg_delimiter(msg) severity failure;
-- Check for v_internal_timeout = 0 and max_receptions = 0. This combination can result in an infinite loop.
if v_internal_timeout = 0 ns and max_receptions = 0 then
alert(ERROR, proc_name & " called with timeout=0 and max_receptions = 0. This combination can result in an infinite loop. " & add_msg_delimiter(msg),scope);
end if;
if v_internal_timeout = 0 ns then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences. " & msg, scope, msg_id_panel);
elsif max_receptions = 0 then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
else
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences and " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
end if;
-- Initial status of check variables
v_check_ok := false;
v_timeout_ok := true;
if max_receptions < 1 then
v_num_of_occurrences_ok := true;
else
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Setup of v_config with correct timeout
v_config.timeout := v_internal_timeout;
-- Check operation
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Receive and check data
uart_receive(v_data_value, msg, rx, terminate_loop, v_config, scope, msg_id_panel, proc_call);
for i in 0 to v_config.num_data_bits-1 loop
if (data_exp(i) = '-' or
v_data_value(i) = data_exp(i)) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
-- Place the received data in the received data buffer for debugging
-- If the FIFO is not full, fill it up
if v_received_data_fifo_write_idx < v_config.num_bytes_to_log_before_expected_data then
v_received_data_fifo(v_received_data_fifo_write_idx)(v_data_value'length-1 downto 0) := v_data_value;
v_received_data_fifo_write_idx := v_received_data_fifo_write_idx + 1;
else
-- If the FIFO is full, left shift all input and append new data
for i in 1 to v_config.num_bytes_to_log_before_expected_data-1 loop
v_received_data_fifo(i-1) := v_received_data_fifo(i);
end loop;
v_received_data_fifo(v_received_data_fifo_write_idx-1)(v_data_value'length-1 downto 0) := v_data_value;
end if;
-- Evaluate number of occurrences, if limited by user
if max_receptions > 0 then
v_num_of_occurrences := v_num_of_occurrences + 1;
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Evaluate timeout if specified by user
if v_internal_timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := now < start_time + v_internal_timeout;
end if;
end loop;
-- Concatenate the string FIFO into a single string with given separators
for i in 0 to v_received_data_fifo_write_idx-1 loop
write(v_received_output_line, to_string(v_received_data_fifo(i), HEX, SKIP_LEADING_0, INCL_RADIX));
if i /= v_received_data_fifo_write_idx-1 then
write(v_received_output_line, C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR);
end if;
end loop;
if max_receptions > 1 then
-- Print the received string of bytes
log(v_config.id_for_bfm_poll_summary, "Last "& to_string(v_received_data_fifo_write_idx) & " received data bytes while waiting for expected data: " & v_received_output_line.all, scope, msg_id_panel);
end if;
if v_check_ok then
log(v_config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time),ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(config.timeout_severity, proc_call & "=> Failed due to timeout. Did not get expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(v_internal_timeout,ns) & ". " & add_msg_delimiter(msg), scope);
elsif not v_num_of_occurrences_ok then
if max_receptions = 1 then
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences, received value " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope);
else
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
else
alert(warning, proc_call & "=> Failed. Terminate loop received. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
end package body uart_bfm_pkg;
| mit | ca93efa48d8ad900065a898c663b9b17 | 0.569777 | 3.931529 | false | true | false | false |
ryos36/polyphony-tutorial | Xorshift/xorshift8.vhdl | 1 | 1,324 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xorshift8 is
port(
clk : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(7 downto 0)
);
end xorshift8;
architecture RTL of xorshift8 is
signal y: std_logic_vector(7 downto 0) := X"a2";
signal state: std_logic_vector(1 downto 0) := "00";
begin
data <= y(7 downto 0);
process(clk)
begin
if clk'event and clk = '1' then
case state is
when "00" =>
d_en_n <= '1';
if kick_n = '0' then
y <= y xor
(y((7 - 3) downto 0) & "000");
state <= "01";
end if;
when "01" =>
y <= y xor
("00000" & y(7 downto 5));
state <= "11";
when "11" =>
y <= y xor
(y((7 - 1) downto 0) & "0");
state <= "10";
when "10" =>
state <= "00";
d_en_n <= '0';
when others =>
null;
end case;
end if;
end process;
end RTL;
| mit | 5a0b0c9b8487925947fed18a21c6dd13 | 0.371601 | 3.987952 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_8_dir/exercise5_8.vhd | 1 | 1,282 | --!
--! @file: exercise5_8.vhd
--! @brief: binary sorter with generate
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity binary_sorter is
generic (N: integer := 5;);
port (
input: in std_logic_vector(N-1 downto 0);
output: out std_logic_vector(N-1 downto 0));
end entity binary_sorter;
--------------------------------------
architecture circuit of binary_sorter is
type oneDoneD is array (0 to N-1) of integer range 0 to N;
signal temp: oneDoneD;
begin
-- for the first bit of the count we initialize it depeding on the first bit of input
temp(0) <= 1 when input(0) = '1' else 0;
-- we do the same thing for all the rest of the input vector
gen: for i in 1 to N-1 generate
temp(i) <= temp(i-1) + 1 when input(i) = '1' else temp(i-1);
end generate gen;
-- for the output we put as many ones as we counted and after that just put zeros
gen1: for i in N-1 downto 0 generate
output(i) <= '1' when temp(N-1) > 0 else '0';
temp(N-1) <= temp(N-1) - 1 when temp(N-1) > 0 else 0;
end generate gen1;
end architecture circuit;
| gpl-3.0 | afbd85d05475baec32d0472c46cbe2b0 | 0.572543 | 3.521978 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_ADD_8b.vhd | 1 | 1,975 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_ADD_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_ADD_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis ADD RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(8 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( UNSIGNED('0' & INPUT_1( 7 downto 0)) + UNSIGNED('0' & INPUT_2( 7 downto 0)) );
rTemp2 := STD_LOGIC_VECTOR( UNSIGNED('0' & INPUT_1(15 downto 8)) + UNSIGNED('0' & INPUT_2(15 downto 8)) );
rTemp3 := STD_LOGIC_VECTOR( UNSIGNED('0' & INPUT_1(23 downto 16)) + UNSIGNED('0' & INPUT_2(23 downto 16)) );
rTemp4 := STD_LOGIC_VECTOR( UNSIGNED('0' & INPUT_1(31 downto 24)) + UNSIGNED('0' & INPUT_2(31 downto 24)) );
if( rTemp1(8) = '1' ) then rTemp1(7 downto 0) := "11111111"; end if;
if( rTemp2(8) = '1' ) then rTemp2(7 downto 0) := "11111111"; end if;
if( rTemp3(8) = '1' ) then rTemp3(7 downto 0) := "11111111"; end if;
if( rTemp4(8) = '1' ) then rTemp4(7 downto 0) := "11111111"; end if;
OUTPUT_1 <= (rTemp4(7 downto 0) & rTemp3(7 downto 0) & rTemp2(7 downto 0) & rTemp1(7 downto 0));
--OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 7810f801c8aea9298d5218251b922e3e | 0.543797 | 3.180354 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_dgen.vhd | 1 | 5,178 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Instruction_Memory_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF Instruction_Memory_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.Instruction_Memory_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| mit | 244e6a104af634672a19da211d3acb6c | 0.582078 | 4.086819 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_scoreboard/tb/sb_uart_sbi_demo_tb.vhd | 1 | 7,654 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_uart;
use bitvis_uart.uart_pif_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.slv_sb_pkg.all;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
-- Test harness entity
entity sb_uart_sbi_demo_tb is
end entity sb_uart_sbi_demo_tb;
-- Test harness architecture
architecture func of sb_uart_sbi_demo_tb is
constant C_SCOPE : string := "TB";
constant C_ADDR_WIDTH : integer := 3;
constant C_DATA_WIDTH : integer := 8;
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal clk_ena : boolean := false;
signal arst : std_logic := '0';
-- SBI signals
signal sbi_if : t_sbi_if(addr(C_ADDR_WIDTH-1 downto 0),
wdata(C_DATA_WIDTH-1 downto 0),
rdata(C_DATA_WIDTH-1 downto 0)) := init_sbi_if_signals(addr_width => C_ADDR_WIDTH,
data_width => C_DATA_WIDTH);
signal terminate_loop : std_logic := '0';
-- UART signals
signal uart_rx : std_logic := '1';
signal uart_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
-- One SB for each side of the DUT
shared variable v_uart_sb : t_generic_sb;
shared variable v_sbi_sb : t_generic_sb;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
wdata => sbi_if.wdata,
rdata => sbi_if.rdata,
-- UART signals
rx_a => uart_tx,
tx => uart_rx
);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
p_clk: clock_generator(clk, clk_ena, C_CLK_PERIOD, "tb clock");
-- Static '1' ready signal for the SBI VVC
sbi_if.ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Sequencer
-----------------------------------------------------------------------------
p_sequencer : process
variable v_data : std_logic_vector(7 downto 0);
variable v_uart_config : t_uart_bfm_config;
begin
set_log_file_name("sb_uart_sbi_demo_log.txt");
set_alert_file_name("sb_uart_sbi_demo_alert.txt");
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ID_POS_ACK);
--disable_log_msg(ID_SEQUENCER_SUB);
log(ID_LOG_HDR_XL, "SCOREBOARD UART-SBI DEMO ", C_SCOPE);
------------------------------------------------------------
clk_ena <= true;
wait for 1 ns;
await_value(arst, '0', 0 ns, 6*C_CLK_PERIOD, TB_ERROR, "await deassertion of arst", C_SCOPE);
wait for C_CLK_PERIOD;
------------------------------------------------------------
-- Config
------------------------------------------------------------
-- Set scope of SBs
v_uart_sb.set_scope("SB UART");
v_sbi_sb.set_scope( "SB SBI");
log(ID_LOG_HDR, "Set configuration", C_SCOPE);
v_uart_sb.config(C_SB_CONFIG_DEFAULT, "Set config for SB UART");
v_sbi_sb.config( C_SB_CONFIG_DEFAULT, "Set config for SB SBI");
log(ID_LOG_HDR, "Enable SBs", C_SCOPE);
v_uart_sb.enable(VOID);
v_sbi_sb.enable(VOID);
-- Enable log msg for data
v_uart_sb.enable_log_msg(ID_DATA);
v_sbi_sb.enable_log_msg( ID_DATA);
v_uart_config := C_UART_BFM_CONFIG_DEFAULT;
v_uart_config.bit_time := C_CLK_PERIOD*16;
------------------------------------------------------------
-- UART --> SBI
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data UART --> SBI", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_sbi_sb.add_expected(v_data);
uart_transmit(v_data, "data to DUT", uart_tx, v_uart_config);
end loop;
for j in 1 to 4 loop
sbi_poll_until(to_unsigned(C_ADDR_RX_DATA_VALID, 3), x"01", 0, 100 ns, "wait on data valid", clk, sbi_if, terminate_loop);
sbi_read(to_unsigned(C_ADDR_RX_DATA, 3), v_data, "read data from DUT", clk, sbi_if);
v_sbi_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_sbi_sb.report_counters(VOID);
------------------------------------------------------------
-- SBI --> UART
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data SBI --> UART", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_uart_sb.add_expected(v_data);
sbi_poll_until(to_unsigned(C_ADDR_TX_READY, 3), x"01", 0, 100 ns, "wait on TX ready", clk, sbi_if, terminate_loop);
sbi_write(to_unsigned(C_ADDR_TX_DATA, 3), v_data, "write data to DUT", clk, sbi_if);
uart_receive(v_data, "data from DUT", uart_rx, terminate_loop, v_uart_config);
v_uart_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_uart_sb.report_counters(VOID);
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
std.env.stop;
wait;
end process;
end architecture func;
| mit | 62e15bc52beba87d52d663be99fddd47 | 0.490854 | 4.06479 | false | true | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_scoreboard/src/generic_sb_pkg.vhd | 1 | 101,838 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.generic_sb_support_pkg.all;
package generic_sb_pkg is
generic (type t_element;
function element_match(received_element : t_element;
expected_element : t_element) return boolean;
function to_string_element(element : t_element) return string;
constant sb_config_default : t_sb_config := C_SB_CONFIG_DEFAULT;
constant GC_QUEUE_COUNT_MAX : natural := 1000;
constant GC_QUEUE_COUNT_THRESHOLD : natural := 950);
type t_generic_sb is protected
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := "");
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := "");
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure enable(
constant msg : in string);
procedure enable(
constant void : in t_void);
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure disable(
constant msg : in string);
procedure disable(
constant void : in t_void);
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure add_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := "");
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure check_received(
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant msg : in string := "");
procedure check_received(
constant received_element : in t_element;
constant msg : in string := "");
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure flush(
constant msg : in string);
procedure flush(
constant void : in t_void);
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure reset(
constant msg : in string);
procedure reset(
constant void : in t_void);
impure function is_empty(
constant instance : in integer) return boolean;
impure function is_empty(
constant void : in t_void) return boolean;
impure function get_entered_count(
constant instance : in integer) return integer;
impure function get_entered_count(
constant void : in t_void) return integer;
impure function get_pending_count(
constant instance : in integer) return integer;
impure function get_pending_count(
constant void : in t_void) return integer;
impure function get_match_count(
constant instance : in integer) return integer;
impure function get_match_count(
constant void : in t_void) return integer;
impure function get_mismatch_count(
constant instance : in integer) return integer;
impure function get_mismatch_count(
constant void : in t_void) return integer;
impure function get_drop_count(
constant instance : in integer) return integer;
impure function get_drop_count(
constant void : in t_void) return integer;
impure function get_initial_garbage_count(
constant instance : in integer) return integer;
impure function get_initial_garbage_count(
constant void : in t_void) return integer;
impure function get_delete_count(
constant instance : in integer) return integer;
impure function get_delete_count(
constant void : in t_void) return integer;
impure function get_overdue_check_count(
constant instance : in integer) return integer;
impure function get_overdue_check_count(
constant void : in t_void) return integer;
procedure set_scope(
constant scope : in string);
impure function get_scope(
constant void : in t_void) return string;
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure enable_log_msg(
constant msg_id : in t_msg_id);
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure disable_log_msg(
constant msg_id : in t_msg_id);
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := "");
procedure report_counters(
constant void : in t_void);
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "");
procedure delete_expected(
constant expected_element : in t_element;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "");
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_element) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element) return integer;
impure function find_expected_position(
constant expected_element : in t_element) return integer;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_element;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_element;
impure function peek_expected(
constant instance : integer) return t_element;
impure function peek_expected(
constant void : t_void) return t_element;
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant instance : integer) return string;
impure function peek_source(
constant void : t_void) return string;
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant instance : integer) return string;
impure function peek_tag(
constant void : t_void) return string;
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return t_element;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return t_element;
impure function fetch_expected(
constant instance : integer;
constant msg : string := "") return t_element;
impure function fetch_expected(
constant msg : string) return t_element;
impure function fetch_expected(
constant void : t_void) return t_element;
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_source(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_source(
constant msg : string) return string;
impure function fetch_source(
constant void : t_void) return string;
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_tag(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_tag(
constant msg : string) return string;
impure function fetch_tag(
constant void : t_void) return string;
impure function exists(
constant instance : integer;
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
end protected t_generic_sb;
end package generic_sb_pkg;
package body generic_sb_pkg is
-- SB type declaration
type t_sb_entry is record
expected_element : t_element;
source : string(1 to C_SB_SOURCE_WIDTH);
tag : string(1 to C_SB_TAG_WIDTH);
entry_time : time;
end record;
-- Declaration of sb_queue_pkg used to store all entries
package sb_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (
t_generic_element => t_sb_entry,
scope => "SB_queue",
GC_QUEUE_COUNT_MAX => 1000,
GC_QUEUE_COUNT_THRESHOLD => 750);
use sb_queue_pkg.all;
type t_generic_sb is protected body
----------------------------------------------------------------------------------------------------
-- Variables
----------------------------------------------------------------------------------------------------
variable vr_scope : string(1 to C_LOG_SCOPE_WIDTH) := (1 to 4 => "?_SB", others => NUL);
variable vr_config : t_sb_config_array(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => sb_config_default);
variable vr_instance_enabled : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
variable vr_sb_queue : sb_queue_pkg.t_generic_queue;
type t_msg_id_panel_array is array(0 to C_MAX_QUEUE_INSTANCE_NUM) of t_msg_id_panel;
variable vr_msg_id_panel_array : t_msg_id_panel_array := (others => C_SB_MSG_ID_PANEL_DEFAULT);
-- Counters
variable vr_entered_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_match_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_mismatch_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_drop_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_initial_garbage_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_delete_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_overdue_check_cnt : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
--==================================================================================================
-- NON PUBLIC METHODS
--==================================================================================================
procedure check_instance_in_range(
constant instance : in integer
) is
begin
check_value_in_range(instance, 0, C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Instance must be within range 0 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
end procedure check_instance_in_range;
procedure check_instance_enabled(
constant instance : in integer
) is
begin
check_value(vr_instance_enabled(instance), TB_ERROR, "The instance is not enabled", vr_scope, ID_NEVER);
end procedure check_instance_enabled;
procedure check_queue_empty(
constant instance : in natural
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "The queue is empty", vr_scope, ID_NEVER);
end procedure check_queue_empty;
procedure check_config_validity(
constant config : in t_sb_config
) is
begin
check_value(config.allow_out_of_order and config.allow_lossy, false, TB_ERROR,
"allow_out_of_order and allow_lossy cannot both be enabled. Se documentation for how to handle both modes.", vr_scope, ID_NEVER);
check_value(config.overdue_check_time_limit >= 0 ns, TB_ERROR,
"overdue_check_time_limit cannot be less than 0 ns.", vr_scope, ID_NEVER);
end procedure;
impure function match_received_vs_entry (
constant received_element : in t_element;
constant sb_entry : in t_sb_entry;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return element_match(received_element, sb_entry.expected_element);
end function match_received_vs_entry;
impure function match_expected_vs_entry (
constant expected_element : in t_element;
constant sb_entry : in t_sb_entry;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return expected_element = sb_entry.expected_element;
end function match_expected_vs_entry;
procedure log(
instance : natural;
msg_id : t_msg_id;
msg : string;
scope : string
) is
begin
if vr_msg_id_panel_array(instance)(msg_id) = ENABLED then
log(msg_id, msg, scope, C_MSG_ID_PANEL_DEFAULT);
end if;
end procedure;
--==================================================================================================
-- PUBLIC METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- config
--
-- Sets config for each instance, by array or instance parameter
--
----------------------------------------------------------------------------------------------------
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := ""
) is
begin
-- Check if range is within limits
check_value(sb_config_array'low >= 0 and sb_config_array'high <= C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Configuration array must be within range 0 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
-- Apply config to the defined range
for i in sb_config_array'low to sb_config_array'high loop
check_config_validity(sb_config_array(i));
log(i, ID_CTRL, "config: config applied to instance " & to_string(i) & "." & add_msg_delimiter(msg), vr_scope);
vr_config(i) := sb_config_array(i);
end loop;
end procedure config;
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "config";
begin
-- Sanity checks
check_instance_in_range(instance);
check_config_validity(sb_config);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
log(instance, ID_CTRL, proc_name & ": config applied to instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
vr_config(instance) := sb_config;
end procedure config;
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := ""
) is
begin
config(1, sb_config, msg, "config: config applied to SB.");
end procedure config;
----------------------------------------------------------------------------------------------------
--
-- enable
--
-- Enable one instance or all instances. Counters is set froom -1 to 0 When enabled for the
-- first time.
--
----------------------------------------------------------------------------------------------------
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "enable";
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": all instances enabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, proc_name & ": instance " & to_string(instance) & " enabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => true);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_entered_cnt(i) = -1 then
vr_entered_cnt(i) := 0;
vr_match_cnt(i) := 0;
vr_mismatch_cnt(i) := 0;
vr_drop_cnt(i) := 0;
vr_initial_garbage_cnt(i) := 0;
vr_delete_cnt(i) := 0;
vr_overdue_check_cnt(i) := 0;
end if;
end loop;
else
vr_instance_enabled(instance) := true;
if vr_entered_cnt(instance) = -1 then
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end if;
end if;
vr_sb_queue.set_scope(instance, "SB queue");
end procedure enable;
procedure enable(
constant msg : in string
) is
begin
enable(1, msg, "enable: SB enabled.");
end procedure enable;
procedure enable(
constant void : in t_void
) is
begin
enable(1, "", "enable: SB enabled.");
end procedure enable;
----------------------------------------------------------------------------------------------------
--
-- disable
--
-- Disable one instance or all instances.
--
----------------------------------------------------------------------------------------------------
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => false);
else
vr_instance_enabled(instance) := false;
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, "disable: all instances disabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, "disable: instance " & to_string(instance) & " disabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end procedure disable;
procedure disable(
constant msg : in string
) is
begin
disable(1, msg, "disable: SB disabled.");
end procedure disable;
procedure disable(
constant void : in t_void
) is
begin
disable(1, "", "disable: SB disabled.");
end procedure disable;
----------------------------------------------------------------------------------------------------
--
-- add_expected
--
-- Adds expected element at the back of queue. Optional tag and source.
--
----------------------------------------------------------------------------------------------------
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "add_expected";
variable v_sb_entry : t_sb_entry;
begin
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- add entry
vr_sb_queue.add(i, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
if tag_usage = NO_TAG then
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end loop;
else
-- Sanity checks
check_instance_in_range(instance);
check_instance_enabled(instance);
-- add entry
vr_sb_queue.add(instance, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if tag_usage = NO_TAG then
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & to_string_element(expected_element) & ". ");
else
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & to_string_element(expected_element) & ", tag: " & to_string(tag) & ". ");
end if;
end procedure add_expected;
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(instance, expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
----------------------------------------------------------------------------------------------------
--
-- check_received
--
-- Checks received against expected. Updates counters acording to match/mismatch and configuration.
--
----------------------------------------------------------------------------------------------------
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "check_received";
procedure check_pending_exists(
constant instance : in integer
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "instance " & to_string(instance) & ": no pending entries to check.", vr_scope, ID_NEVER);
end procedure check_pending_exists;
procedure check_received_instance(
constant instance : in integer
) is
variable v_matched : boolean := false;
variable v_entry : t_sb_entry;
variable v_dropped_num : natural := 0;
begin
check_pending_exists(instance);
-- If OOB
if vr_config(instance).allow_out_of_order then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- Delete entry
vr_sb_queue.delete(instance, POSITION, i, SINGLE);
exit;
end if;
end loop;
-- If LOSSY
elsif vr_config(instance).allow_lossy then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- Delete matching entry and preceding entries
for j in i downto 1 loop
vr_sb_queue.delete(instance, POSITION, j, SINGLE);
end loop;
v_dropped_num := i - 1;
exit;
end if;
end loop;
-- Not OOB or LOSSY
else
v_entry := vr_sb_queue.peek(instance);
if match_received_vs_entry(received_element, v_entry, tag_usage, tag) then
v_matched := true;
-- delete entry
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
end if;
end if;
-- Update counters
vr_drop_cnt(instance) := vr_drop_cnt(instance) + v_dropped_num;
if v_matched then
vr_match_cnt(instance) := vr_match_cnt(instance) + 1;
elsif vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage then
vr_initial_garbage_cnt(instance) := vr_initial_garbage_cnt(instance) + 1;
else
vr_mismatch_cnt(instance) := vr_mismatch_cnt(instance) + 1;
end if;
-- Check if overdue time
if v_matched and (vr_config(instance).overdue_check_time_limit /= 0 ns) and (now-v_entry.entry_time > vr_config(instance).overdue_check_time_limit) then
if ext_proc_call = "" then
alert(vr_config(instance).overdue_check_alert_level, proc_name & "() instance " & to_string(instance) &" => TIME LIMIT OVERDUE: time limit is "
& to_string(vr_config(instance).overdue_check_time_limit) & ", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
else
alert(vr_config(instance).overdue_check_alert_level, ext_proc_call & " => TIME LIMIT OVERDUE: time limit is " & to_string(vr_config(instance).overdue_check_time_limit) &
", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
end if;
-- Update counter
vr_overdue_check_cnt(instance) := vr_overdue_check_cnt(instance) + 1;
end if;
-- Logging
if v_matched then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & to_string_element(v_entry.expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & to_string_element(v_entry.expected_element) &
". tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
-- Called from other SB method
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " => MATCH, for received: " & to_string_element(received_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " => MATCH, for received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
-- Initial garbage
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) &
"; received: " & to_string_element(received_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) & ", tag: '" & to_string(v_entry.tag) &
"'; received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) &
"; received: " & to_string_element(received_element) & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & to_string_element(v_entry.expected_element) & ", tag: " & to_string(v_entry.tag) &
"; received: " & to_string_element(received_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end if;
end procedure check_received_instance;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
check_received_instance(i);
end if;
end loop;
else
check_instance_enabled(instance);
check_received_instance(instance);
end if;
end procedure check_received;
procedure check_received(
constant received_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
check_received(1, received_element, tag_usage, tag, msg, "check_received()");
end procedure check_received;
procedure check_received(
constant instance : in integer;
constant received_element : in t_element;
constant msg : in string := ""
) is
begin
check_received(instance, received_element, NO_TAG, "", msg);
end procedure check_received;
procedure check_received(
constant received_element : in t_element;
constant msg : in string := ""
) is
begin
check_received(received_element, NO_TAG, "", msg);
end procedure check_received;
----------------------------------------------------------------------------------------------------
--
-- flush
--
-- Deletes all entries in queue and updates delete counter.
--
----------------------------------------------------------------------------------------------------
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "flush";
begin
if instance = ALL_INSTANCES then
log(ID_DATA, proc_name & ": flushing all instances." & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_DATA, proc_name & ": flushing all enabled instances." & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": flushing instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
-- update counters
vr_delete_cnt(instance) := vr_delete_cnt(instance) + vr_sb_queue.get_count(instance);
-- flush queue
vr_sb_queue.flush(instance);
end if;
end procedure flush;
procedure flush(
constant msg : in string
) is
begin
flush(1, msg, "flush: flushing SB.");
end procedure flush;
procedure flush(
constant void : in t_void
) is
begin
flush("");
end procedure flush;
----------------------------------------------------------------------------------------------------
--
-- reset
--
-- Resets all counters and flushes queue. Also resets entry number count.
--
----------------------------------------------------------------------------------------------------
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "reset";
procedure reset_instance(
constant instance : natural
) is
begin
-- reset instance 0 only if it is used
if not(vr_sb_queue.is_empty(0)) or (instance > 0) then
vr_sb_queue.reset(instance);
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end if;
end procedure reset_instance;
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all instances. " & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
reset_instance(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all enabled instances. " & add_msg_delimiter(msg), vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
reset_instance(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": reseting instance " & to_string(instance) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
reset_instance(instance);
end if;
end procedure reset;
procedure reset(
constant msg : in string
) is
begin
reset(1, msg, "reset: reseting SB.");
end procedure reset;
procedure reset(
constant void : in t_void
) is
begin
reset("");
end procedure reset;
----------------------------------------------------------------------------------------------------
--
-- is_empty
--
-- Returns true if scoreboard instance is empty, false if not.
--
----------------------------------------------------------------------------------------------------
impure function is_empty(
constant instance : in integer
) return boolean is
begin
return vr_sb_queue.is_empty(instance);
end function is_empty;
impure function is_empty(
constant void : in t_void
) return boolean is
begin
return is_empty(1);
end function is_empty;
----------------------------------------------------------------------------------------------------
--
-- get_entered_count
--
-- Returns total number of entries made to scoreboard instance.
-- Added + inserted.
--
----------------------------------------------------------------------------------------------------
impure function get_entered_count(
constant instance : in integer
) return integer is
begin
return vr_entered_cnt(instance);
end function get_entered_count;
impure function get_entered_count(
constant void : in t_void
) return integer is
begin
return get_entered_count(1);
end function get_entered_count;
----------------------------------------------------------------------------------------------------
--
-- get_pending_count
--
-- Returns number of entries en scoreboard instance at the moment.
-- Added + inserted - checked - deleted.
--
----------------------------------------------------------------------------------------------------
impure function get_pending_count(
constant instance : in integer
) return integer is
begin
if vr_entered_cnt(instance) = -1 then
return -1;
else
return vr_sb_queue.get_count(instance);
end if;
end function get_pending_count;
impure function get_pending_count(
constant void : in t_void
) return integer is
begin
return get_pending_count(1);
end function get_pending_count;
----------------------------------------------------------------------------------------------------
--
-- get_match_count
--
-- Returns number of entries checked and matched against a received.
--
----------------------------------------------------------------------------------------------------
impure function get_match_count(
constant instance : in integer
) return integer is
begin
return vr_match_cnt(instance);
end function get_match_count;
impure function get_match_count(
constant void : in t_void
) return integer is
begin
return get_match_count(1);
end function get_match_count;
----------------------------------------------------------------------------------------------------
--
-- get_mismatch_count
--
-- Returns number of entries checked and not matched against a received.
--
----------------------------------------------------------------------------------------------------
impure function get_mismatch_count(
constant instance : in integer
) return integer is
begin
return vr_mismatch_cnt(instance);
end function get_mismatch_count;
impure function get_mismatch_count(
constant void : in t_void
) return integer is
begin
return get_mismatch_count(1);
end function get_mismatch_count;
----------------------------------------------------------------------------------------------------
--
-- get_drop_count
--
-- Returns number of entries dropped, total number of preceding entries before match.
-- Only relevant during lossy mode.
--
----------------------------------------------------------------------------------------------------
impure function get_drop_count(
constant instance : in integer
) return integer is
begin
return vr_drop_cnt(instance);
end function get_drop_count;
impure function get_drop_count(
constant void : in t_void
) return integer is
begin
return get_drop_count(1);
end function get_drop_count;
----------------------------------------------------------------------------------------------------
--
-- get_initial_garbage_count
--
-- Returns number of received checked before first match.
-- Only relevant when allow_initial_garbage is enabled.
--
----------------------------------------------------------------------------------------------------
impure function get_initial_garbage_count(
constant instance : in integer
) return integer is
begin
return vr_initial_garbage_cnt(instance);
end function get_initial_garbage_count;
impure function get_initial_garbage_count(
constant void : in t_void
) return integer is
begin
return get_initial_garbage_count(1);
end function get_initial_garbage_count;
----------------------------------------------------------------------------------------------------
--
-- get_delete_count
--
-- Returns number of deleted entries.
-- Delete + fetch + flush.
--
----------------------------------------------------------------------------------------------------
impure function get_delete_count(
constant instance : in integer
) return integer is
begin
return vr_delete_cnt(instance);
end function get_delete_count;
impure function get_delete_count(
constant void : in t_void
) return integer is
begin
return get_delete_count(1);
end function get_delete_count;
----------------------------------------------------------------------------------------------------
--
-- get_overdue_check_count
--
-- Returns number of received checked when time limit is overdue.
-- Only relevant when overdue_check_time_limit is set.
--
----------------------------------------------------------------------------------------------------
impure function get_overdue_check_count(
constant instance : in integer
) return integer is
begin
return vr_overdue_check_cnt(instance);
end function get_overdue_check_count;
impure function get_overdue_check_count(
constant void : in t_void
) return integer is
begin
return get_overdue_check_count(1);
end function get_overdue_check_count;
----------------------------------------------------------------------------------------------------
--
-- set_scope / get_scope
--
-- Set/Get the scope of the scoreboard.
--
----------------------------------------------------------------------------------------------------
procedure set_scope(
constant scope : in string
) is
begin
vr_scope := pad_string(scope, NUL, C_LOG_SCOPE_WIDTH);
end procedure set_scope;
impure function get_scope(
constant void : in t_void
) return string is
begin
return vr_scope;
end function get_scope;
----------------------------------------------------------------------------------------------------
--
-- enable_log_msg
--
-- Enables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "enable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for all instances", vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := ENABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := ENABLED;
end if;
end procedure enable_log_msg;
procedure enable_log_msg(
constant msg_id : in t_msg_id
) is
begin
enable_log_msg(1, msg_id, "enable_log_msg: "& ": message id " & to_string(msg_id) & " enabled");
end procedure enable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- disable_log_msg
--
-- Disables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "disable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for all instances", vr_scope);
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := DISABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := DISABLED;
end if;
end procedure disable_log_msg;
procedure disable_log_msg(
constant msg_id : in t_msg_id
) is
begin
disable_log_msg(1, msg_id, "disable_log_msg: "& ": message id " & to_string(msg_id) & " disabled");
end procedure disable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- report_conters
--
-- Prints a report of all counters to transcript for either specified instance, all enabled
-- instances or all instances.
--
----------------------------------------------------------------------------------------------------
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := ""
) is
variable v_line : line;
variable v_line_copy : line;
variable v_status_failed : boolean := true;
variable v_mismatch : boolean := false;
constant C_HEADER : string := "*** SCOREBOARD COUNTERS SUMMARY: " & to_string(vr_scope) & " ***";
constant prefix : string := C_LOG_PREFIX & " ";
constant log_counter_width : positive := 8; -- shouldn't be smaller than 8 due to the counters names
variable v_log_extra_space : integer := 0;
-- add simulation time stamp to scoreboard report header
impure function timestamp_header(value : time; txt : string) return string is
variable v_line : line;
variable v_delimiter_pos : natural;
variable v_timestamp_width : natural;
variable v_result : string(1 to 50);
variable v_return : string(1 to txt'length) := txt;
begin
-- get a time stamp
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE);
v_timestamp_width := v_line'length;
v_result(1 to v_timestamp_width) := v_line.all;
deallocate(v_line);
v_delimiter_pos := pos_of_leftmost('.', v_result(1 to v_timestamp_width), 0);
-- truncate decimals and add units
if C_LOG_TIME_BASE = ns then
v_result(v_delimiter_pos+2 to v_delimiter_pos+5) := " ns ";
else
v_result(v_delimiter_pos+2 to v_delimiter_pos+5) := " ps ";
end if;
v_timestamp_width := v_delimiter_pos + 5;
-- add time string to return string
v_return := v_result(1 to v_timestamp_width) & txt(1 to txt'length-v_timestamp_width);
return v_return(1 to txt'length);
end function timestamp_header;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - prefix'length - 20 - log_counter_width*6 - 15 - 13)/8;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small, the report will not be properly aligned.", vr_scope);
v_log_extra_space := 1;
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
timestamp_header(now, justify(C_HEADER, LEFT, C_LOG_LINE_WIDTH - prefix'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
write(v_line,
justify(
fill_string(' ', 16) &
justify("ENTERED" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("PENDING" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MATCH" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MISMATCH" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("DROP" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("INITIAL_GARBAGE", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("DELETE" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("OVERDUE_CHECK" , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
if instance = ALL_INSTANCES or instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if instance = ALL_INSTANCES or (instance = ALL_ENABLED_INSTANCES and vr_instance_enabled(i)) then
write(v_line,
justify(
"instance: " &
justify(to_string(i), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_pending_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_match_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_mismatch_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_drop_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_initial_garbage_count(i)), center, 15, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_delete_count(i)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_overdue_check_count(i)) , center, 13, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
else
write(v_line,
justify(
"instance: " &
justify(to_string(instance), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_pending_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_match_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_mismatch_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_drop_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_initial_garbage_count(instance)), center, 15, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_delete_count(instance)) , center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_overdue_check_count(instance)) , center, 13, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to transcript
write (v_line_copy, v_line.all); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end procedure report_counters;
procedure report_counters(
constant void : in t_void
) is
begin
report_counters(1, "no instance label");
end procedure report_counters;
--==================================================================================================
-- ADVANCED METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- insert_expected
--
-- Inserts expected element to the queue based on position or entry number
--
----------------------------------------------------------------------------------------------------
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "insert_expected";
variable v_sb_entry : t_sb_entry;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 0 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- Check that instance is enabled
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(i, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
end if;
end loop;
else
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(instance, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
end if;
-- Logging
if ext_proc_call = "" then
if instance = ALL_ENABLED_INSTANCES then
if identifier_option = POSITION then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if identifier_option = POSITION then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " Expected: " & to_string_element(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " Expected: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure insert_expected;
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if identifier_option = POSITION then
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with position " & to_string(identifier) & ".");
else
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with entry number " & to_string(identifier) & ".");
end if;
end procedure insert_expected;
----------------------------------------------------------------------------------------------------
--
-- find_expected_entry_num
--
-- Returns entry number of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if match_expected_vs_entry(expected_element, v_sb_entry, tag_usage, tag) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, expected_element, tag_usage, tag);
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_element
) return integer is
begin
return find_expected_entry_num(instance, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_element
) return integer is
begin
return find_expected_entry_num(1, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, tag_usage, tag);
end function find_expected_entry_num;
----------------------------------------------------------------------------------------------------
--
-- find_expected_position
--
-- Returns position of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if match_expected_vs_entry(expected_element, v_sb_entry, tag_usage, tag) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, expected_element, tag_usage, tag);
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_element
) return integer is
begin
return find_expected_position(instance, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_element
) return integer is
begin
return find_expected_position(1, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, tag_usage, tag);
end function find_expected_position;
----------------------------------------------------------------------------------------------------
--
-- delete_expected
--
-- Deletes expected element in queue based on specified element, position or entry number
--
----------------------------------------------------------------------------------------------------
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, expected_element, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, tag_usage, tag, msg, "delete_expected: value: " & to_string_element(expected_element) & ", tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_element;
constant msg : in string := ""
) is
begin
delete_expected(instance, expected_element, NO_TAG, "", msg, "delete_expected: instance " & to_string(instance) & ", value: " & to_string_element(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_element;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, NO_TAG, "", msg, "delete_expected: instance value: " & to_string_element(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, tag_usage, tag, msg, "delete_expected: tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier_min, identifier_max);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := ""
) is
begin
delete_expected(1, identifier_option, identifier_min, identifier_max, msg, "delete_expected: entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier, range_option);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
if range_option = SINGLE then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entry with identifier " & to_string(identifier_option) &
" " & to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier) & " " & to_string(range_option) & " deleted. " & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := ""
) is
begin
if range_option = SINGLE then
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entry with identifier '" & to_string(identifier_option) &
" " & to_string(identifier) & " deleted. ");
else
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entries with identifier '" & to_string(identifier_option) &
" range " & to_string(identifier) & " to " & to_string(range_option) & " deleted. ");
end if;
end procedure delete_expected;
----------------------------------------------------------------------------------------------------
-- non public local_entry
-- Used by all peek functions
----------------------------------------------------------------------------------------------------
impure function peek_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
begin
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
return vr_sb_queue.peek(instance, identifier_option, identifier);
end function peek_entry;
----------------------------------------------------------------------------------------------------
--
-- peek_expected
--
-- Returns expected element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_element is
begin
return peek_entry(instance, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_element is
begin
return peek_entry(1, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant instance : integer
) return t_element is
begin
return peek_entry(instance, POSITION, 1).expected_element;
end function peek_expected;
impure function peek_expected(
constant void : t_void
) return t_element is
begin
return peek_entry(1, POSITION, 1).expected_element;
end function peek_expected;
----------------------------------------------------------------------------------------------------
--
-- peek_source
--
-- Returns source element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).source);
end function peek_source;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_source(1, identifier_option, identifier);
end function peek_source;
impure function peek_source(
constant instance : integer
) return string is
begin
return peek_source(instance, POSITION, 1);
end function peek_source;
impure function peek_source(
constant void : t_void
) return string is
begin
return peek_source(1, POSITION, 1);
end function peek_source;
----------------------------------------------------------------------------------------------------
--
-- peek_tag
--
-- Returns tag from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).tag);
end function peek_tag;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_tag(1, identifier_option, identifier);
end function peek_tag;
impure function peek_tag(
constant instance : integer
) return string is
begin
return peek_tag(instance, POSITION, 1);
end function peek_tag;
impure function peek_tag(
constant void : t_void
) return string is
begin
return peek_tag(1, POSITION, 1);
end function peek_tag;
----------------------------------------------------------------------------------------------------
-- Non public fetch_entry
-- Used by all fetch functions
----------------------------------------------------------------------------------------------------
impure function fetch_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
v_sb_entry := vr_sb_queue.fetch(instance, identifier_option, identifier);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
return v_sb_entry;
end function fetch_entry;
----------------------------------------------------------------------------------------------------
--
-- fetch_expected
--
-- Returns expected element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return t_element is
constant proc_name : string := "fetch_expected";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching expected by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return fetch_entry(instance, identifier_option, identifier).expected_element;
end function fetch_expected;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return t_element is
begin
return fetch_expected(1, identifier_option, identifier, msg, "fetch_expected: fetching expected by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_expected;
impure function fetch_expected(
constant instance : integer;
constant msg : string := ""
) return t_element is
begin
return fetch_expected(instance, POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant msg : string
) return t_element is
begin
return fetch_expected(POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant void : t_void
) return t_element is
begin
return fetch_expected(POSITION, 1);
end function fetch_expected;
----------------------------------------------------------------------------------------------------
--
-- fetch_source
--
-- Returns source element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_source";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching source by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).source);
end function fetch_source;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_source(1, identifier_option, identifier, msg, "fetch_source: fetching source by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_source;
impure function fetch_source(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_source(instance, POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant msg : string
) return string is
begin
return fetch_source(POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant void : t_void
) return string is
begin
return fetch_source(POSITION, 1);
end function fetch_source;
----------------------------------------------------------------------------------------------------
--
-- fetch_tag
--
-- Returns tag from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_tag";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching tag by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).tag);
end function fetch_tag;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_tag(1, identifier_option, identifier, msg, "fetch_tag: fetching tag by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_tag;
impure function fetch_tag(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_tag(instance, POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant msg : string
) return string is
begin
return fetch_tag(POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant void : t_void
) return string is
begin
return fetch_tag(POSITION, 1);
end function fetch_tag;
----------------------------------------------------------------------------------------------------
--
-- exists
--
-- Returns true if entry exists, false if not.
--
----------------------------------------------------------------------------------------------------
impure function exists(
constant instance : integer;
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return (find_expected_position(instance, expected_element, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant expected_element : t_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return exists(1, expected_element, tag_usage, tag);
end function exists;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return (find_expected_position(instance, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return exists(1, tag_usage, tag);
end function exists;
end protected body;
end package body generic_sb_pkg;
| mit | 5c85ebdf11b8842a58603541af6d5de1 | 0.54898 | 4.379752 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_pkg.vhd | 1 | 6,073 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Video_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Video_Memory_TB_PKG;
PACKAGE BODY Video_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Video_Memory_TB_PKG;
| mit | 0ad96ec59672f47573b19909086ec006 | 0.577474 | 4.410312 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/example10_2_dir/example10_2.vhd | 1 | 1,155 | use std.textio.all;
--------------------------------------
entity read_from_file is
--generic declarations
end entity read_from_file;
--------------------------------------
architecture circuit of read_from_file is
file f: text open read_mode is "test_file.txt"; -- reado
signal clk: bit := '0';
signal t_out: time range 0 ns to 800 ns;
signal i_out: natural range 0 to 7;
begin
proc: process
variable l: line;
variable str1: string(1 to 2);
variable str2: string(1 to 3);
variable t: time range 0 ns to 800 ns;
variable i: natural range 0 to 7;
-- variable reached: natural range 0 to 1 := 0;
begin
wait for 50 ns;
clk <= '1';
if (not endfile(f)) then
readline(f, l);
read(l, str1);
read(l, t);
read(l, str2);
read(l, i);
t_out <= t;
i_out <= i;
-- else
-- reached := 1;
end if;
wait for 50 ns;
clk <= '0';
-- if (reached = 1) then
-- wait;
end if;
end process proc;
end architecture circuit;
| gpl-3.0 | cd257540f21c00a4f94015ff32468168 | 0.478788 | 3.902027 | false | false | false | false |
siam28/neppielight | dvid_in/dvid_gearbox.vhd | 2 | 2,399 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: Gearbox - Behavioral
-- Project Name: DVI-I Input
-- Description: Receives the 5-bits-per-cycle data from the serialisers at twice
-- the pixel clock, then 'downshifts' the data to 10-bit words.
--
-- The 'framing' signal allows to bit-slip to different word
-- framing, allowing the design to hunt for the sync codewords.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gearbox is
Port ( clk_fabric_x2 : in STD_LOGIC;
invert : in STD_LOGIC;
framing : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(4 downto 0);
data_out : out std_logic_vector(9 downto 0));
end gearbox;
architecture Behavioral of gearbox is
signal every_other : std_logic := '0';
signal joined : std_logic_vector(14 downto 0);
begin
process(clk_fabric_x2)
begin
if rising_edge(clk_fabric_x2) then
if every_other = '1' then
case framing is
when "0000" => data_out <= joined( 9 downto 0);
when "0001" => data_out <= joined(10 downto 1);
when "0010" => data_out <= joined(11 downto 2);
when "0011" => data_out <= joined(12 downto 3);
when "0100" => data_out <= joined(13 downto 4);
when others => NULL;
end case;
else
case framing is
when "0101" => data_out <= joined( 9 downto 0);
when "0110" => data_out <= joined(10 downto 1);
when "0111" => data_out <= joined(11 downto 2);
when "1000" => data_out <= joined(12 downto 3);
when "1001" => data_out <= joined(13 downto 4);
when others => NULL;
end case;
end if;
if invert = '1' then
joined <= data_in & joined(joined'high downto 5) ;
else
joined <= (data_in xor "11111") & joined(joined'high downto 5) ;
end if;
every_other <= not every_other;
end if;
end process;
end Behavioral;
| gpl-2.0 | 5a61c404271555ce222338f1b01ea9a8 | 0.506878 | 4.093857 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/RGB_2_Y.vhd | 1 | 1,883 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity RGB_2_Y is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end RGB_2_Y;
architecture rtl of RGB_2_YUV is
constant s_rgb_30 : UNSIGNED(11 downto 0) := "001001100100";
constant s_rgb_59 : UNSIGNED(11 downto 0) := "010010110010";
constant s_rgb_11 : UNSIGNED(11 downto 0) := "000011101001";
SIGNAL INPUT_R : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_G : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_B : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_Y : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL s_rgb_out_y : UNSIGNED(19 downto 0) := (others => '0');
SIGNAL rgb_in_r_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
begin
INPUT_R <= INPUT_1( 7 downto 0);
INPUT_G <= INPUT_1(15 downto 8);
INPUT_B <= INPUT_1(23 downto 16);
OUTPUT_1 <= "000000000000000000000000" & INPUT_Y;
process(INPUT_R, INPUT_G, INPUT_B)
begin
rgb_in_r_reg_Y <= s_rgb_30 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Y <= s_rgb_59 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Y <= s_rgb_11 * UNSIGNED(INPUT_B);
s_rgb_out_y <= rgb_in_r_reg_Y + (rgb_in_g_reg_Y + rgb_in_b_reg_Y);
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(19 downto 12));
end process;
end rtl;
| gpl-3.0 | 37f8d7b39bda2ac6757241d60c70782f | 0.590547 | 2.648383 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/asip_config.vhd | 2 | 6,807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package asip_config is
-- INSTRUCTION TYPE (00)
constant ENABLE_UNIMP : integer := 0 ; -- "000";
constant ENABLE_BICC : integer := 1 ; -- "010";
constant ENABLE_SETHI : integer := 1 ; -- "100";
constant ENABLE_FBFCC : integer := 0 ; -- "110";
constant ENABLE_CBCCC : integer := 0 ; -- "111";
-- INSTRUCTION TYPE (01)
constant ENABLE_CALL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (10)
constant ENABLE_IADD : integer := 1 ; -- "000000";
constant ENABLE_IAND : integer := 1 ; -- "000001";
constant ENABLE_IOR : integer := 1 ; -- "000010";
constant ENABLE_IXOR : integer := 1 ; -- "000011";
constant ENABLE_ISUB : integer := 1 ; -- "000100";
constant ENABLE_ANDN : integer := 1 ; -- "000101";
constant ENABLE_ORN : integer := 0 ; -- "000110";
constant ENABLE_IXNOR : integer := 0 ; -- "000111";
constant ENABLE_ADDX : integer := 1 ; -- "001000";
constant ENABLE_CUSTOM_1 : integer := 0 ; -- "001001";
constant ENABLE_UMUL : integer := 0 ; -- "001010";
constant ENABLE_SMUL : integer := 1 ; -- "001011";
constant ENABLE_SUBX : integer := 0 ; -- "001100";
constant ENABLE_CUSTOM_2 : integer := 0 ; -- "001101";
constant ENABLE_UDIV : integer := 0 ; -- "001110";
constant ENABLE_SDIV : integer := 1 ; -- "001111";
constant ENABLE_ADDCC : integer := 0 ; -- "010000";
constant ENABLE_ANDCC : integer := 1 ; -- "010001";
constant ENABLE_ORCC : integer := 1 ; -- "010010";
constant ENABLE_XORCC : integer := 0 ; -- "010011";
constant ENABLE_SUBCC : integer := 1 ; -- "010100";
constant ENABLE_ANDNCC : integer := 0 ; -- "010101";
constant ENABLE_ORNCC : integer := 0 ; -- "010110";
constant ENABLE_XNORCC : integer := 0 ; -- "010111";
constant ENABLE_ADDXCC : integer := 0 ; -- "011000";
constant ENABLE_CUSTOM_3 : integer := 0 ; -- "011001";
constant ENABLE_UMULCC : integer := 0 ; -- "011010";
constant ENABLE_SMULCC : integer := 0 ; -- "011011";
constant ENABLE_SUBXCC : integer := 0 ; -- "011100";
constant ENABLE_CUSTOM_4 : integer := 0 ; -- "011101";
constant ENABLE_UDIVCC : integer := 0 ; -- "011110";
constant ENABLE_SDIVCC : integer := 0 ; -- "011111";
constant ENABLE_TADDCC : integer := 0 ; -- "100000";
constant ENABLE_TSUBCC : integer := 0 ; -- "100001";
constant ENABLE_TADDCCTV : integer := 0 ; -- "100010";
constant ENABLE_TSUBCCTV : integer := 0 ; -- "100011";
constant ENABLE_MULSCC : integer := 0 ; -- "100100";
constant ENABLE_ISLL : integer := 1 ; -- "100101";
constant ENABLE_ISRL : integer := 1 ; -- "100110";
constant ENABLE_ISRA : integer := 1 ; -- "100111";
constant ENABLE_RDY : integer := 1 ; -- "101000";
constant ENABLE_RDPSR : integer := 1 ; -- "101001";
constant ENABLE_RDWIM : integer := 0 ; -- "101010";
constant ENABLE_RDTBR : integer := 0 ; -- "101011";
constant ENABLE_CUSTOM_5 : integer := 0 ; -- "101100";
constant ENABLE_CUSTOM_6 : integer := 0 ; -- "101101";
constant ENABLE_CUSTOM_7 : integer := 0 ; -- "101110";
constant ENABLE_CUSTOM_8 : integer := 0 ; -- "101111";
constant ENABLE_WRY : integer := 1 ; -- "110000";
constant ENABLE_WRPSR : integer := 1 ; -- "110001";
constant ENABLE_WRWIM : integer := 1 ; -- "110010";
constant ENABLE_WRTBR : integer := 1 ; -- "110011";
constant ENABLE_FPOP1 : integer := 0 ; -- "110100";
constant ENABLE_FPOP2 : integer := 0 ; -- "110101";
constant ENABLE_CPOP1 : integer := 0 ; -- "110110";
constant ENABLE_CPOP2 : integer := 0 ; -- "110111";
constant ENABLE_JMPL : integer := 1 ; -- "111000";
constant ENABLE_RETT : integer := 0 ; -- "111001";
constant ENABLE_TICC : integer := 0 ; -- "111010";
constant ENABLE_FLUSH : integer := 1 ; -- "111011";
constant ENABLE_SAVE : integer := 1 ; -- "111100";
constant ENABLE_RESTORE : integer := 1 ; -- "111101";
constant ENABLE_UMAC : integer := 0 ; -- "111110";
constant ENABLE_SMAC : integer := 0 ; -- "111111";
-- INSTRUCTION TYPE (11)
constant ENABLE_LD : integer := 1 ; -- "000000";
constant ENABLE_LDUB : integer := 0 ; -- "000001";
constant ENABLE_LDUH : integer := 0 ; -- "000010";
constant ENABLE_LDD : integer := 0 ; -- "000011";
constant ENABLE_ST : integer := 1 ; -- "000100";
constant ENABLE_STB : integer := 0 ; -- "000101";
constant ENABLE_STH : integer := 0 ; -- "000110";
constant ENABLE_ISTD : integer := 1 ; -- "000111";
constant ENABLE_LDSB : integer := 0 ; -- "001001";
constant ENABLE_LDSH : integer := 0 ; -- "001010";
constant ENABLE_LDSTUB : integer := 0 ; -- "001101";
constant ENABLE_SWAP : integer := 0 ; -- "001111";
constant ENABLE_LDA : integer := 0 ; -- "010000";
constant ENABLE_LDUBA : integer := 0 ; -- "010001";
constant ENABLE_LDUHA : integer := 0 ; -- "010010";
constant ENABLE_LDDA : integer := 0 ; -- "010011";
constant ENABLE_STA : integer := 1 ; -- "010100";
constant ENABLE_STBA : integer := 0 ; -- "010101";
constant ENABLE_STHA : integer := 0 ; -- "010110";
constant ENABLE_STDA : integer := 0 ; -- "010111";
constant ENABLE_LDSBA : integer := 0 ; -- "011001";
constant ENABLE_LDSHA : integer := 0 ; -- "011010";
constant ENABLE_LDSTUBA : integer := 0 ; -- "011101";
constant ENABLE_SWAPA : integer := 0 ; -- "011111";
constant ENABLE_LDF : integer := 0 ; -- "100000";
constant ENABLE_LDFSR : integer := 0 ; -- "100001";
constant ENABLE_LDDF : integer := 0 ; -- "100011";
constant ENABLE_STF : integer := 0 ; -- "100100";
constant ENABLE_STFSR : integer := 0 ; -- "100101";
constant ENABLE_STDFQ : integer := 0 ; -- "100110";
constant ENABLE_STDF : integer := 0 ; -- "100111";
constant ENABLE_LDC : integer := 0 ; -- "110000";
constant ENABLE_LDCSR : integer := 0 ; -- "110001";
constant ENABLE_LDDC : integer := 0 ; -- "110011";
constant ENABLE_STC : integer := 0 ; -- "110100";
constant ENABLE_STCSR : integer := 0 ; -- "110101";
constant ENABLE_STDCQ : integer := 0 ; -- "110110";
constant ENABLE_STDC : integer := 0 ; -- "110111";
constant ENABLE_CASA : integer := 0 ; -- "111100";
end;
package body asip_config is
-- NOTHING FOR NOW ;-)
end;
| gpl-3.0 | 738b87e20142ced6b52ff357a5838d72 | 0.549581 | 3.503345 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/example_design/Instruction_Memory_prod_exdes ([email protected] 2015-09-19-15-43-09).vhd | 1 | 5,312 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Instruction_Memory_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end Instruction_Memory_exdes;
architecture xilinx of Instruction_Memory_exdes is
component Instruction_Memory is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Instruction_Memory
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | a162355be561dedff5bfc982ae5d4c5f | 0.500753 | 4.627178 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/mlite_cpu.vhd | 1 | 16,135 | ---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a two or three stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #0:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #1:
-- 2. The memory returns the opcode.
-- Stage #2:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #3 (part of stage #2 if using two stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #3b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a two stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 0 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
---------------------------------------------------------------------
LIBRARY ieee;
USE work.mlite_pack.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY mlite_cpu IS
GENERIC(
memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 3
); --2 or 3
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
intr_in : IN std_logic;
address_next : OUT std_logic_vector(31 DOWNTO 2); --for synch ram
byte_we_next : OUT std_logic_vector(3 DOWNTO 0);
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_w : OUT std_logic_vector(31 DOWNTO 0);
data_r : IN std_logic_vector(31 DOWNTO 0);
mem_pause : IN std_logic
);
END; --entity mlite_cpu
ARCHITECTURE logic OF mlite_cpu IS
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
SIGNAL opcode : std_logic_vector(31 DOWNTO 0);
SIGNAL rs_index : std_logic_vector(5 DOWNTO 0);
SIGNAL rt_index : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_index : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_indexD : std_logic_vector(5 DOWNTO 0);
SIGNAL reg_source : std_logic_vector(31 DOWNTO 0);
SIGNAL reg_target : std_logic_vector(31 DOWNTO 0);
SIGNAL reg_dest : std_logic_vector(31 DOWNTO 0);
SIGNAL reg_destD : std_logic_vector(31 DOWNTO 0);
SIGNAL a_bus : std_logic_vector(31 DOWNTO 0);
SIGNAL a_busD : std_logic_vector(31 DOWNTO 0);
SIGNAL b_bus : std_logic_vector(31 DOWNTO 0);
SIGNAL b_busD : std_logic_vector(31 DOWNTO 0);
SIGNAL c_bus : std_logic_vector(31 DOWNTO 0);
SIGNAL c_alu : std_logic_vector(31 DOWNTO 0);
SIGNAL c_shift : std_logic_vector(31 DOWNTO 0);
SIGNAL c_mult : std_logic_vector(31 DOWNTO 0);
SIGNAL c_memory : std_logic_vector(31 DOWNTO 0);
SIGNAL imm : std_logic_vector(15 DOWNTO 0);
SIGNAL pc_future : std_logic_vector(31 DOWNTO 2);
SIGNAL pc_current : std_logic_vector(31 DOWNTO 2);
SIGNAL pc_plus4 : std_logic_vector(31 DOWNTO 2);
SIGNAL alu_func : alu_function_type;
SIGNAL alu_funcD : alu_function_type;
SIGNAL shift_func : shift_function_type;
SIGNAL shift_funcD : shift_function_type;
SIGNAL mult_func : mult_function_type;
SIGNAL mult_funcD : mult_function_type;
--
--
--
SIGNAL calu_1_func : std_logic_vector(5 DOWNTO 0);
SIGNAL calu_1_funcD : std_logic_vector(5 DOWNTO 0);
SIGNAL salu_1_func : std_logic_vector(5 DOWNTO 0);
SIGNAL salu_1_funcD : std_logic_vector(5 DOWNTO 0);
SIGNAL branch_func : branch_function_type;
SIGNAL take_branch : std_logic;
SIGNAL a_source : a_source_type;
SIGNAL b_source : b_source_type;
SIGNAL c_source : c_source_type;
SIGNAL pc_source : pc_source_type;
SIGNAL mem_source : mem_source_type;
SIGNAL pause_mult : std_logic;
SIGNAL pause_ctrl : std_logic;
SIGNAL pause_pipeline : std_logic;
SIGNAL pause_any : std_logic;
SIGNAL pause_non_ctrl : std_logic;
SIGNAL pause_bank : std_logic;
SIGNAL nullify_op : std_logic;
SIGNAL intr_enable : std_logic;
SIGNAL intr_signal : std_logic;
SIGNAL exception_sig : std_logic;
SIGNAL reset_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL reset : std_logic;
--
-- SIGNAUX NECESSAIRES LA CONNEXION DES ALU D'EXTENSION
--
SIGNAL comb_alu_1_func : std_logic_vector(5 DOWNTO 0);
SIGNAL comb_alu_1_out : std_logic_vector(31 DOWNTO 0);
SIGNAL sequ_alu_1_start : std_logic;
SIGNAL sequ_alu_1_func : std_logic_vector(5 DOWNTO 0);
SIGNAL sequ_alu_1_out : std_logic_vector(31 DOWNTO 0);
SIGNAL pause_salu_1 : std_logic;
BEGIN --architecture
pause_any <= (mem_pause OR pause_ctrl) OR (pause_mult OR pause_pipeline OR pause_salu_1);
pause_non_ctrl <= (mem_pause OR pause_mult OR pause_salu_1) OR pause_pipeline;
pause_bank <= (mem_pause OR pause_ctrl OR pause_mult OR pause_salu_1) AND NOT pause_pipeline;
nullify_op <= '1' WHEN (pc_source = FROM_LBRANCH AND take_branch = '0') OR intr_signal = '1' OR exception_sig = '1' ELSE '0';
c_bus <= c_alu OR c_shift OR c_mult OR comb_alu_1_out OR sequ_alu_1_out;
reset <= '1' WHEN reset_in = '1' OR reset_reg /= "1111" ELSE '0';
-----------------------------------------------------------------------------------
--
--
--synchronize reset and interrupt pins
intr_proc : PROCESS(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
BEGIN
IF reset_in = '1' THEN
reset_reg <= "0000";
intr_signal <= '0';
ELSIF rising_edge(clk) THEN
IF reset_reg /= "1111" THEN
reset_reg <= reset_reg + 1;
END IF;
--don't try to interrupt a multi-cycle instruction
IF pause_any = '0' THEN
IF intr_in = '1' AND intr_enable = '1' AND
pc_source = FROM_INC4 THEN
--the epc will contain pc+4
intr_signal <= '1';
ELSE
intr_signal <= '0';
END IF;
else
-- report "PAUSE";
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------------
--
--
u1_pc_next : pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 DOWNTO 2),
opcode25_0 => opcode(25 DOWNTO 0),
pc_source => pc_source,
pc_future => pc_future,
pc_current => pc_current,
pc_plus4 => pc_plus4
);
-----------------------------------------------------------------------------------
--
--
-- INSTANCIATION DU DEBUGGER --
-- synopsys translate_off
-- syn hesis off
-- dis_unit: disassembler PORT MAP (
-- clk,
-- reset_in,
-- pause_any,
-- opcode,
-- pc_current
-- );
-- syn hesis on
-- synopsys translate_on
-- FIN DU DEBUGGER --
-----------------------------------------------------------------------------------
--
--
u2_mem_ctrl : mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
address_next => address_next,
byte_we_next => byte_we_next,
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r
);
-----------------------------------------------------------------------------------
--
--
u3_control : control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
calu_1_func => calu_1_func,
salu_1_func => salu_1_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out => pc_source,
mem_source_out => mem_source,
exception_out => exception_sig);
-----------------------------------------------------------------------------------
--
--
u4_reg_bank : reg_bank
GENERIC MAP(memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
pause => pause_bank,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable
);
-----------------------------------------------------------------------------------
--
--
u5_bus_mux : bus_mux PORT MAP (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch
);
-----------------------------------------------------------------------------------
--
--
u6_alu : alu
GENERIC MAP (alu_type => alu_type)
PORT MAP (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu
);
-----------------------------------------------------------------------------------
--
--
u61_alu : comb_alu_1
PORT MAP (
clk => clk,
reset_in => reset,
a_in => a_busD,
b_in => b_busD,
alu_function => calu_1_funcD,
c_alu => comb_alu_1_out
);
-----------------------------------------------------------------------------------
--
--
u62_alu : sequ_alu_1
PORT MAP (
clk => clk,
reset_in => reset,
a_in => a_busD,
b_in => b_busD,
alu_function => salu_1_funcD,
c_alu => sequ_alu_1_out,
pause_out => pause_salu_1
);
-----------------------------------------------------------------------------------
--
--
u7_shifter : shifter
GENERIC MAP (shifter_type => shifter_type)
PORT MAP (
value => b_busD,
shift_amount => a_busD(4 DOWNTO 0),
shift_func => shift_funcD,
c_shift => c_shift
);
-----------------------------------------------------------------------------------
--
--
u8_mult : mult
GENERIC MAP (mult_type => mult_type)
PORT MAP (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult
);
-----------------------------------------------------------------------------------
--
--
u9_pipeline : pipeline PORT MAP (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
calu_1_func => calu_1_func,
calu_1_funcD => calu_1_funcD,
salu_1_func => salu_1_func,
salu_1_funcD => salu_1_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline
);
END; --architecture logic
| gpl-3.0 | ec1f6980790bcc92dd765ffe0f38d12c | 0.47115 | 3.828904 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_3_dir/exercise8_3.vhd | 1 | 1,407 | --!
--! @file: exercise8_3.vhd
--! @brief: circuilar shift with compenet #1 constant stages
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
-- Main code
--------------------------------------
entity exercise8_3 is
generic (N: integer := 5); -- num of stages
port (
clk, load: in std_logic;
d: in twoD(0 to M-1, N-1 downto 0);
q: buffer twoD(0 to M-1, N-1 downto 0));
constant M: integer := 8; -- bits per stage
end entity exercise8_3;
--------------------------------------
architecture circuit of exercise8_3 is
signal u: twoD(0 to M-1, N-1 downto 0); -- output of muxes
signal v: twoD(0 to M-1, N-1 downto 0); -- output of ffs
begin
gen1: for i in N-1 downto 0 generate -- width
gen2: for j in 0 to M-1 generate -- length
mux1: mux port map (
a => d(i, j),
b => v(i, M-1( - j)),
sel => load,
q => u(i, j)
);
dff1: flipflop port map (
d => u(i, j),
clk => clk,
q => v(i, j)
);
end generate gen2;
end generate gen1;
end architecture circuit;
--------------------------------------
| gpl-3.0 | a481de5af020fd75619d1b2d811cf36f | 0.455579 | 3.722222 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ddr_ctrl.vhd | 1 | 13,376 | ---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
| gpl-3.0 | 0d0bf4fb968b734bcde0a394afc294f6 | 0.513532 | 3.811912 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/simulation/bmg_stim_gen.vhd | 1 | 7,820 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(12 DOWNTO 0) <= WRITE_ADDR(12 DOWNTO 0);
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 8192
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | b72f6eff3e5aed658c4368327336315f | 0.541176 | 3.734479 | false | false | false | false |
chibby0ne/vhdl-book | Chapter9/my_comps_dir/my_comps.vhd | 1 | 2,659 | --!
--! @file: my_comps.vhd
--! @brief: overloaded and and not
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package my_comps is
function my_and(a, b : std_logic_vector) return std_logic_vector
function my_not(a : std_logic_vector) return std_logic_vector
end package my_comps;
------------------------------
package body my_comps is
type stdlogic_table is array(std_ulogic, std_ulogic) of std_ulogic;
constant and_table: stdlogic_table := (
--------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'). -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), --| 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), --| Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), --| W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), --| W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'). -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), --| H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X')); --| - |
type stdlogic_1d is array (std_ulogic) of std_ulogic;
constant not_table: stdlogic_1d :=
--------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-- functions
function my_and(a, b : std_logic_vector) return std_logic_vector is
alias aa: std_logic_vector(1 to a'length) is a;
alias bb: std_logic_vector(1 to b'length) is b;
variable result: std_logic_vector(1 to a'length);
begin
assert (a'length = b'length)
report "Inputs have different size"
severity failure;
for1: for i in result'range loop
result(i) := and_table(aa(i), bb(i));
end loop label;
return result;
end function my_and;
function my_not(a : std_logic_vector) return std_logic_vector is
alias aa: std_logic_vector(1 to a'length) is a;
variable result: std_logic_vector(1 to a'length);
begin
for1: for i in result'range loop
result(i) := not_table(aa(i));
end loop for1;
return result;
end function my_not;
end package body my_comps;
--------------------------------------
| gpl-3.0 | 44883bc2b5430f7eb37916fe8993bd5b | 0.412185 | 3.109942 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/cache.vhd | 1 | 6,254 | ---------------------------------------------------------------------
-- TITLE: Cache Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/22/08
-- FILENAME: cache.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Control 4KB unified cache that uses the upper 4KB of the 8KB
-- internal RAM. Only lowest 2MB of DDR is cached.
-- Only include file for Xilinx FPGAs.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity cache is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end; --cache
architecture logic of cache is
subtype state_type is std_logic_vector(1 downto 0);
constant STATE_IDLE : state_type := "00";
constant STATE_CHECKING : state_type := "01";
constant STATE_MISSED : state_type := "10";
constant STATE_WAITING : state_type := "11";
signal state_reg : state_type;
signal state : state_type;
signal state_next : state_type;
signal cache_address : std_logic_vector(10 downto 0);
signal cache_tag_in : std_logic_vector(8 downto 0);
signal cache_tag_reg : std_logic_vector(8 downto 0);
signal cache_tag_out : std_logic_vector(8 downto 0);
signal cache_we : std_logic;
begin
cache_proc: process(clk, reset, mem_busy, cache_address,
state_reg, state, state_next,
address_next, byte_we_next, cache_tag_in, --Stage1
cache_tag_reg, cache_tag_out, --Stage2
cpu_address) --Stage3
begin
case state_reg is
when STATE_IDLE => --cache idle
cache_checking <= '0';
cache_miss <= '0';
state <= STATE_IDLE;
when STATE_CHECKING => --current read in cached range, check if match
cache_checking <= '1';
if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
cache_miss <= '1';
state <= STATE_MISSED;
else
cache_miss <= '0';
state <= STATE_IDLE;
end if;
when STATE_MISSED => --current read cache miss
cache_checking <= '0';
cache_miss <= '1';
if mem_busy = '1' then
state <= STATE_MISSED;
else
state <= STATE_WAITING;
end if;
when STATE_WAITING => --waiting for memory access to complete
cache_checking <= '0';
cache_miss <= '0';
if mem_busy = '1' then
state <= STATE_WAITING;
else
state <= STATE_IDLE;
end if;
when others =>
cache_checking <= '0';
cache_miss <= '0';
state <= STATE_IDLE;
end case; --state
if state = STATE_IDLE then --check if next access in cached range
cache_address <= '0' & address_next(11 downto 2);
if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
cache_access <= '1';
if byte_we_next = "0000" then --read cycle
cache_we <= '0';
state_next <= STATE_CHECKING; --need to check if match
else
cache_we <= '1'; --update cache tag
state_next <= STATE_WAITING;
end if;
else
cache_access <= '0';
cache_we <= '0';
state_next <= STATE_IDLE;
end if;
else
cache_address <= '0' & cpu_address(11 downto 2);
cache_access <= '0';
if state = STATE_MISSED then
cache_we <= '1'; --update cache tag
else
cache_we <= '0';
end if;
state_next <= state;
end if;
if byte_we_next = "0000" or byte_we_next = "1111" then --read or 32-bit write
cache_tag_in <= address_next(20 downto 12);
else
cache_tag_in <= ONES(8 downto 0); --invalid tag
end if;
if reset = '1' then
state_reg <= STATE_IDLE;
cache_tag_reg <= ZERO(8 downto 0);
elsif rising_edge(clk) then
state_reg <= state_next;
if state = STATE_IDLE and state_reg /= STATE_MISSED then
cache_tag_reg <= cache_tag_in;
end if;
end if;
end process;
-- cache_xilinx: if memory_type = "XILINX_16X" generate
-- begin
-- cache_tag: RAMB16_S9 --Xilinx specific
-- port map (
-- DO => cache_tag_out(7 downto 0),
-- DOP => cache_tag_out(8 downto 8),
-- ADDR => cache_address, --registered
-- CLK => clk,
-- DI => cache_tag_in(7 downto 0), --registered
-- DIP => cache_tag_in(8 downto 8),
-- EN => '1',
-- SSR => ZERO(0),
-- WE => cache_we);
-- end generate; --cache_xilinx
cache_generic: if memory_type /= "XILINX_16X" generate
begin
cache_tag: process(clk, cache_address, cache_tag_in, cache_we)
constant ADDRESS_WIDTH : natural := 10;
type storage_array is array(natural range 0 to 2 ** ADDRESS_WIDTH - 1) of std_logic_vector(8 downto 0);
variable storage : storage_array;
variable index : natural := 0;
begin
if rising_edge(clk) then
index := conv_integer(cache_address(ADDRESS_WIDTH-1 downto 0));
if cache_we = '1' then
storage(index) := cache_tag_in;
end if;
cache_tag_out <= storage(index);
end if;
end process; --cache_tag
end generate; --cache_generic
end; --logic
| gpl-3.0 | 637cea4abebe75a244b2cc29e5219ead | 0.527343 | 3.75165 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example1_dir/vending_machine.vhd | 1 | 4,382 | --
-- vending machine FSM
--
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine is
--generic declarations
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;
candy_out, nickel_out, dime_out: out std_logic);
end entity vending_machine;
--------------------------------------
architecture circuit of vending_machine is
type state is (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
begin
--------------------------------------
-- lower section of FSM (sequential part)
--------------------------------------
process (rst, clk)
--declarativepart
begin
if (rst = '1') then
pr_state <= st0;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------
-- upper section of FSM (combinational part)
--------------------------------------
process (pr_state, nickel_in, dime_in, quarter_in)
--declarativepart
begin
case pr_state is
when st0 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st5;
elsif (dime_in) then
nx_state <= st10;
elsif (quarter_in) then
nx_state <= st25;
else
nx_state <= st0;
end if;
when st5 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st10;
elsif (dime_in) then
nx_state <= st15;
elsif (quarter_in) then
nx_state <= st30;
else
nx_state <= st5;
end if;
when st10 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st15;
elsif (dime_in) then
nx_state <= st20;
elsif (quarter_in) then
nx_state <= st35;
else
nx_state <= st10;
end if;
when st15 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st20;
elsif (dime_in) then
nx_state <= st25;
elsif (quarter_in) then
nx_state <= st40;
else
nx_state <= st15;
end if;
when st20 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st25;
elsif (dime_in) then
nx_state <= st30;
elsif (quarter_in) then
nx_state <= st45;
else
nx_state <= st20;
end if;
when st25 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st0;
when st35 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st40 =>
candy_out <= '0';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st35;
when st45 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '1';
nx_state <= st35;
end case;
end process;
end architecture circuit;
| gpl-3.0 | c2fe604b77561ff261260a49a774904b | 0.361707 | 4.593291 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example2_dir/vending_machine_noglitch_tb.vhd | 1 | 1,431 | --------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine_noglitch_tb is
end entity vending_machine_noglitch_tb;
--------------------------------------
architecture circuit of vending_machine_noglitch_tb is
-- dut declaration
component vending_machine_noglitch is
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;
new_candy_out, new_nickel_out, new_dime_out: out std_logic);
end component vending_machine_noglitch;
-- signal declaration
signal clk_tb: std_logic := '0';
signal rst_tb: std_logic := '1';
signal nickel_in_tb, dime_in_tb, quarter_in_tb: boolean;
signal candy_out_tb, nickel_out_tb, dime_out_tb: std_logic;
begin
-- dut instantiation
dut: vending_machine_noglitch port map (
clk_tb, rst_tb, nickel_in_tb, dime_in_tb, quarter_in_tb, candy_out_tb, nickel_out_tb, dime_out_tb
);
-- stimuli generation
-- clock
clk_tb <= not clk_tb after 20 ns;
-- rst
rst_tb <= '0' after 40 ns;
-- nickel_in
nickel_in_tb <= false, true after 120 ns, false after 160 ns;
-- dime_in
dime_in_tb <= false, true after 200 ns, false after 240 ns;
-- quarter_in
quarter_in_tb <= false, true after 280 ns, false after 320 ns;
end architecture circuit;
| gpl-3.0 | 5e97e8461eff13acb984d58bef6ac4ea | 0.590496 | 3.641221 | false | false | false | false |
siam28/neppielight | neppielight.vhd | 2 | 4,220 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity neppielight is
Port ( clk50 : in STD_LOGIC;
hdmi_in_p : in STD_LOGIC_VECTOR(3 downto 0);
hdmi_in_n : in STD_LOGIC_VECTOR(3 downto 0);
hdmi_in_sclk : inout STD_LOGIC;
hdmi_in_sdat : inout STD_LOGIC;
hdmi_out_p : out STD_LOGIC_VECTOR(3 downto 0);
hdmi_out_n : out STD_LOGIC_VECTOR(3 downto 0);
leds : out std_logic_vector(7 downto 0);
spiout_mosi: out std_logic;
spiout_sck: out std_logic);
end neppielight;
architecture Behavioral of neppielight is
COMPONENT dvid_out
PORT(
clk_pixel : IN std_logic;
red_p : IN std_logic_vector(7 downto 0);
green_p : IN std_logic_vector(7 downto 0);
blue_p : IN std_logic_vector(7 downto 0);
blank : IN std_logic;
hsync : IN std_logic;
vsync : IN std_logic;
tmds_out_p : OUT std_logic_vector(3 downto 0);
tmds_out_n : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT averager
PORT(
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer: OUT std_logic_vector(0 to 24*25-1 );
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic
);
END COMPONENT;
COMPONENT dvid_in
PORT(
clk_pixel : out std_logic;
leds : out std_logic_vector(7 downto 0) := (others => '0');
red_p : out std_logic_vector(7 downto 0);
green_p : out std_logic_vector(7 downto 0);
blue_p : out std_logic_vector(7 downto 0);
blank : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
tmds_in_p : in std_logic_vector(3 downto 0);
tmds_in_n : in std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT spiout
PORT(
clk50 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (25*24-1 downto 0);
MOSI : out STD_LOGIC;
SCK : out STD_LOGIC
);
END COMPONENT;
signal clk_pixel : std_logic;
signal i_red : std_logic_vector(7 downto 0);
signal i_green : std_logic_vector(7 downto 0);
signal i_blue : std_logic_vector(7 downto 0);
signal i_blank : std_logic;
signal i_hsync : std_logic;
signal i_vsync : std_logic;
signal o_red : std_logic_vector(7 downto 0);
signal o_green : std_logic_vector(7 downto 0);
signal o_blue : std_logic_vector(7 downto 0);
signal o_blank : std_logic;
signal o_hsync : std_logic;
signal o_vsync : std_logic;
signal framebuffer : std_logic_vector(0 to 25*24-1) := (others => '0');
begin
hdmi_in_sclk <= 'Z';
hdmi_in_sdat <= 'Z';
Inst_dvid_in: dvid_in PORT MAP(
tmds_in_p => hdmi_in_p,
tmds_in_n => hdmi_in_n,
leds => leds,
clk_pixel => clk_pixel,
red_p => i_red,
green_p => i_green,
blue_p => i_blue,
blank => i_blank,
hsync => i_hsync,
vsync => i_vsync
);
Inst_averager: averager PORT MAP(
clk_pixel => clk_pixel,
i_red => i_red,
i_green => i_green,
i_blue => i_blue,
i_blank => i_blank,
i_hsync => i_hsync,
i_vsync => i_vsync,
--
framebuffer => framebuffer,
o_red => o_red,
o_green => o_green,
o_blue => o_blue,
o_blank => o_blank,
o_hsync => o_hsync,
o_vsync => o_vsync
);
Inst_dvid_out: dvid_out PORT MAP(
clk_pixel => clk_pixel,
red_p => o_red,
green_p => o_green,
blue_p => o_blue,
blank => o_blank,
hsync => o_hsync,
vsync => o_vsync,
tmds_out_p => hdmi_out_p,
tmds_out_n => hdmi_out_n
);
Inst_spout: spiout PORT MAP(
clk50 => clk50,
data => framebuffer,
MOSI => SPIOUT_MOSI,
SCK => SPIOUT_SCK
);
end Behavioral;
| gpl-2.0 | 09b0042e25f1b18797a251f4871f7f47 | 0.559242 | 2.796554 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_dgen.vhd | 1 | 5,142 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Video_Memory_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF Video_Memory_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.Video_Memory_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| mit | 88d6561e95c0de8e506fcb63377662e1 | 0.579152 | 4.058406 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/exercise2_dir/non_periodic_stimuli.vhd | 1 | 2,657 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: non_periodic_stimuli.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-04-01
--!
--!
--------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_support.all;
use work.pkg_types.all;
--------------------------------------
entity non_periodic_stimuli is
--generic declarations
end entity non_periodic_stimuli;
--------------------------------------
architecture circuit of non_periodic_stimuli is
signal sig1: std_logic := '1';
signal sig2: std_logic := '1';
signal sig3: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(3, sig3'length));
begin
-- sig1
-- (i) concurrent
-- sig1 <= '0' after 25 ns, '1' after 75 ns, '0' after 100ns;
-- (ii) sequential
sig1_proc: process
--declarativepart
begin
sig1 <= '1';
wait for 25 ns;
sig1 <= '0';
wait for 50 ns;
sig1 <= '1';
wait for 25 ns;
sig1 <= '0';
wait;
end process sig1_proc;
-- sig2
-- (i) concurrent
-- sig2 <= '0' after 25 ns, '1' after 75 ns, '0' after 100 ns, '1' after 125 ns, '0' after 175 ns, '1' after 200 ns, '0' after 225 ns;
-- (ii) sequential
sig2_proc: process
--declarativepart
begin
sig2 <= '1';
wait for 25 ns;
sig2 <= '0';
wait for 50 ns;
sig2 <= '1';
wait for 25 ns;
sig2 <= '0';
wait for 25 ns;
sig2 <= '1';
wait for 50 ns;
sig2 <= '0';
wait for 25 ns;
sig2 <= '1';
wait for 25 ns;
sig2 <= '0';
wait;
end process sig2_proc;
-- sig3
-- (i) concurrent
-- sig3 <= std_logic_vector(to_unsigned(0, sig3'length)) after 25 ns,
-- std_logic_vector(to_unsigned(99, sig3'length)) after 50 ns,
-- std_logic_vector(to_unsigned(17, sig3'length)) after 100 ns,
-- std_logic_vector(to_unsigned(255, sig3'length)) after 175 ns;
--
-- (ii) sequential
sig3_proc: process
begin
sig3 <= std_logic_vector(to_unsigned(3, sig3'length));
wait for 25 ns;
sig3 <= std_logic_vector(to_unsigned(0, sig3'length));
wait for 25 ns;
sig3 <= std_logic_vector(to_unsigned(99, sig3'length));
wait for 50 ns;
sig3 <= std_logic_vector(to_unsigned(17, sig3'length));
wait for 75 ns;
sig3 <= std_logic_vector(to_unsigned(255, sig3'length));
wait;
end process sig3_proc;
end architecture circuit;
| gpl-3.0 | 43066d445470453adc94f4321e6a780e | 0.523146 | 3.437257 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_CombRAM.vhd | 1 | 2,219 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY TB_Q16_8_NodeRAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(15 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(15 downto 0)
);
END;
architecture cRAM of TB_Q16_8_NodeRAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
signal RAM : ram_type;
SIGNAL READ_C : UNSIGNED(11 downto 0);
SIGNAL WRITE_C : UNSIGNED(11 downto 0);
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
begin
if reset = '0' then
WRITE_C <= TO_UNSIGNED(0, 12);
elsif clock'event and clock = '1' then
if write_en = '1' then
TEMP := WRITE_C + TO_UNSIGNED(1, 12);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
WRITE_C <= TEMP;
else
WRITE_C <= WRITE_C;
end if;
end if;
end process;
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
elsif clock'event and clock = '1' then
if read_en = '1' then
TEMP := READ_C + TO_UNSIGNED(1, 12);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
READ_C <= TEMP;
else
READ_C <= READ_C;
end if;
end if;
end process;
--
--
--
process(clock)
begin
if clock'event and clock = '1' then
if WRITE_EN = '1' then
RAM( to_integer( WRITE_C ) ) <= INPUT_1;
end if;
OUTPUT_1 <= RAM( to_integer(READ_C) );
end if;
end process;
END cRAM;
| gpl-3.0 | 6d604fd74ee75f7c634433fbc49d3aed | 0.511942 | 3.147518 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_pkg.vhd | 1 | 6,098 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE dist_mem_gen_v7_2_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END dist_mem_gen_v7_2_TB_PKG;
PACKAGE BODY dist_mem_gen_v7_2_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END dist_mem_gen_v7_2_TB_PKG;
| mit | 19c55b109a0343cf78d75ede87092cf4 | 0.576746 | 4.318697 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_C_to_V_RAM.vhd | 1 | 45,914 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_C_to_V_RAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_C_to_V_RAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
type rom_type is array (0 to 1824-1) of UNSIGNED (10 downto 0);
signal RAM : ram_type;
constant ROM : rom_type:= (
TO_UNSIGNED( 75, 11), TO_UNSIGNED( 618, 11), TO_UNSIGNED( 732, 11), TO_UNSIGNED(1425, 11), TO_UNSIGNED(1500, 11), TO_UNSIGNED(1683, 11), TO_UNSIGNED( 84, 11), TO_UNSIGNED( 621, 11),
TO_UNSIGNED( 738, 11), TO_UNSIGNED(1428, 11), TO_UNSIGNED(1506, 11), TO_UNSIGNED(1614, 11), TO_UNSIGNED( 86, 11), TO_UNSIGNED( 624, 11), TO_UNSIGNED( 744, 11), TO_UNSIGNED(1437, 11),
TO_UNSIGNED(1488, 11), TO_UNSIGNED(1819, 11), TO_UNSIGNED( 12, 11), TO_UNSIGNED( 88, 11), TO_UNSIGNED( 627, 11), TO_UNSIGNED( 750, 11), TO_UNSIGNED(1440, 11), TO_UNSIGNED(1512, 11),
TO_UNSIGNED( 15, 11), TO_UNSIGNED( 90, 11), TO_UNSIGNED( 630, 11), TO_UNSIGNED( 756, 11), TO_UNSIGNED(1443, 11), TO_UNSIGNED(1524, 11), TO_UNSIGNED( 18, 11), TO_UNSIGNED( 92, 11),
TO_UNSIGNED( 633, 11), TO_UNSIGNED( 762, 11), TO_UNSIGNED(1446, 11), TO_UNSIGNED(1518, 11), TO_UNSIGNED( 21, 11), TO_UNSIGNED( 94, 11), TO_UNSIGNED( 636, 11), TO_UNSIGNED( 768, 11),
TO_UNSIGNED(1449, 11), TO_UNSIGNED(1542, 11), TO_UNSIGNED( 24, 11), TO_UNSIGNED( 96, 11), TO_UNSIGNED( 639, 11), TO_UNSIGNED( 774, 11), TO_UNSIGNED(1452, 11), TO_UNSIGNED(1548, 11),
TO_UNSIGNED( 27, 11), TO_UNSIGNED( 98, 11), TO_UNSIGNED( 642, 11), TO_UNSIGNED( 780, 11), TO_UNSIGNED(1455, 11), TO_UNSIGNED(1530, 11), TO_UNSIGNED( 30, 11), TO_UNSIGNED( 100, 11),
TO_UNSIGNED( 645, 11), TO_UNSIGNED( 786, 11), TO_UNSIGNED(1461, 11), TO_UNSIGNED(1536, 11), TO_UNSIGNED( 33, 11), TO_UNSIGNED( 102, 11), TO_UNSIGNED( 648, 11), TO_UNSIGNED( 792, 11),
TO_UNSIGNED(1458, 11), TO_UNSIGNED(1554, 11), TO_UNSIGNED( 36, 11), TO_UNSIGNED( 104, 11), TO_UNSIGNED( 651, 11), TO_UNSIGNED( 798, 11), TO_UNSIGNED(1485, 11), TO_UNSIGNED(1560, 11),
TO_UNSIGNED( 39, 11), TO_UNSIGNED( 106, 11), TO_UNSIGNED( 654, 11), TO_UNSIGNED( 804, 11), TO_UNSIGNED(1572, 11), TO_UNSIGNED(1617, 11), TO_UNSIGNED( 42, 11), TO_UNSIGNED( 108, 11),
TO_UNSIGNED( 657, 11), TO_UNSIGNED( 810, 11), TO_UNSIGNED(1398, 11), TO_UNSIGNED(1566, 11), TO_UNSIGNED( 45, 11), TO_UNSIGNED( 110, 11), TO_UNSIGNED( 660, 11), TO_UNSIGNED( 816, 11),
TO_UNSIGNED(1401, 11), TO_UNSIGNED(1584, 11), TO_UNSIGNED( 48, 11), TO_UNSIGNED( 112, 11), TO_UNSIGNED( 663, 11), TO_UNSIGNED( 822, 11), TO_UNSIGNED(1404, 11), TO_UNSIGNED(1578, 11),
TO_UNSIGNED( 51, 11), TO_UNSIGNED( 114, 11), TO_UNSIGNED( 666, 11), TO_UNSIGNED( 828, 11), TO_UNSIGNED(1413, 11), TO_UNSIGNED(1596, 11), TO_UNSIGNED( 54, 11), TO_UNSIGNED( 116, 11),
TO_UNSIGNED( 669, 11), TO_UNSIGNED( 690, 11), TO_UNSIGNED(1416, 11), TO_UNSIGNED(1602, 11), TO_UNSIGNED( 57, 11), TO_UNSIGNED( 118, 11), TO_UNSIGNED( 672, 11), TO_UNSIGNED( 696, 11),
TO_UNSIGNED(1419, 11), TO_UNSIGNED(1590, 11), TO_UNSIGNED( 0, 11), TO_UNSIGNED( 60, 11), TO_UNSIGNED( 120, 11), TO_UNSIGNED( 675, 11), TO_UNSIGNED( 702, 11), TO_UNSIGNED(1407, 11),
TO_UNSIGNED( 63, 11), TO_UNSIGNED( 122, 11), TO_UNSIGNED( 678, 11), TO_UNSIGNED( 708, 11), TO_UNSIGNED(1410, 11), TO_UNSIGNED(1476, 11), TO_UNSIGNED( 66, 11), TO_UNSIGNED( 124, 11),
TO_UNSIGNED( 681, 11), TO_UNSIGNED( 714, 11), TO_UNSIGNED(1434, 11), TO_UNSIGNED(1464, 11), TO_UNSIGNED( 69, 11), TO_UNSIGNED( 126, 11), TO_UNSIGNED( 684, 11), TO_UNSIGNED( 720, 11),
TO_UNSIGNED(1431, 11), TO_UNSIGNED(1470, 11), TO_UNSIGNED( 72, 11), TO_UNSIGNED( 128, 11), TO_UNSIGNED( 687, 11), TO_UNSIGNED( 726, 11), TO_UNSIGNED(1422, 11), TO_UNSIGNED(1494, 11),
TO_UNSIGNED( 186, 11), TO_UNSIGNED( 234, 11), TO_UNSIGNED( 775, 11), TO_UNSIGNED( 906, 11), TO_UNSIGNED(1435, 11), TO_UNSIGNED(1585, 11), TO_UNSIGNED( 188, 11), TO_UNSIGNED( 236, 11),
TO_UNSIGNED( 781, 11), TO_UNSIGNED( 909, 11), TO_UNSIGNED(1432, 11), TO_UNSIGNED(1579, 11), TO_UNSIGNED( 190, 11), TO_UNSIGNED( 238, 11), TO_UNSIGNED( 787, 11), TO_UNSIGNED( 912, 11),
TO_UNSIGNED(1423, 11), TO_UNSIGNED(1597, 11), TO_UNSIGNED( 192, 11), TO_UNSIGNED( 240, 11), TO_UNSIGNED( 793, 11), TO_UNSIGNED( 915, 11), TO_UNSIGNED(1426, 11), TO_UNSIGNED(1603, 11),
TO_UNSIGNED( 194, 11), TO_UNSIGNED( 242, 11), TO_UNSIGNED( 799, 11), TO_UNSIGNED( 918, 11), TO_UNSIGNED(1429, 11), TO_UNSIGNED(1591, 11), TO_UNSIGNED( 1, 11), TO_UNSIGNED( 196, 11),
TO_UNSIGNED( 244, 11), TO_UNSIGNED( 805, 11), TO_UNSIGNED( 921, 11), TO_UNSIGNED(1438, 11), TO_UNSIGNED( 198, 11), TO_UNSIGNED( 246, 11), TO_UNSIGNED( 811, 11), TO_UNSIGNED( 924, 11),
TO_UNSIGNED(1441, 11), TO_UNSIGNED(1477, 11), TO_UNSIGNED( 200, 11), TO_UNSIGNED( 248, 11), TO_UNSIGNED( 817, 11), TO_UNSIGNED( 927, 11), TO_UNSIGNED(1444, 11), TO_UNSIGNED(1465, 11),
TO_UNSIGNED( 202, 11), TO_UNSIGNED( 250, 11), TO_UNSIGNED( 823, 11), TO_UNSIGNED( 930, 11), TO_UNSIGNED(1447, 11), TO_UNSIGNED(1471, 11), TO_UNSIGNED( 204, 11), TO_UNSIGNED( 252, 11),
TO_UNSIGNED( 829, 11), TO_UNSIGNED( 933, 11), TO_UNSIGNED(1450, 11), TO_UNSIGNED(1495, 11), TO_UNSIGNED( 206, 11), TO_UNSIGNED( 254, 11), TO_UNSIGNED( 691, 11), TO_UNSIGNED( 936, 11),
TO_UNSIGNED(1453, 11), TO_UNSIGNED(1501, 11), TO_UNSIGNED( 208, 11), TO_UNSIGNED( 256, 11), TO_UNSIGNED( 697, 11), TO_UNSIGNED( 939, 11), TO_UNSIGNED(1456, 11), TO_UNSIGNED(1507, 11),
TO_UNSIGNED( 210, 11), TO_UNSIGNED( 258, 11), TO_UNSIGNED( 703, 11), TO_UNSIGNED( 942, 11), TO_UNSIGNED(1462, 11), TO_UNSIGNED(1489, 11), TO_UNSIGNED( 212, 11), TO_UNSIGNED( 260, 11),
TO_UNSIGNED( 709, 11), TO_UNSIGNED( 945, 11), TO_UNSIGNED(1459, 11), TO_UNSIGNED(1513, 11), TO_UNSIGNED( 214, 11), TO_UNSIGNED( 262, 11), TO_UNSIGNED( 715, 11), TO_UNSIGNED( 948, 11),
TO_UNSIGNED(1486, 11), TO_UNSIGNED(1525, 11), TO_UNSIGNED( 216, 11), TO_UNSIGNED( 264, 11), TO_UNSIGNED( 721, 11), TO_UNSIGNED( 951, 11), TO_UNSIGNED(1519, 11), TO_UNSIGNED(1618, 11),
TO_UNSIGNED( 218, 11), TO_UNSIGNED( 266, 11), TO_UNSIGNED( 727, 11), TO_UNSIGNED( 954, 11), TO_UNSIGNED(1399, 11), TO_UNSIGNED(1543, 11), TO_UNSIGNED( 220, 11), TO_UNSIGNED( 268, 11),
TO_UNSIGNED( 733, 11), TO_UNSIGNED( 957, 11), TO_UNSIGNED(1402, 11), TO_UNSIGNED(1549, 11), TO_UNSIGNED( 222, 11), TO_UNSIGNED( 270, 11), TO_UNSIGNED( 739, 11), TO_UNSIGNED( 960, 11),
TO_UNSIGNED(1405, 11), TO_UNSIGNED(1531, 11), TO_UNSIGNED( 224, 11), TO_UNSIGNED( 272, 11), TO_UNSIGNED( 745, 11), TO_UNSIGNED( 963, 11), TO_UNSIGNED(1414, 11), TO_UNSIGNED(1537, 11),
TO_UNSIGNED( 226, 11), TO_UNSIGNED( 274, 11), TO_UNSIGNED( 751, 11), TO_UNSIGNED( 966, 11), TO_UNSIGNED(1417, 11), TO_UNSIGNED(1555, 11), TO_UNSIGNED( 228, 11), TO_UNSIGNED( 276, 11),
TO_UNSIGNED( 757, 11), TO_UNSIGNED( 969, 11), TO_UNSIGNED(1420, 11), TO_UNSIGNED(1561, 11), TO_UNSIGNED( 230, 11), TO_UNSIGNED( 278, 11), TO_UNSIGNED( 763, 11), TO_UNSIGNED( 972, 11),
TO_UNSIGNED(1408, 11), TO_UNSIGNED(1573, 11), TO_UNSIGNED( 232, 11), TO_UNSIGNED( 280, 11), TO_UNSIGNED( 769, 11), TO_UNSIGNED( 975, 11), TO_UNSIGNED(1411, 11), TO_UNSIGNED(1567, 11),
TO_UNSIGNED( 235, 11), TO_UNSIGNED( 282, 11), TO_UNSIGNED( 788, 11), TO_UNSIGNED(1206, 11), TO_UNSIGNED(1556, 11), TO_UNSIGNED(1635, 11), TO_UNSIGNED( 237, 11), TO_UNSIGNED( 284, 11),
TO_UNSIGNED( 794, 11), TO_UNSIGNED(1209, 11), TO_UNSIGNED(1562, 11), TO_UNSIGNED(1629, 11), TO_UNSIGNED( 239, 11), TO_UNSIGNED( 286, 11), TO_UNSIGNED( 800, 11), TO_UNSIGNED(1194, 11),
TO_UNSIGNED(1574, 11), TO_UNSIGNED(1632, 11), TO_UNSIGNED( 241, 11), TO_UNSIGNED( 288, 11), TO_UNSIGNED( 806, 11), TO_UNSIGNED(1215, 11), TO_UNSIGNED(1568, 11), TO_UNSIGNED(1641, 11),
TO_UNSIGNED( 243, 11), TO_UNSIGNED( 290, 11), TO_UNSIGNED( 812, 11), TO_UNSIGNED(1212, 11), TO_UNSIGNED(1586, 11), TO_UNSIGNED(1638, 11), TO_UNSIGNED( 245, 11), TO_UNSIGNED( 292, 11),
TO_UNSIGNED( 818, 11), TO_UNSIGNED(1221, 11), TO_UNSIGNED(1580, 11), TO_UNSIGNED(1644, 11), TO_UNSIGNED( 247, 11), TO_UNSIGNED( 294, 11), TO_UNSIGNED( 824, 11), TO_UNSIGNED(1224, 11),
TO_UNSIGNED(1598, 11), TO_UNSIGNED(1650, 11), TO_UNSIGNED( 249, 11), TO_UNSIGNED( 296, 11), TO_UNSIGNED( 830, 11), TO_UNSIGNED(1227, 11), TO_UNSIGNED(1604, 11), TO_UNSIGNED(1647, 11),
TO_UNSIGNED( 251, 11), TO_UNSIGNED( 298, 11), TO_UNSIGNED( 692, 11), TO_UNSIGNED(1218, 11), TO_UNSIGNED(1592, 11), TO_UNSIGNED(1653, 11), TO_UNSIGNED( 2, 11), TO_UNSIGNED( 253, 11),
TO_UNSIGNED( 300, 11), TO_UNSIGNED( 698, 11), TO_UNSIGNED(1233, 11), TO_UNSIGNED(1656, 11), TO_UNSIGNED( 255, 11), TO_UNSIGNED( 302, 11), TO_UNSIGNED( 704, 11), TO_UNSIGNED(1236, 11),
TO_UNSIGNED(1478, 11), TO_UNSIGNED(1659, 11), TO_UNSIGNED( 257, 11), TO_UNSIGNED( 304, 11), TO_UNSIGNED( 710, 11), TO_UNSIGNED(1239, 11), TO_UNSIGNED(1466, 11), TO_UNSIGNED(1662, 11),
TO_UNSIGNED( 259, 11), TO_UNSIGNED( 306, 11), TO_UNSIGNED( 716, 11), TO_UNSIGNED(1230, 11), TO_UNSIGNED(1472, 11), TO_UNSIGNED(1665, 11), TO_UNSIGNED( 261, 11), TO_UNSIGNED( 308, 11),
TO_UNSIGNED( 722, 11), TO_UNSIGNED(1251, 11), TO_UNSIGNED(1496, 11), TO_UNSIGNED(1671, 11), TO_UNSIGNED( 263, 11), TO_UNSIGNED( 310, 11), TO_UNSIGNED( 728, 11), TO_UNSIGNED(1242, 11),
TO_UNSIGNED(1502, 11), TO_UNSIGNED(1668, 11), TO_UNSIGNED( 265, 11), TO_UNSIGNED( 312, 11), TO_UNSIGNED( 734, 11), TO_UNSIGNED(1245, 11), TO_UNSIGNED(1508, 11), TO_UNSIGNED(1674, 11),
TO_UNSIGNED( 267, 11), TO_UNSIGNED( 314, 11), TO_UNSIGNED( 740, 11), TO_UNSIGNED(1248, 11), TO_UNSIGNED(1490, 11), TO_UNSIGNED(1677, 11), TO_UNSIGNED( 269, 11), TO_UNSIGNED( 316, 11),
TO_UNSIGNED( 746, 11), TO_UNSIGNED(1257, 11), TO_UNSIGNED(1514, 11), TO_UNSIGNED(1680, 11), TO_UNSIGNED( 271, 11), TO_UNSIGNED( 318, 11), TO_UNSIGNED( 752, 11), TO_UNSIGNED(1254, 11),
TO_UNSIGNED(1482, 11), TO_UNSIGNED(1526, 11), TO_UNSIGNED( 273, 11), TO_UNSIGNED( 320, 11), TO_UNSIGNED( 758, 11), TO_UNSIGNED(1263, 11), TO_UNSIGNED(1520, 11), TO_UNSIGNED(1608, 11),
TO_UNSIGNED( 275, 11), TO_UNSIGNED( 322, 11), TO_UNSIGNED( 764, 11), TO_UNSIGNED(1260, 11), TO_UNSIGNED(1544, 11), TO_UNSIGNED(1611, 11), TO_UNSIGNED( 277, 11), TO_UNSIGNED( 324, 11),
TO_UNSIGNED( 770, 11), TO_UNSIGNED(1197, 11), TO_UNSIGNED(1550, 11), TO_UNSIGNED(1620, 11), TO_UNSIGNED( 279, 11), TO_UNSIGNED( 326, 11), TO_UNSIGNED( 776, 11), TO_UNSIGNED(1200, 11),
TO_UNSIGNED(1532, 11), TO_UNSIGNED(1623, 11), TO_UNSIGNED( 281, 11), TO_UNSIGNED( 328, 11), TO_UNSIGNED( 782, 11), TO_UNSIGNED(1203, 11), TO_UNSIGNED(1538, 11), TO_UNSIGNED(1626, 11),
TO_UNSIGNED( 330, 11), TO_UNSIGNED( 378, 11), TO_UNSIGNED( 705, 11), TO_UNSIGNED( 885, 11), TO_UNSIGNED(1605, 11), TO_UNSIGNED(1669, 11), TO_UNSIGNED( 332, 11), TO_UNSIGNED( 380, 11),
TO_UNSIGNED( 711, 11), TO_UNSIGNED( 888, 11), TO_UNSIGNED(1593, 11), TO_UNSIGNED(1675, 11), TO_UNSIGNED( 3, 11), TO_UNSIGNED( 334, 11), TO_UNSIGNED( 382, 11), TO_UNSIGNED( 717, 11),
TO_UNSIGNED( 891, 11), TO_UNSIGNED(1678, 11), TO_UNSIGNED( 336, 11), TO_UNSIGNED( 384, 11), TO_UNSIGNED( 723, 11), TO_UNSIGNED( 894, 11), TO_UNSIGNED(1479, 11), TO_UNSIGNED(1681, 11),
TO_UNSIGNED( 338, 11), TO_UNSIGNED( 386, 11), TO_UNSIGNED( 729, 11), TO_UNSIGNED( 897, 11), TO_UNSIGNED(1467, 11), TO_UNSIGNED(1483, 11), TO_UNSIGNED( 340, 11), TO_UNSIGNED( 388, 11),
TO_UNSIGNED( 735, 11), TO_UNSIGNED( 900, 11), TO_UNSIGNED(1473, 11), TO_UNSIGNED(1609, 11), TO_UNSIGNED( 342, 11), TO_UNSIGNED( 390, 11), TO_UNSIGNED( 741, 11), TO_UNSIGNED( 903, 11),
TO_UNSIGNED(1497, 11), TO_UNSIGNED(1612, 11), TO_UNSIGNED( 344, 11), TO_UNSIGNED( 392, 11), TO_UNSIGNED( 747, 11), TO_UNSIGNED( 834, 11), TO_UNSIGNED(1503, 11), TO_UNSIGNED(1621, 11),
TO_UNSIGNED( 346, 11), TO_UNSIGNED( 394, 11), TO_UNSIGNED( 753, 11), TO_UNSIGNED( 837, 11), TO_UNSIGNED(1509, 11), TO_UNSIGNED(1624, 11), TO_UNSIGNED( 348, 11), TO_UNSIGNED( 396, 11),
TO_UNSIGNED( 759, 11), TO_UNSIGNED( 840, 11), TO_UNSIGNED(1491, 11), TO_UNSIGNED(1627, 11), TO_UNSIGNED( 350, 11), TO_UNSIGNED( 398, 11), TO_UNSIGNED( 765, 11), TO_UNSIGNED( 843, 11),
TO_UNSIGNED(1515, 11), TO_UNSIGNED(1636, 11), TO_UNSIGNED( 352, 11), TO_UNSIGNED( 400, 11), TO_UNSIGNED( 771, 11), TO_UNSIGNED( 846, 11), TO_UNSIGNED(1527, 11), TO_UNSIGNED(1630, 11),
TO_UNSIGNED( 354, 11), TO_UNSIGNED( 402, 11), TO_UNSIGNED( 777, 11), TO_UNSIGNED( 849, 11), TO_UNSIGNED(1521, 11), TO_UNSIGNED(1633, 11), TO_UNSIGNED( 356, 11), TO_UNSIGNED( 404, 11),
TO_UNSIGNED( 783, 11), TO_UNSIGNED( 852, 11), TO_UNSIGNED(1545, 11), TO_UNSIGNED(1642, 11), TO_UNSIGNED( 358, 11), TO_UNSIGNED( 406, 11), TO_UNSIGNED( 789, 11), TO_UNSIGNED( 855, 11),
TO_UNSIGNED(1551, 11), TO_UNSIGNED(1639, 11), TO_UNSIGNED( 360, 11), TO_UNSIGNED( 408, 11), TO_UNSIGNED( 795, 11), TO_UNSIGNED( 858, 11), TO_UNSIGNED(1533, 11), TO_UNSIGNED(1645, 11),
TO_UNSIGNED( 362, 11), TO_UNSIGNED( 410, 11), TO_UNSIGNED( 801, 11), TO_UNSIGNED( 861, 11), TO_UNSIGNED(1539, 11), TO_UNSIGNED(1651, 11), TO_UNSIGNED( 364, 11), TO_UNSIGNED( 412, 11),
TO_UNSIGNED( 807, 11), TO_UNSIGNED( 864, 11), TO_UNSIGNED(1557, 11), TO_UNSIGNED(1648, 11), TO_UNSIGNED( 366, 11), TO_UNSIGNED( 414, 11), TO_UNSIGNED( 813, 11), TO_UNSIGNED( 867, 11),
TO_UNSIGNED(1563, 11), TO_UNSIGNED(1654, 11), TO_UNSIGNED( 368, 11), TO_UNSIGNED( 416, 11), TO_UNSIGNED( 819, 11), TO_UNSIGNED( 870, 11), TO_UNSIGNED(1575, 11), TO_UNSIGNED(1657, 11),
TO_UNSIGNED( 370, 11), TO_UNSIGNED( 418, 11), TO_UNSIGNED( 825, 11), TO_UNSIGNED( 873, 11), TO_UNSIGNED(1569, 11), TO_UNSIGNED(1660, 11), TO_UNSIGNED( 372, 11), TO_UNSIGNED( 420, 11),
TO_UNSIGNED( 831, 11), TO_UNSIGNED( 876, 11), TO_UNSIGNED(1587, 11), TO_UNSIGNED(1663, 11), TO_UNSIGNED( 374, 11), TO_UNSIGNED( 422, 11), TO_UNSIGNED( 693, 11), TO_UNSIGNED( 879, 11),
TO_UNSIGNED(1581, 11), TO_UNSIGNED(1666, 11), TO_UNSIGNED( 376, 11), TO_UNSIGNED( 424, 11), TO_UNSIGNED( 699, 11), TO_UNSIGNED( 882, 11), TO_UNSIGNED(1599, 11), TO_UNSIGNED(1672, 11),
TO_UNSIGNED( 379, 11), TO_UNSIGNED( 426, 11), TO_UNSIGNED( 682, 11), TO_UNSIGNED( 736, 11), TO_UNSIGNED(1198, 11), TO_UNSIGNED(1540, 11), TO_UNSIGNED( 381, 11), TO_UNSIGNED( 428, 11),
TO_UNSIGNED( 685, 11), TO_UNSIGNED( 742, 11), TO_UNSIGNED(1201, 11), TO_UNSIGNED(1558, 11), TO_UNSIGNED( 383, 11), TO_UNSIGNED( 430, 11), TO_UNSIGNED( 688, 11), TO_UNSIGNED( 748, 11),
TO_UNSIGNED(1204, 11), TO_UNSIGNED(1564, 11), TO_UNSIGNED( 385, 11), TO_UNSIGNED( 432, 11), TO_UNSIGNED( 619, 11), TO_UNSIGNED( 754, 11), TO_UNSIGNED(1207, 11), TO_UNSIGNED(1576, 11),
TO_UNSIGNED( 387, 11), TO_UNSIGNED( 434, 11), TO_UNSIGNED( 622, 11), TO_UNSIGNED( 760, 11), TO_UNSIGNED(1210, 11), TO_UNSIGNED(1570, 11), TO_UNSIGNED( 389, 11), TO_UNSIGNED( 436, 11),
TO_UNSIGNED( 625, 11), TO_UNSIGNED( 766, 11), TO_UNSIGNED(1195, 11), TO_UNSIGNED(1588, 11), TO_UNSIGNED( 391, 11), TO_UNSIGNED( 438, 11), TO_UNSIGNED( 628, 11), TO_UNSIGNED( 772, 11),
TO_UNSIGNED(1216, 11), TO_UNSIGNED(1582, 11), TO_UNSIGNED( 393, 11), TO_UNSIGNED( 440, 11), TO_UNSIGNED( 631, 11), TO_UNSIGNED( 778, 11), TO_UNSIGNED(1213, 11), TO_UNSIGNED(1600, 11),
TO_UNSIGNED( 395, 11), TO_UNSIGNED( 442, 11), TO_UNSIGNED( 634, 11), TO_UNSIGNED( 784, 11), TO_UNSIGNED(1222, 11), TO_UNSIGNED(1606, 11), TO_UNSIGNED( 397, 11), TO_UNSIGNED( 444, 11),
TO_UNSIGNED( 637, 11), TO_UNSIGNED( 790, 11), TO_UNSIGNED(1225, 11), TO_UNSIGNED(1594, 11), TO_UNSIGNED( 4, 11), TO_UNSIGNED( 399, 11), TO_UNSIGNED( 446, 11), TO_UNSIGNED( 640, 11),
TO_UNSIGNED( 796, 11), TO_UNSIGNED(1228, 11), TO_UNSIGNED( 401, 11), TO_UNSIGNED( 448, 11), TO_UNSIGNED( 643, 11), TO_UNSIGNED( 802, 11), TO_UNSIGNED(1219, 11), TO_UNSIGNED(1480, 11),
TO_UNSIGNED( 403, 11), TO_UNSIGNED( 450, 11), TO_UNSIGNED( 646, 11), TO_UNSIGNED( 808, 11), TO_UNSIGNED(1234, 11), TO_UNSIGNED(1468, 11), TO_UNSIGNED( 405, 11), TO_UNSIGNED( 452, 11),
TO_UNSIGNED( 649, 11), TO_UNSIGNED( 814, 11), TO_UNSIGNED(1237, 11), TO_UNSIGNED(1474, 11), TO_UNSIGNED( 407, 11), TO_UNSIGNED( 454, 11), TO_UNSIGNED( 652, 11), TO_UNSIGNED( 820, 11),
TO_UNSIGNED(1240, 11), TO_UNSIGNED(1498, 11), TO_UNSIGNED( 409, 11), TO_UNSIGNED( 456, 11), TO_UNSIGNED( 655, 11), TO_UNSIGNED( 826, 11), TO_UNSIGNED(1231, 11), TO_UNSIGNED(1504, 11),
TO_UNSIGNED( 411, 11), TO_UNSIGNED( 458, 11), TO_UNSIGNED( 658, 11), TO_UNSIGNED( 832, 11), TO_UNSIGNED(1252, 11), TO_UNSIGNED(1510, 11), TO_UNSIGNED( 413, 11), TO_UNSIGNED( 460, 11),
TO_UNSIGNED( 661, 11), TO_UNSIGNED( 694, 11), TO_UNSIGNED(1243, 11), TO_UNSIGNED(1492, 11), TO_UNSIGNED( 415, 11), TO_UNSIGNED( 462, 11), TO_UNSIGNED( 664, 11), TO_UNSIGNED( 700, 11),
TO_UNSIGNED(1246, 11), TO_UNSIGNED(1516, 11), TO_UNSIGNED( 417, 11), TO_UNSIGNED( 464, 11), TO_UNSIGNED( 667, 11), TO_UNSIGNED( 706, 11), TO_UNSIGNED(1249, 11), TO_UNSIGNED(1528, 11),
TO_UNSIGNED( 419, 11), TO_UNSIGNED( 466, 11), TO_UNSIGNED( 670, 11), TO_UNSIGNED( 712, 11), TO_UNSIGNED(1258, 11), TO_UNSIGNED(1522, 11), TO_UNSIGNED( 421, 11), TO_UNSIGNED( 468, 11),
TO_UNSIGNED( 673, 11), TO_UNSIGNED( 718, 11), TO_UNSIGNED(1255, 11), TO_UNSIGNED(1546, 11), TO_UNSIGNED( 423, 11), TO_UNSIGNED( 470, 11), TO_UNSIGNED( 676, 11), TO_UNSIGNED( 724, 11),
TO_UNSIGNED(1264, 11), TO_UNSIGNED(1552, 11), TO_UNSIGNED( 425, 11), TO_UNSIGNED( 472, 11), TO_UNSIGNED( 679, 11), TO_UNSIGNED( 730, 11), TO_UNSIGNED(1261, 11), TO_UNSIGNED(1534, 11),
TO_UNSIGNED( 474, 11), TO_UNSIGNED( 522, 11), TO_UNSIGNED(1062, 11), TO_UNSIGNED(1332, 11), TO_UNSIGNED(1631, 11), TO_UNSIGNED(1729, 11), TO_UNSIGNED( 476, 11), TO_UNSIGNED( 524, 11),
TO_UNSIGNED(1068, 11), TO_UNSIGNED(1326, 11), TO_UNSIGNED(1634, 11), TO_UNSIGNED(1723, 11), TO_UNSIGNED( 478, 11), TO_UNSIGNED( 526, 11), TO_UNSIGNED(1074, 11), TO_UNSIGNED(1350, 11),
TO_UNSIGNED(1643, 11), TO_UNSIGNED(1735, 11), TO_UNSIGNED( 480, 11), TO_UNSIGNED( 528, 11), TO_UNSIGNED(1080, 11), TO_UNSIGNED(1356, 11), TO_UNSIGNED(1640, 11), TO_UNSIGNED(1771, 11),
TO_UNSIGNED( 482, 11), TO_UNSIGNED( 530, 11), TO_UNSIGNED(1086, 11), TO_UNSIGNED(1338, 11), TO_UNSIGNED(1646, 11), TO_UNSIGNED(1777, 11), TO_UNSIGNED( 484, 11), TO_UNSIGNED( 532, 11),
TO_UNSIGNED(1092, 11), TO_UNSIGNED(1344, 11), TO_UNSIGNED(1652, 11), TO_UNSIGNED(1741, 11), TO_UNSIGNED( 486, 11), TO_UNSIGNED( 534, 11), TO_UNSIGNED(1098, 11), TO_UNSIGNED(1368, 11),
TO_UNSIGNED(1649, 11), TO_UNSIGNED(1747, 11), TO_UNSIGNED( 488, 11), TO_UNSIGNED( 536, 11), TO_UNSIGNED(1104, 11), TO_UNSIGNED(1374, 11), TO_UNSIGNED(1655, 11), TO_UNSIGNED(1753, 11),
TO_UNSIGNED( 490, 11), TO_UNSIGNED( 538, 11), TO_UNSIGNED(1110, 11), TO_UNSIGNED(1362, 11), TO_UNSIGNED(1658, 11), TO_UNSIGNED(1759, 11), TO_UNSIGNED( 492, 11), TO_UNSIGNED( 540, 11),
TO_UNSIGNED(1116, 11), TO_UNSIGNED(1392, 11), TO_UNSIGNED(1661, 11), TO_UNSIGNED(1765, 11), TO_UNSIGNED( 494, 11), TO_UNSIGNED( 542, 11), TO_UNSIGNED( 978, 11), TO_UNSIGNED(1380, 11),
TO_UNSIGNED(1664, 11), TO_UNSIGNED(1801, 11), TO_UNSIGNED( 496, 11), TO_UNSIGNED( 544, 11), TO_UNSIGNED( 984, 11), TO_UNSIGNED(1386, 11), TO_UNSIGNED(1667, 11), TO_UNSIGNED(1789, 11),
TO_UNSIGNED( 130, 11), TO_UNSIGNED( 498, 11), TO_UNSIGNED( 546, 11), TO_UNSIGNED( 990, 11), TO_UNSIGNED(1673, 11), TO_UNSIGNED(1795, 11), TO_UNSIGNED( 78, 11), TO_UNSIGNED( 500, 11),
TO_UNSIGNED( 548, 11), TO_UNSIGNED( 996, 11), TO_UNSIGNED(1670, 11), TO_UNSIGNED(1807, 11), TO_UNSIGNED( 502, 11), TO_UNSIGNED( 550, 11), TO_UNSIGNED(1002, 11), TO_UNSIGNED(1272, 11),
TO_UNSIGNED(1676, 11), TO_UNSIGNED(1783, 11), TO_UNSIGNED( 6, 11), TO_UNSIGNED( 504, 11), TO_UNSIGNED( 552, 11), TO_UNSIGNED(1008, 11), TO_UNSIGNED(1278, 11), TO_UNSIGNED(1679, 11),
TO_UNSIGNED( 506, 11), TO_UNSIGNED( 554, 11), TO_UNSIGNED(1014, 11), TO_UNSIGNED(1284, 11), TO_UNSIGNED(1682, 11), TO_UNSIGNED(1813, 11), TO_UNSIGNED( 136, 11), TO_UNSIGNED( 508, 11),
TO_UNSIGNED( 556, 11), TO_UNSIGNED(1020, 11), TO_UNSIGNED(1266, 11), TO_UNSIGNED(1484, 11), TO_UNSIGNED( 510, 11), TO_UNSIGNED( 558, 11), TO_UNSIGNED(1026, 11), TO_UNSIGNED(1296, 11),
TO_UNSIGNED(1610, 11), TO_UNSIGNED(1687, 11), TO_UNSIGNED( 512, 11), TO_UNSIGNED( 560, 11), TO_UNSIGNED(1032, 11), TO_UNSIGNED(1290, 11), TO_UNSIGNED(1613, 11), TO_UNSIGNED(1711, 11),
TO_UNSIGNED( 514, 11), TO_UNSIGNED( 562, 11), TO_UNSIGNED(1038, 11), TO_UNSIGNED(1308, 11), TO_UNSIGNED(1622, 11), TO_UNSIGNED(1699, 11), TO_UNSIGNED( 516, 11), TO_UNSIGNED( 564, 11),
TO_UNSIGNED(1044, 11), TO_UNSIGNED(1302, 11), TO_UNSIGNED(1625, 11), TO_UNSIGNED(1705, 11), TO_UNSIGNED( 518, 11), TO_UNSIGNED( 566, 11), TO_UNSIGNED(1050, 11), TO_UNSIGNED(1314, 11),
TO_UNSIGNED(1628, 11), TO_UNSIGNED(1693, 11), TO_UNSIGNED( 520, 11), TO_UNSIGNED( 568, 11), TO_UNSIGNED(1056, 11), TO_UNSIGNED(1320, 11), TO_UNSIGNED(1637, 11), TO_UNSIGNED(1717, 11),
TO_UNSIGNED( 523, 11), TO_UNSIGNED( 570, 11), TO_UNSIGNED( 695, 11), TO_UNSIGNED( 877, 11), TO_UNSIGNED(1445, 11), TO_UNSIGNED(1535, 11), TO_UNSIGNED( 525, 11), TO_UNSIGNED( 572, 11),
TO_UNSIGNED( 701, 11), TO_UNSIGNED( 880, 11), TO_UNSIGNED(1448, 11), TO_UNSIGNED(1541, 11), TO_UNSIGNED( 527, 11), TO_UNSIGNED( 574, 11), TO_UNSIGNED( 707, 11), TO_UNSIGNED( 883, 11),
TO_UNSIGNED(1451, 11), TO_UNSIGNED(1559, 11), TO_UNSIGNED( 529, 11), TO_UNSIGNED( 576, 11), TO_UNSIGNED( 713, 11), TO_UNSIGNED( 886, 11), TO_UNSIGNED(1454, 11), TO_UNSIGNED(1565, 11),
TO_UNSIGNED( 531, 11), TO_UNSIGNED( 578, 11), TO_UNSIGNED( 719, 11), TO_UNSIGNED( 889, 11), TO_UNSIGNED(1457, 11), TO_UNSIGNED(1577, 11), TO_UNSIGNED( 533, 11), TO_UNSIGNED( 580, 11),
TO_UNSIGNED( 725, 11), TO_UNSIGNED( 892, 11), TO_UNSIGNED(1463, 11), TO_UNSIGNED(1571, 11), TO_UNSIGNED( 535, 11), TO_UNSIGNED( 582, 11), TO_UNSIGNED( 731, 11), TO_UNSIGNED( 895, 11),
TO_UNSIGNED(1460, 11), TO_UNSIGNED(1589, 11), TO_UNSIGNED( 537, 11), TO_UNSIGNED( 584, 11), TO_UNSIGNED( 737, 11), TO_UNSIGNED( 898, 11), TO_UNSIGNED(1487, 11), TO_UNSIGNED(1583, 11),
TO_UNSIGNED( 539, 11), TO_UNSIGNED( 586, 11), TO_UNSIGNED( 743, 11), TO_UNSIGNED( 901, 11), TO_UNSIGNED(1601, 11), TO_UNSIGNED(1619, 11), TO_UNSIGNED( 541, 11), TO_UNSIGNED( 588, 11),
TO_UNSIGNED( 749, 11), TO_UNSIGNED( 904, 11), TO_UNSIGNED(1400, 11), TO_UNSIGNED(1607, 11), TO_UNSIGNED( 543, 11), TO_UNSIGNED( 590, 11), TO_UNSIGNED( 755, 11), TO_UNSIGNED( 835, 11),
TO_UNSIGNED(1403, 11), TO_UNSIGNED(1595, 11), TO_UNSIGNED( 5, 11), TO_UNSIGNED( 545, 11), TO_UNSIGNED( 592, 11), TO_UNSIGNED( 761, 11), TO_UNSIGNED( 838, 11), TO_UNSIGNED(1406, 11),
TO_UNSIGNED( 547, 11), TO_UNSIGNED( 594, 11), TO_UNSIGNED( 767, 11), TO_UNSIGNED( 841, 11), TO_UNSIGNED(1415, 11), TO_UNSIGNED(1481, 11), TO_UNSIGNED( 549, 11), TO_UNSIGNED( 596, 11),
TO_UNSIGNED( 773, 11), TO_UNSIGNED( 844, 11), TO_UNSIGNED(1418, 11), TO_UNSIGNED(1469, 11), TO_UNSIGNED( 551, 11), TO_UNSIGNED( 598, 11), TO_UNSIGNED( 779, 11), TO_UNSIGNED( 847, 11),
TO_UNSIGNED(1421, 11), TO_UNSIGNED(1475, 11), TO_UNSIGNED( 553, 11), TO_UNSIGNED( 600, 11), TO_UNSIGNED( 785, 11), TO_UNSIGNED( 850, 11), TO_UNSIGNED(1409, 11), TO_UNSIGNED(1499, 11),
TO_UNSIGNED( 555, 11), TO_UNSIGNED( 602, 11), TO_UNSIGNED( 791, 11), TO_UNSIGNED( 853, 11), TO_UNSIGNED(1412, 11), TO_UNSIGNED(1505, 11), TO_UNSIGNED( 557, 11), TO_UNSIGNED( 604, 11),
TO_UNSIGNED( 797, 11), TO_UNSIGNED( 856, 11), TO_UNSIGNED(1436, 11), TO_UNSIGNED(1511, 11), TO_UNSIGNED( 559, 11), TO_UNSIGNED( 606, 11), TO_UNSIGNED( 803, 11), TO_UNSIGNED( 859, 11),
TO_UNSIGNED(1433, 11), TO_UNSIGNED(1493, 11), TO_UNSIGNED( 561, 11), TO_UNSIGNED( 608, 11), TO_UNSIGNED( 809, 11), TO_UNSIGNED( 862, 11), TO_UNSIGNED(1424, 11), TO_UNSIGNED(1517, 11),
TO_UNSIGNED( 563, 11), TO_UNSIGNED( 610, 11), TO_UNSIGNED( 815, 11), TO_UNSIGNED( 865, 11), TO_UNSIGNED(1427, 11), TO_UNSIGNED(1529, 11), TO_UNSIGNED( 565, 11), TO_UNSIGNED( 612, 11),
TO_UNSIGNED( 821, 11), TO_UNSIGNED( 868, 11), TO_UNSIGNED(1430, 11), TO_UNSIGNED(1523, 11), TO_UNSIGNED( 567, 11), TO_UNSIGNED( 614, 11), TO_UNSIGNED( 827, 11), TO_UNSIGNED( 871, 11),
TO_UNSIGNED(1439, 11), TO_UNSIGNED(1547, 11), TO_UNSIGNED( 569, 11), TO_UNSIGNED( 616, 11), TO_UNSIGNED( 833, 11), TO_UNSIGNED( 874, 11), TO_UNSIGNED(1442, 11), TO_UNSIGNED(1553, 11),
TO_UNSIGNED( 76, 11), TO_UNSIGNED( 571, 11), TO_UNSIGNED( 922, 11), TO_UNSIGNED(1105, 11), TO_UNSIGNED(1339, 11), TO_UNSIGNED(1796, 11), TO_UNSIGNED( 573, 11), TO_UNSIGNED( 925, 11),
TO_UNSIGNED(1111, 11), TO_UNSIGNED(1345, 11), TO_UNSIGNED(1615, 11), TO_UNSIGNED(1808, 11), TO_UNSIGNED( 575, 11), TO_UNSIGNED( 928, 11), TO_UNSIGNED(1117, 11), TO_UNSIGNED(1369, 11),
TO_UNSIGNED(1784, 11), TO_UNSIGNED(1820, 11), TO_UNSIGNED( 7, 11), TO_UNSIGNED( 13, 11), TO_UNSIGNED( 577, 11), TO_UNSIGNED( 931, 11), TO_UNSIGNED( 979, 11), TO_UNSIGNED(1375, 11),
TO_UNSIGNED( 16, 11), TO_UNSIGNED( 579, 11), TO_UNSIGNED( 934, 11), TO_UNSIGNED( 985, 11), TO_UNSIGNED(1363, 11), TO_UNSIGNED(1814, 11), TO_UNSIGNED( 19, 11), TO_UNSIGNED( 137, 11),
TO_UNSIGNED( 581, 11), TO_UNSIGNED( 937, 11), TO_UNSIGNED( 991, 11), TO_UNSIGNED(1393, 11), TO_UNSIGNED( 22, 11), TO_UNSIGNED( 583, 11), TO_UNSIGNED( 940, 11), TO_UNSIGNED( 997, 11),
TO_UNSIGNED(1381, 11), TO_UNSIGNED(1688, 11), TO_UNSIGNED( 25, 11), TO_UNSIGNED( 585, 11), TO_UNSIGNED( 943, 11), TO_UNSIGNED(1003, 11), TO_UNSIGNED(1387, 11), TO_UNSIGNED(1712, 11),
TO_UNSIGNED( 28, 11), TO_UNSIGNED( 131, 11), TO_UNSIGNED( 587, 11), TO_UNSIGNED( 946, 11), TO_UNSIGNED(1009, 11), TO_UNSIGNED(1700, 11), TO_UNSIGNED( 31, 11), TO_UNSIGNED( 79, 11),
TO_UNSIGNED( 589, 11), TO_UNSIGNED( 949, 11), TO_UNSIGNED(1015, 11), TO_UNSIGNED(1706, 11), TO_UNSIGNED( 34, 11), TO_UNSIGNED( 591, 11), TO_UNSIGNED( 952, 11), TO_UNSIGNED(1021, 11),
TO_UNSIGNED(1273, 11), TO_UNSIGNED(1694, 11), TO_UNSIGNED( 37, 11), TO_UNSIGNED( 593, 11), TO_UNSIGNED( 955, 11), TO_UNSIGNED(1027, 11), TO_UNSIGNED(1279, 11), TO_UNSIGNED(1718, 11),
TO_UNSIGNED( 40, 11), TO_UNSIGNED( 595, 11), TO_UNSIGNED( 958, 11), TO_UNSIGNED(1033, 11), TO_UNSIGNED(1285, 11), TO_UNSIGNED(1730, 11), TO_UNSIGNED( 43, 11), TO_UNSIGNED( 597, 11),
TO_UNSIGNED( 961, 11), TO_UNSIGNED(1039, 11), TO_UNSIGNED(1267, 11), TO_UNSIGNED(1724, 11), TO_UNSIGNED( 46, 11), TO_UNSIGNED( 599, 11), TO_UNSIGNED( 964, 11), TO_UNSIGNED(1045, 11),
TO_UNSIGNED(1297, 11), TO_UNSIGNED(1736, 11), TO_UNSIGNED( 49, 11), TO_UNSIGNED( 601, 11), TO_UNSIGNED( 967, 11), TO_UNSIGNED(1051, 11), TO_UNSIGNED(1291, 11), TO_UNSIGNED(1772, 11),
TO_UNSIGNED( 52, 11), TO_UNSIGNED( 603, 11), TO_UNSIGNED( 970, 11), TO_UNSIGNED(1057, 11), TO_UNSIGNED(1309, 11), TO_UNSIGNED(1778, 11), TO_UNSIGNED( 55, 11), TO_UNSIGNED( 605, 11),
TO_UNSIGNED( 973, 11), TO_UNSIGNED(1063, 11), TO_UNSIGNED(1303, 11), TO_UNSIGNED(1742, 11), TO_UNSIGNED( 58, 11), TO_UNSIGNED( 607, 11), TO_UNSIGNED( 976, 11), TO_UNSIGNED(1069, 11),
TO_UNSIGNED(1315, 11), TO_UNSIGNED(1748, 11), TO_UNSIGNED( 61, 11), TO_UNSIGNED( 609, 11), TO_UNSIGNED( 907, 11), TO_UNSIGNED(1075, 11), TO_UNSIGNED(1321, 11), TO_UNSIGNED(1754, 11),
TO_UNSIGNED( 64, 11), TO_UNSIGNED( 611, 11), TO_UNSIGNED( 910, 11), TO_UNSIGNED(1081, 11), TO_UNSIGNED(1333, 11), TO_UNSIGNED(1760, 11), TO_UNSIGNED( 67, 11), TO_UNSIGNED( 613, 11),
TO_UNSIGNED( 913, 11), TO_UNSIGNED(1087, 11), TO_UNSIGNED(1327, 11), TO_UNSIGNED(1766, 11), TO_UNSIGNED( 70, 11), TO_UNSIGNED( 615, 11), TO_UNSIGNED( 916, 11), TO_UNSIGNED(1093, 11),
TO_UNSIGNED(1351, 11), TO_UNSIGNED(1802, 11), TO_UNSIGNED( 73, 11), TO_UNSIGNED( 617, 11), TO_UNSIGNED( 919, 11), TO_UNSIGNED(1099, 11), TO_UNSIGNED(1357, 11), TO_UNSIGNED(1790, 11),
TO_UNSIGNED( 8, 11), TO_UNSIGNED( 132, 11), TO_UNSIGNED( 671, 11), TO_UNSIGNED(1028, 11), TO_UNSIGNED(1196, 11), TO_UNSIGNED(1684, 11), TO_UNSIGNED(1685, 11), TO_UNSIGNED( 80, 11),
TO_UNSIGNED( 85, 11), TO_UNSIGNED( 674, 11), TO_UNSIGNED(1034, 11), TO_UNSIGNED(1217, 11), TO_UNSIGNED(1815, 11), TO_UNSIGNED(1822, 11), TO_UNSIGNED( 87, 11), TO_UNSIGNED( 138, 11),
TO_UNSIGNED( 142, 11), TO_UNSIGNED( 677, 11), TO_UNSIGNED(1040, 11), TO_UNSIGNED(1214, 11), TO_UNSIGNED(1274, 11), TO_UNSIGNED( 89, 11), TO_UNSIGNED( 144, 11), TO_UNSIGNED( 680, 11),
TO_UNSIGNED(1046, 11), TO_UNSIGNED(1223, 11), TO_UNSIGNED(1280, 11), TO_UNSIGNED(1689, 11), TO_UNSIGNED( 91, 11), TO_UNSIGNED( 146, 11), TO_UNSIGNED( 683, 11), TO_UNSIGNED(1052, 11),
TO_UNSIGNED(1226, 11), TO_UNSIGNED(1286, 11), TO_UNSIGNED(1713, 11), TO_UNSIGNED( 93, 11), TO_UNSIGNED( 148, 11), TO_UNSIGNED( 686, 11), TO_UNSIGNED(1058, 11), TO_UNSIGNED(1229, 11),
TO_UNSIGNED(1268, 11), TO_UNSIGNED(1701, 11), TO_UNSIGNED( 95, 11), TO_UNSIGNED( 150, 11), TO_UNSIGNED( 689, 11), TO_UNSIGNED(1064, 11), TO_UNSIGNED(1220, 11), TO_UNSIGNED(1298, 11),
TO_UNSIGNED(1707, 11), TO_UNSIGNED( 97, 11), TO_UNSIGNED( 152, 11), TO_UNSIGNED( 620, 11), TO_UNSIGNED(1070, 11), TO_UNSIGNED(1235, 11), TO_UNSIGNED(1292, 11), TO_UNSIGNED(1695, 11),
TO_UNSIGNED( 99, 11), TO_UNSIGNED( 154, 11), TO_UNSIGNED( 623, 11), TO_UNSIGNED(1076, 11), TO_UNSIGNED(1238, 11), TO_UNSIGNED(1310, 11), TO_UNSIGNED(1719, 11), TO_UNSIGNED( 101, 11),
TO_UNSIGNED( 156, 11), TO_UNSIGNED( 626, 11), TO_UNSIGNED(1082, 11), TO_UNSIGNED(1241, 11), TO_UNSIGNED(1304, 11), TO_UNSIGNED(1731, 11), TO_UNSIGNED( 103, 11), TO_UNSIGNED( 158, 11),
TO_UNSIGNED( 629, 11), TO_UNSIGNED(1088, 11), TO_UNSIGNED(1232, 11), TO_UNSIGNED(1316, 11), TO_UNSIGNED(1725, 11), TO_UNSIGNED( 105, 11), TO_UNSIGNED( 160, 11), TO_UNSIGNED( 632, 11),
TO_UNSIGNED(1094, 11), TO_UNSIGNED(1253, 11), TO_UNSIGNED(1322, 11), TO_UNSIGNED(1737, 11), TO_UNSIGNED( 107, 11), TO_UNSIGNED( 162, 11), TO_UNSIGNED( 635, 11), TO_UNSIGNED(1100, 11),
TO_UNSIGNED(1244, 11), TO_UNSIGNED(1334, 11), TO_UNSIGNED(1773, 11), TO_UNSIGNED( 109, 11), TO_UNSIGNED( 164, 11), TO_UNSIGNED( 638, 11), TO_UNSIGNED(1106, 11), TO_UNSIGNED(1247, 11),
TO_UNSIGNED(1328, 11), TO_UNSIGNED(1779, 11), TO_UNSIGNED( 111, 11), TO_UNSIGNED( 166, 11), TO_UNSIGNED( 641, 11), TO_UNSIGNED(1112, 11), TO_UNSIGNED(1250, 11), TO_UNSIGNED(1352, 11),
TO_UNSIGNED(1743, 11), TO_UNSIGNED( 113, 11), TO_UNSIGNED( 168, 11), TO_UNSIGNED( 644, 11), TO_UNSIGNED(1118, 11), TO_UNSIGNED(1259, 11), TO_UNSIGNED(1358, 11), TO_UNSIGNED(1749, 11),
TO_UNSIGNED( 115, 11), TO_UNSIGNED( 170, 11), TO_UNSIGNED( 647, 11), TO_UNSIGNED( 980, 11), TO_UNSIGNED(1256, 11), TO_UNSIGNED(1340, 11), TO_UNSIGNED(1755, 11), TO_UNSIGNED( 117, 11),
TO_UNSIGNED( 172, 11), TO_UNSIGNED( 650, 11), TO_UNSIGNED( 986, 11), TO_UNSIGNED(1265, 11), TO_UNSIGNED(1346, 11), TO_UNSIGNED(1761, 11), TO_UNSIGNED( 119, 11), TO_UNSIGNED( 174, 11),
TO_UNSIGNED( 653, 11), TO_UNSIGNED( 992, 11), TO_UNSIGNED(1262, 11), TO_UNSIGNED(1370, 11), TO_UNSIGNED(1767, 11), TO_UNSIGNED( 121, 11), TO_UNSIGNED( 176, 11), TO_UNSIGNED( 656, 11),
TO_UNSIGNED( 998, 11), TO_UNSIGNED(1199, 11), TO_UNSIGNED(1376, 11), TO_UNSIGNED(1803, 11), TO_UNSIGNED( 123, 11), TO_UNSIGNED( 178, 11), TO_UNSIGNED( 659, 11), TO_UNSIGNED(1004, 11),
TO_UNSIGNED(1202, 11), TO_UNSIGNED(1364, 11), TO_UNSIGNED(1791, 11), TO_UNSIGNED( 125, 11), TO_UNSIGNED( 180, 11), TO_UNSIGNED( 662, 11), TO_UNSIGNED(1010, 11), TO_UNSIGNED(1205, 11),
TO_UNSIGNED(1394, 11), TO_UNSIGNED(1797, 11), TO_UNSIGNED( 127, 11), TO_UNSIGNED( 182, 11), TO_UNSIGNED( 665, 11), TO_UNSIGNED(1016, 11), TO_UNSIGNED(1208, 11), TO_UNSIGNED(1382, 11),
TO_UNSIGNED(1809, 11), TO_UNSIGNED( 129, 11), TO_UNSIGNED( 184, 11), TO_UNSIGNED( 668, 11), TO_UNSIGNED(1022, 11), TO_UNSIGNED(1211, 11), TO_UNSIGNED(1388, 11), TO_UNSIGNED(1785, 11),
TO_UNSIGNED( 187, 11), TO_UNSIGNED( 836, 11), TO_UNSIGNED(1083, 11), TO_UNSIGNED(1140, 11), TO_UNSIGNED(1371, 11), TO_UNSIGNED(1686, 11), TO_UNSIGNED(1690, 11), TO_UNSIGNED( 189, 11),
TO_UNSIGNED( 839, 11), TO_UNSIGNED(1089, 11), TO_UNSIGNED(1143, 11), TO_UNSIGNED(1377, 11), TO_UNSIGNED(1714, 11), TO_UNSIGNED(1823, 11), TO_UNSIGNED( 143, 11), TO_UNSIGNED( 191, 11),
TO_UNSIGNED( 842, 11), TO_UNSIGNED(1095, 11), TO_UNSIGNED(1146, 11), TO_UNSIGNED(1365, 11), TO_UNSIGNED(1702, 11), TO_UNSIGNED( 145, 11), TO_UNSIGNED( 193, 11), TO_UNSIGNED( 845, 11),
TO_UNSIGNED(1101, 11), TO_UNSIGNED(1149, 11), TO_UNSIGNED(1395, 11), TO_UNSIGNED(1708, 11), TO_UNSIGNED( 147, 11), TO_UNSIGNED( 195, 11), TO_UNSIGNED( 848, 11), TO_UNSIGNED(1107, 11),
TO_UNSIGNED(1152, 11), TO_UNSIGNED(1383, 11), TO_UNSIGNED(1696, 11), TO_UNSIGNED( 149, 11), TO_UNSIGNED( 197, 11), TO_UNSIGNED( 851, 11), TO_UNSIGNED(1113, 11), TO_UNSIGNED(1155, 11),
TO_UNSIGNED(1389, 11), TO_UNSIGNED(1720, 11), TO_UNSIGNED( 133, 11), TO_UNSIGNED( 151, 11), TO_UNSIGNED( 199, 11), TO_UNSIGNED( 854, 11), TO_UNSIGNED(1119, 11), TO_UNSIGNED(1158, 11),
TO_UNSIGNED(1732, 11), TO_UNSIGNED( 81, 11), TO_UNSIGNED( 153, 11), TO_UNSIGNED( 201, 11), TO_UNSIGNED( 857, 11), TO_UNSIGNED( 981, 11), TO_UNSIGNED(1161, 11), TO_UNSIGNED(1726, 11),
TO_UNSIGNED( 155, 11), TO_UNSIGNED( 203, 11), TO_UNSIGNED( 860, 11), TO_UNSIGNED( 987, 11), TO_UNSIGNED(1164, 11), TO_UNSIGNED(1275, 11), TO_UNSIGNED(1738, 11), TO_UNSIGNED( 157, 11),
TO_UNSIGNED( 205, 11), TO_UNSIGNED( 863, 11), TO_UNSIGNED( 993, 11), TO_UNSIGNED(1167, 11), TO_UNSIGNED(1281, 11), TO_UNSIGNED(1774, 11), TO_UNSIGNED( 159, 11), TO_UNSIGNED( 207, 11),
TO_UNSIGNED( 866, 11), TO_UNSIGNED( 999, 11), TO_UNSIGNED(1170, 11), TO_UNSIGNED(1287, 11), TO_UNSIGNED(1780, 11), TO_UNSIGNED( 161, 11), TO_UNSIGNED( 209, 11), TO_UNSIGNED( 869, 11),
TO_UNSIGNED(1005, 11), TO_UNSIGNED(1173, 11), TO_UNSIGNED(1269, 11), TO_UNSIGNED(1744, 11), TO_UNSIGNED( 163, 11), TO_UNSIGNED( 211, 11), TO_UNSIGNED( 872, 11), TO_UNSIGNED(1011, 11),
TO_UNSIGNED(1176, 11), TO_UNSIGNED(1299, 11), TO_UNSIGNED(1750, 11), TO_UNSIGNED( 165, 11), TO_UNSIGNED( 213, 11), TO_UNSIGNED( 875, 11), TO_UNSIGNED(1017, 11), TO_UNSIGNED(1179, 11),
TO_UNSIGNED(1293, 11), TO_UNSIGNED(1756, 11), TO_UNSIGNED( 167, 11), TO_UNSIGNED( 215, 11), TO_UNSIGNED( 878, 11), TO_UNSIGNED(1023, 11), TO_UNSIGNED(1182, 11), TO_UNSIGNED(1311, 11),
TO_UNSIGNED(1762, 11), TO_UNSIGNED( 169, 11), TO_UNSIGNED( 217, 11), TO_UNSIGNED( 881, 11), TO_UNSIGNED(1029, 11), TO_UNSIGNED(1185, 11), TO_UNSIGNED(1305, 11), TO_UNSIGNED(1768, 11),
TO_UNSIGNED( 171, 11), TO_UNSIGNED( 219, 11), TO_UNSIGNED( 884, 11), TO_UNSIGNED(1035, 11), TO_UNSIGNED(1188, 11), TO_UNSIGNED(1317, 11), TO_UNSIGNED(1804, 11), TO_UNSIGNED( 173, 11),
TO_UNSIGNED( 221, 11), TO_UNSIGNED( 887, 11), TO_UNSIGNED(1041, 11), TO_UNSIGNED(1191, 11), TO_UNSIGNED(1323, 11), TO_UNSIGNED(1792, 11), TO_UNSIGNED( 175, 11), TO_UNSIGNED( 223, 11),
TO_UNSIGNED( 890, 11), TO_UNSIGNED(1047, 11), TO_UNSIGNED(1122, 11), TO_UNSIGNED(1335, 11), TO_UNSIGNED(1798, 11), TO_UNSIGNED( 177, 11), TO_UNSIGNED( 225, 11), TO_UNSIGNED( 893, 11),
TO_UNSIGNED(1053, 11), TO_UNSIGNED(1125, 11), TO_UNSIGNED(1329, 11), TO_UNSIGNED(1810, 11), TO_UNSIGNED( 179, 11), TO_UNSIGNED( 227, 11), TO_UNSIGNED( 896, 11), TO_UNSIGNED(1059, 11),
TO_UNSIGNED(1128, 11), TO_UNSIGNED(1353, 11), TO_UNSIGNED(1786, 11), TO_UNSIGNED( 9, 11), TO_UNSIGNED( 181, 11), TO_UNSIGNED( 229, 11), TO_UNSIGNED( 899, 11), TO_UNSIGNED(1065, 11),
TO_UNSIGNED(1131, 11), TO_UNSIGNED(1359, 11), TO_UNSIGNED( 183, 11), TO_UNSIGNED( 231, 11), TO_UNSIGNED( 902, 11), TO_UNSIGNED(1071, 11), TO_UNSIGNED(1134, 11), TO_UNSIGNED(1341, 11),
TO_UNSIGNED(1816, 11), TO_UNSIGNED( 139, 11), TO_UNSIGNED( 185, 11), TO_UNSIGNED( 233, 11), TO_UNSIGNED( 905, 11), TO_UNSIGNED(1077, 11), TO_UNSIGNED(1137, 11), TO_UNSIGNED(1347, 11),
TO_UNSIGNED( 283, 11), TO_UNSIGNED( 331, 11), TO_UNSIGNED(1000, 11), TO_UNSIGNED(1123, 11), TO_UNSIGNED(1300, 11), TO_UNSIGNED(1616, 11), TO_UNSIGNED(1721, 11), TO_UNSIGNED( 285, 11),
TO_UNSIGNED( 333, 11), TO_UNSIGNED(1006, 11), TO_UNSIGNED(1126, 11), TO_UNSIGNED(1294, 11), TO_UNSIGNED(1733, 11), TO_UNSIGNED(1821, 11), TO_UNSIGNED( 14, 11), TO_UNSIGNED( 287, 11),
TO_UNSIGNED( 335, 11), TO_UNSIGNED(1012, 11), TO_UNSIGNED(1129, 11), TO_UNSIGNED(1312, 11), TO_UNSIGNED(1727, 11), TO_UNSIGNED( 17, 11), TO_UNSIGNED( 289, 11), TO_UNSIGNED( 337, 11),
TO_UNSIGNED(1018, 11), TO_UNSIGNED(1132, 11), TO_UNSIGNED(1306, 11), TO_UNSIGNED(1739, 11), TO_UNSIGNED( 20, 11), TO_UNSIGNED( 291, 11), TO_UNSIGNED( 339, 11), TO_UNSIGNED(1024, 11),
TO_UNSIGNED(1135, 11), TO_UNSIGNED(1318, 11), TO_UNSIGNED(1775, 11), TO_UNSIGNED( 23, 11), TO_UNSIGNED( 293, 11), TO_UNSIGNED( 341, 11), TO_UNSIGNED(1030, 11), TO_UNSIGNED(1138, 11),
TO_UNSIGNED(1324, 11), TO_UNSIGNED(1781, 11), TO_UNSIGNED( 26, 11), TO_UNSIGNED( 295, 11), TO_UNSIGNED( 343, 11), TO_UNSIGNED(1036, 11), TO_UNSIGNED(1141, 11), TO_UNSIGNED(1336, 11),
TO_UNSIGNED(1745, 11), TO_UNSIGNED( 29, 11), TO_UNSIGNED( 297, 11), TO_UNSIGNED( 345, 11), TO_UNSIGNED(1042, 11), TO_UNSIGNED(1144, 11), TO_UNSIGNED(1330, 11), TO_UNSIGNED(1751, 11),
TO_UNSIGNED( 32, 11), TO_UNSIGNED( 299, 11), TO_UNSIGNED( 347, 11), TO_UNSIGNED(1048, 11), TO_UNSIGNED(1147, 11), TO_UNSIGNED(1354, 11), TO_UNSIGNED(1757, 11), TO_UNSIGNED( 35, 11),
TO_UNSIGNED( 301, 11), TO_UNSIGNED( 349, 11), TO_UNSIGNED(1054, 11), TO_UNSIGNED(1150, 11), TO_UNSIGNED(1360, 11), TO_UNSIGNED(1763, 11), TO_UNSIGNED( 38, 11), TO_UNSIGNED( 303, 11),
TO_UNSIGNED( 351, 11), TO_UNSIGNED(1060, 11), TO_UNSIGNED(1153, 11), TO_UNSIGNED(1342, 11), TO_UNSIGNED(1769, 11), TO_UNSIGNED( 41, 11), TO_UNSIGNED( 305, 11), TO_UNSIGNED( 353, 11),
TO_UNSIGNED(1066, 11), TO_UNSIGNED(1156, 11), TO_UNSIGNED(1348, 11), TO_UNSIGNED(1805, 11), TO_UNSIGNED( 44, 11), TO_UNSIGNED( 307, 11), TO_UNSIGNED( 355, 11), TO_UNSIGNED(1072, 11),
TO_UNSIGNED(1159, 11), TO_UNSIGNED(1372, 11), TO_UNSIGNED(1793, 11), TO_UNSIGNED( 47, 11), TO_UNSIGNED( 309, 11), TO_UNSIGNED( 357, 11), TO_UNSIGNED(1078, 11), TO_UNSIGNED(1162, 11),
TO_UNSIGNED(1378, 11), TO_UNSIGNED(1799, 11), TO_UNSIGNED( 50, 11), TO_UNSIGNED( 311, 11), TO_UNSIGNED( 359, 11), TO_UNSIGNED(1084, 11), TO_UNSIGNED(1165, 11), TO_UNSIGNED(1366, 11),
TO_UNSIGNED(1811, 11), TO_UNSIGNED( 53, 11), TO_UNSIGNED( 313, 11), TO_UNSIGNED( 361, 11), TO_UNSIGNED(1090, 11), TO_UNSIGNED(1168, 11), TO_UNSIGNED(1396, 11), TO_UNSIGNED(1787, 11),
TO_UNSIGNED( 10, 11), TO_UNSIGNED( 56, 11), TO_UNSIGNED( 315, 11), TO_UNSIGNED( 363, 11), TO_UNSIGNED(1096, 11), TO_UNSIGNED(1171, 11), TO_UNSIGNED(1384, 11), TO_UNSIGNED( 59, 11),
TO_UNSIGNED( 317, 11), TO_UNSIGNED( 365, 11), TO_UNSIGNED(1102, 11), TO_UNSIGNED(1174, 11), TO_UNSIGNED(1390, 11), TO_UNSIGNED(1817, 11), TO_UNSIGNED( 62, 11), TO_UNSIGNED( 134, 11),
TO_UNSIGNED( 140, 11), TO_UNSIGNED( 319, 11), TO_UNSIGNED( 367, 11), TO_UNSIGNED(1108, 11), TO_UNSIGNED(1177, 11), TO_UNSIGNED( 65, 11), TO_UNSIGNED( 82, 11), TO_UNSIGNED( 321, 11),
TO_UNSIGNED( 369, 11), TO_UNSIGNED(1114, 11), TO_UNSIGNED(1180, 11), TO_UNSIGNED(1691, 11), TO_UNSIGNED( 68, 11), TO_UNSIGNED( 323, 11), TO_UNSIGNED( 371, 11), TO_UNSIGNED(1120, 11),
TO_UNSIGNED(1183, 11), TO_UNSIGNED(1276, 11), TO_UNSIGNED(1715, 11), TO_UNSIGNED( 71, 11), TO_UNSIGNED( 325, 11), TO_UNSIGNED( 373, 11), TO_UNSIGNED( 982, 11), TO_UNSIGNED(1186, 11),
TO_UNSIGNED(1282, 11), TO_UNSIGNED(1703, 11), TO_UNSIGNED( 74, 11), TO_UNSIGNED( 327, 11), TO_UNSIGNED( 375, 11), TO_UNSIGNED( 988, 11), TO_UNSIGNED(1189, 11), TO_UNSIGNED(1288, 11),
TO_UNSIGNED(1709, 11), TO_UNSIGNED( 77, 11), TO_UNSIGNED( 329, 11), TO_UNSIGNED( 377, 11), TO_UNSIGNED( 994, 11), TO_UNSIGNED(1192, 11), TO_UNSIGNED(1270, 11), TO_UNSIGNED(1697, 11),
TO_UNSIGNED( 427, 11), TO_UNSIGNED( 475, 11), TO_UNSIGNED( 944, 11), TO_UNSIGNED(1025, 11), TO_UNSIGNED(1169, 11), TO_UNSIGNED(1343, 11), TO_UNSIGNED(1752, 11), TO_UNSIGNED( 429, 11),
TO_UNSIGNED( 477, 11), TO_UNSIGNED( 947, 11), TO_UNSIGNED(1031, 11), TO_UNSIGNED(1172, 11), TO_UNSIGNED(1349, 11), TO_UNSIGNED(1758, 11), TO_UNSIGNED( 431, 11), TO_UNSIGNED( 479, 11),
TO_UNSIGNED( 950, 11), TO_UNSIGNED(1037, 11), TO_UNSIGNED(1175, 11), TO_UNSIGNED(1373, 11), TO_UNSIGNED(1764, 11), TO_UNSIGNED( 433, 11), TO_UNSIGNED( 481, 11), TO_UNSIGNED( 953, 11),
TO_UNSIGNED(1043, 11), TO_UNSIGNED(1178, 11), TO_UNSIGNED(1379, 11), TO_UNSIGNED(1770, 11), TO_UNSIGNED( 435, 11), TO_UNSIGNED( 483, 11), TO_UNSIGNED( 956, 11), TO_UNSIGNED(1049, 11),
TO_UNSIGNED(1181, 11), TO_UNSIGNED(1367, 11), TO_UNSIGNED(1806, 11), TO_UNSIGNED( 437, 11), TO_UNSIGNED( 485, 11), TO_UNSIGNED( 959, 11), TO_UNSIGNED(1055, 11), TO_UNSIGNED(1184, 11),
TO_UNSIGNED(1397, 11), TO_UNSIGNED(1794, 11), TO_UNSIGNED( 439, 11), TO_UNSIGNED( 487, 11), TO_UNSIGNED( 962, 11), TO_UNSIGNED(1061, 11), TO_UNSIGNED(1187, 11), TO_UNSIGNED(1385, 11),
TO_UNSIGNED(1800, 11), TO_UNSIGNED( 441, 11), TO_UNSIGNED( 489, 11), TO_UNSIGNED( 965, 11), TO_UNSIGNED(1067, 11), TO_UNSIGNED(1190, 11), TO_UNSIGNED(1391, 11), TO_UNSIGNED(1812, 11),
TO_UNSIGNED( 135, 11), TO_UNSIGNED( 443, 11), TO_UNSIGNED( 491, 11), TO_UNSIGNED( 968, 11), TO_UNSIGNED(1073, 11), TO_UNSIGNED(1193, 11), TO_UNSIGNED(1788, 11), TO_UNSIGNED( 11, 11),
TO_UNSIGNED( 83, 11), TO_UNSIGNED( 445, 11), TO_UNSIGNED( 493, 11), TO_UNSIGNED( 971, 11), TO_UNSIGNED(1079, 11), TO_UNSIGNED(1124, 11), TO_UNSIGNED( 447, 11), TO_UNSIGNED( 495, 11),
TO_UNSIGNED( 974, 11), TO_UNSIGNED(1085, 11), TO_UNSIGNED(1127, 11), TO_UNSIGNED(1277, 11), TO_UNSIGNED(1818, 11), TO_UNSIGNED( 141, 11), TO_UNSIGNED( 449, 11), TO_UNSIGNED( 497, 11),
TO_UNSIGNED( 977, 11), TO_UNSIGNED(1091, 11), TO_UNSIGNED(1130, 11), TO_UNSIGNED(1283, 11), TO_UNSIGNED( 451, 11), TO_UNSIGNED( 499, 11), TO_UNSIGNED( 908, 11), TO_UNSIGNED(1097, 11),
TO_UNSIGNED(1133, 11), TO_UNSIGNED(1289, 11), TO_UNSIGNED(1692, 11), TO_UNSIGNED( 453, 11), TO_UNSIGNED( 501, 11), TO_UNSIGNED( 911, 11), TO_UNSIGNED(1103, 11), TO_UNSIGNED(1136, 11),
TO_UNSIGNED(1271, 11), TO_UNSIGNED(1716, 11), TO_UNSIGNED( 455, 11), TO_UNSIGNED( 503, 11), TO_UNSIGNED( 914, 11), TO_UNSIGNED(1109, 11), TO_UNSIGNED(1139, 11), TO_UNSIGNED(1301, 11),
TO_UNSIGNED(1704, 11), TO_UNSIGNED( 457, 11), TO_UNSIGNED( 505, 11), TO_UNSIGNED( 917, 11), TO_UNSIGNED(1115, 11), TO_UNSIGNED(1142, 11), TO_UNSIGNED(1295, 11), TO_UNSIGNED(1710, 11),
TO_UNSIGNED( 459, 11), TO_UNSIGNED( 507, 11), TO_UNSIGNED( 920, 11), TO_UNSIGNED(1121, 11), TO_UNSIGNED(1145, 11), TO_UNSIGNED(1313, 11), TO_UNSIGNED(1698, 11), TO_UNSIGNED( 461, 11),
TO_UNSIGNED( 509, 11), TO_UNSIGNED( 923, 11), TO_UNSIGNED( 983, 11), TO_UNSIGNED(1148, 11), TO_UNSIGNED(1307, 11), TO_UNSIGNED(1722, 11), TO_UNSIGNED( 463, 11), TO_UNSIGNED( 511, 11),
TO_UNSIGNED( 926, 11), TO_UNSIGNED( 989, 11), TO_UNSIGNED(1151, 11), TO_UNSIGNED(1319, 11), TO_UNSIGNED(1734, 11), TO_UNSIGNED( 465, 11), TO_UNSIGNED( 513, 11), TO_UNSIGNED( 929, 11),
TO_UNSIGNED( 995, 11), TO_UNSIGNED(1154, 11), TO_UNSIGNED(1325, 11), TO_UNSIGNED(1728, 11), TO_UNSIGNED( 467, 11), TO_UNSIGNED( 515, 11), TO_UNSIGNED( 932, 11), TO_UNSIGNED(1001, 11),
TO_UNSIGNED(1157, 11), TO_UNSIGNED(1337, 11), TO_UNSIGNED(1740, 11), TO_UNSIGNED( 469, 11), TO_UNSIGNED( 517, 11), TO_UNSIGNED( 935, 11), TO_UNSIGNED(1007, 11), TO_UNSIGNED(1160, 11),
TO_UNSIGNED(1331, 11), TO_UNSIGNED(1776, 11), TO_UNSIGNED( 471, 11), TO_UNSIGNED( 519, 11), TO_UNSIGNED( 938, 11), TO_UNSIGNED(1013, 11), TO_UNSIGNED(1163, 11), TO_UNSIGNED(1355, 11),
TO_UNSIGNED(1782, 11), TO_UNSIGNED( 473, 11), TO_UNSIGNED( 521, 11), TO_UNSIGNED( 941, 11), TO_UNSIGNED(1019, 11), TO_UNSIGNED(1166, 11), TO_UNSIGNED(1361, 11), TO_UNSIGNED(1746, 11)
);
SIGNAL READ_C : UNSIGNED(10 downto 0);
SIGNAL WRITE_C : UNSIGNED(10 downto 0);
SIGNAL ROM_ADR : UNSIGNED(10 downto 0);
SIGNAL IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL WE_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_C_to_V_RAM : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
PROCESS(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
BEGIN
IF reset = '0' THEN
WRITE_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' THEN
IF WRITE_EN = '1' AND HOLDN = '1' THEN
TEMP := WRITE_C + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
WE_BIS <= '1';
WRITE_C <= TEMP;
ELSE
WE_BIS <= '0';
WRITE_C <= WRITE_C;
END IF;
IN_BIS <= INPUT_1(15 downto 0);
END if;
END PROCESS;
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
end if;
READ_C <= TEMP;
TMP := RAM( to_integer( TEMP ) );
OUTPUT_1 <= STD_LOGIC_VECTOR(RESIZE( SIGNED( TMP ), 32 )) ;
end if;
end process;
--
--
--
process(clock)
VARIABLE ADR : INTEGER RANGE 0 to 1823;
VARIABLE POS : INTEGER RANGE 0 to 1823;
begin
if clock'event and clock = '1' then
ADR := to_integer( WRITE_C );
ROM_ADR <= ROM( ADR );
end if;
end process;
--
--
--
process(clock)
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
-- IF reset = '0' THEN
-- OUTPUT_1 <= (OTHERS => '0');
if clock'event and clock = '1' then
if WE_BIS = '1' then
-- synthesis translate_off
-- printmsg("(Q16_8_V_to_C_RAM) ===> WRITING (" & to_int_str( STD_LOGIC_VECTOR(IN_BIS),6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(ROM_ADR),6) );
-- synthesis translate_on
RAM( to_integer( ROM_ADR ) ) <= IN_BIS;
end if;
end if;
end process;
END cRAM;
| gpl-3.0 | cea751b778c999432eb670b64eb6f646 | 0.64978 | 2.827043 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/RGB_2_YUV.vhd | 1 | 6,656 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity RGB_2_YUV is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end RGB_2_YUV;
architecture rtl of RGB_2_YUV is
constant s_rgb_30 : UNSIGNED(24 downto 0) := "0010011001000101101000011";
constant s_rgb_59 : UNSIGNED(24 downto 0) := "0100101100100010110100001";
constant s_rgb_11 : UNSIGNED(24 downto 0) := "0000111010010111100011010";
constant s_rgb_17 : UNSIGNED(24 downto 0) := "0001010110011001010001011";
constant s_rgb_33 : UNSIGNED(24 downto 0) := "0010101001100110101110100";
constant s_rgb_50 : UNSIGNED(24 downto 0) := "0100000000000000000000000";
constant s_rgb_42 : UNSIGNED(24 downto 0) := "0011010110010111101000100";
constant s_rgb_08 : UNSIGNED(24 downto 0) := "0000101001101000010111011";
constant s_rgb_128 : UNSIGNED(31 downto 0) := "10000000000000000000000000000000"; -- TO_UNSIGNED(128, 32); --"10000000000000000000000000000000";
signal PIPE_START : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL INPUT_R : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_G : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_B : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_Y : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_U : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL s_rgb_out_y : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cb : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cr : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL rgb_in_r_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
begin
INPUT_R <= INPUT_1( 7 downto 0);
INPUT_G <= INPUT_1(15 downto 8);
INPUT_B <= INPUT_1(23 downto 16);
OUTPUT_1 <= "00000000" & INPUT_V & INPUT_U & INPUT_Y;
-- NOUS NECESSITONS N CYCLES MAIS LE SIGNAL nREADY PEUT
-- ETRE SOUMIS 2 CYCLES AVANT LA FIN ;-)
nready <= PIPE_START(1);
ready <= PIPE_START(1) OR PIPE_START(0) OR start;
icc <= "0000";
process(rst, clk)
begin
if rst = '0' then
INPUT_Y <= (others => '0');
INPUT_U <= (others => '0');
INPUT_V <= (others => '0');
PIPE_START <= "0000";
elsif rising_edge(clk) then
if (flush = '1') then
PIPE_START <= "0000";
elsif (holdn = '0') then
PIPE_START <= PIPE_START;
else
-- ON NE REAGIT PAS IMMEDIATEMENT LORSQUE L'ON RECOIT LE SIGNAL
-- START CAR IL EST DELIVRE PAR L'ETAGE DE DECODAGE (LES ENTREES
-- DU CALCUL NE SERONT DISPONIBLES QU'UN CYCLE APRES).
PIPE_START <= PIPE_START(2 downto 0) & start;
--if start = '1' then
--REPORT "COMPUTATION START...";
--printmsg("(RGB) ===> (000) COMPUTATION START...");
--end if;
-- ON MULTIPLIE LES DONNEES ENTRANTES PAR LES CONSTANTES
-- CODEES EN VIRGULE FIXE
if PIPE_START(0) = '1' then
--REPORT "RUNNING FIRST SLICE...";
--printmsg("(RGB) ===> (001) RUNNING FIRST SLICE...");
--printmsg("(RGB) ===> (001) DATA ARE (" & to_int_str(INPUT_B,6) & ", " & to_int_str(INPUT_G,6) & ", " & to_int_str(INPUT_R,6) & ")");
rgb_in_r_reg_Y <= s_rgb_30 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Y <= s_rgb_59 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Y <= s_rgb_11 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cb <= s_rgb_17 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cb <= s_rgb_33 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cb <= s_rgb_50 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cr <= s_rgb_50 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cr <= s_rgb_42 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cr <= s_rgb_08 * UNSIGNED(INPUT_B);
end if;
if PIPE_START(1) = '1' then
--REPORT "RUNNING SECOND SLICE...";
--printmsg("(RGB) ===> (010) RUNNING SECOND SLICE...");
s_rgb_out_y <= rgb_in_r_reg_Y + (rgb_in_g_reg_Y + rgb_in_b_reg_Y);
s_rgb_out_cb <= (s_rgb_128 - rgb_in_r_reg_Cb) - (rgb_in_g_reg_Cb + rgb_in_b_reg_Cb);
s_rgb_out_cr <= (s_rgb_128 + rgb_in_r_reg_Cr) - (rgb_in_g_reg_Cr - rgb_in_b_reg_Cr);
end if;
if PIPE_START(2) = '1' then
--REPORT "RUNNING THIRD SLICE...";
--printmsg("(RGB) ===> (011) RUNNING THIRD SLICE...");
if (s_rgb_out_y(23)='1') then
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24) + 1);
else
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24));
end if;
if (s_rgb_out_cb(23)='1') then
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24) + 1);
else
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24));
end if;
if (s_rgb_out_cr(23)='1') then
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24) + 1);
else
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24));
end if;
--printmsg("(PGDC) ===> (011) DATA Y = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_y (31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA U = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA V = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24)),6) & ")");
else
INPUT_Y <= INPUT_Y;
INPUT_U <= INPUT_U;
INPUT_V <= INPUT_V;
end if;
end if;
end if;
end process;
--process(INPUT_Y, INPUT_U, INPUT_V)
--BEGIN
-- printmsg("(PGDC) ===> (111) DATA ARE (" & to_int_str(INPUT_V,6) & ", " & to_int_str(INPUT_U,6) & ", " & to_int_str(INPUT_Y,6) & ")");
--END PROCESS;
end rtl;
| gpl-3.0 | da3a7a9cbd20c6cedb51b7fdca2c730f | 0.56881 | 2.856652 | false | false | false | false |
ryos36/polyphony-tutorial | misc/vhdl/Life0/life0.vhdl | 1 | 858 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity life0 is
port(
clk : in std_logic;
din : in std_logic;
dout : out std_logic
);
end life0;
architecture RTL of life0 is
signal line: std_logic_vector(2 downto 0);
signal dout_reg: std_logic;
begin
dout <= dout_reg;
process(clk)
begin
if clk'event and clk = '1' then
line(0) <= din;
line(1) <= line(0);
line(2) <= line(1);
case line is
when "011" =>
dout_reg <= '1';
when "101" =>
dout_reg <= '1';
when "110" =>
dout_reg <= '1';
when others =>
dout_reg <= '0';
end case;
end if;
end process;
end RTL;
| mit | a82e6d8cba72e704737d33fa5e960aed | 0.439394 | 3.730435 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/testbench/tb_soc_plasma/tbench.vhd | 1 | 7,404 | ---------------------------------------------------------------------
-- TITLE: Test Bench
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a test bench for testing the Plasma CPU core.
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.mlite_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY tbench IS
END; --entity tbench
ARCHITECTURE logic OF tbench IS
CONSTANT memory_type : STRING :=
-- "TRI_PORT_X";
"DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
CONSTANT log_file : STRING :=
-- "UNUSED";
"output.txt";
SIGNAL clk : STD_LOGIC := '1';
SIGNAL reset : STD_LOGIC := '1';
SIGNAL interrupt : STD_LOGIC := '0';
--signal mem_write : std_logic;
SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 2);
SIGNAL data_write : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL pause1 : STD_LOGIC := '0';
SIGNAL pause2 : STD_LOGIC := '0';
SIGNAL pause : STD_LOGIC;
SIGNAL no_ddr_start : STD_LOGIC;
SIGNAL no_ddr_stop : STD_LOGIC;
SIGNAL byte_we : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL uart_write : STD_LOGIC;
SIGNAL gpioA_in : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
--
-- SIGNAUX PERMETTANT D'INTERCONNECTER LE PROCESSEUR AVEC LE BUS PCIe
-- EN SIMULATION CES DERNIERS SONT CABLES A LA MASSE (PAS DE PCIe)
--
SIGNAL fifo_1_out_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL fifo_1_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL fifo_2_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL fifo_2_in_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL fifo_1_read_en : STD_LOGIC;
SIGNAL fifo_1_empty : STD_LOGIC;
SIGNAL fifo_2_write_en : STD_LOGIC;
SIGNAL fifo_2_full : STD_LOGIC;
SIGNAL fifo_1_full : STD_LOGIC;
SIGNAL fifo_1_valid : STD_LOGIC;
SIGNAL fifo_2_empty : STD_LOGIC;
SIGNAL fifo_2_valid : STD_LOGIC;
SIGNAL clk_VGA : STD_LOGIC:='0';
component plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
clk_VGA : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
--data_write : out std_logic_vector(31 downto 0);
--data_read : in std_logic_vector(31 downto 0);
---mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
-- BLG START
fifo_1_out_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_read_en : OUT STD_LOGIC;
fifo_1_empty : IN STD_LOGIC;
fifo_2_in_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_write_en : OUT STD_LOGIC;
fifo_2_full : IN STD_LOGIC;
fifo_1_full : IN STD_LOGIC;
fifo_1_valid : IN STD_LOGIC;
fifo_2_empty : IN STD_LOGIC;
fifo_2_valid : IN STD_LOGIC;
fifo_1_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_2_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
-- BLG END
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --entity plasma
--
-- Fin de gestion du PCIe
--
COMPONENT PCIE_IN IS
PORT(
clk : IN STD_LOGIC;
fifo_out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_read_en : IN STD_LOGIC;
fifo_full : OUT STD_LOGIC;
fifo_empty : OUT STD_LOGIC;
fifo_valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT PCIE_OUT IS
PORT(
clk : IN STD_LOGIC;
fifo_in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_write_en : IN STD_LOGIC;
fifo_full : OUT STD_LOGIC;
fifo_valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT PCIE_CMP IS
PORT(
clk : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_valid : IN STD_LOGIC
);
END COMPONENT;
BEGIN --architecture
--Uncomment the line below to test interrupts
interrupt <= '1' AFTER 20 us WHEN interrupt = '0' ELSE '0' AFTER 445 ns;
pcie_i : PCIE_IN
PORT MAP (
clk => clk,
fifo_out_data => fifo_1_out_data,
fifo_compteur => fifo_1_compteur,
fifo_read_en => fifo_1_read_en,
fifo_empty => fifo_1_empty,
fifo_full => fifo_1_full,
fifo_valid => fifo_1_valid
);
pcie_o : PCIE_OUT
PORT MAP (
clk => clk,
fifo_in_data => fifo_2_in_data,
fifo_compteur => fifo_2_compteur,
fifo_write_en => fifo_2_write_en,
fifo_full => fifo_2_full,
fifo_valid => fifo_2_valid
);
clk <= NOT clk AFTER 50 ns;
clk_VGA <= NOT clk_VGA AFTER 25 ns;
reset <= '0' AFTER 500 ns;
pause1 <= '1' AFTER 700 ns WHEN pause1 = '0' ELSE '0' AFTER 200 ns;
pause2 <= '1' AFTER 300 ns WHEN pause2 = '0' ELSE '0' AFTER 200 ns;
pause <= pause1 OR pause2;
gpioA_in(7 DOWNTO 0) <= "00000010";
u1_plasma : plasma
GENERIC MAP (
memory_type => memory_type,
ethernet => '1',
eUart => '1',
use_cache => '0',
log_file => log_file
)
PORT MAP (
clk => clk,
clk_VGA => clk_VGA,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => open,
byte_we => open,
--data_write => open,
--data_read => data_read,
-- mem_pause_in => pause,
-- BLG START
fifo_1_out_data => fifo_1_out_data,
fifo_1_read_en => fifo_1_read_en,
fifo_1_empty => fifo_1_empty,
fifo_2_in_data => fifo_2_in_data,
fifo_1_write_en => fifo_2_write_en,
fifo_2_full => fifo_2_full,
fifo_1_full => fifo_1_full,
fifo_1_valid => fifo_1_valid,
fifo_2_empty => fifo_2_empty,
fifo_2_valid => fifo_2_valid,
fifo_1_compteur => fifo_1_compteur,
fifo_2_compteur => fifo_2_compteur,
VGA_hs => open,
VGA_vs => open,
VGA_red => open,
VGA_green => open,
VGA_blue => open,
-- BLG END
-- no_ddr_start => no_ddr_start,
--no_ddr_stop => no_ddr_stop,
gpio0_out => OPEN,
gpioA_in => gpioA_in
);
END; --architecture logic
| gpl-3.0 | 573b3f5c7370a09f551e2ad7a29b5984 | 0.552404 | 3.198272 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/coproc_4.vhd | 2 | 1,408 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 | cf8cf35686d5cc2fd6ef37b6519e9fa6 | 0.508523 | 3.705263 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_IndexRAM.vhd | 1 | 46,384 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_IndexRAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(15 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(15 downto 0)
);
END;
architecture cRAM of Q16_8_IndexRAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
type rom_type is array (0 to 1824-1) of UNSIGNED (11 downto 0);
signal RAM : ram_type;
signal WE_BIS : STD_LOGIC;
signal IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
constant ROM : rom_type:= (
TO_UNSIGNED(75, 12), TO_UNSIGNED(618, 12),
TO_UNSIGNED(732, 12), TO_UNSIGNED(1425, 12),
TO_UNSIGNED(1500, 12), TO_UNSIGNED(1683, 12),
TO_UNSIGNED(84, 12), TO_UNSIGNED(621, 12),
TO_UNSIGNED(738, 12), TO_UNSIGNED(1428, 12),
TO_UNSIGNED(1506, 12), TO_UNSIGNED(1614, 12),
TO_UNSIGNED(86, 12), TO_UNSIGNED(624, 12),
TO_UNSIGNED(744, 12), TO_UNSIGNED(1437, 12),
TO_UNSIGNED(1488, 12), TO_UNSIGNED(1819, 12),
TO_UNSIGNED(12, 12), TO_UNSIGNED(88, 12),
TO_UNSIGNED(627, 12), TO_UNSIGNED(750, 12),
TO_UNSIGNED(1440, 12), TO_UNSIGNED(1512, 12),
TO_UNSIGNED(15, 12), TO_UNSIGNED(90, 12),
TO_UNSIGNED(630, 12), TO_UNSIGNED(756, 12),
TO_UNSIGNED(1443, 12), TO_UNSIGNED(1524, 12),
TO_UNSIGNED(18, 12), TO_UNSIGNED(92, 12),
TO_UNSIGNED(633, 12), TO_UNSIGNED(762, 12),
TO_UNSIGNED(1446, 12), TO_UNSIGNED(1518, 12),
TO_UNSIGNED(21, 12), TO_UNSIGNED(94, 12),
TO_UNSIGNED(636, 12), TO_UNSIGNED(768, 12),
TO_UNSIGNED(1449, 12), TO_UNSIGNED(1542, 12),
TO_UNSIGNED(24, 12), TO_UNSIGNED(96, 12),
TO_UNSIGNED(639, 12), TO_UNSIGNED(774, 12),
TO_UNSIGNED(1452, 12), TO_UNSIGNED(1548, 12),
TO_UNSIGNED(27, 12), TO_UNSIGNED(98, 12),
TO_UNSIGNED(642, 12), TO_UNSIGNED(780, 12),
TO_UNSIGNED(1455, 12), TO_UNSIGNED(1530, 12),
TO_UNSIGNED(30, 12), TO_UNSIGNED(100, 12),
TO_UNSIGNED(645, 12), TO_UNSIGNED(786, 12),
TO_UNSIGNED(1461, 12), TO_UNSIGNED(1536, 12),
TO_UNSIGNED(33, 12), TO_UNSIGNED(102, 12),
TO_UNSIGNED(648, 12), TO_UNSIGNED(792, 12),
TO_UNSIGNED(1458, 12), TO_UNSIGNED(1554, 12),
TO_UNSIGNED(36, 12), TO_UNSIGNED(104, 12),
TO_UNSIGNED(651, 12), TO_UNSIGNED(798, 12),
TO_UNSIGNED(1485, 12), TO_UNSIGNED(1560, 12),
TO_UNSIGNED(39, 12), TO_UNSIGNED(106, 12),
TO_UNSIGNED(654, 12), TO_UNSIGNED(804, 12),
TO_UNSIGNED(1572, 12), TO_UNSIGNED(1617, 12),
TO_UNSIGNED(42, 12), TO_UNSIGNED(108, 12),
TO_UNSIGNED(657, 12), TO_UNSIGNED(810, 12),
TO_UNSIGNED(1398, 12), TO_UNSIGNED(1566, 12),
TO_UNSIGNED(45, 12), TO_UNSIGNED(110, 12),
TO_UNSIGNED(660, 12), TO_UNSIGNED(816, 12),
TO_UNSIGNED(1401, 12), TO_UNSIGNED(1584, 12),
TO_UNSIGNED(48, 12), TO_UNSIGNED(112, 12),
TO_UNSIGNED(663, 12), TO_UNSIGNED(822, 12),
TO_UNSIGNED(1404, 12), TO_UNSIGNED(1578, 12),
TO_UNSIGNED(51, 12), TO_UNSIGNED(114, 12),
TO_UNSIGNED(666, 12), TO_UNSIGNED(828, 12),
TO_UNSIGNED(1413, 12), TO_UNSIGNED(1596, 12),
TO_UNSIGNED(54, 12), TO_UNSIGNED(116, 12),
TO_UNSIGNED(669, 12), TO_UNSIGNED(690, 12),
TO_UNSIGNED(1416, 12), TO_UNSIGNED(1602, 12),
TO_UNSIGNED(57, 12), TO_UNSIGNED(118, 12),
TO_UNSIGNED(672, 12), TO_UNSIGNED(696, 12),
TO_UNSIGNED(1419, 12), TO_UNSIGNED(1590, 12),
TO_UNSIGNED(0, 12), TO_UNSIGNED(60, 12),
TO_UNSIGNED(120, 12), TO_UNSIGNED(675, 12),
TO_UNSIGNED(702, 12), TO_UNSIGNED(1407, 12),
TO_UNSIGNED(63, 12), TO_UNSIGNED(122, 12),
TO_UNSIGNED(678, 12), TO_UNSIGNED(708, 12),
TO_UNSIGNED(1410, 12), TO_UNSIGNED(1476, 12),
TO_UNSIGNED(66, 12), TO_UNSIGNED(124, 12),
TO_UNSIGNED(681, 12), TO_UNSIGNED(714, 12),
TO_UNSIGNED(1434, 12), TO_UNSIGNED(1464, 12),
TO_UNSIGNED(69, 12), TO_UNSIGNED(126, 12),
TO_UNSIGNED(684, 12), TO_UNSIGNED(720, 12),
TO_UNSIGNED(1431, 12), TO_UNSIGNED(1470, 12),
TO_UNSIGNED(72, 12), TO_UNSIGNED(128, 12),
TO_UNSIGNED(687, 12), TO_UNSIGNED(726, 12),
TO_UNSIGNED(1422, 12), TO_UNSIGNED(1494, 12),
TO_UNSIGNED(186, 12), TO_UNSIGNED(234, 12),
TO_UNSIGNED(775, 12), TO_UNSIGNED(906, 12),
TO_UNSIGNED(1435, 12), TO_UNSIGNED(1585, 12),
TO_UNSIGNED(188, 12), TO_UNSIGNED(236, 12),
TO_UNSIGNED(781, 12), TO_UNSIGNED(909, 12),
TO_UNSIGNED(1432, 12), TO_UNSIGNED(1579, 12),
TO_UNSIGNED(190, 12), TO_UNSIGNED(238, 12),
TO_UNSIGNED(787, 12), TO_UNSIGNED(912, 12),
TO_UNSIGNED(1423, 12), TO_UNSIGNED(1597, 12),
TO_UNSIGNED(192, 12), TO_UNSIGNED(240, 12),
TO_UNSIGNED(793, 12), TO_UNSIGNED(915, 12),
TO_UNSIGNED(1426, 12), TO_UNSIGNED(1603, 12),
TO_UNSIGNED(194, 12), TO_UNSIGNED(242, 12),
TO_UNSIGNED(799, 12), TO_UNSIGNED(918, 12),
TO_UNSIGNED(1429, 12), TO_UNSIGNED(1591, 12),
TO_UNSIGNED(1, 12), TO_UNSIGNED(196, 12),
TO_UNSIGNED(244, 12), TO_UNSIGNED(805, 12),
TO_UNSIGNED(921, 12), TO_UNSIGNED(1438, 12),
TO_UNSIGNED(198, 12), TO_UNSIGNED(246, 12),
TO_UNSIGNED(811, 12), TO_UNSIGNED(924, 12),
TO_UNSIGNED(1441, 12), TO_UNSIGNED(1477, 12),
TO_UNSIGNED(200, 12), TO_UNSIGNED(248, 12),
TO_UNSIGNED(817, 12), TO_UNSIGNED(927, 12),
TO_UNSIGNED(1444, 12), TO_UNSIGNED(1465, 12),
TO_UNSIGNED(202, 12), TO_UNSIGNED(250, 12),
TO_UNSIGNED(823, 12), TO_UNSIGNED(930, 12),
TO_UNSIGNED(1447, 12), TO_UNSIGNED(1471, 12),
TO_UNSIGNED(204, 12), TO_UNSIGNED(252, 12),
TO_UNSIGNED(829, 12), TO_UNSIGNED(933, 12),
TO_UNSIGNED(1450, 12), TO_UNSIGNED(1495, 12),
TO_UNSIGNED(206, 12), TO_UNSIGNED(254, 12),
TO_UNSIGNED(691, 12), TO_UNSIGNED(936, 12),
TO_UNSIGNED(1453, 12), TO_UNSIGNED(1501, 12),
TO_UNSIGNED(208, 12), TO_UNSIGNED(256, 12),
TO_UNSIGNED(697, 12), TO_UNSIGNED(939, 12),
TO_UNSIGNED(1456, 12), TO_UNSIGNED(1507, 12),
TO_UNSIGNED(210, 12), TO_UNSIGNED(258, 12),
TO_UNSIGNED(703, 12), TO_UNSIGNED(942, 12),
TO_UNSIGNED(1462, 12), TO_UNSIGNED(1489, 12),
TO_UNSIGNED(212, 12), TO_UNSIGNED(260, 12),
TO_UNSIGNED(709, 12), TO_UNSIGNED(945, 12),
TO_UNSIGNED(1459, 12), TO_UNSIGNED(1513, 12),
TO_UNSIGNED(214, 12), TO_UNSIGNED(262, 12),
TO_UNSIGNED(715, 12), TO_UNSIGNED(948, 12),
TO_UNSIGNED(1486, 12), TO_UNSIGNED(1525, 12),
TO_UNSIGNED(216, 12), TO_UNSIGNED(264, 12),
TO_UNSIGNED(721, 12), TO_UNSIGNED(951, 12),
TO_UNSIGNED(1519, 12), TO_UNSIGNED(1618, 12),
TO_UNSIGNED(218, 12), TO_UNSIGNED(266, 12),
TO_UNSIGNED(727, 12), TO_UNSIGNED(954, 12),
TO_UNSIGNED(1399, 12), TO_UNSIGNED(1543, 12),
TO_UNSIGNED(220, 12), TO_UNSIGNED(268, 12),
TO_UNSIGNED(733, 12), TO_UNSIGNED(957, 12),
TO_UNSIGNED(1402, 12), TO_UNSIGNED(1549, 12),
TO_UNSIGNED(222, 12), TO_UNSIGNED(270, 12),
TO_UNSIGNED(739, 12), TO_UNSIGNED(960, 12),
TO_UNSIGNED(1405, 12), TO_UNSIGNED(1531, 12),
TO_UNSIGNED(224, 12), TO_UNSIGNED(272, 12),
TO_UNSIGNED(745, 12), TO_UNSIGNED(963, 12),
TO_UNSIGNED(1414, 12), TO_UNSIGNED(1537, 12),
TO_UNSIGNED(226, 12), TO_UNSIGNED(274, 12),
TO_UNSIGNED(751, 12), TO_UNSIGNED(966, 12),
TO_UNSIGNED(1417, 12), TO_UNSIGNED(1555, 12),
TO_UNSIGNED(228, 12), TO_UNSIGNED(276, 12),
TO_UNSIGNED(757, 12), TO_UNSIGNED(969, 12),
TO_UNSIGNED(1420, 12), TO_UNSIGNED(1561, 12),
TO_UNSIGNED(230, 12), TO_UNSIGNED(278, 12),
TO_UNSIGNED(763, 12), TO_UNSIGNED(972, 12),
TO_UNSIGNED(1408, 12), TO_UNSIGNED(1573, 12),
TO_UNSIGNED(232, 12), TO_UNSIGNED(280, 12),
TO_UNSIGNED(769, 12), TO_UNSIGNED(975, 12),
TO_UNSIGNED(1411, 12), TO_UNSIGNED(1567, 12),
TO_UNSIGNED(235, 12), TO_UNSIGNED(282, 12),
TO_UNSIGNED(788, 12), TO_UNSIGNED(1206, 12),
TO_UNSIGNED(1556, 12), TO_UNSIGNED(1635, 12),
TO_UNSIGNED(237, 12), TO_UNSIGNED(284, 12),
TO_UNSIGNED(794, 12), TO_UNSIGNED(1209, 12),
TO_UNSIGNED(1562, 12), TO_UNSIGNED(1629, 12),
TO_UNSIGNED(239, 12), TO_UNSIGNED(286, 12),
TO_UNSIGNED(800, 12), TO_UNSIGNED(1194, 12),
TO_UNSIGNED(1574, 12), TO_UNSIGNED(1632, 12),
TO_UNSIGNED(241, 12), TO_UNSIGNED(288, 12),
TO_UNSIGNED(806, 12), TO_UNSIGNED(1215, 12),
TO_UNSIGNED(1568, 12), TO_UNSIGNED(1641, 12),
TO_UNSIGNED(243, 12), TO_UNSIGNED(290, 12),
TO_UNSIGNED(812, 12), TO_UNSIGNED(1212, 12),
TO_UNSIGNED(1586, 12), TO_UNSIGNED(1638, 12),
TO_UNSIGNED(245, 12), TO_UNSIGNED(292, 12),
TO_UNSIGNED(818, 12), TO_UNSIGNED(1221, 12),
TO_UNSIGNED(1580, 12), TO_UNSIGNED(1644, 12),
TO_UNSIGNED(247, 12), TO_UNSIGNED(294, 12),
TO_UNSIGNED(824, 12), TO_UNSIGNED(1224, 12),
TO_UNSIGNED(1598, 12), TO_UNSIGNED(1650, 12),
TO_UNSIGNED(249, 12), TO_UNSIGNED(296, 12),
TO_UNSIGNED(830, 12), TO_UNSIGNED(1227, 12),
TO_UNSIGNED(1604, 12), TO_UNSIGNED(1647, 12),
TO_UNSIGNED(251, 12), TO_UNSIGNED(298, 12),
TO_UNSIGNED(692, 12), TO_UNSIGNED(1218, 12),
TO_UNSIGNED(1592, 12), TO_UNSIGNED(1653, 12),
TO_UNSIGNED(2, 12), TO_UNSIGNED(253, 12),
TO_UNSIGNED(300, 12), TO_UNSIGNED(698, 12),
TO_UNSIGNED(1233, 12), TO_UNSIGNED(1656, 12),
TO_UNSIGNED(255, 12), TO_UNSIGNED(302, 12),
TO_UNSIGNED(704, 12), TO_UNSIGNED(1236, 12),
TO_UNSIGNED(1478, 12), TO_UNSIGNED(1659, 12),
TO_UNSIGNED(257, 12), TO_UNSIGNED(304, 12),
TO_UNSIGNED(710, 12), TO_UNSIGNED(1239, 12),
TO_UNSIGNED(1466, 12), TO_UNSIGNED(1662, 12),
TO_UNSIGNED(259, 12), TO_UNSIGNED(306, 12),
TO_UNSIGNED(716, 12), TO_UNSIGNED(1230, 12),
TO_UNSIGNED(1472, 12), TO_UNSIGNED(1665, 12),
TO_UNSIGNED(261, 12), TO_UNSIGNED(308, 12),
TO_UNSIGNED(722, 12), TO_UNSIGNED(1251, 12),
TO_UNSIGNED(1496, 12), TO_UNSIGNED(1671, 12),
TO_UNSIGNED(263, 12), TO_UNSIGNED(310, 12),
TO_UNSIGNED(728, 12), TO_UNSIGNED(1242, 12),
TO_UNSIGNED(1502, 12), TO_UNSIGNED(1668, 12),
TO_UNSIGNED(265, 12), TO_UNSIGNED(312, 12),
TO_UNSIGNED(734, 12), TO_UNSIGNED(1245, 12),
TO_UNSIGNED(1508, 12), TO_UNSIGNED(1674, 12),
TO_UNSIGNED(267, 12), TO_UNSIGNED(314, 12),
TO_UNSIGNED(740, 12), TO_UNSIGNED(1248, 12),
TO_UNSIGNED(1490, 12), TO_UNSIGNED(1677, 12),
TO_UNSIGNED(269, 12), TO_UNSIGNED(316, 12),
TO_UNSIGNED(746, 12), TO_UNSIGNED(1257, 12),
TO_UNSIGNED(1514, 12), TO_UNSIGNED(1680, 12),
TO_UNSIGNED(271, 12), TO_UNSIGNED(318, 12),
TO_UNSIGNED(752, 12), TO_UNSIGNED(1254, 12),
TO_UNSIGNED(1482, 12), TO_UNSIGNED(1526, 12),
TO_UNSIGNED(273, 12), TO_UNSIGNED(320, 12),
TO_UNSIGNED(758, 12), TO_UNSIGNED(1263, 12),
TO_UNSIGNED(1520, 12), TO_UNSIGNED(1608, 12),
TO_UNSIGNED(275, 12), TO_UNSIGNED(322, 12),
TO_UNSIGNED(764, 12), TO_UNSIGNED(1260, 12),
TO_UNSIGNED(1544, 12), TO_UNSIGNED(1611, 12),
TO_UNSIGNED(277, 12), TO_UNSIGNED(324, 12),
TO_UNSIGNED(770, 12), TO_UNSIGNED(1197, 12),
TO_UNSIGNED(1550, 12), TO_UNSIGNED(1620, 12),
TO_UNSIGNED(279, 12), TO_UNSIGNED(326, 12),
TO_UNSIGNED(776, 12), TO_UNSIGNED(1200, 12),
TO_UNSIGNED(1532, 12), TO_UNSIGNED(1623, 12),
TO_UNSIGNED(281, 12), TO_UNSIGNED(328, 12),
TO_UNSIGNED(782, 12), TO_UNSIGNED(1203, 12),
TO_UNSIGNED(1538, 12), TO_UNSIGNED(1626, 12),
TO_UNSIGNED(330, 12), TO_UNSIGNED(378, 12),
TO_UNSIGNED(705, 12), TO_UNSIGNED(885, 12),
TO_UNSIGNED(1605, 12), TO_UNSIGNED(1669, 12),
TO_UNSIGNED(332, 12), TO_UNSIGNED(380, 12),
TO_UNSIGNED(711, 12), TO_UNSIGNED(888, 12),
TO_UNSIGNED(1593, 12), TO_UNSIGNED(1675, 12),
TO_UNSIGNED(3, 12), TO_UNSIGNED(334, 12),
TO_UNSIGNED(382, 12), TO_UNSIGNED(717, 12),
TO_UNSIGNED(891, 12), TO_UNSIGNED(1678, 12),
TO_UNSIGNED(336, 12), TO_UNSIGNED(384, 12),
TO_UNSIGNED(723, 12), TO_UNSIGNED(894, 12),
TO_UNSIGNED(1479, 12), TO_UNSIGNED(1681, 12),
TO_UNSIGNED(338, 12), TO_UNSIGNED(386, 12),
TO_UNSIGNED(729, 12), TO_UNSIGNED(897, 12),
TO_UNSIGNED(1467, 12), TO_UNSIGNED(1483, 12),
TO_UNSIGNED(340, 12), TO_UNSIGNED(388, 12),
TO_UNSIGNED(735, 12), TO_UNSIGNED(900, 12),
TO_UNSIGNED(1473, 12), TO_UNSIGNED(1609, 12),
TO_UNSIGNED(342, 12), TO_UNSIGNED(390, 12),
TO_UNSIGNED(741, 12), TO_UNSIGNED(903, 12),
TO_UNSIGNED(1497, 12), TO_UNSIGNED(1612, 12),
TO_UNSIGNED(344, 12), TO_UNSIGNED(392, 12),
TO_UNSIGNED(747, 12), TO_UNSIGNED(834, 12),
TO_UNSIGNED(1503, 12), TO_UNSIGNED(1621, 12),
TO_UNSIGNED(346, 12), TO_UNSIGNED(394, 12),
TO_UNSIGNED(753, 12), TO_UNSIGNED(837, 12),
TO_UNSIGNED(1509, 12), TO_UNSIGNED(1624, 12),
TO_UNSIGNED(348, 12), TO_UNSIGNED(396, 12),
TO_UNSIGNED(759, 12), TO_UNSIGNED(840, 12),
TO_UNSIGNED(1491, 12), TO_UNSIGNED(1627, 12),
TO_UNSIGNED(350, 12), TO_UNSIGNED(398, 12),
TO_UNSIGNED(765, 12), TO_UNSIGNED(843, 12),
TO_UNSIGNED(1515, 12), TO_UNSIGNED(1636, 12),
TO_UNSIGNED(352, 12), TO_UNSIGNED(400, 12),
TO_UNSIGNED(771, 12), TO_UNSIGNED(846, 12),
TO_UNSIGNED(1527, 12), TO_UNSIGNED(1630, 12),
TO_UNSIGNED(354, 12), TO_UNSIGNED(402, 12),
TO_UNSIGNED(777, 12), TO_UNSIGNED(849, 12),
TO_UNSIGNED(1521, 12), TO_UNSIGNED(1633, 12),
TO_UNSIGNED(356, 12), TO_UNSIGNED(404, 12),
TO_UNSIGNED(783, 12), TO_UNSIGNED(852, 12),
TO_UNSIGNED(1545, 12), TO_UNSIGNED(1642, 12),
TO_UNSIGNED(358, 12), TO_UNSIGNED(406, 12),
TO_UNSIGNED(789, 12), TO_UNSIGNED(855, 12),
TO_UNSIGNED(1551, 12), TO_UNSIGNED(1639, 12),
TO_UNSIGNED(360, 12), TO_UNSIGNED(408, 12),
TO_UNSIGNED(795, 12), TO_UNSIGNED(858, 12),
TO_UNSIGNED(1533, 12), TO_UNSIGNED(1645, 12),
TO_UNSIGNED(362, 12), TO_UNSIGNED(410, 12),
TO_UNSIGNED(801, 12), TO_UNSIGNED(861, 12),
TO_UNSIGNED(1539, 12), TO_UNSIGNED(1651, 12),
TO_UNSIGNED(364, 12), TO_UNSIGNED(412, 12),
TO_UNSIGNED(807, 12), TO_UNSIGNED(864, 12),
TO_UNSIGNED(1557, 12), TO_UNSIGNED(1648, 12),
TO_UNSIGNED(366, 12), TO_UNSIGNED(414, 12),
TO_UNSIGNED(813, 12), TO_UNSIGNED(867, 12),
TO_UNSIGNED(1563, 12), TO_UNSIGNED(1654, 12),
TO_UNSIGNED(368, 12), TO_UNSIGNED(416, 12),
TO_UNSIGNED(819, 12), TO_UNSIGNED(870, 12),
TO_UNSIGNED(1575, 12), TO_UNSIGNED(1657, 12),
TO_UNSIGNED(370, 12), TO_UNSIGNED(418, 12),
TO_UNSIGNED(825, 12), TO_UNSIGNED(873, 12),
TO_UNSIGNED(1569, 12), TO_UNSIGNED(1660, 12),
TO_UNSIGNED(372, 12), TO_UNSIGNED(420, 12),
TO_UNSIGNED(831, 12), TO_UNSIGNED(876, 12),
TO_UNSIGNED(1587, 12), TO_UNSIGNED(1663, 12),
TO_UNSIGNED(374, 12), TO_UNSIGNED(422, 12),
TO_UNSIGNED(693, 12), TO_UNSIGNED(879, 12),
TO_UNSIGNED(1581, 12), TO_UNSIGNED(1666, 12),
TO_UNSIGNED(376, 12), TO_UNSIGNED(424, 12),
TO_UNSIGNED(699, 12), TO_UNSIGNED(882, 12),
TO_UNSIGNED(1599, 12), TO_UNSIGNED(1672, 12),
TO_UNSIGNED(379, 12), TO_UNSIGNED(426, 12),
TO_UNSIGNED(682, 12), TO_UNSIGNED(736, 12),
TO_UNSIGNED(1198, 12), TO_UNSIGNED(1540, 12),
TO_UNSIGNED(381, 12), TO_UNSIGNED(428, 12),
TO_UNSIGNED(685, 12), TO_UNSIGNED(742, 12),
TO_UNSIGNED(1201, 12), TO_UNSIGNED(1558, 12),
TO_UNSIGNED(383, 12), TO_UNSIGNED(430, 12),
TO_UNSIGNED(688, 12), TO_UNSIGNED(748, 12),
TO_UNSIGNED(1204, 12), TO_UNSIGNED(1564, 12),
TO_UNSIGNED(385, 12), TO_UNSIGNED(432, 12),
TO_UNSIGNED(619, 12), TO_UNSIGNED(754, 12),
TO_UNSIGNED(1207, 12), TO_UNSIGNED(1576, 12),
TO_UNSIGNED(387, 12), TO_UNSIGNED(434, 12),
TO_UNSIGNED(622, 12), TO_UNSIGNED(760, 12),
TO_UNSIGNED(1210, 12), TO_UNSIGNED(1570, 12),
TO_UNSIGNED(389, 12), TO_UNSIGNED(436, 12),
TO_UNSIGNED(625, 12), TO_UNSIGNED(766, 12),
TO_UNSIGNED(1195, 12), TO_UNSIGNED(1588, 12),
TO_UNSIGNED(391, 12), TO_UNSIGNED(438, 12),
TO_UNSIGNED(628, 12), TO_UNSIGNED(772, 12),
TO_UNSIGNED(1216, 12), TO_UNSIGNED(1582, 12),
TO_UNSIGNED(393, 12), TO_UNSIGNED(440, 12),
TO_UNSIGNED(631, 12), TO_UNSIGNED(778, 12),
TO_UNSIGNED(1213, 12), TO_UNSIGNED(1600, 12),
TO_UNSIGNED(395, 12), TO_UNSIGNED(442, 12),
TO_UNSIGNED(634, 12), TO_UNSIGNED(784, 12),
TO_UNSIGNED(1222, 12), TO_UNSIGNED(1606, 12),
TO_UNSIGNED(397, 12), TO_UNSIGNED(444, 12),
TO_UNSIGNED(637, 12), TO_UNSIGNED(790, 12),
TO_UNSIGNED(1225, 12), TO_UNSIGNED(1594, 12),
TO_UNSIGNED(4, 12), TO_UNSIGNED(399, 12),
TO_UNSIGNED(446, 12), TO_UNSIGNED(640, 12),
TO_UNSIGNED(796, 12), TO_UNSIGNED(1228, 12),
TO_UNSIGNED(401, 12), TO_UNSIGNED(448, 12),
TO_UNSIGNED(643, 12), TO_UNSIGNED(802, 12),
TO_UNSIGNED(1219, 12), TO_UNSIGNED(1480, 12),
TO_UNSIGNED(403, 12), TO_UNSIGNED(450, 12),
TO_UNSIGNED(646, 12), TO_UNSIGNED(808, 12),
TO_UNSIGNED(1234, 12), TO_UNSIGNED(1468, 12),
TO_UNSIGNED(405, 12), TO_UNSIGNED(452, 12),
TO_UNSIGNED(649, 12), TO_UNSIGNED(814, 12),
TO_UNSIGNED(1237, 12), TO_UNSIGNED(1474, 12),
TO_UNSIGNED(407, 12), TO_UNSIGNED(454, 12),
TO_UNSIGNED(652, 12), TO_UNSIGNED(820, 12),
TO_UNSIGNED(1240, 12), TO_UNSIGNED(1498, 12),
TO_UNSIGNED(409, 12), TO_UNSIGNED(456, 12),
TO_UNSIGNED(655, 12), TO_UNSIGNED(826, 12),
TO_UNSIGNED(1231, 12), TO_UNSIGNED(1504, 12),
TO_UNSIGNED(411, 12), TO_UNSIGNED(458, 12),
TO_UNSIGNED(658, 12), TO_UNSIGNED(832, 12),
TO_UNSIGNED(1252, 12), TO_UNSIGNED(1510, 12),
TO_UNSIGNED(413, 12), TO_UNSIGNED(460, 12),
TO_UNSIGNED(661, 12), TO_UNSIGNED(694, 12),
TO_UNSIGNED(1243, 12), TO_UNSIGNED(1492, 12),
TO_UNSIGNED(415, 12), TO_UNSIGNED(462, 12),
TO_UNSIGNED(664, 12), TO_UNSIGNED(700, 12),
TO_UNSIGNED(1246, 12), TO_UNSIGNED(1516, 12),
TO_UNSIGNED(417, 12), TO_UNSIGNED(464, 12),
TO_UNSIGNED(667, 12), TO_UNSIGNED(706, 12),
TO_UNSIGNED(1249, 12), TO_UNSIGNED(1528, 12),
TO_UNSIGNED(419, 12), TO_UNSIGNED(466, 12),
TO_UNSIGNED(670, 12), TO_UNSIGNED(712, 12),
TO_UNSIGNED(1258, 12), TO_UNSIGNED(1522, 12),
TO_UNSIGNED(421, 12), TO_UNSIGNED(468, 12),
TO_UNSIGNED(673, 12), TO_UNSIGNED(718, 12),
TO_UNSIGNED(1255, 12), TO_UNSIGNED(1546, 12),
TO_UNSIGNED(423, 12), TO_UNSIGNED(470, 12),
TO_UNSIGNED(676, 12), TO_UNSIGNED(724, 12),
TO_UNSIGNED(1264, 12), TO_UNSIGNED(1552, 12),
TO_UNSIGNED(425, 12), TO_UNSIGNED(472, 12),
TO_UNSIGNED(679, 12), TO_UNSIGNED(730, 12),
TO_UNSIGNED(1261, 12), TO_UNSIGNED(1534, 12),
TO_UNSIGNED(474, 12), TO_UNSIGNED(522, 12),
TO_UNSIGNED(1062, 12), TO_UNSIGNED(1332, 12),
TO_UNSIGNED(1631, 12), TO_UNSIGNED(1729, 12),
TO_UNSIGNED(476, 12), TO_UNSIGNED(524, 12),
TO_UNSIGNED(1068, 12), TO_UNSIGNED(1326, 12),
TO_UNSIGNED(1634, 12), TO_UNSIGNED(1723, 12),
TO_UNSIGNED(478, 12), TO_UNSIGNED(526, 12),
TO_UNSIGNED(1074, 12), TO_UNSIGNED(1350, 12),
TO_UNSIGNED(1643, 12), TO_UNSIGNED(1735, 12),
TO_UNSIGNED(480, 12), TO_UNSIGNED(528, 12),
TO_UNSIGNED(1080, 12), TO_UNSIGNED(1356, 12),
TO_UNSIGNED(1640, 12), TO_UNSIGNED(1771, 12),
TO_UNSIGNED(482, 12), TO_UNSIGNED(530, 12),
TO_UNSIGNED(1086, 12), TO_UNSIGNED(1338, 12),
TO_UNSIGNED(1646, 12), TO_UNSIGNED(1777, 12),
TO_UNSIGNED(484, 12), TO_UNSIGNED(532, 12),
TO_UNSIGNED(1092, 12), TO_UNSIGNED(1344, 12),
TO_UNSIGNED(1652, 12), TO_UNSIGNED(1741, 12),
TO_UNSIGNED(486, 12), TO_UNSIGNED(534, 12),
TO_UNSIGNED(1098, 12), TO_UNSIGNED(1368, 12),
TO_UNSIGNED(1649, 12), TO_UNSIGNED(1747, 12),
TO_UNSIGNED(488, 12), TO_UNSIGNED(536, 12),
TO_UNSIGNED(1104, 12), TO_UNSIGNED(1374, 12),
TO_UNSIGNED(1655, 12), TO_UNSIGNED(1753, 12),
TO_UNSIGNED(490, 12), TO_UNSIGNED(538, 12),
TO_UNSIGNED(1110, 12), TO_UNSIGNED(1362, 12),
TO_UNSIGNED(1658, 12), TO_UNSIGNED(1759, 12),
TO_UNSIGNED(492, 12), TO_UNSIGNED(540, 12),
TO_UNSIGNED(1116, 12), TO_UNSIGNED(1392, 12),
TO_UNSIGNED(1661, 12), TO_UNSIGNED(1765, 12),
TO_UNSIGNED(494, 12), TO_UNSIGNED(542, 12),
TO_UNSIGNED(978, 12), TO_UNSIGNED(1380, 12),
TO_UNSIGNED(1664, 12), TO_UNSIGNED(1801, 12),
TO_UNSIGNED(496, 12), TO_UNSIGNED(544, 12),
TO_UNSIGNED(984, 12), TO_UNSIGNED(1386, 12),
TO_UNSIGNED(1667, 12), TO_UNSIGNED(1789, 12),
TO_UNSIGNED(130, 12), TO_UNSIGNED(498, 12),
TO_UNSIGNED(546, 12), TO_UNSIGNED(990, 12),
TO_UNSIGNED(1673, 12), TO_UNSIGNED(1795, 12),
TO_UNSIGNED(78, 12), TO_UNSIGNED(500, 12),
TO_UNSIGNED(548, 12), TO_UNSIGNED(996, 12),
TO_UNSIGNED(1670, 12), TO_UNSIGNED(1807, 12),
TO_UNSIGNED(502, 12), TO_UNSIGNED(550, 12),
TO_UNSIGNED(1002, 12), TO_UNSIGNED(1272, 12),
TO_UNSIGNED(1676, 12), TO_UNSIGNED(1783, 12),
TO_UNSIGNED(6, 12), TO_UNSIGNED(504, 12),
TO_UNSIGNED(552, 12), TO_UNSIGNED(1008, 12),
TO_UNSIGNED(1278, 12), TO_UNSIGNED(1679, 12),
TO_UNSIGNED(506, 12), TO_UNSIGNED(554, 12),
TO_UNSIGNED(1014, 12), TO_UNSIGNED(1284, 12),
TO_UNSIGNED(1682, 12), TO_UNSIGNED(1813, 12),
TO_UNSIGNED(136, 12), TO_UNSIGNED(508, 12),
TO_UNSIGNED(556, 12), TO_UNSIGNED(1020, 12),
TO_UNSIGNED(1266, 12), TO_UNSIGNED(1484, 12),
TO_UNSIGNED(510, 12), TO_UNSIGNED(558, 12),
TO_UNSIGNED(1026, 12), TO_UNSIGNED(1296, 12),
TO_UNSIGNED(1610, 12), TO_UNSIGNED(1687, 12),
TO_UNSIGNED(512, 12), TO_UNSIGNED(560, 12),
TO_UNSIGNED(1032, 12), TO_UNSIGNED(1290, 12),
TO_UNSIGNED(1613, 12), TO_UNSIGNED(1711, 12),
TO_UNSIGNED(514, 12), TO_UNSIGNED(562, 12),
TO_UNSIGNED(1038, 12), TO_UNSIGNED(1308, 12),
TO_UNSIGNED(1622, 12), TO_UNSIGNED(1699, 12),
TO_UNSIGNED(516, 12), TO_UNSIGNED(564, 12),
TO_UNSIGNED(1044, 12), TO_UNSIGNED(1302, 12),
TO_UNSIGNED(1625, 12), TO_UNSIGNED(1705, 12),
TO_UNSIGNED(518, 12), TO_UNSIGNED(566, 12),
TO_UNSIGNED(1050, 12), TO_UNSIGNED(1314, 12),
TO_UNSIGNED(1628, 12), TO_UNSIGNED(1693, 12),
TO_UNSIGNED(520, 12), TO_UNSIGNED(568, 12),
TO_UNSIGNED(1056, 12), TO_UNSIGNED(1320, 12),
TO_UNSIGNED(1637, 12), TO_UNSIGNED(1717, 12),
TO_UNSIGNED(523, 12), TO_UNSIGNED(570, 12),
TO_UNSIGNED(695, 12), TO_UNSIGNED(877, 12),
TO_UNSIGNED(1445, 12), TO_UNSIGNED(1535, 12),
TO_UNSIGNED(525, 12), TO_UNSIGNED(572, 12),
TO_UNSIGNED(701, 12), TO_UNSIGNED(880, 12),
TO_UNSIGNED(1448, 12), TO_UNSIGNED(1541, 12),
TO_UNSIGNED(527, 12), TO_UNSIGNED(574, 12),
TO_UNSIGNED(707, 12), TO_UNSIGNED(883, 12),
TO_UNSIGNED(1451, 12), TO_UNSIGNED(1559, 12),
TO_UNSIGNED(529, 12), TO_UNSIGNED(576, 12),
TO_UNSIGNED(713, 12), TO_UNSIGNED(886, 12),
TO_UNSIGNED(1454, 12), TO_UNSIGNED(1565, 12),
TO_UNSIGNED(531, 12), TO_UNSIGNED(578, 12),
TO_UNSIGNED(719, 12), TO_UNSIGNED(889, 12),
TO_UNSIGNED(1457, 12), TO_UNSIGNED(1577, 12),
TO_UNSIGNED(533, 12), TO_UNSIGNED(580, 12),
TO_UNSIGNED(725, 12), TO_UNSIGNED(892, 12),
TO_UNSIGNED(1463, 12), TO_UNSIGNED(1571, 12),
TO_UNSIGNED(535, 12), TO_UNSIGNED(582, 12),
TO_UNSIGNED(731, 12), TO_UNSIGNED(895, 12),
TO_UNSIGNED(1460, 12), TO_UNSIGNED(1589, 12),
TO_UNSIGNED(537, 12), TO_UNSIGNED(584, 12),
TO_UNSIGNED(737, 12), TO_UNSIGNED(898, 12),
TO_UNSIGNED(1487, 12), TO_UNSIGNED(1583, 12),
TO_UNSIGNED(539, 12), TO_UNSIGNED(586, 12),
TO_UNSIGNED(743, 12), TO_UNSIGNED(901, 12),
TO_UNSIGNED(1601, 12), TO_UNSIGNED(1619, 12),
TO_UNSIGNED(541, 12), TO_UNSIGNED(588, 12),
TO_UNSIGNED(749, 12), TO_UNSIGNED(904, 12),
TO_UNSIGNED(1400, 12), TO_UNSIGNED(1607, 12),
TO_UNSIGNED(543, 12), TO_UNSIGNED(590, 12),
TO_UNSIGNED(755, 12), TO_UNSIGNED(835, 12),
TO_UNSIGNED(1403, 12), TO_UNSIGNED(1595, 12),
TO_UNSIGNED(5, 12), TO_UNSIGNED(545, 12),
TO_UNSIGNED(592, 12), TO_UNSIGNED(761, 12),
TO_UNSIGNED(838, 12), TO_UNSIGNED(1406, 12),
TO_UNSIGNED(547, 12), TO_UNSIGNED(594, 12),
TO_UNSIGNED(767, 12), TO_UNSIGNED(841, 12),
TO_UNSIGNED(1415, 12), TO_UNSIGNED(1481, 12),
TO_UNSIGNED(549, 12), TO_UNSIGNED(596, 12),
TO_UNSIGNED(773, 12), TO_UNSIGNED(844, 12),
TO_UNSIGNED(1418, 12), TO_UNSIGNED(1469, 12),
TO_UNSIGNED(551, 12), TO_UNSIGNED(598, 12),
TO_UNSIGNED(779, 12), TO_UNSIGNED(847, 12),
TO_UNSIGNED(1421, 12), TO_UNSIGNED(1475, 12),
TO_UNSIGNED(553, 12), TO_UNSIGNED(600, 12),
TO_UNSIGNED(785, 12), TO_UNSIGNED(850, 12),
TO_UNSIGNED(1409, 12), TO_UNSIGNED(1499, 12),
TO_UNSIGNED(555, 12), TO_UNSIGNED(602, 12),
TO_UNSIGNED(791, 12), TO_UNSIGNED(853, 12),
TO_UNSIGNED(1412, 12), TO_UNSIGNED(1505, 12),
TO_UNSIGNED(557, 12), TO_UNSIGNED(604, 12),
TO_UNSIGNED(797, 12), TO_UNSIGNED(856, 12),
TO_UNSIGNED(1436, 12), TO_UNSIGNED(1511, 12),
TO_UNSIGNED(559, 12), TO_UNSIGNED(606, 12),
TO_UNSIGNED(803, 12), TO_UNSIGNED(859, 12),
TO_UNSIGNED(1433, 12), TO_UNSIGNED(1493, 12),
TO_UNSIGNED(561, 12), TO_UNSIGNED(608, 12),
TO_UNSIGNED(809, 12), TO_UNSIGNED(862, 12),
TO_UNSIGNED(1424, 12), TO_UNSIGNED(1517, 12),
TO_UNSIGNED(563, 12), TO_UNSIGNED(610, 12),
TO_UNSIGNED(815, 12), TO_UNSIGNED(865, 12),
TO_UNSIGNED(1427, 12), TO_UNSIGNED(1529, 12),
TO_UNSIGNED(565, 12), TO_UNSIGNED(612, 12),
TO_UNSIGNED(821, 12), TO_UNSIGNED(868, 12),
TO_UNSIGNED(1430, 12), TO_UNSIGNED(1523, 12),
TO_UNSIGNED(567, 12), TO_UNSIGNED(614, 12),
TO_UNSIGNED(827, 12), TO_UNSIGNED(871, 12),
TO_UNSIGNED(1439, 12), TO_UNSIGNED(1547, 12),
TO_UNSIGNED(569, 12), TO_UNSIGNED(616, 12),
TO_UNSIGNED(833, 12), TO_UNSIGNED(874, 12),
TO_UNSIGNED(1442, 12), TO_UNSIGNED(1553, 12),
TO_UNSIGNED(76, 12), TO_UNSIGNED(571, 12),
TO_UNSIGNED(922, 12), TO_UNSIGNED(1105, 12),
TO_UNSIGNED(1339, 12), TO_UNSIGNED(1796, 12),
TO_UNSIGNED(573, 12), TO_UNSIGNED(925, 12),
TO_UNSIGNED(1111, 12), TO_UNSIGNED(1345, 12),
TO_UNSIGNED(1615, 12), TO_UNSIGNED(1808, 12),
TO_UNSIGNED(575, 12), TO_UNSIGNED(928, 12),
TO_UNSIGNED(1117, 12), TO_UNSIGNED(1369, 12),
TO_UNSIGNED(1784, 12), TO_UNSIGNED(1820, 12),
TO_UNSIGNED(7, 12), TO_UNSIGNED(13, 12),
TO_UNSIGNED(577, 12), TO_UNSIGNED(931, 12),
TO_UNSIGNED(979, 12), TO_UNSIGNED(1375, 12),
TO_UNSIGNED(16, 12), TO_UNSIGNED(579, 12),
TO_UNSIGNED(934, 12), TO_UNSIGNED(985, 12),
TO_UNSIGNED(1363, 12), TO_UNSIGNED(1814, 12),
TO_UNSIGNED(19, 12), TO_UNSIGNED(137, 12),
TO_UNSIGNED(581, 12), TO_UNSIGNED(937, 12),
TO_UNSIGNED(991, 12), TO_UNSIGNED(1393, 12),
TO_UNSIGNED(22, 12), TO_UNSIGNED(583, 12),
TO_UNSIGNED(940, 12), TO_UNSIGNED(997, 12),
TO_UNSIGNED(1381, 12), TO_UNSIGNED(1688, 12),
TO_UNSIGNED(25, 12), TO_UNSIGNED(585, 12),
TO_UNSIGNED(943, 12), TO_UNSIGNED(1003, 12),
TO_UNSIGNED(1387, 12), TO_UNSIGNED(1712, 12),
TO_UNSIGNED(28, 12), TO_UNSIGNED(131, 12),
TO_UNSIGNED(587, 12), TO_UNSIGNED(946, 12),
TO_UNSIGNED(1009, 12), TO_UNSIGNED(1700, 12),
TO_UNSIGNED(31, 12), TO_UNSIGNED(79, 12),
TO_UNSIGNED(589, 12), TO_UNSIGNED(949, 12),
TO_UNSIGNED(1015, 12), TO_UNSIGNED(1706, 12),
TO_UNSIGNED(34, 12), TO_UNSIGNED(591, 12),
TO_UNSIGNED(952, 12), TO_UNSIGNED(1021, 12),
TO_UNSIGNED(1273, 12), TO_UNSIGNED(1694, 12),
TO_UNSIGNED(37, 12), TO_UNSIGNED(593, 12),
TO_UNSIGNED(955, 12), TO_UNSIGNED(1027, 12),
TO_UNSIGNED(1279, 12), TO_UNSIGNED(1718, 12),
TO_UNSIGNED(40, 12), TO_UNSIGNED(595, 12),
TO_UNSIGNED(958, 12), TO_UNSIGNED(1033, 12),
TO_UNSIGNED(1285, 12), TO_UNSIGNED(1730, 12),
TO_UNSIGNED(43, 12), TO_UNSIGNED(597, 12),
TO_UNSIGNED(961, 12), TO_UNSIGNED(1039, 12),
TO_UNSIGNED(1267, 12), TO_UNSIGNED(1724, 12),
TO_UNSIGNED(46, 12), TO_UNSIGNED(599, 12),
TO_UNSIGNED(964, 12), TO_UNSIGNED(1045, 12),
TO_UNSIGNED(1297, 12), TO_UNSIGNED(1736, 12),
TO_UNSIGNED(49, 12), TO_UNSIGNED(601, 12),
TO_UNSIGNED(967, 12), TO_UNSIGNED(1051, 12),
TO_UNSIGNED(1291, 12), TO_UNSIGNED(1772, 12),
TO_UNSIGNED(52, 12), TO_UNSIGNED(603, 12),
TO_UNSIGNED(970, 12), TO_UNSIGNED(1057, 12),
TO_UNSIGNED(1309, 12), TO_UNSIGNED(1778, 12),
TO_UNSIGNED(55, 12), TO_UNSIGNED(605, 12),
TO_UNSIGNED(973, 12), TO_UNSIGNED(1063, 12),
TO_UNSIGNED(1303, 12), TO_UNSIGNED(1742, 12),
TO_UNSIGNED(58, 12), TO_UNSIGNED(607, 12),
TO_UNSIGNED(976, 12), TO_UNSIGNED(1069, 12),
TO_UNSIGNED(1315, 12), TO_UNSIGNED(1748, 12),
TO_UNSIGNED(61, 12), TO_UNSIGNED(609, 12),
TO_UNSIGNED(907, 12), TO_UNSIGNED(1075, 12),
TO_UNSIGNED(1321, 12), TO_UNSIGNED(1754, 12),
TO_UNSIGNED(64, 12), TO_UNSIGNED(611, 12),
TO_UNSIGNED(910, 12), TO_UNSIGNED(1081, 12),
TO_UNSIGNED(1333, 12), TO_UNSIGNED(1760, 12),
TO_UNSIGNED(67, 12), TO_UNSIGNED(613, 12),
TO_UNSIGNED(913, 12), TO_UNSIGNED(1087, 12),
TO_UNSIGNED(1327, 12), TO_UNSIGNED(1766, 12),
TO_UNSIGNED(70, 12), TO_UNSIGNED(615, 12),
TO_UNSIGNED(916, 12), TO_UNSIGNED(1093, 12),
TO_UNSIGNED(1351, 12), TO_UNSIGNED(1802, 12),
TO_UNSIGNED(73, 12), TO_UNSIGNED(617, 12),
TO_UNSIGNED(919, 12), TO_UNSIGNED(1099, 12),
TO_UNSIGNED(1357, 12), TO_UNSIGNED(1790, 12),
TO_UNSIGNED(8, 12), TO_UNSIGNED(132, 12),
TO_UNSIGNED(671, 12), TO_UNSIGNED(1028, 12),
TO_UNSIGNED(1196, 12), TO_UNSIGNED(1684, 12),
TO_UNSIGNED(1685, 12), TO_UNSIGNED(80, 12),
TO_UNSIGNED(85, 12), TO_UNSIGNED(674, 12),
TO_UNSIGNED(1034, 12), TO_UNSIGNED(1217, 12),
TO_UNSIGNED(1815, 12), TO_UNSIGNED(1822, 12),
TO_UNSIGNED(87, 12), TO_UNSIGNED(138, 12),
TO_UNSIGNED(142, 12), TO_UNSIGNED(677, 12),
TO_UNSIGNED(1040, 12), TO_UNSIGNED(1214, 12),
TO_UNSIGNED(1274, 12), TO_UNSIGNED(89, 12),
TO_UNSIGNED(144, 12), TO_UNSIGNED(680, 12),
TO_UNSIGNED(1046, 12), TO_UNSIGNED(1223, 12),
TO_UNSIGNED(1280, 12), TO_UNSIGNED(1689, 12),
TO_UNSIGNED(91, 12), TO_UNSIGNED(146, 12),
TO_UNSIGNED(683, 12), TO_UNSIGNED(1052, 12),
TO_UNSIGNED(1226, 12), TO_UNSIGNED(1286, 12),
TO_UNSIGNED(1713, 12), TO_UNSIGNED(93, 12),
TO_UNSIGNED(148, 12), TO_UNSIGNED(686, 12),
TO_UNSIGNED(1058, 12), TO_UNSIGNED(1229, 12),
TO_UNSIGNED(1268, 12), TO_UNSIGNED(1701, 12),
TO_UNSIGNED(95, 12), TO_UNSIGNED(150, 12),
TO_UNSIGNED(689, 12), TO_UNSIGNED(1064, 12),
TO_UNSIGNED(1220, 12), TO_UNSIGNED(1298, 12),
TO_UNSIGNED(1707, 12), TO_UNSIGNED(97, 12),
TO_UNSIGNED(152, 12), TO_UNSIGNED(620, 12),
TO_UNSIGNED(1070, 12), TO_UNSIGNED(1235, 12),
TO_UNSIGNED(1292, 12), TO_UNSIGNED(1695, 12),
TO_UNSIGNED(99, 12), TO_UNSIGNED(154, 12),
TO_UNSIGNED(623, 12), TO_UNSIGNED(1076, 12),
TO_UNSIGNED(1238, 12), TO_UNSIGNED(1310, 12),
TO_UNSIGNED(1719, 12), TO_UNSIGNED(101, 12),
TO_UNSIGNED(156, 12), TO_UNSIGNED(626, 12),
TO_UNSIGNED(1082, 12), TO_UNSIGNED(1241, 12),
TO_UNSIGNED(1304, 12), TO_UNSIGNED(1731, 12),
TO_UNSIGNED(103, 12), TO_UNSIGNED(158, 12),
TO_UNSIGNED(629, 12), TO_UNSIGNED(1088, 12),
TO_UNSIGNED(1232, 12), TO_UNSIGNED(1316, 12),
TO_UNSIGNED(1725, 12), TO_UNSIGNED(105, 12),
TO_UNSIGNED(160, 12), TO_UNSIGNED(632, 12),
TO_UNSIGNED(1094, 12), TO_UNSIGNED(1253, 12),
TO_UNSIGNED(1322, 12), TO_UNSIGNED(1737, 12),
TO_UNSIGNED(107, 12), TO_UNSIGNED(162, 12),
TO_UNSIGNED(635, 12), TO_UNSIGNED(1100, 12),
TO_UNSIGNED(1244, 12), TO_UNSIGNED(1334, 12),
TO_UNSIGNED(1773, 12), TO_UNSIGNED(109, 12),
TO_UNSIGNED(164, 12), TO_UNSIGNED(638, 12),
TO_UNSIGNED(1106, 12), TO_UNSIGNED(1247, 12),
TO_UNSIGNED(1328, 12), TO_UNSIGNED(1779, 12),
TO_UNSIGNED(111, 12), TO_UNSIGNED(166, 12),
TO_UNSIGNED(641, 12), TO_UNSIGNED(1112, 12),
TO_UNSIGNED(1250, 12), TO_UNSIGNED(1352, 12),
TO_UNSIGNED(1743, 12), TO_UNSIGNED(113, 12),
TO_UNSIGNED(168, 12), TO_UNSIGNED(644, 12),
TO_UNSIGNED(1118, 12), TO_UNSIGNED(1259, 12),
TO_UNSIGNED(1358, 12), TO_UNSIGNED(1749, 12),
TO_UNSIGNED(115, 12), TO_UNSIGNED(170, 12),
TO_UNSIGNED(647, 12), TO_UNSIGNED(980, 12),
TO_UNSIGNED(1256, 12), TO_UNSIGNED(1340, 12),
TO_UNSIGNED(1755, 12), TO_UNSIGNED(117, 12),
TO_UNSIGNED(172, 12), TO_UNSIGNED(650, 12),
TO_UNSIGNED(986, 12), TO_UNSIGNED(1265, 12),
TO_UNSIGNED(1346, 12), TO_UNSIGNED(1761, 12),
TO_UNSIGNED(119, 12), TO_UNSIGNED(174, 12),
TO_UNSIGNED(653, 12), TO_UNSIGNED(992, 12),
TO_UNSIGNED(1262, 12), TO_UNSIGNED(1370, 12),
TO_UNSIGNED(1767, 12), TO_UNSIGNED(121, 12),
TO_UNSIGNED(176, 12), TO_UNSIGNED(656, 12),
TO_UNSIGNED(998, 12), TO_UNSIGNED(1199, 12),
TO_UNSIGNED(1376, 12), TO_UNSIGNED(1803, 12),
TO_UNSIGNED(123, 12), TO_UNSIGNED(178, 12),
TO_UNSIGNED(659, 12), TO_UNSIGNED(1004, 12),
TO_UNSIGNED(1202, 12), TO_UNSIGNED(1364, 12),
TO_UNSIGNED(1791, 12), TO_UNSIGNED(125, 12),
TO_UNSIGNED(180, 12), TO_UNSIGNED(662, 12),
TO_UNSIGNED(1010, 12), TO_UNSIGNED(1205, 12),
TO_UNSIGNED(1394, 12), TO_UNSIGNED(1797, 12),
TO_UNSIGNED(127, 12), TO_UNSIGNED(182, 12),
TO_UNSIGNED(665, 12), TO_UNSIGNED(1016, 12),
TO_UNSIGNED(1208, 12), TO_UNSIGNED(1382, 12),
TO_UNSIGNED(1809, 12), TO_UNSIGNED(129, 12),
TO_UNSIGNED(184, 12), TO_UNSIGNED(668, 12),
TO_UNSIGNED(1022, 12), TO_UNSIGNED(1211, 12),
TO_UNSIGNED(1388, 12), TO_UNSIGNED(1785, 12),
TO_UNSIGNED(187, 12), TO_UNSIGNED(836, 12),
TO_UNSIGNED(1083, 12), TO_UNSIGNED(1140, 12),
TO_UNSIGNED(1371, 12), TO_UNSIGNED(1686, 12),
TO_UNSIGNED(1690, 12), TO_UNSIGNED(189, 12),
TO_UNSIGNED(839, 12), TO_UNSIGNED(1089, 12),
TO_UNSIGNED(1143, 12), TO_UNSIGNED(1377, 12),
TO_UNSIGNED(1714, 12), TO_UNSIGNED(1823, 12),
TO_UNSIGNED(143, 12), TO_UNSIGNED(191, 12),
TO_UNSIGNED(842, 12), TO_UNSIGNED(1095, 12),
TO_UNSIGNED(1146, 12), TO_UNSIGNED(1365, 12),
TO_UNSIGNED(1702, 12), TO_UNSIGNED(145, 12),
TO_UNSIGNED(193, 12), TO_UNSIGNED(845, 12),
TO_UNSIGNED(1101, 12), TO_UNSIGNED(1149, 12),
TO_UNSIGNED(1395, 12), TO_UNSIGNED(1708, 12),
TO_UNSIGNED(147, 12), TO_UNSIGNED(195, 12),
TO_UNSIGNED(848, 12), TO_UNSIGNED(1107, 12),
TO_UNSIGNED(1152, 12), TO_UNSIGNED(1383, 12),
TO_UNSIGNED(1696, 12), TO_UNSIGNED(149, 12),
TO_UNSIGNED(197, 12), TO_UNSIGNED(851, 12),
TO_UNSIGNED(1113, 12), TO_UNSIGNED(1155, 12),
TO_UNSIGNED(1389, 12), TO_UNSIGNED(1720, 12),
TO_UNSIGNED(133, 12), TO_UNSIGNED(151, 12),
TO_UNSIGNED(199, 12), TO_UNSIGNED(854, 12),
TO_UNSIGNED(1119, 12), TO_UNSIGNED(1158, 12),
TO_UNSIGNED(1732, 12), TO_UNSIGNED(81, 12),
TO_UNSIGNED(153, 12), TO_UNSIGNED(201, 12),
TO_UNSIGNED(857, 12), TO_UNSIGNED(981, 12),
TO_UNSIGNED(1161, 12), TO_UNSIGNED(1726, 12),
TO_UNSIGNED(155, 12), TO_UNSIGNED(203, 12),
TO_UNSIGNED(860, 12), TO_UNSIGNED(987, 12),
TO_UNSIGNED(1164, 12), TO_UNSIGNED(1275, 12),
TO_UNSIGNED(1738, 12), TO_UNSIGNED(157, 12),
TO_UNSIGNED(205, 12), TO_UNSIGNED(863, 12),
TO_UNSIGNED(993, 12), TO_UNSIGNED(1167, 12),
TO_UNSIGNED(1281, 12), TO_UNSIGNED(1774, 12),
TO_UNSIGNED(159, 12), TO_UNSIGNED(207, 12),
TO_UNSIGNED(866, 12), TO_UNSIGNED(999, 12),
TO_UNSIGNED(1170, 12), TO_UNSIGNED(1287, 12),
TO_UNSIGNED(1780, 12), TO_UNSIGNED(161, 12),
TO_UNSIGNED(209, 12), TO_UNSIGNED(869, 12),
TO_UNSIGNED(1005, 12), TO_UNSIGNED(1173, 12),
TO_UNSIGNED(1269, 12), TO_UNSIGNED(1744, 12),
TO_UNSIGNED(163, 12), TO_UNSIGNED(211, 12),
TO_UNSIGNED(872, 12), TO_UNSIGNED(1011, 12),
TO_UNSIGNED(1176, 12), TO_UNSIGNED(1299, 12),
TO_UNSIGNED(1750, 12), TO_UNSIGNED(165, 12),
TO_UNSIGNED(213, 12), TO_UNSIGNED(875, 12),
TO_UNSIGNED(1017, 12), TO_UNSIGNED(1179, 12),
TO_UNSIGNED(1293, 12), TO_UNSIGNED(1756, 12),
TO_UNSIGNED(167, 12), TO_UNSIGNED(215, 12),
TO_UNSIGNED(878, 12), TO_UNSIGNED(1023, 12),
TO_UNSIGNED(1182, 12), TO_UNSIGNED(1311, 12),
TO_UNSIGNED(1762, 12), TO_UNSIGNED(169, 12),
TO_UNSIGNED(217, 12), TO_UNSIGNED(881, 12),
TO_UNSIGNED(1029, 12), TO_UNSIGNED(1185, 12),
TO_UNSIGNED(1305, 12), TO_UNSIGNED(1768, 12),
TO_UNSIGNED(171, 12), TO_UNSIGNED(219, 12),
TO_UNSIGNED(884, 12), TO_UNSIGNED(1035, 12),
TO_UNSIGNED(1188, 12), TO_UNSIGNED(1317, 12),
TO_UNSIGNED(1804, 12), TO_UNSIGNED(173, 12),
TO_UNSIGNED(221, 12), TO_UNSIGNED(887, 12),
TO_UNSIGNED(1041, 12), TO_UNSIGNED(1191, 12),
TO_UNSIGNED(1323, 12), TO_UNSIGNED(1792, 12),
TO_UNSIGNED(175, 12), TO_UNSIGNED(223, 12),
TO_UNSIGNED(890, 12), TO_UNSIGNED(1047, 12),
TO_UNSIGNED(1122, 12), TO_UNSIGNED(1335, 12),
TO_UNSIGNED(1798, 12), TO_UNSIGNED(177, 12),
TO_UNSIGNED(225, 12), TO_UNSIGNED(893, 12),
TO_UNSIGNED(1053, 12), TO_UNSIGNED(1125, 12),
TO_UNSIGNED(1329, 12), TO_UNSIGNED(1810, 12),
TO_UNSIGNED(179, 12), TO_UNSIGNED(227, 12),
TO_UNSIGNED(896, 12), TO_UNSIGNED(1059, 12),
TO_UNSIGNED(1128, 12), TO_UNSIGNED(1353, 12),
TO_UNSIGNED(1786, 12), TO_UNSIGNED(9, 12),
TO_UNSIGNED(181, 12), TO_UNSIGNED(229, 12),
TO_UNSIGNED(899, 12), TO_UNSIGNED(1065, 12),
TO_UNSIGNED(1131, 12), TO_UNSIGNED(1359, 12),
TO_UNSIGNED(183, 12), TO_UNSIGNED(231, 12),
TO_UNSIGNED(902, 12), TO_UNSIGNED(1071, 12),
TO_UNSIGNED(1134, 12), TO_UNSIGNED(1341, 12),
TO_UNSIGNED(1816, 12), TO_UNSIGNED(139, 12),
TO_UNSIGNED(185, 12), TO_UNSIGNED(233, 12),
TO_UNSIGNED(905, 12), TO_UNSIGNED(1077, 12),
TO_UNSIGNED(1137, 12), TO_UNSIGNED(1347, 12),
TO_UNSIGNED(283, 12), TO_UNSIGNED(331, 12),
TO_UNSIGNED(1000, 12), TO_UNSIGNED(1123, 12),
TO_UNSIGNED(1300, 12), TO_UNSIGNED(1616, 12),
TO_UNSIGNED(1721, 12), TO_UNSIGNED(285, 12),
TO_UNSIGNED(333, 12), TO_UNSIGNED(1006, 12),
TO_UNSIGNED(1126, 12), TO_UNSIGNED(1294, 12),
TO_UNSIGNED(1733, 12), TO_UNSIGNED(1821, 12),
TO_UNSIGNED(14, 12), TO_UNSIGNED(287, 12),
TO_UNSIGNED(335, 12), TO_UNSIGNED(1012, 12),
TO_UNSIGNED(1129, 12), TO_UNSIGNED(1312, 12),
TO_UNSIGNED(1727, 12), TO_UNSIGNED(17, 12),
TO_UNSIGNED(289, 12), TO_UNSIGNED(337, 12),
TO_UNSIGNED(1018, 12), TO_UNSIGNED(1132, 12),
TO_UNSIGNED(1306, 12), TO_UNSIGNED(1739, 12),
TO_UNSIGNED(20, 12), TO_UNSIGNED(291, 12),
TO_UNSIGNED(339, 12), TO_UNSIGNED(1024, 12),
TO_UNSIGNED(1135, 12), TO_UNSIGNED(1318, 12),
TO_UNSIGNED(1775, 12), TO_UNSIGNED(23, 12),
TO_UNSIGNED(293, 12), TO_UNSIGNED(341, 12),
TO_UNSIGNED(1030, 12), TO_UNSIGNED(1138, 12),
TO_UNSIGNED(1324, 12), TO_UNSIGNED(1781, 12),
TO_UNSIGNED(26, 12), TO_UNSIGNED(295, 12),
TO_UNSIGNED(343, 12), TO_UNSIGNED(1036, 12),
TO_UNSIGNED(1141, 12), TO_UNSIGNED(1336, 12),
TO_UNSIGNED(1745, 12), TO_UNSIGNED(29, 12),
TO_UNSIGNED(297, 12), TO_UNSIGNED(345, 12),
TO_UNSIGNED(1042, 12), TO_UNSIGNED(1144, 12),
TO_UNSIGNED(1330, 12), TO_UNSIGNED(1751, 12),
TO_UNSIGNED(32, 12), TO_UNSIGNED(299, 12),
TO_UNSIGNED(347, 12), TO_UNSIGNED(1048, 12),
TO_UNSIGNED(1147, 12), TO_UNSIGNED(1354, 12),
TO_UNSIGNED(1757, 12), TO_UNSIGNED(35, 12),
TO_UNSIGNED(301, 12), TO_UNSIGNED(349, 12),
TO_UNSIGNED(1054, 12), TO_UNSIGNED(1150, 12),
TO_UNSIGNED(1360, 12), TO_UNSIGNED(1763, 12),
TO_UNSIGNED(38, 12), TO_UNSIGNED(303, 12),
TO_UNSIGNED(351, 12), TO_UNSIGNED(1060, 12),
TO_UNSIGNED(1153, 12), TO_UNSIGNED(1342, 12),
TO_UNSIGNED(1769, 12), TO_UNSIGNED(41, 12),
TO_UNSIGNED(305, 12), TO_UNSIGNED(353, 12),
TO_UNSIGNED(1066, 12), TO_UNSIGNED(1156, 12),
TO_UNSIGNED(1348, 12), TO_UNSIGNED(1805, 12),
TO_UNSIGNED(44, 12), TO_UNSIGNED(307, 12),
TO_UNSIGNED(355, 12), TO_UNSIGNED(1072, 12),
TO_UNSIGNED(1159, 12), TO_UNSIGNED(1372, 12),
TO_UNSIGNED(1793, 12), TO_UNSIGNED(47, 12),
TO_UNSIGNED(309, 12), TO_UNSIGNED(357, 12),
TO_UNSIGNED(1078, 12), TO_UNSIGNED(1162, 12),
TO_UNSIGNED(1378, 12), TO_UNSIGNED(1799, 12),
TO_UNSIGNED(50, 12), TO_UNSIGNED(311, 12),
TO_UNSIGNED(359, 12), TO_UNSIGNED(1084, 12),
TO_UNSIGNED(1165, 12), TO_UNSIGNED(1366, 12),
TO_UNSIGNED(1811, 12), TO_UNSIGNED(53, 12),
TO_UNSIGNED(313, 12), TO_UNSIGNED(361, 12),
TO_UNSIGNED(1090, 12), TO_UNSIGNED(1168, 12),
TO_UNSIGNED(1396, 12), TO_UNSIGNED(1787, 12),
TO_UNSIGNED(10, 12), TO_UNSIGNED(56, 12),
TO_UNSIGNED(315, 12), TO_UNSIGNED(363, 12),
TO_UNSIGNED(1096, 12), TO_UNSIGNED(1171, 12),
TO_UNSIGNED(1384, 12), TO_UNSIGNED(59, 12),
TO_UNSIGNED(317, 12), TO_UNSIGNED(365, 12),
TO_UNSIGNED(1102, 12), TO_UNSIGNED(1174, 12),
TO_UNSIGNED(1390, 12), TO_UNSIGNED(1817, 12),
TO_UNSIGNED(62, 12), TO_UNSIGNED(134, 12),
TO_UNSIGNED(140, 12), TO_UNSIGNED(319, 12),
TO_UNSIGNED(367, 12), TO_UNSIGNED(1108, 12),
TO_UNSIGNED(1177, 12), TO_UNSIGNED(65, 12),
TO_UNSIGNED(82, 12), TO_UNSIGNED(321, 12),
TO_UNSIGNED(369, 12), TO_UNSIGNED(1114, 12),
TO_UNSIGNED(1180, 12), TO_UNSIGNED(1691, 12),
TO_UNSIGNED(68, 12), TO_UNSIGNED(323, 12),
TO_UNSIGNED(371, 12), TO_UNSIGNED(1120, 12),
TO_UNSIGNED(1183, 12), TO_UNSIGNED(1276, 12),
TO_UNSIGNED(1715, 12), TO_UNSIGNED(71, 12),
TO_UNSIGNED(325, 12), TO_UNSIGNED(373, 12),
TO_UNSIGNED(982, 12), TO_UNSIGNED(1186, 12),
TO_UNSIGNED(1282, 12), TO_UNSIGNED(1703, 12),
TO_UNSIGNED(74, 12), TO_UNSIGNED(327, 12),
TO_UNSIGNED(375, 12), TO_UNSIGNED(988, 12),
TO_UNSIGNED(1189, 12), TO_UNSIGNED(1288, 12),
TO_UNSIGNED(1709, 12), TO_UNSIGNED(77, 12),
TO_UNSIGNED(329, 12), TO_UNSIGNED(377, 12),
TO_UNSIGNED(994, 12), TO_UNSIGNED(1192, 12),
TO_UNSIGNED(1270, 12), TO_UNSIGNED(1697, 12),
TO_UNSIGNED(427, 12), TO_UNSIGNED(475, 12),
TO_UNSIGNED(944, 12), TO_UNSIGNED(1025, 12),
TO_UNSIGNED(1169, 12), TO_UNSIGNED(1343, 12),
TO_UNSIGNED(1752, 12), TO_UNSIGNED(429, 12),
TO_UNSIGNED(477, 12), TO_UNSIGNED(947, 12),
TO_UNSIGNED(1031, 12), TO_UNSIGNED(1172, 12),
TO_UNSIGNED(1349, 12), TO_UNSIGNED(1758, 12),
TO_UNSIGNED(431, 12), TO_UNSIGNED(479, 12),
TO_UNSIGNED(950, 12), TO_UNSIGNED(1037, 12),
TO_UNSIGNED(1175, 12), TO_UNSIGNED(1373, 12),
TO_UNSIGNED(1764, 12), TO_UNSIGNED(433, 12),
TO_UNSIGNED(481, 12), TO_UNSIGNED(953, 12),
TO_UNSIGNED(1043, 12), TO_UNSIGNED(1178, 12),
TO_UNSIGNED(1379, 12), TO_UNSIGNED(1770, 12),
TO_UNSIGNED(435, 12), TO_UNSIGNED(483, 12),
TO_UNSIGNED(956, 12), TO_UNSIGNED(1049, 12),
TO_UNSIGNED(1181, 12), TO_UNSIGNED(1367, 12),
TO_UNSIGNED(1806, 12), TO_UNSIGNED(437, 12),
TO_UNSIGNED(485, 12), TO_UNSIGNED(959, 12),
TO_UNSIGNED(1055, 12), TO_UNSIGNED(1184, 12),
TO_UNSIGNED(1397, 12), TO_UNSIGNED(1794, 12),
TO_UNSIGNED(439, 12), TO_UNSIGNED(487, 12),
TO_UNSIGNED(962, 12), TO_UNSIGNED(1061, 12),
TO_UNSIGNED(1187, 12), TO_UNSIGNED(1385, 12),
TO_UNSIGNED(1800, 12), TO_UNSIGNED(441, 12),
TO_UNSIGNED(489, 12), TO_UNSIGNED(965, 12),
TO_UNSIGNED(1067, 12), TO_UNSIGNED(1190, 12),
TO_UNSIGNED(1391, 12), TO_UNSIGNED(1812, 12),
TO_UNSIGNED(135, 12), TO_UNSIGNED(443, 12),
TO_UNSIGNED(491, 12), TO_UNSIGNED(968, 12),
TO_UNSIGNED(1073, 12), TO_UNSIGNED(1193, 12),
TO_UNSIGNED(1788, 12), TO_UNSIGNED(11, 12),
TO_UNSIGNED(83, 12), TO_UNSIGNED(445, 12),
TO_UNSIGNED(493, 12), TO_UNSIGNED(971, 12),
TO_UNSIGNED(1079, 12), TO_UNSIGNED(1124, 12),
TO_UNSIGNED(447, 12), TO_UNSIGNED(495, 12),
TO_UNSIGNED(974, 12), TO_UNSIGNED(1085, 12),
TO_UNSIGNED(1127, 12), TO_UNSIGNED(1277, 12),
TO_UNSIGNED(1818, 12), TO_UNSIGNED(141, 12),
TO_UNSIGNED(449, 12), TO_UNSIGNED(497, 12),
TO_UNSIGNED(977, 12), TO_UNSIGNED(1091, 12),
TO_UNSIGNED(1130, 12), TO_UNSIGNED(1283, 12),
TO_UNSIGNED(451, 12), TO_UNSIGNED(499, 12),
TO_UNSIGNED(908, 12), TO_UNSIGNED(1097, 12),
TO_UNSIGNED(1133, 12), TO_UNSIGNED(1289, 12),
TO_UNSIGNED(1692, 12), TO_UNSIGNED(453, 12),
TO_UNSIGNED(501, 12), TO_UNSIGNED(911, 12),
TO_UNSIGNED(1103, 12), TO_UNSIGNED(1136, 12),
TO_UNSIGNED(1271, 12), TO_UNSIGNED(1716, 12),
TO_UNSIGNED(455, 12), TO_UNSIGNED(503, 12),
TO_UNSIGNED(914, 12), TO_UNSIGNED(1109, 12),
TO_UNSIGNED(1139, 12), TO_UNSIGNED(1301, 12),
TO_UNSIGNED(1704, 12), TO_UNSIGNED(457, 12),
TO_UNSIGNED(505, 12), TO_UNSIGNED(917, 12),
TO_UNSIGNED(1115, 12), TO_UNSIGNED(1142, 12),
TO_UNSIGNED(1295, 12), TO_UNSIGNED(1710, 12),
TO_UNSIGNED(459, 12), TO_UNSIGNED(507, 12),
TO_UNSIGNED(920, 12), TO_UNSIGNED(1121, 12),
TO_UNSIGNED(1145, 12), TO_UNSIGNED(1313, 12),
TO_UNSIGNED(1698, 12), TO_UNSIGNED(461, 12),
TO_UNSIGNED(509, 12), TO_UNSIGNED(923, 12),
TO_UNSIGNED(983, 12), TO_UNSIGNED(1148, 12),
TO_UNSIGNED(1307, 12), TO_UNSIGNED(1722, 12),
TO_UNSIGNED(463, 12), TO_UNSIGNED(511, 12),
TO_UNSIGNED(926, 12), TO_UNSIGNED(989, 12),
TO_UNSIGNED(1151, 12), TO_UNSIGNED(1319, 12),
TO_UNSIGNED(1734, 12), TO_UNSIGNED(465, 12),
TO_UNSIGNED(513, 12), TO_UNSIGNED(929, 12),
TO_UNSIGNED(995, 12), TO_UNSIGNED(1154, 12),
TO_UNSIGNED(1325, 12), TO_UNSIGNED(1728, 12),
TO_UNSIGNED(467, 12), TO_UNSIGNED(515, 12),
TO_UNSIGNED(932, 12), TO_UNSIGNED(1001, 12),
TO_UNSIGNED(1157, 12), TO_UNSIGNED(1337, 12),
TO_UNSIGNED(1740, 12), TO_UNSIGNED(469, 12),
TO_UNSIGNED(517, 12), TO_UNSIGNED(935, 12),
TO_UNSIGNED(1007, 12), TO_UNSIGNED(1160, 12),
TO_UNSIGNED(1331, 12), TO_UNSIGNED(1776, 12),
TO_UNSIGNED(471, 12), TO_UNSIGNED(519, 12),
TO_UNSIGNED(938, 12), TO_UNSIGNED(1013, 12),
TO_UNSIGNED(1163, 12), TO_UNSIGNED(1355, 12),
TO_UNSIGNED(1782, 12), TO_UNSIGNED(473, 12),
TO_UNSIGNED(521, 12), TO_UNSIGNED(941, 12),
TO_UNSIGNED(1019, 12), TO_UNSIGNED(1166, 12),
TO_UNSIGNED(1361, 12), TO_UNSIGNED(1746, 12)
);
SIGNAL READ_C : UNSIGNED(11 downto 0);
SIGNAL WRITE_C : UNSIGNED(11 downto 0);
SIGNAL ROM_ADR : UNSIGNED(11 downto 0);
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
begin
if reset = '0' then
WRITE_C <= TO_UNSIGNED(0, 12);
elsif clock'event and clock = '1' then
if write_en = '1' then
TEMP := WRITE_C + TO_UNSIGNED(1, 12);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
WRITE_C <= TEMP;
else
WRITE_C <= WRITE_C;
end if;
WE_BIS <= write_en;
IN_BIS <= INPUT_1;
end if;
end process;
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
elsif clock'event and clock = '1' then
if read_en = '1' then
TEMP := READ_C + TO_UNSIGNED(1, 12);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
READ_C <= TEMP;
else
READ_C <= READ_C;
end if;
end if;
end process;
--
--
--
process(clock)
VARIABLE ADR : INTEGER RANGE 0 to 1823;
VARIABLE POS : INTEGER RANGE 0 to 1823;
begin
if clock'event and clock = '1' then
ADR := to_integer( WRITE_C );
ROM_ADR <= ROM( ADR );
end if;
end process;
--
--
--
process(clock)
begin
if clock'event and clock = '1' then
if WE_BIS = '1' then
RAM( to_integer( ROM_ADR ) ) <= IN_BIS;
end if;
OUTPUT_1 <= RAM( to_integer(READ_C) );
end if;
end process;
END cRAM;
| gpl-3.0 | f73412b1bcd08bad34f7e3cd8ba3a2da | 0.636426 | 2.824848 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_uart/src/vvc_cmd_pkg.vhd | 1 | 6,709 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
TRANSMIT, RECEIVE, EXPECT);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := C_DATA_MAX_LENGTH;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
max_receptions : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => FETCH_RESULT, -- Default unless overwritten by a common operation
data => (others => '0'),
max_receptions => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | db6d44b7d614875994a032c7a430b8e8 | 0.449247 | 5.148887 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/coproc_2.vhd | 1 | 3,643 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
-- data1 := UNSIGNED( INPUT_1(7 downto 0) );
-- data2 := UNSIGNED( INPUT_1(15 downto 8) );
-- data3 := UNSIGNED( INPUT_1(23 downto 16) );
-- data4 := UNSIGNED( INPUT_1(31 downto 24) );
-- diff1 := data1 - min_reg; -- 8
-- diff2 := data2 - min_reg; -- 8
-- diff3 := data3 - min_reg; -- 8
-- diff4 := data4 - min_reg; -- 8
-- mult1 := diff1 * beta_reg; -- 24
-- mult2 := diff2 * beta_reg; -- 24
-- mult3 := diff3 * beta_reg; -- 24
-- mult4 := diff4 * beta_reg; -- 24
-- OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
-- OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
-- OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
-- OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
--beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
beta_tmp <= (others => '0');
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | a56f845be779bf34325eca52ef68bfb3 | 0.544881 | 3.113675 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/COMB_RGB_2_YUV.vhd | 1 | 4,378 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity COMB_RGB_2_YUV is
port(
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end COMB_RGB_2_YUV;
architecture rtl of COMB_RGB_2_YUV is
constant s_rgb_30 : UNSIGNED(11 downto 0) := "001001100100";
constant s_rgb_59 : UNSIGNED(11 downto 0) := "010010110010";
constant s_rgb_11 : UNSIGNED(11 downto 0) := "000011101001";
constant s_rgb_17 : UNSIGNED(11 downto 0) := "000101011001";
constant s_rgb_33 : UNSIGNED(11 downto 0) := "001010100110";
constant s_rgb_50 : UNSIGNED(11 downto 0) := "010000000000";
constant s_rgb_42 : UNSIGNED(11 downto 0) := "001101011001";
constant s_rgb_08 : UNSIGNED(11 downto 0) := "000010100110";
constant s_rgb_128 : SIGNED(11 downto 0) := TO_SIGNED(128, 20);
begin
process(INPUT_1)
VARIABLE INPUT_R : UNSIGNED(7 downto 0);
VARIABLE INPUT_G : UNSIGNED(7 downto 0);
VARIABLE INPUT_B : UNSIGNED(7 downto 0);
VARIABLE rgb_in_r_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_g_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_b_reg_Y : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_r_reg_Cb : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_g_reg_Cb : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_b_reg_Cb : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_r_reg_Cr : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_g_reg_Cr : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE rgb_in_b_reg_Cr : UNSIGNED(19 downto 0):= (others => '0');
VARIABLE s_rgb_out_y : SIGNED(20 downto 0):= (others => '0');
VARIABLE s_rgb_out_cb : SIGNED(20 downto 0):= (others => '0');
VARIABLE s_rgb_out_cr : SIGNED(20 downto 0):= (others => '0');
VARIABLE INPUT_Y : SIGNED(8 downto 0);
VARIABLE INPUT_U : SIGNED(8 downto 0);
VARIABLE INPUT_V : SIGNED(8 downto 0);
begin
-- ON ISOLE L'INFORMATION UTILE
INPUT_R := UNSIGNED(INPUT_1( 7 downto 0));
INPUT_G := UNSIGNED(INPUT_1(15 downto 8));
INPUT_B := UNSIGNED(INPUT_1(23 downto 16));
-- ON REALISE TOUTES LES MULTIPLICATIONS PAR DES VALEURS CONSTANTES
rgb_in_r_reg_Y := s_rgb_30 * INPUT_R; -- RESULTAT SUR 20 BITS
rgb_in_g_reg_Y := s_rgb_59 * INPUT_G; -- RESULTAT SUR 20 BITS
rgb_in_b_reg_Y := s_rgb_11 * INPUT_B; -- RESULTAT SUR 20 BITS
rgb_in_r_reg_Cb := s_rgb_17 * INPUT_R; -- RESULTAT SUR 20 BITS
rgb_in_g_reg_Cb := s_rgb_33 * INPUT_G; -- RESULTAT SUR 20 BITS
rgb_in_b_reg_Cb := s_rgb_50 * INPUT_B; -- RESULTAT SUR 20 BITS
rgb_in_r_reg_Cr := s_rgb_50 * INPUT_R; -- RESULTAT SUR 20 BITS
rgb_in_g_reg_Cr := s_rgb_42 * INPUT_G; -- RESULTAT SUR 20 BITS
rgb_in_b_reg_Cr := s_rgb_08 * INPUT_B; -- RESULTAT SUR 20 BITS
-- ON SOMME COMME IL CONVIENT TOUS LES RESULTATS TEMPORAIRES
s_rgb_out_y := SIGNED('0' & rgb_in_r_reg_Y) + (SIGNED('0' & rgb_in_g_reg_Y) + SIGNED('0' & rgb_in_b_reg_Y));
s_rgb_out_cb := (s_rgb_128 - SIGNED('0' & rgb_in_r_reg_Cb)) - (SIGNED('0' & rgb_in_g_reg_Cb) + SIGNED('0' & rgb_in_b_reg_Cb));
s_rgb_out_cr := (s_rgb_128 + SIGNED('0' & rgb_in_r_reg_Cr)) - (SIGNED('0' & rgb_in_g_reg_Cr) - SIGNED('0' & rgb_in_b_reg_Cr));
-- ON RECUPERE SEULEMENT LES BITS QUI NOUS INTERESSENT
INPUT_Y := s_rgb_out_y (20 downto 12);
INPUT_U := s_rgb_out_cb(20 downto 12);
INPUT_V := s_rgb_out_cr(20 downto 12);
-- ON REALISE LA SATURATION DES DONNEES ENTRE 0 ET 255
if ( INPUT_Y > TO_SIGNED(255, 9) ) then INPUT_Y := TO_SIGNED(255, 9); elsif ( INPUT_Y < TO_SIGNED(0, 9) ) then INPUT_Y := TO_SIGNED(0, 9); end if;
if ( INPUT_U > TO_SIGNED(255, 9) ) then INPUT_U := TO_SIGNED(255, 9); elsif ( INPUT_U < TO_SIGNED(0, 9) ) then INPUT_U := TO_SIGNED(0, 9); end if;
if ( INPUT_V > TO_SIGNED(255, 9) ) then INPUT_V := TO_SIGNED(255, 9); elsif ( INPUT_V < TO_SIGNED(0, 9) ) then INPUT_V := TO_SIGNED(0, 9); end if;
-- ON GENERE LA SORTIE DU COMPOSANT
OUTPUT_1 <= "00000000" & STD_LOGIC_VECTOR(INPUT_V(7 downto 0)) & STD_LOGIC_VECTOR(INPUT_U(7 downto 0)) & STD_LOGIC_VECTOR(INPUT_Y(7 downto 0));
end process;
end rtl;
| gpl-3.0 | 671e09c483718fc8462fa0b17f1d2db4 | 0.611466 | 2.710836 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram_boot_for_simu.vhd | 1 | 6,637 |
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
-- with this example
-- The following code will infer a Single port Block RAM and initialize it using a FILE
-- Place the following code before the begin of the architecture
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.ALL;
ENTITY RAM IS
GENERIC(
memory_type : string := "DEFAULT";
block_count : integer := 03);
PORT(
clk : IN std_logic;
enable : IN std_logic;
write_byte_enable : IN std_logic_vector(3 DOWNTO 0);
address : IN std_logic_vector(31 DOWNTO 2);
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0)
);
END;
ARCHITECTURE logic OF RAM IS
CONSTANT TAILLE_LOADER : INTEGER := 64*1024; -- TAILLE EN OCTETS (NORMALEMENT)
TYPE memoire IS ARRAY(0 TO TAILLE_LOADER-1) OF bit_vector(7 DOWNTO 0);
IMPURE FUNCTION load_memoire (filename : IN string; byte : IN integer) RETURN memoire IS
FILE ram_file : text IS IN filename;
VARIABLE line_name : line;
VARIABLE line_temp : bit_vector(31 DOWNTO 0);
VARIABLE ram_name : memoire;
BEGIN
FOR I IN memoire'range LOOP
IF (NOT endfile(ram_file)) THEN
readline(ram_file, line_name);
read (line_name, line_temp);
IF(byte = 1) THEN
ram_name(I) := line_temp(31 DOWNTO 24);
ELSIF(byte = 2) THEN
ram_name(I) := line_temp(23 DOWNTO 16);
ELSIF(byte = 3) THEN
ram_name(I) := line_temp(15 DOWNTO 8);
ELSIF(byte = 4) THEN
ram_name(I) := line_temp(7 DOWNTO 0);
END IF;
END IF;
END LOOP;
RETURN ram_name;
END FUNCTION;
SIGNAL laRAM1 : memoire := load_memoire("../code_bin.txt", 1);
SIGNAL laRAM2 : memoire := load_memoire("../code_bin.txt", 2);
SIGNAL laRAM3 : memoire := load_memoire("../code_bin.txt", 3);
SIGNAL laRAM4 : memoire := load_memoire("../code_bin.txt", 4);
--
-- CETTE MEMOIRE EST MICROSCOPIQUE... PAS LA PEINE D'UTILISER UN BLOC RAM POUR
-- SON IMPLANTATION...
--
-- attribute RAM_STYLE : string;
-- attribute RAM_STYLE of laRAM1: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM2: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM3: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM4: signal is "PIPE_DISTRIBUTED";
BEGIN
--
-- ON GERE LES BITS (31 => 24)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(3) = '1' THEN
laRAM1(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(31 DOWNTO 24));
data_read(31 DOWNTO 24) <= data_write(31 DOWNTO 24);
ELSE
data_read(31 DOWNTO 24) <= to_stdlogicvector(laRAM1(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (23 => 16)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(2) = '1' THEN
laRAM2(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(23 DOWNTO 16));
data_read(23 DOWNTO 16) <= data_write(23 DOWNTO 16);
ELSE
data_read(23 DOWNTO 16) <= to_stdlogicvector(laRAM2(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (15 => 8)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(1) = '1' THEN
laRAM3(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(15 DOWNTO 8));
data_read(15 DOWNTO 8) <= data_write(15 DOWNTO 8);
ELSE
data_read(15 DOWNTO 8) <= to_stdlogicvector(laRAM3(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (7 => 0)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(0) = '1' THEN
laRAM4(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(7 DOWNTO 0));
data_read(7 DOWNTO 0) <= data_write(7 DOWNTO 0);
ELSE
data_read(7 DOWNTO 0) <= to_stdlogicvector(laRAM4(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
END; --architecture logic
| gpl-3.0 | b5b3d1c6ae097a33b6f8cd136f19307b | 0.548139 | 3.829775 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_rng.vhd | 1 | 4,246 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Video_Memory_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Video_Memory_TB_RNG;
ARCHITECTURE BEHAVIORAL OF Video_Memory_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit | 528923af02a711ffe372109f39aee545 | 0.584079 | 4.4 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_GRT_8b.vhd | 1 | 1,707 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_GRT_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_GRT_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
--process
--begin
-- wait for 1 ns;
-- printmsg("(IMS) MMX 8bis GRT RESSOURCE : ALLOCATION OK !");
-- wait;
--end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
if( UNSIGNED(INPUT_1( 7 downto 0)) > UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := "11111111"; else rTemp1 := "00000000"; end if;
if( UNSIGNED(INPUT_1(15 downto 8)) > UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := "11111111"; else rTemp2 := "00000000"; end if;
if( UNSIGNED(INPUT_1(23 downto 16)) > UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := "11111111"; else rTemp3 := "00000000"; end if;
if( UNSIGNED(INPUT_1(31 downto 24)) > UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := "11111111"; else rTemp4 := "00000000"; end if;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 578195da4f12f1f0a2ab65fe4b080cdd | 0.546573 | 3.427711 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram.vhd | 1 | 6,150 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 13;
begin
generic_ram:
if memory_type /= "ALTERA_LPM" generate
begin
--Simulate a synchronous RAM
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable mem_size : natural := 2 ** ADDRESS_WIDTH;
variable data : std_logic_vector(31 downto 0);
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to mem_size/4 - 1) of word;
variable storage : storage_array;
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) := data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) := data;
end if;
end if;
data_read <= data;
end process;
end generate; --generic_ram
altera_ram:
if memory_type = "ALTERA_LPM" generate
signal byte_we : std_logic_vector(3 downto 0);
begin
byte_we <= write_byte_enable when enable = '1' else "0000";
lpm_ram_io_component0 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code0.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(31 downto 24),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(3),
q => data_read(31 downto 24));
lpm_ram_io_component1 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code1.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(23 downto 16),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(2),
q => data_read(23 downto 16));
lpm_ram_io_component2 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code2.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(15 downto 8),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(1),
q => data_read(15 downto 8));
lpm_ram_io_component3 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code3.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(7 downto 0),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(0),
q => data_read(7 downto 0));
end generate; --altera_ram
--For XILINX see ram_xilinx.vhd
end; --architecture logic
| gpl-3.0 | c6d7152dce57124f53b79f6d66c30b96 | 0.523577 | 3.952442 | false | false | false | false |
idpromnut/tek7854mpu | debugger/debug_hdl/toplevel.vhd | 1 | 2,197 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity toplevel is
port ( clk : in std_ulogic; -- 50 MHz clock
mojo_tx : out std_ulogic; -- Debug data out to PC
idpromnut_tx : out std_ulogic; -- Debug data out to test header
led0 : out std_ulogic; -- Status LED
led1 : out std_ulogic;
led2 : out std_ulogic;
led3 : out std_ulogic;
led4 : out std_ulogic;
led5 : out std_ulogic;
led6 : out std_ulogic;
led7 : out std_ulogic
);
end toplevel;
architecture Behavioral of toplevel is
signal ser_wr: std_ulogic;
signal ser_ready: std_ulogic;
signal ser_ready_last: std_ulogic;
signal ser_data_in: std_ulogic_vector(7 downto 0);
signal ser_data_out: std_ulogic;
type ctrl_state is ( state_wait );
signal state: ctrl_state := state_wait;
type mem is array(0 to 26) of std_ulogic_vector(7 downto 0);
constant data_rom: mem := (
x"4e", x"4f", x"4e", x"20",
x"47", x"45", x"4e", x"55",
x"49", x"4e", x"45", x"20",
x"32", x"53", x"43", x"34",
x"37", x"35", x"37", x"20",
x"46", x"4f", x"55", x"4e",
x"44", x"0d", x"0a" );
signal rom_addr: natural := 0;
begin
transmitter: entity work.serial_tx
generic map ( clk_period => 20 ns )
port map (
clk => clk,
wr => ser_wr,
ready => ser_ready,
data_out => ser_data_out,
data_in => ser_data_in );
mojo_tx <= ser_data_out;
idpromnut_tx <= ser_data_out;
ser_data_in <= data_rom(rom_addr);
ser_wr <= ser_ready;
ser_ready_last <= ser_ready when rising_edge(clk);
--led0 <= not ser_ready;
led0 <= data_rom(rom_addr)(0);
led1 <= data_rom(rom_addr)(1);
led2 <= data_rom(rom_addr)(2);
led3 <= data_rom(rom_addr)(3);
led4 <= data_rom(rom_addr)(4);
led5 <= data_rom(rom_addr)(5);
led6 <= data_rom(rom_addr)(6);
led7 <= data_rom(rom_addr)(7);
process(clk, ser_ready)
begin
if rising_edge(clk) then
if ser_ready = '1' and ser_ready_last = '0' then
if rom_addr = data_rom'high then
rom_addr <= 0;
else
rom_addr <= rom_addr + 1;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 6b2cc7f57f6a524fa18edfd0614333a8 | 0.578516 | 2.770492 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/UNDEF/DIVIDER_32b_4x.vhd | 1 | 3,483 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_32b_4x is
generic(SIZE: INTEGER := 32);
port(
reset : in STD_LOGIC;
start : in STD_LOGIC;
clk : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
INPUT_2 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_2 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
ready : out STD_LOGIC
);
end DIVIDER_32b_4x;
architecture behav of DIVIDER_32b_4x is
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to (SIZE/4);
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
begin
process(reset, start, clk)
variable tbuf1 : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2 : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf3 : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
begin
if reset = '1' then
OUTPUT_1 <= (others => '0');
OUTPUT_2 <= (others => '0');
sm <= 0;
ready <= '0';
elsif rising_edge(clk) then
case sm is
when 0 =>
OUTPUT_1 <= buf2;
OUTPUT_2 <= buf1;
ready <= '0';
buf2 <= (others => 'X');
dbuf <= INPUT_2;
buf1 <= (others => 'X');
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
sm <= sm + 1;
else
sm <= sm;
end if;
when others =>
-- PREMIERE ITERATION DEROULEE DE LA DIVISION
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf1((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf1((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
else
tbuf1 := buf((2 * SIZE - 2) downto 0) & '0';
end if;
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
if tbuf1((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf2((2 * SIZE - 1) downto SIZE) := '0' & (tbuf1((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf2((SIZE - 1) downto 0) := tbuf1((SIZE - 2) downto 0) & '1';
else
tbuf2 := tbuf1((2 * SIZE - 2) downto 0) & '0';
end if;
-- TROISIEME ITERATION DEROULEE DE LA DIVISION
if tbuf2((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf3((2 * SIZE - 1) downto SIZE) := '0' & (tbuf2((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf3((SIZE - 1) downto 0) := tbuf2((SIZE - 2) downto 0) & '1';
else
tbuf3 := tbuf2((2 * SIZE - 2) downto 0) & '0';
end if;
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
if tbuf3((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1((2 * SIZE - 1) downto SIZE) <= '0' & (tbuf3((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2((SIZE - 1) downto 0) <= tbuf3((SIZE - 2) downto 0) & '1';
else
buf <= tbuf3((2 * SIZE - 2) downto 0) & '0';
end if;
-- QUEL VA ETRE NOTRE PROCHAIN ETAT ?
if sm /= (SIZE/4) then
sm <= sm + 1;
ready <= '0';
else
sm <= 0;
ready <= '1';
end if;
end case;
end if;
end process;
end behav;
| gpl-3.0 | 2fe73ad524c864f6e12b661b7917d4a9 | 0.511341 | 2.845588 | false | false | false | false |
ryos36/polyphony-tutorial | misc/vhdl/Life0/life0_tb.vhdl | 1 | 1,455 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity life0_tb is
end life0_tb;
architecture behav of life0_tb is
component life0
port(
clk : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component;
signal clk : std_logic;
signal data : std_logic_vector(31 downto 0)
:= "01110101111010101101110110101011";
signal din : std_logic;
signal result : std_logic;
constant clk_period : time := 10 ns;
begin
-------------------------------------------------------------------
din <= data(0);
l0 : life0
port map (
clk => clk,
din => din,
dout => result
);
-------------------------------------------------------------------
clk_producer: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-------------------------------------------------------------------
kicker: process(clk)
begin
if clk'event and clk = '1' then
data <= data(0) & data(31 downto 1);
end if;
end process;
-------------------------------------------------------------------
data_cosumer: process(clk)
variable line0 : line;
begin
if clk'event and clk = '1' then
write( line0, String'("result:"));
write( line0, result );
writeline( output, line0);
end if;
end process;
end behav;
| mit | 1df05f7934b8aea17b4744230a8c297f | 0.493471 | 3.849206 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/cpt_iter.vhd | 1 | 1,543 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:50:17 04/04/2016
-- Design Name:
-- Module Name: cpt_iter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cpt_iter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
inib : in std_logic;
endcalcul : in STD_LOGIC;
iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0));
end cpt_iter;
architecture Behavioral of cpt_iter is
Signal iterS : unsigned(ITER_RANGE-1 downto 0);
begin
process(reset,clock)
begin
if reset='1' then
iterS<=to_unsigned(5,ITER_RANGE);
elsif rising_edge(clock) then
if inib = '1' then
if endcalcul ='1' then
if iterS < (ITER_MAX-10) then
iterS<=iterS+1;
else
iterS<=to_unsigned(10,ITER_RANGE);
end if;
end if;
end if;
end if;
end process;
iter<=std_logic_vector(iterS);
end Behavioral; | gpl-3.0 | 9cbf13219f0470430cd2b2a6fc29a75c | 0.604018 | 3.522831 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_SUB.vhd | 1 | 1,667 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_SUB is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_SUB is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_SUB : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
begin
OP1 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) );
OP2 := SIGNED( INPUT_2(15) & INPUT_2(15 downto 0) );
OP3 := OP1 - OP2;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 1e087a0c133e7753f2402645c27c8d37 | 0.467906 | 3.814645 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/Shared.vhd | 1 | 1,514 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package CONSTANTS is
-- Param --
constant PARAM_DELAY : integer := 50000000; --~500ms
-- Fixed format --
constant FIXED : INTEGER := 28; --Number of bits for , part
-- Data size --
constant XY_RANGE : INTEGER := 32; --Number of bits for x and y data
constant ITER_MAX : INTEGER := 256; --Max number of iteration
constant ITER_RANGE : INTEGER := 8;
constant ADDR_BIT_MUX : INTEGER := 16;
constant ADDR_BIT : INTEGER := 18;
constant QUATRE : SIGNED (XY_RANGE-1 downto 0) := to_signed(4,32) sll FIXED ;
constant bit_per_pixel : integer := 12;
constant COLOR_MAX : integer := 2047;
constant NBR_PIXEL : integer := 38399;
end CONSTANTS;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package FUNCTIONS is
function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR;
function mult(A : SIGNED; B : SIGNED; QF : integer) return SIGNED;
end FUNCTIONS;
package body FUNCTIONS is
--Maths functions
function mult(A : SIGNED; B : SIGNED; QF : integer) return SIGNED is
CONSTANT DMAX_R : integer := A'LENGTH + B'LENGTH;
CONSTANT PHI : integer := A'LENGTH - QF;
VARIABLE r : SIGNED(DMAX_R-1 DOWNTO 0);
begin
r := A*B;
return r(DMAX_R - PHI - 1 downto QF);
end mult;
function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(mult(SIGNED(A),SIGNED(B),QF));
end mult;
end FUNCTIONS; | gpl-3.0 | 7a6c7f7a5ecca3a25ee598f9478cbbd1 | 0.688904 | 3.154167 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/example_design/Ram_prod ([email protected] 2015-09-19-17-37-53).vhd | 1 | 10,326 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Ram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Ram.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Ram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Ram_prod;
ARCHITECTURE xilinx OF Ram_prod IS
COMPONENT Ram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Ram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 6e91941fae5c9a2219cfaf2bcdd1c44a | 0.479663 | 3.828699 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/example_design/Font_prod_exdes.vhd | 1 | 5,236 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Font_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(8-1 downto 0)
);
end Font_exdes;
architecture xilinx of Font_exdes is
component Font is
PORT (
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Font
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | 91cfbe72b38012b3873ae0d60db5fbab | 0.494461 | 4.601054 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_rng.vhd | 1 | 4,266 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dist_mem_gen_v7_2_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END dist_mem_gen_v7_2_TB_RNG;
ARCHITECTURE BEHAVIORAL OF dist_mem_gen_v7_2_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit | 18efa8063c6cc5c857bb42c7124d6711 | 0.583216 | 4.296073 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_reg1.vhd | 1 | 1,278 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:41 05/06/2017
-- Design Name:
-- Module Name: Mux_reg1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_reg1 is
Port ( alusrca : in STD_LOGIC_VECTOR (1 downto 0);
muxreg1 : in STD_LOGIC_VECTOR (15 downto 0);
mux_PC : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataA : out STD_LOGIC_VECTOR (15 downto 0));
end mux_reg1;
architecture Behavioral of mux_reg1 is
begin
process(alusrca)
begin
case alusrca is
when "00"=>
mux_dataA<=muxreg1;
when "01"=>
mux_dataA<=mux_PC;
when others=>null;
end case;
end process;
end Behavioral;
| apache-2.0 | 1f6f12ba22c0fc3516efd3ea07c9156f | 0.591549 | 3.747801 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_i2c/src/vvc_context.vhd | 1 | 1,396 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_i2c;
use bitvis_vip_i2c.vvc_cmd_pkg.all;
use bitvis_vip_i2c.vvc_methods_pkg.all;
use bitvis_vip_i2c.td_vvc_framework_common_methods_pkg.all;
end context; | mit | c90a5c8902206988b6959c04be7fb592 | 0.525788 | 5.328244 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/ex_mem_segment_regfile.vhd | 1 | 1,917 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ex_mem_segment_regfile is
port
(
ex_mem_segment_regfile_clk: in std_logic;
ex_mem_segment_regfile_write_in: in std_logic;
ex_mem_segment_regfile_alu_result_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_alu_result_out: out std_logic_vector(15 downto 0);
ex_mem_segment_regfile_mem_we_in: in std_logic;
ex_mem_segment_regfile_mem_we_out: out std_logic;
ex_mem_segment_regfile_reg_ry_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_reg_ry_out: out std_logic_vector(15 downto 0);
ex_mem_segment_regfile_src_result_in: in std_logic_vector(1 downto 0);
ex_mem_segment_regfile_src_result_out: out std_logic_vector(1 downto 0);
ex_mem_segment_regfile_reg_we_in: in std_logic;
ex_mem_segment_regfile_reg_we_out: out std_logic;
ex_mem_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
ex_mem_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
ex_mem_segment_regfile_imm_in: in std_logic_vector(15 downto 0);
ex_mem_segment_regfile_imm_out: out std_logic_vector(15 downto 0)
);
end ex_mem_segment_regfile;
architecture Behavioral of ex_mem_segment_regfile is
begin
process (ex_mem_segment_regfile_clk, ex_mem_segment_regfile_write_in)
begin
if (ex_mem_segment_regfile_write_in = '1') then
ex_mem_segment_regfile_alu_result_out <= ex_mem_segment_regfile_alu_result_in;
ex_mem_segment_regfile_reg_ry_out <= ex_mem_segment_regfile_reg_ry_in;
ex_mem_segment_regfile_mem_we_out <= ex_mem_segment_regfile_mem_we_in;
ex_mem_segment_regfile_src_result_out <= ex_mem_segment_regfile_src_result_in;
ex_mem_segment_regfile_reg_we_out <= ex_mem_segment_regfile_reg_we_in;
ex_mem_segment_regfile_imm_out <= ex_mem_segment_regfile_imm_in;
end if;
end process;
end Behavioral; | apache-2.0 | 714b3f06491c3ef9ec54c36e7f541512 | 0.723005 | 2.68864 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/conversion.vhd | 1 | 43,372 | --------------------------------------------------------------------------------
-- File Name: conversions.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was originally written by SEVA Technologies, Inc. and donated
-- to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
-- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int
-- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function
-- int_to_slv
-- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str
-- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0
-- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in
-- function int_to_slv) from > to >=
-- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- integer | to_slv | N/A | N/A | N/A | N/A
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
-- FROM TO: integer
-- -----------------|---------------|
-- std_logic_vector | to_int |
--------------------------------------------------------------------------------
PACKAGE conversion IS
----------------------------------------------------------------------------
-- the conversions in this package are not intended to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
-- <these packages are mutually exclusive>
-- conv_integer(std_logic_vector)
-- <except for this conversion, these packages are unnecessary)
-- to minimize compile problems write:
-- use std_logic_unsigned.conv_integer;
-- use std_logic_signed.conv_integer;
--
-- std_logic_vector, signed and unsigned types are "closely related"
-- no type conversion functions are needed, use type casting or qualified
-- expressions
--
-- type1(object of type2) <type casting>
-- type1'(expression of type2) <qualified expression>
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
function to_sint_str(x : std_logic_vector(31 downto 0);
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- integer to std_logic_vector
function int_to_slv (x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
END conversion;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversion IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
-- function min(x,y: integer) return integer is
-- begin
-- if x < y then return x; else return y; end if;
-- end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
variable slv4_val : slv4;
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
slv4_val := int(i to i+3);
case slv4_val is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
--when "LLLL" => r(ptr) := 'L';
--when "HHHH" => r(ptr) := 'H';
--when "UUUU" => r(ptr) := 'U';
--when "XXXX" => r(ptr) := 'X';
--when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",decimal,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_sint_str(x : std_logic_vector(31 downto 0);
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
VARIABLE SIGN : STD_LOGIC;
VARIABLE XX : std_logic_vector(31 downto 0);
begin
SIGN := x(31);
XX := STD_LOGIC_VECTOR( abs( SIGNED(x) ) );
if( SIGN = '1' )THEN
return "-" & to_int_str(to_nat(XX),rtn_len,justify,basespec);
end if;
return to_int_str(to_nat(XX),rtn_len,justify,basespec);
end to_sint_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function int_to_slv(x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : integer := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
if int >= 0 or int = 0 then
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
else
int := 2**(rtn_len - 1) + int;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
r(33-rtn_len) := '1';
return r(33-rtn_len to 32);
end if;
end int_to_slv;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
END conversion;
| gpl-3.0 | 1f89a4ae222988d4f162c25a4f1c800f | 0.444665 | 3.959828 | false | false | false | false |
chibby0ne/vhdl-book | Chapter13/ram_dir/ram.vhd | 1 | 2,508 | -- ram implementation according to the book, usign ram initialization files and only std_logic based ports
-- lessons learned:
-- initialization files of different vendor only work for vendor's fpga
-- reading ram is not registered. ram's output is not registered so whenever address changes output changes as well
-- writing to ram is registered. ram's input is written on the output (and the ram itself) when there's a rising edge and write enable = 1
--
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
--------------------------------------------------------
entity ram is
generic (M: natural := 4; -- 2**M = depth
N: natural := 8); -- N = width
port (
clk: in std_logic;
we: in std_logic;
address: in std_logic_vector(M-1 downto 0);
data_in: in std_logic_vector(N-1 downto 0);
data_out: out std_logic_vector(N-1 downto 0));
end entity ram;
--------------------------------------------------------
--------------------------------------------------------
architecture circuit of ram is
-- signal declarations
type memory is array (0 to 2**M-1) of std_logic_vector(N-1 downto 0);
signal myram: memory := (
2 => std_logic_vector(to_unsigned(255, N)),
3 => std_logic_vector(to_unsigned(26, N)),
4 => std_logic_vector(to_unsigned(5, N)),
5 => std_logic_vector(to_unsigned(80, N)),
6 => std_logic_vector(to_unsigned(176, N)),
15 => std_logic_vector(to_unsigned(17, N)),
others => std_logic_vector(to_unsigned(0, N)));
-- attribute ram_init_file: string;
-- attribute ram_init_file of myram: signal is "ram_contents.mif";
signal address_int: integer range 0 to 2**M - 1;
begin
--------------------------------------------------------
-- type casting entity ports
--------------------------------------------------------
address_int <= to_integer(unsigned(address));
--------------------------------------------------------------------------------------
-- ram operation
--------------------------------------------------------------------------------------
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
myram(address_int) <= data_in;
end if;
end if;
end process;
data_out <= myram(address_int);
end architecture circuit;
| gpl-3.0 | bd62cc6f54f0336a4dd48c3529fe3fe4 | 0.485646 | 4.486583 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_exdes.vhd | 1 | 3,970 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity dist_mem_gen_v7_2_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end dist_mem_gen_v7_2_exdes;
architecture xilinx of dist_mem_gen_v7_2_exdes is
component dist_mem_gen_v7_2 is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : dist_mem_gen_v7_2
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | b6e34367eb5a502de232a3e45f3f9a3f | 0.571788 | 4.445689 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/example_design/Ram_prod.vhd | 1 | 10,322 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Ram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Ram.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Ram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Ram_prod;
ARCHITECTURE xilinx OF Ram_prod IS
COMPONENT Ram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Ram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | d7234cc0db7ea28aa95ed7a7af65e8d0 | 0.479461 | 3.827215 | false | false | false | false |
chibby0ne/vhdl-book | Chapter4/exercise7_dir/exercise7/exercise7.vhd | 1 | 1,510 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------
entity ent is
--generic declarations
port (
reset: in std_logic ;
clk: in std_logic ;
v: in std_logic_vector(3 downto 0) ;
x: in std_logic_vector(3 downto 0) ;
y: in std_logic_vector(7 downto 0) ;
z: in std_logic_vector(7 downto 0) ;
out1: out std_logic ;
out2: out std_logic ;
out3: out std_logic ;
out4: out std_logic );
end entity;
------------------------------
architecture circuit of ent is
signal v_sig: signed(3 downto 0) := signed(v);
signal x_sig: signed(3 downto 0):= signed(x);
signal y_sig: signed(7 downto 0) := signed(y);
signal z_sig: signed(7 downto 0) := signed(z);
signal a: integer range 0 to 7;
signal b: signed(3 downto 0);
signal c: signed(3 downto 0);
signal d: signed(3 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (v_sig > x_sig) then
out1 <= '1';
elsif ( v_sig + x_sig <= z_sig) then
out2 <= '1';
end if;
end if;
-- out1 <= '1' when v_sig > x_sig else '0';
-- out2 <= '1' when v_sig + x_sig <= z_sig else '0';
-- out3 <= '1' when y_sig = ((abs(x_sig))**3) else '0';
-- out3 <= '1' when (7 * v_sig) rem x = (7 *v_sig) mod x else '0';
end process;
end architecture;
------------------------------
| gpl-3.0 | daebf022803329cd2bbfb1e744f01fb6 | 0.494702 | 3.275488 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/example_design/Video_Memory_prod_exdes.vhd | 1 | 5,954 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Video_Memory_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(16-1 downto 0)
);
end Video_Memory_exdes;
architecture xilinx of Video_Memory_exdes is
SIGNAL CLK_i : std_logic;
component Video_Memory is
PORT (
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC;
WE : IN STD_LOGIC;
SPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0')
);
end component;
begin
dmg0 : Video_Memory
port map (
DPRA => DPRA,
CLK => CLK_i,
WE => WE,
SPO => SPO,
DPO => DPO,
A => A,
D => D
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
| mit | 258bff33f1671b31529b7ec99619c781 | 0.474807 | 4.572965 | false | false | false | false |
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