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karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_MIN_8b.vhd | 1 | 1,778 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MIN_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MIN_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MIN RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
if( UNSIGNED(INPUT_1( 7 downto 0)) < UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := INPUT_1( 7 downto 0); else rTemp1 := INPUT_2( 7 downto 0); end if;
if( UNSIGNED(INPUT_1(15 downto 8)) < UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := INPUT_1(15 downto 8); else rTemp2 := INPUT_2(15 downto 8); end if;
if( UNSIGNED(INPUT_1(23 downto 16)) < UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := INPUT_1(23 downto 16); else rTemp3 := INPUT_2(23 downto 16); end if;
if( UNSIGNED(INPUT_1(31 downto 24)) < UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := INPUT_1(31 downto 24); else rTemp4 := INPUT_2(31 downto 24); end if;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | a3c759b3e7d4fea1e012948927d069e5 | 0.556243 | 3.323364 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/simulation/bmg_stim_gen ([email protected] 2015-09-19-17-37-53).vhd | 1 | 7,822 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(13 DOWNTO 0) <= WRITE_ADDR(13 DOWNTO 0);
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16384
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | 93f14bab9e087d365d25e48a181bbf35 | 0.541294 | 3.735435 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mcmgmt.vhd | 1 | 3,063 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mcmgmt is
port
(
mcmgmt_clk: in std_logic;
mcmgmt_rst: in std_logic;
mcmgmt_port_mem1_oe: out std_logic;
mcmgmt_port_mem1_we: out std_logic;
mcmgmt_port_mem1_en: out std_logic;
mcmgmt_port_mem1_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem1_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_mem2_oe: out std_logic;
mcmgmt_port_mem2_we: out std_logic;
mcmgmt_port_mem2_en: out std_logic;
mcmgmt_port_mem2_addr: out std_logic_vector(17 downto 0);
mcmgmt_port_mem2_data: inout std_logic_vector(15 downto 0);
mcmgmt_port_com_data_ready: in std_logic;
mcmgmt_port_com_rdn: out std_logic;
mcmgmt_port_com_tbre: inout std_logic;
mcmgmt_port_com_tsre: inout std_logic;
mcmgmt_port_com_wrn: out std_logic;
mcmgmt_addr: in std_logic_vector(19 downto 0);
mcmgmt_idata: in std_logic_vector(15 downto 0);
mcmgmt_odata: out std_logic_vector(15 downto 0);
mcmgmt_rw: in std_logic;
mcmgmt_by_byte: in std_logic;
mcmgmt_byte_select: in std_logic;
mcmgmt_free: out std_logic;
mcmgmt_int: out std_logic;
mcmgmt_debug_status: out std_logic_vector(4 downto 0)
);
end mcmgmt;
architecture Behavioral of mcmgmt is
signal mcmgmt_status: std_logic_vector(4 downto 0) := "00001";
signal mcmgmt_rst_cache: std_logic := '1';
begin
mcmgmt_debug_status <= mcmgmt_status;
process (mcmgmt_clk)
begin
mcmgmt_rst_cache <= mcmgmt_rst;
mcmgmt_debug_status <= mcmgmt_status;
if (mcmgmt_rst = '0' and mcmgmt_rst_cache = '1') then
mcmgmt_status <= "00000";
mcmgmt_odata <= "0000000000000000";
--mcmgmt_free <= '1';
--mcmgmt_int <= '0';
mcmgmt_odata <= "0000000000000000";
else
if (rising_edge(mcmgmt_clk)) then
if (mcmgmt_status = "00000") then
mcmgmt_free <= '1';
mcmgmt_int <= '0';
mcmgmt_odata <= "0000000000000000";
else
case mcmgmt_status is
when "00001" =>
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_oe <= '1';
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_mem1_addr <= "000100000000000000";
mcmgmt_port_mem1_data <= "1101010101010100";
mcmgmt_port_com_rdn <= '1';
mcmgmt_free <= '1';
mcmgmt_status <= "00010";
when "00010" =>
mcmgmt_port_mem1_oe <= '1';
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_we <= '0';
mcmgmt_port_com_rdn <= '1';
mcmgmt_status <= "00000";
when "00101" =>
mcmgmt_status <= "00100";
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_com_rdn <= '1';
when "00110" =>
mcmgmt_port_mem1_oe <= '0';
mcmgmt_port_mem1_en <= '0';
mcmgmt_port_mem1_we <= '1';
mcmgmt_port_com_rdn <= '1';
mcmgmt_port_mem1_addr <= "000100000000000000";
mcmgmt_port_mem1_data <= "ZZZZZZZZZZZZZZZZ";
mcmgmt_status <= "00101";
when "00111" =>
mcmgmt_status <= "00000";
mcmgmt_odata <= mcmgmt_port_mem1_data;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 203ae8b08a9a307f9f4cfa88b5a5bfca | 0.639896 | 2.817847 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/vga_bitmap_160x100.vhd | 2 | 11,975 | -------------------------------------------------------------------------------
-- Bitmap VGA display
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.CONSTANTS.all;
entity VGA_bitmap_160x100 is
generic(grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
-- ADDR : in std_logic_vector(13 downto 0);
endcalcul : in std_logic;
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_160x100;
architecture Behavioral of VGA_bitmap_160x100 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 16383) of std_logic_vector(bit_per_pixel - 1 downto 0);
signal screen : GRAM; -- the memory representation of the image
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 15999:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
signal ADDR : unsigned(13 downto 0);
begin
ADDRmanagement : process(clk,reset, data_write)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR < 15999 then
ADDR<=ADDR+1;
else
ADDR<=(others=>'0');
end if;
end if;
end if;
end if;
end process;
-- This process performs data access (read and write) to the memory
memory_management : process(clk)
begin
if clk'event and clk='1' then
next_pixel <= screen(pix_read_addr);
data_out <= screen(to_integer(ADDR));
if data_write = '1' then
screen(to_integer(ADDR)) <= data_in;
end if;
end if;
end process;
pixel_read_addr : process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 16)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (not TOP_line) and h_counter = 0 and ((v_counter mod 4)/= 3) then
-- each line is repeated 4 times, the first 3 times, we have to restart at the
-- beginning og the line instead of continue to the next line
pix_read_addr <= pix_read_addr - 160;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 75 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 475 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
when others => null;
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 6a2f0a3ba8d718caf01183b343a7ec07 | 0.488935 | 3.622202 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/coproc_1.vhd | 1 | 2,792 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2, val3, min, max , max_tmp, min_tmp: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
-- Registres contenant les valeurs du min et du max courant
-- Quand reset actif, alors on initialise min et max
-- A chaque écriture dans le coproc, on met à jour le min et le max avec les 4 nouvelles valeurs
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
min <= (others => '1');
max <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
min <= min_tmp;
max <= max_tmp;
ELSE
min <= min;
max <= max;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_tmp <= max0123;
else
max_tmp <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_tmp <= min0123;
else
min_tmp <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min&max;
end; --architecture logic
| gpl-3.0 | b37415455deef4175bc427ad5ba85da8 | 0.563441 | 3.177677 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/exercise1_dir/periodic_stimuli.vhd | 1 | 1,451 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: periodic_stimuli.vhd
--! @brief: write and simulate a vhdl code that generates the signs sig1 and sig2 and signal y
--! @author: Antonio Gutierrez
--! @date: 2014-04-01
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity periodic_stimuli is
--generic declarations
end entity periodic_stimuli;
--------------------------------------
architecture circuit of periodic_stimuli is
signal sig1: std_logic := '1';
signal sig2: std_logic := '1';
signal y: std_logic: = '1';
begin
-- stimuli sig1
-- (ii) sequential
sig1_proc: process
begin
sig1 <= '1';
wait for 25 ns;
sig1 <= '0';
wait for 50 ns;
end process sig1_proc;
sig2_proc: process
begin
sig2 <= '1';
wait for 25 ns;
sig2 <= '0';
wait for 50 ns;
sig2 <= '1';
wait for 25 ns;
sig2 <= '0';
wait for 25 ns;
sig2 <= '1';
wait for 50 ns;
sig2 <= '0';
wait for 25 ns;
end process sig2_proc;
y_proc: process
begin
y <= '1';
wait for 20 ns;
y <= '0';
wait for 10 ns;
y <= '1';
wait for 10 ns;
y <= '0';
wait for 40 ns;
end process y_proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 8dd7c1347634257aff128c3c982c113b | 0.472777 | 3.879679 | false | false | false | false |
chibby0ne/vhdl-book | Chapter2/registered_comp_add_dir/registered_comp_add.vhd | 1 | 686 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity registered_comp_add is
port (clk: in std_logic;
a, b: in integer range 0 to 7;
reg_comp: out std_logic;
reg_sum: out integer range 0 to 15;);
end entity;
------------------------------
architecture circuit of registered_comp_add is
signal comp: std_logic;
signal sum: integer range 0 to 15;
begin
comp <= '1' when a > b else '0';
sum <= a + b;
process (clk, rst)
begin
if (clk'event and clk = '1') then
reg_comp <= comp;
reg_sum <= sum;
end if;
end process
end architecture;
| gpl-3.0 | e5efae44a3fb498924ba81eea6bb2198 | 0.505831 | 3.897727 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_ROM_iPos.vhd | 1 | 13,234 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_ROM_iPos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_ROM_iPos is
type rom_type is array (0 to 576-1) of UNSIGNED(2 downto 0);
constant rom_iPos : rom_type := (
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3),
TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(2, 3), TO_UNSIGNED(2, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(3, 3), TO_UNSIGNED(2, 3)
);
SIGNAL READ_C : UNSIGNED(11 downto 0);
--SIGNAL WRITE_C : UNSIGNED(11 downto 0);
--SIGNAL ROM_ADR : UNSIGNED(11 downto 0);
--signal IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
--signal WE_BIS : STD_LOGIC;
--signal HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
--WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
--WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
VARIABLE ADR : INTEGER RANGE 0 to 576;
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
OUTPUT_1(2 downto 0) <= "000";
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 12);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
end if;
READ_C <= TEMP;
ADR := to_integer( TEMP );
OUTPUT_1(2 downto 0) <= STD_LOGIC_VECTOR( rom_iPos( ADR ) );
end if;
end process;
OUTPUT_1(31 downto 3) <= "00000000000000000000000000000";
END cRAM; | gpl-3.0 | 51dde3f2f615824960ab48341dac18ad | 0.598912 | 2.475033 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/reg_bank.vhd | 1 | 5,748 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
--use UNISIM.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
-- tri_port_mem:
-- if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable tri_port_ram : ram_type := (others => ZERO);
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
-- end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
-- dual_port_mem:
-- if memory_type = "DUAL_PORT_" generate
-- ram_proc2: process(clk, addr_read1, addr_read2,
-- addr_write, reg_dest_new, write_enable)
-- variable dual_port_ram1 : ram_type := (others => ZERO);
-- variable dual_port_ram2 : ram_type := (others => ZERO);
-- begin
-- data_out1 <= dual_port_ram1(conv_integer(addr_read1));
-- data_out2 <= dual_port_ram2(conv_integer(addr_read2));
-- if rising_edge(clk) then
-- if write_enable = '1' then
-- dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
-- dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
-- end if;
-- end if;
-- end process;
-- end generate; --dual_port_mem
end; --architecture ram_block
| gpl-3.0 | c04a4308f93b6b2f9da0dd4418a5c623 | 0.554628 | 3.539409 | false | false | false | false |
AlmuHS/VHDL-Binary-Clock | Test_CLK.vhd | 1 | 2,570 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:52:43 02/14/2016
-- Design Name:
-- Module Name: /home/almu/RelojBinario2/Test_CLK.vhd
-- Project Name: RelojBinario2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: digi_clk
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_CLK IS
END Test_CLK;
ARCHITECTURE behavior OF Test_CLK IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT digi_clk
PORT(
clk1 : IN std_logic;
seconds : OUT std_logic_vector(5 downto 0);
minutes : OUT std_logic_vector(5 downto 0);
hours : OUT std_logic_vector(3 downto 0);
set_hour : IN std_logic;
set_minutes : IN std_logic
);
END COMPONENT;
--Inputs
signal clk1 : std_logic := '0';
signal set_hour : std_logic := '0';
signal set_minutes : std_logic := '0';
--Outputs
signal seconds : std_logic_vector(5 downto 0);
signal minutes : std_logic_vector(5 downto 0);
signal hours : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk1_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: digi_clk PORT MAP (
clk1 => clk1,
seconds => seconds,
minutes => minutes,
hours => hours,
set_hour => set_hour,
set_minutes => set_minutes
);
-- Clock process definitions
clk1_process :process
begin
clk1 <= '0';
wait for clk1_period/2;
clk1 <= '1';
wait for clk1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk1_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | ac95a8b88b406c53e1c8df42f98bd9eb | 0.593385 | 3.858859 | false | true | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_FullXorMin.vhd | 1 | 2,068 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_FullXorMin is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_FullXorMin IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_FullXorMin : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
VARIABLE SIGN : STD_LOGIC;
BEGIN
--
-- ON RECUPERE NOS OPERANDES
--
OP1 := SIGNED( INPUT_1(15 downto 0));
MIN1 := SIGNED('0' & INPUT_2(30 downto 16)); -- VALEUR ABSOLUE => PAS DE BIT DE SIGNE (TJS POSITIF)
MIN2 := SIGNED('0' & INPUT_2(14 downto 0)); -- VALEUR ABSOLUE => PAS DE BIT DE SIGNE (TJS POSITIF)
SIGN := INPUT_2(31);
--
-- ON CALCULE LA VALEUR ABSOLUE DE L'ENTREE
--
OP1 := abs( OP1 );
--
-- ON CALCULE LE MIN QUI VA BIEN
--
IF OP1 < MIN1 THEN
MIN2 := MIN1;
MIN1 := OP1;
ELSIF OP1 < MIN2 THEN
MIN2 := OP1;
END IF;
--
-- ON S'OCCUPE DU BIT DE SIGNE DU RESULTAT
--
SIGN := SIGN XOR (NOT INPUT_1(15) );
--
-- ON REFORME LE RESULTAT AVANT DE LE RENVOYER
--
OUTPUT_1 <= SIGN & STD_LOGIC_VECTOR(MIN1(14 downto 0)) & '0' & STD_LOGIC_VECTOR(MIN2(14 downto 0));
END PROCESS;
-------------------------------------------------------------------------
END;
| gpl-3.0 | 0b74cb2a63ce0c8978d5371a9cfb226a | 0.483559 | 3.535043 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_CondSelect.vhd | 1 | 1,932 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_CondSelect is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_CondSelect IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_CondSelect : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE aOP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
VARIABLE CST1 : SIGNED(15 downto 0);
VARIABLE CST2 : SIGNED(15 downto 0);
VARIABLE RESU : SIGNED(15 downto 0);
BEGIN
-- ON RECUPERE NOS OPERANDES
OP1 := SIGNED(INPUT_1(15 downto 0));
MIN1 := SIGNED(INPUT_2(31 downto 16));
MIN2 := SIGNED(INPUT_2(15 downto 0));
aOP1 := abs( OP1 );
CST1 := MIN2 - TO_SIGNED(38, 16); -- BETA_FIX;
CST2 := MIN1 - TO_SIGNED(38, 16); -- BETA_FIX;
IF CST1 < TO_SIGNED(0, 16) THEN CST1 := TO_SIGNED(0, 16); END IF;
IF CST2 < TO_SIGNED(0, 16) THEN CST2 := TO_SIGNED(0, 16); END IF;
if ( aOP1 = MIN1 ) THEN
RESU := CST1;
ELSE
RESU := CST2;
END IF;
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(RESU);
END PROCESS;
-------------------------------------------------------------------------
END;
| gpl-3.0 | e111ff4aff9db193282abe9f376e8f0f | 0.490683 | 3.624765 | false | false | false | false |
chibby0ne/vhdl-book | Chapter9/my_package_dir/my_package.vhd | 1 | 1,314 | --!
--! @file: my_package.vhd
--! @brief: example9_2
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package my_package is
function order_and_fill(input : unsigned; bits: natural) return unsigned
end package my_package;
------------------------------
package body my_package is
function order_and_fill(input : unsigned; bits: natural) return unsigned is
variable a: unsigned(input'length-1 downto 0);
variable result: unsigned(bits-1 downto 0);
begin
-- check input size
assert (input'length <= bits)
report "Improper input size!"
severity failure;
-- organize input
if (input'left > input'right) then
a := input;
else
for1: for i in a'range loop
a(i) := input(input'left + i);
end loop for1;
end if;
-- fill with zeros
if (a'length < bits) then
result(bits-1 downto a'length) := (others => '0');
result(a'length-1 downto 0) := a;
else
result := a;
end if;
return result;
end function order_and_fill;
end package body my_package;
| gpl-3.0 | 7cf6c877e4826ede7c43bbf1b885327d | 0.530441 | 4.068111 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/tuto_plasma/coproc_1.vhd | 2 | 2,842 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2, val3, min, max , max_tmp, min_tmp: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
-- Registres contenant les valeurs du min et du max courant
-- Quand reset actif, alors on initialise min et max
-- A chaque écriture dans le coproc, on met à jour le min et le max avec les 4 nouvelles valeurs
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
min <= (others => '1');
max <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
min <= min_tmp;
max <= max_tmp;
ELSE
min <= min;
max <= max;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_tmp <= max0123;
else
max_tmp <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_tmp <= min0123;
else
min_tmp <= min;
end if;
end process;
--OUTPUT_1 <= "0000000000000000"&min&max;
OUTPUT_1 <= "00000000000000000000000000000000";
end; --architecture logic
| gpl-3.0 | 654d7a04e4f65098874f8ad4ece160d8 | 0.567254 | 3.201804 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_3_dir/exercise5_3.vhd | 1 | 928 | --!
--! @file: exercise5_3.vhd
--! @brief: design a generic AND and NAND gate using concurrent code
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity and__nand_gate is
generic (N: integer := 5;);
port (
x: in std_logic_vector(N-1 downto 0) ;
y: out std_logic);
end entity and_gate;
--------------------------------------
architecture and_circuit of and_gate is
begin
with x select
y <= '1' when (others => '1'),
'0' when others;
end architecture and_circuit;
--------------------------------------
architecture nand_circuit of and_gate is
--signals and declarations
begin
with x select
y <= '0' when (others => '1'),
'1' when others;
end architecture nand_circuit;
--------------------------------------
| gpl-3.0 | d7596a8f5cb875570115dc6396725e72 | 0.502155 | 4.088106 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_rng.vhd | 1 | 4,270 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Instruction_Memory_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Instruction_Memory_TB_RNG;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit | 693208a09f0f1b5dcdc06a3b915438ad | 0.586417 | 4.42487 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_ROM_2Pos.vhd | 1 | 7,613 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_ROM_2Pos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_ROM_2Pos is
type rom_type is array (0 to 288-1) of UNSIGNED(2 downto 0);
constant rom_2Pos : rom_type := (
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3)
);
SIGNAL READ_C : UNSIGNED(11 downto 0);
--SIGNAL WRITE_C : UNSIGNED(11 downto 0);
--SIGNAL ROM_ADR : UNSIGNED(11 downto 0);
--signal IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
--signal WE_BIS : STD_LOGIC;
--signal HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
--WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
--WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
VARIABLE ADR : INTEGER RANGE 0 to 288;
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
OUTPUT_1(2 downto 0) <= "000";
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 12);
IF TEMP = 288 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
end if;
READ_C <= TEMP;
ADR := to_integer( TEMP );
OUTPUT_1(2 downto 0) <= STD_LOGIC_VECTOR( rom_2Pos( ADR ) );
end if;
end process;
OUTPUT_1(31 downto 3) <= "00000000000000000000000000000";
END cRAM; | gpl-3.0 | 910c90ca4bc34aee4c52ed065404d790 | 0.587154 | 2.564163 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/core_pkg.vhd | 1 | 19,467 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : core_pkg.vhd
-- Design name : core_pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with components and type definitions for the interface
-- of the components
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.std_pkg.all;
package core_pkg is
constant C_8_ZEROS : std_logic_vector ( 7 downto 0) := (others => '0');
constant C_16_ZEROS : std_logic_vector (15 downto 0) := (others => '0');
constant C_24_ZEROS : std_logic_vector (23 downto 0) := (others => '0');
constant C_32_ZEROS : std_logic_vector (31 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------
-- TYPES USED IN MB-LITE
----------------------------------------------------------------------------------------------
type alu_operation is (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
type src_type_a is (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_ZERO);
type src_type_b is (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
type carry_type is (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
type carry_keep_type is (CARRY_NOT_KEEP, CARRY_KEEP);
type branch_condition is (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
type transfer_size is (WORD, HALFWORD, BYTE);
type ctrl_execution is record
alu_op : alu_operation;
alu_src_a : src_type_a;
alu_src_b : src_type_b;
operation : std_logic;
carry : carry_type;
carry_keep : carry_keep_type;
branch_cond : branch_condition;
delay : std_logic;
end record;
type ctrl_memory is record
mem_write : std_logic;
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type ctrl_memory_writeback_type is record
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type forward_type is record
reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_write : std_logic;
end record;
type imem_in_type is record
dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
end record;
type imem_out_type is record
adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
ena_o : std_logic;
end record;
type fetch_in_type is record
hazard : std_logic;
branch : std_logic;
branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
type fetch_out_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
type gprf_out_type is record
dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type decode_in_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
interrupt : std_logic;
flush_id : std_logic;
end record;
type decode_out_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
hazard : std_logic;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_dec : forward_type;
end record;
type gprf_in_type is record
adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
wre_i : std_logic;
end record;
type execute_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
branch : std_logic;
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
flush_id : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type execute_in_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
fwd_dec : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_mem : forward_type;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type mem_in_type is record
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
branch : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type mem_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
end record;
type dmem_in_type is record
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
type dmem_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
sel_o : std_logic_vector(3 downto 0);
we_o : std_logic;
ena_o : std_logic;
end record;
type dmem_in_array_type is array(natural range <>) of dmem_in_type;
type dmem_out_array_type is array(natural range <>) of dmem_out_type;
-- WB-master inputs from the wb-slaves
type wb_mst_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
ack_i : std_logic; -- buscycle acknowledge input
int_i : std_logic; -- interrupt request input
end record;
-- WB-master outputs to the wb-slaves
type wb_mst_out_type is record
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
we_o : std_logic; -- write enable output
stb_o : std_logic; -- strobe signals
sel_o : std_logic_vector(3 downto 0); -- select output array
cyc_o : std_logic; -- valid BUS cycle output
end record;
-- WB-slave inputs, from the WB-master
type wb_slv_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus input
we_i : std_logic; -- Write enable input
stb_i : std_logic; -- strobe signals / core select signal
sel_i : std_logic_vector(3 downto 0); -- select output array
cyc_i : std_logic; -- valid BUS cycle input
end record;
-- WB-slave outputs to the WB-master
type wb_slv_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus output
ack_o : std_logic; -- Bus cycle acknowledge output
int_o : std_logic; -- interrupt request output
end record;
----------------------------------------------------------------------------------------------
-- COMPONENTS USED IN MB-LITE
----------------------------------------------------------------------------------------------
component core
generic
(
CFG_IMEM_WIDTH : integer := 32;
CFG_IMEM_SIZE : integer := 16;
CFG_DMEM_WIDTH : integer := 32;
CFG_DMEM_SIZE : integer := 32;
G_INTERRUPT : boolean := true;
G_USE_HW_MUL : boolean := true;
G_USE_BARREL : boolean := true;
G_DEBUG : boolean := true
);
port
(
-- instruction memory interface
imem_dat_i : in std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
imem_adr_o : out std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
imem_ena_o : out std_logic;
-- data memory interfa
dmem_dat_i : in std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_ena_i : in std_logic;
dmem_dat_o : out std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_adr_o : out std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
dmem_sel_o : out std_logic_vector(3 downto 0);
dmem_we_o : out std_logic;
dmem_ena_o : out std_logic;
int_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_wb
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_async_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component fetch
port (
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component decode
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component gprf
port (
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component execute
generic (
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port (
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component mem
port (
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_address_decoder
generic (
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
);
port (
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type;
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS USED IN MB-LITE
----------------------------------------------------------------------------------------------
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector;
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector) return std_logic;
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector) return std_logic_vector;
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector;
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector;
end core_pkg;
package body core_pkg is
-- This function select the register value:
-- A) zero
-- B) bypass value read from register file
-- C) value from register file
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector is
variable tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
if CFG_REG_FORCE_ZERO = true and is_zero(reg) = '1' then
tmp := (others => '0');
elsif CFG_REG_FWD_WRB = true and write = '1' then
tmp := wb_dat;
else
tmp := reg_dat;
end if;
return tmp;
end select_register_data;
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
-- and the signal needs to be written back to the register file.
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector ) return std_logic is
begin
return reg_write and compare(reg_a, reg_d);
end forward_condition;
-- This function aligns the memory load operation (Big endian decoding).
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector ) return std_logic_vector is
begin
case size is
when byte =>
case address(1 downto 0) is
when "00" => return C_24_ZEROS & data(31 downto 24);
when "01" => return C_24_ZEROS & data(23 downto 16);
when "10" => return C_24_ZEROS & data(15 downto 8);
when "11" => return C_24_ZEROS & data( 7 downto 0);
when others => return C_32_ZEROS;
end case;
when halfword =>
case address(1 downto 0) is
when "00" => return C_16_ZEROS & data(31 downto 16);
when "10" => return C_16_ZEROS & data(15 downto 0);
when others => return C_32_ZEROS;
end case;
when others =>
return data;
end case;
end align_mem_load;
-- This function repeats the operand to all positions in a memory store operation.
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector is
begin
case size is
when byte => return data( 7 downto 0) & data( 7 downto 0) & data(7 downto 0) & data(7 downto 0);
when halfword => return data(15 downto 0) & data(15 downto 0);
when others => return data;
end case;
end align_mem_store;
-- This function selects the correct bytes for memory writes (Big endian encoding).
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector is
begin
case size is
when BYTE =>
case address is
when "00" => return "1000";
when "01" => return "0100";
when "10" => return "0010";
when "11" => return "0001";
when others => return "0000";
end case;
when HALFWORD =>
case address is
-- Big endian encoding
when "10" => return "0011";
when "00" => return "1100";
when others => return "0000";
end case;
when others =>
return "1111";
end case;
end decode_mem_store;
end core_pkg; | lgpl-3.0 | 9586b9e9ded3447f16b97f7bab13acfa | 0.521498 | 3.8648 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/HAMMING_ENC_24b.vhd | 1 | 3,174 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:03:26 02/20/2011
-- Design Name:
-- Module Name: hamming_encoder_26bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hamming_encoder_26b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end hamming_encoder_26b;
architecture Behavioral of hamming_encoder_26b is
SUBTYPE parity_ham_26bit IS std_logic_vector(5 DOWNTO 0);
SUBTYPE data_ham_26bit IS std_logic_vector(25 DOWNTO 0);
SUBTYPE coded_ham_26bit IS std_logic_vector(31 DOWNTO 0);
---------------------
-- HAMMING ENCODER --
---------------------
FUNCTION hamming_encoder_26bit(data_in:data_ham_26bit) RETURN parity_ham_26bit IS
VARIABLE parity: parity_ham_26bit;
BEGIN
parity(5) := data_in(11) XOR data_in(12) XOR data_in(13) XOR data_in(14) XOR data_in(15) XOR
data_in(16) XOR data_in(17) XOR data_in(18) XOR data_in(19) XOR data_in(20) XOR
data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(4) := data_in(4) XOR data_in(5) XOR data_in(6) XOR data_in(7) XOR data_in(8) XOR
data_in(9) XOR data_in(10) XOR data_in(18) XOR data_in(19) XOR data_in(20) XOR
data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(3) := data_in(1) XOR data_in(2) XOR data_in(3) XOR data_in(7) XOR data_in(8) XOR
data_in(9) XOR data_in(10) XOR data_in(14) XOR data_in(15) XOR data_in(16) XOR
data_in(17) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(2) := data_in(0) XOR data_in(2) XOR data_in(3) XOR data_in(5) XOR data_in(6) XOR
data_in(9) XOR data_in(10) XOR data_in(12) XOR data_in(13) XOR data_in(16) XOR
data_in(17) XOR data_in(20) XOR data_in(21) XOR data_in(24) XOR data_in(25);
parity(1) := data_in(0) XOR data_in(1) XOR data_in(3) XOR data_in(4) XOR data_in(6) XOR
data_in(8) XOR data_in(10) XOR data_in(11) XOR data_in(13) XOR data_in(15) XOR
data_in(17) XOR data_in(19) XOR data_in(21) XOR data_in(23) XOR data_in(25);
parity(0) := data_in(0) XOR data_in(1) XOR data_in(2) XOR data_in(3) XOR data_in(4) XOR
data_in(5) XOR data_in(6) XOR data_in(7) XOR data_in(8) XOR data_in(9) XOR
data_in(10) XOR data_in(11) XOR data_in(12) XOR data_in(13) XOR data_in(14) XOR
data_in(15) XOR data_in(16) XOR data_in(17) XOR data_in(18) XOR data_in(19) XOR
data_in(20) XOR data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR
data_in(25) XOR parity(1) XOR parity(2) XOR parity(3) XOR parity(4) XOR
parity(5) ;
RETURN parity;
END;
begin
PROCESS(INPUT_1)
BEGIN
OUTPUT_1 <= hamming_encoder_26bit( INPUT_1(25 downto 0) ) & INPUT_1(25 downto 0);
end process;
end Behavioral;
| gpl-3.0 | 6c9a50645712f3cbcd1754bae438ed75 | 0.604915 | 2.640599 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_vvc_framework/src_target_dependent/td_target_support_pkg.vhd | 1 | 15,464 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
package td_target_support_pkg is
signal global_vvc_ack : std_logic; -- ACK on global triggers
signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers
shared variable protected_multicast_semaphore : t_protected_semaphore;
shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx;
type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods
trigger : std_logic;
vvc_name : string(1 to C_VVC_NAME_MAX_LENGTH); -- as scope is vvc_name & ',' and number
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := (
trigger => 'L',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved;
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved;
subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved;
-------------------------------------------
-- to_string
-------------------------------------------
-- to_string method for VVC name, instance and channel
-- - If channel is set to NA, it will not be included in the string
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel := NA
) return string;
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Returns an encapsulated command index as string
impure function format_command_idx(
command : t_vvc_cmd_record -- VVC dedicated
) return string;
-------------------------------------------
-- send_command_to_vvc
-------------------------------------------
-- Sends command to VVC and waits for ACK or timeout
-- - Logs with ID_UVVM_SEND_CMD when sending to VVC
-- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs
procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- set_vvc_target_defaults
-------------------------------------------
-- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT
function set_vvc_target_defaults (
constant vvc_name : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) return t_vvc_target_record;
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- acknowledge_cmd
-------------------------------------------
-- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'.
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
);
end package td_target_support_pkg;
package body td_target_support_pkg is
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is
-- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name)
constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length
variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low);
variable v_cnt : integer := 0;
variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL);
variable v_line : line;
variable v_width : integer := 0;
begin
if input_vector'length = 1 then
return input_vector(input_vector'low);
else
for i in input_vector'range loop
-- The VVC is used if instance_idx is not -1 (which is the default value)
if input_vector(i).vvc_instance_idx /= -1 then
-- count the number of sequencer trying to access the VVC
v_cnt := v_cnt + 1;
v_result := input_vector(i);
-- generating string with all instance_idx for report in case of failure
write(v_line, string'(" "));
write(v_line, input_vector(i).vvc_instance_idx);
-- Ensure there is room for the last item and dots
v_width := v_line'length;
if v_width > (C_LINE_LENGTH_MAX-15) then
write(v_line, string'("..."));
exit;
end if;
end if;
end loop;
if v_width > 0 then
v_instance_string(1 to v_width) := v_line.all;
end if;
deallocate(v_line);
check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), "Multiple scopes", ID_NEVER);
return v_result;
end if;
end resolved;
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel:= NA
) return string is
variable v_instance : integer;
variable v_channel : t_channel;
begin
if vvc_instance = -1 then
v_instance := value.vvc_instance_idx;
else
v_instance := vvc_instance;
end if;
if vvc_channel = NA then
v_channel := value.vvc_channel;
else
v_channel := vvc_channel;
end if;
if v_channel = NA then
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES";
else
return to_string(value.vvc_name) & "," & to_string(v_instance);
end if;
else
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES" & "," & to_string(v_channel);
else
return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel);
end if;
end if;
end;
function set_vvc_target_defaults (
constant vvc_name : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) return t_vvc_target_record is
variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT;
begin
if vvc_name'length > C_MAX_VVC_NAME_LENGTH then
alert(TB_FAILURE, "vvc_name is too long. Shorten name or set C_MAX_VVC_NAME_LENGTH in adaptation_pkg to desired length.", scope);
end if;
v_rec.vvc_name := (others => NUL);
v_rec.vvc_name(1 to vvc_name'length) := vvc_name;
return v_rec;
end function;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
-- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here.
-- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command.
-- It is guaranteed that no time delay occurs, only delta cycle delay.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
target.vvc_instance_idx <= vvc_instance_idx;
target.vvc_channel <= vvc_channel;
shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length);
shared_vvc_cmd.msg := (others => NUL); -- default empty
shared_vvc_cmd.msg(1 to msg'length) := msg;
shared_vvc_cmd.command_type := command_type;
shared_vvc_cmd.operation := operation;
end procedure;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation);
end procedure;
impure function format_command_idx(
command : t_vvc_cmd_record
) return string is
begin
return format_command_idx(command.cmd_idx);
end;
procedure send_command_to_vvc(
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": ";
variable v_ack_cmd_idx : integer := -1;
variable v_start_time : time;
variable v_local_vvc_cmd : t_vvc_cmd_record;
variable v_local_cmd_idx : integer;
variable v_was_multicast : boolean := false;
begin
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", scope, ID_NEVER);
-- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
shared_vvc_cmd.cmd_idx := shared_cmd_idx;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
wait for 0 ns;
if (vvc_target.vvc_instance_idx = ALL_INSTANCES) then
await_semaphore_in_delta_cycles(protected_multicast_semaphore);
if global_vvc_busy /= 'L' then
wait until global_vvc_busy = 'L';
end if;
v_was_multicast := true;
end if;
v_start_time := now;
-- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer
-- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs.
v_local_vvc_cmd := shared_vvc_cmd;
-- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released
v_local_cmd_idx := shared_cmd_idx;
-- trigger the target -> vvc continues in await_cmd_from_sequencer
vvc_target.trigger <= '1';
wait for 0 ns;
-- the default value of vvc_target drives trigger to 'L' again
vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name, scope);
while v_ack_cmd_idx /= v_local_cmd_idx loop
wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now);
v_ack_cmd_idx := protected_acknowledge_index.get_index;
if not (global_vvc_ack'event) then
tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", scope);
-- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- release the semaphore as no VVC can do this
release_semaphore(protected_semaphore);
return;
end if;
end loop;
if (v_was_multicast = true) then
release_semaphore(protected_multicast_semaphore);
end if;
log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), scope);
-- clean up and prepare for next
wait for 0 ns; -- wait for executor to stop driving global_vvc_ack
end procedure;
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
) is
begin
-- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously.
while(protected_acknowledge_index.set_index(command_idx) = false) loop
-- if it can't set the acknowledge_index wait for one delta cycle and try again
wait for 0 ns;
end loop;
vvc_ack <= '1';
wait until vvc_ack = '1';
vvc_ack <= 'Z';
wait for 0 ns;
protected_acknowledge_index.release_index;
end procedure;
end package body td_target_support_pkg;
| mit | 4ed1a1f43b4041a75e7b492eef27caaa | 0.604565 | 3.911966 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/pc_next.vhd | 1 | 2,383 | ---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in, opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); -- pc_reg + 1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
-- BEGIN ENABLE_(J,JAL)
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
-- END ENABLE_(J,JAL)
-- BEGIN ENABLE_(BEQ,BNE,BLEZ,BGTZ,COP0,JR,JALR,REGIMM)
when FROM_BRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
-- END ENABLE_(BEQ,BNE,BLEZ,BGTZ,COP0)
when FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
| gpl-3.0 | 7eb0baf1f291fc753cb82746a2700403 | 0.557281 | 3.207268 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/shifter.vhd | 1 | 3,635 | ---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <=
-- BEGIN ENABLE_(SRA,SRAV)
"1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED and value(31) = '1' else
-- END ENABLE_(SRA,SRAV)
"0000000000000000";
-- BEGIN ENABLE_(SLL,SLLV)
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
-- END ENABLE_(SLL,SLLV)
-- BEGIN ENABLE_(SRL,SRLV,SRA,SRAV)
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
-- END ENABLE_(SRL,SRLV,SRA,SRAV)
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <=
-- BEGIN ENABLE_(SLL,SLLV)
shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
-- END ENABLE_(SLL,SLLV)
-- BEGIN ENABLE_(SRL,SRLV)
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED else
-- END ENABLE_(SRL,SRLV)
-- BEGIN ENABLE_(SRA,SRAV)
shift16R when shift_func = SHIFT_RIGHT_SIGNED else
-- END ENABLE_(SRA,SRAV)
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
-- BEGIN ENABLE_(SLL,SLLV)
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
-- END ENABLE_(SLL,SLLV)
c_shift <=
-- BEGIN ENABLE_(SRL,SRLV)
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED else
-- END ENABLE_(SRL,SRLV)
-- BEGIN ENABLE_(SRA,SRAV)
shift16R when shift_func = SHIFT_RIGHT_SIGNED else
-- END ENABLE_(SRA,SRAV)
(others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 | a9449db3268616bcb8fbe122949a7cf9 | 0.620358 | 3.24264 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_axistream/src/vvc_context.vhd | 1 | 1,420 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_axistream;
use bitvis_vip_axistream.vvc_cmd_pkg.all;
use bitvis_vip_axistream.vvc_methods_pkg.all;
use bitvis_vip_axistream.td_vvc_framework_common_methods_pkg.all;
end context; | mit | 50ace8a7a6be6cc0ada26bab892f3f83 | 0.533803 | 5.590551 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/synthese/IPBus_ml605_ASIP/RAM_single_port.vhd | 1 | 1,796 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:34 05/19/2016
-- Design Name:
-- Module Name: RAM_single_port - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_single_port is
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(11 downto 0);
ADDR : in STD_LOGIC_VECTOR (16 downto 0);
data_out : out STD_LOGIC_VECTOR (11 downto 0));
end RAM_single_port;
architecture Behavioral of RAM_single_port is
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 12;
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 76799) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal screen : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write = '1') then
screen(to_integer(unsigned(ADDR))) <= data_in;
data_out <= data_in;
else
data_out <= screen(to_integer(unsigned(ADDR)));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 13c0e824c2a15715df04e90d4d07200c | 0.607461 | 3.687885 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/UNDEF/DIVIDER_32b_4x_fast.vhd | 1 | 5,231 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_32b_4x_fast is
generic(SIZE: INTEGER := 32);
port(
reset : in STD_LOGIC;
start : in STD_LOGIC;
clk : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
INPUT_2 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_2 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
ready : out STD_LOGIC
);
end DIVIDER_32b_4x_fast;
ARCHITECTURE behav of DIVIDER_32b_4x_fast IS
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to (SIZE/4);
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
begin
process(reset, start, clk)
variable tbuf2 : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf1v : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf1f : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2vv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2vf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2fv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2ff : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf3v : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf3f : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4vv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4vf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4fv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4ff : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
begin
if reset = '1' then
OUTPUT_1 <= (others => '0');
OUTPUT_2 <= (others => '0');
sm <= 0;
ready <= '0';
elsif rising_edge(clk) then
case sm is
when 0 =>
OUTPUT_1 <= buf2;
OUTPUT_2 <= buf1;
ready <= '0';
buf2 <= (others => 'X');
dbuf <= INPUT_2;
buf1 <= (others => 'X');
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
sm <= sm + 1;
else
sm <= sm;
end if;
when others =>
-- PREMIERE ITERATION DEROULEE DE LA DIVISION
tbuf1v((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf1v((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
tbuf1f := buf((2 * SIZE - 2) downto 0) & '0';
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
tbuf2vv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf1v((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf2vv((SIZE - 1) downto 0) := tbuf1v((SIZE - 2) downto 0) & '1';
tbuf2vf := tbuf1v((2 * SIZE - 2) downto 0) & '0';
tbuf2fv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf1f((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf2fv((SIZE - 1) downto 0) := tbuf1f((SIZE - 2) downto 0) & '1';
tbuf2ff := tbuf1f((2 * SIZE - 2) downto 0) & '0';
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
if tbuf1v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf2 := tbuf2vv;
else
tbuf2 := tbuf2vf;
end if;
else
if tbuf1v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf2 := tbuf2fv;
else
tbuf2 := tbuf2ff;
end if;
end if;
-- TROISIEME ITERATION DEROULEE DE LA DIVISION
tbuf3v((2 * SIZE - 1) downto SIZE) := '0' & (tbuf2((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf3v((SIZE - 1) downto 0) := tbuf2((SIZE - 2) downto 0) & '1';
tbuf3f := tbuf2((2 * SIZE - 2) downto 0) & '0';
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
tbuf4vv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf3v((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf4vv((SIZE - 1) downto 0) := tbuf3v((SIZE - 2) downto 0) & '1';
tbuf4vf := tbuf3v((2 * SIZE - 2) downto 0) & '0';
tbuf4fv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf3f((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf4fv((SIZE - 1) downto 0) := tbuf3f((SIZE - 2) downto 0) & '1';
tbuf4ff := tbuf3f((2 * SIZE - 2) downto 0) & '0';
if tbuf2((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
if tbuf3v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf <= tbuf4vv;
else
buf <= tbuf4vf;
end if;
else
if tbuf3f((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf <= tbuf4fv;
else
buf <= tbuf4ff;
end if;
end if;
-- QUEL VA ETRE NOTRE PROCHAIN ETAT ?
if sm /= (SIZE/4) then
sm <= sm + 1;
ready <= '0';
else
sm <= 0;
ready <= '1';
end if;
end case;
end if;
end process;
end behav;
| gpl-3.0 | a20459cad48df9170d2c4c823542fcd2 | 0.51061 | 2.864732 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_checker.vhd | 1 | 5,766 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF Instruction_Memory_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.Instruction_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit | c065aa1a8d02983400d8dc167ffd37a9 | 0.590357 | 4.074912 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/example_design/Video_Memory_exdes.vhd | 1 | 5,009 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Video_Memory_exdes is
PORT (
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0')
);
end Video_Memory_exdes;
architecture xilinx of Video_Memory_exdes is
SIGNAL CLK_i : std_logic;
component Video_Memory is
PORT (
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC;
WE : IN STD_LOGIC;
SPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0')
);
end component;
begin
dmg0 : Video_Memory
port map (
DPRA => DPRA,
CLK => CLK_i,
WE => WE,
SPO => SPO,
DPO => DPO,
A => A,
D => D
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
| mit | 029278092a175c4d599b520d5884ed3b | 0.516071 | 4.516682 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_10_dir/exercise6_10.vhd | 1 | 3,168 | --!
--! @file: exercise6_10.vhd
--! @brief: two digit timer
--! @author: Antonio Gutierrez
--! @date: 2013-10-28
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity two_digit_timer is
generic (fclk: integer := 50_000_000); -- clock freq in Mhz
port (
rst: in std_logic;
ena: in std_logic;
clk: in std_logic;
full_count: out std_logic;
ssd1: out std_logic_vector(3 downto 0);
ssd2: out std_logic_vector(2 downto 0));
end entity two_digit_timer;
--------------------------------------
architecture circuit of two_digit_timer is
begin
-- counter with its inputs and outputs
proc: process (clk, rst)
variable count: integer range 0 to fclk := 0; -- used to know when a second has passed
variable count1: integer range 0 to 9 := 0; -- units
variable count2: integer range 0 to 6 := 0; -- decens
variable full: boolean := false;
begin
if (rst = '1') then
count1:= 0;
count2:= 0;
full := false;
elsif (ena = '1' and clk'event and clk = '1') then -- rising edge and ena asserted?
count := count + 1; -- then increment count of clock periods
if (count = fclk) then -- completed a second?
count := 0;
if (full /= true) then -- haven't reached 60?
count1 := count1 + 1; -- then increment units
if (count1 = 10) then -- units more than 9?
count1 := 0; -- then reset units and increment decens
count2 := count2 + 1;
if (count2 = 6) then -- decens = 60?
full := true; -- flag completion of count
end if;
end if;
end if;
end if;
end if;
-- SSD drivers
digit1: case count1 is
when 0 => ssd1 <= "0000000";
when 1 => ssd1 <= "0000000";
when 2 => ssd1 <= "0000000";
when 3 => ssd1 <= "0000000";
when 4 => ssd1 <= "0000000";
when 5 => ssd1 <= "0000000";
when 6 => ssd1 <= "0000000";
when 7 => ssd1 <= "0000000";
when 8 => ssd1 <= "0000000";
when others => ssd1 <= "0000000";
end case digit1;
digit2: case count2 is
when 0 => ssd2 <= "0000000";
when 1 => ssd2 <= "0000000";
when 2 => ssd2 <= "0000000";
when 3 => ssd2 <= "0000000";
when 4 => ssd2 <= "0000000";
when 5 => ssd2 <= "0000000";
when others => ssd2 <= "0000000";
end case digit2;
end process proc;
full_count = '1' when full = '1' else '0';
end architecture circuit;
--------------------------------------
| gpl-3.0 | 79e12cb371c88ef1d03805e4931bacb4 | 0.433712 | 4.480905 | false | false | false | false |
siam28/neppielight | dvid_in/dvid_input_channel.vhd | 2 | 4,904 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: input_channel - Behavioral
-- Description: The end-to-end processing of a TMDS input channel
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity input_channel is
GENERIC(
fixed_delay : in natural
);
Port ( clk_fabric : in STD_LOGIC;
clk_fabric_x2 : in STD_LOGIC;
clk_input : in STD_LOGIC;
strobe : in STD_LOGIC;
tmds_p : in STD_LOGIC;
tmds_n : in STD_LOGIC;
invert : in STD_LOGIC;
framing : in std_logic_vector(3 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
control : out STD_LOGIC_VECTOR (1 downto 0);
active_data : out std_logic;
sync_seen : out std_logic;
adjust_delay : IN std_logic;
increase_delay : IN std_logic;
reset_delay : IN std_logic;
start_calibrate : IN std_logic;
calibrate_busy : OUT std_logic
);
end input_channel;
architecture Behavioral of input_channel is
COMPONENT input_delay
GENERIC(
fixed_delay : in natural
);
PORT(
bit_clock : IN std_logic;
data_in : IN std_logic;
data_out : OUT std_logic;
control_clock : IN std_logic;
adjust_delay : IN std_logic;
increase_delay : IN std_logic;
reset_delay : IN std_logic;
start_calibrate : IN std_logic;
calibrate_busy : OUT std_logic
);
END COMPONENT;
COMPONENT input_serialiser
PORT(
clk_fabric_x2 : IN std_logic;
clk_input : IN std_logic;
strobe : IN std_logic;
ser_input : IN std_logic;
ser_data : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT gearbox
PORT(
clk_fabric_x2 : IN std_logic;
framing : IN std_logic_vector(3 downto 0);
invert : IN std_logic;
data_in : IN std_logic_vector(4 downto 0);
data_out : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
COMPONENT tmds_decode
PORT(
clk : IN std_logic;
data_in : IN std_logic_vector(9 downto 0);
data_out : OUT std_logic_vector(7 downto 0);
c : OUT std_logic_vector(1 downto 0);
active_data : OUT std_logic
);
END COMPONENT;
signal serial_data : std_logic;
signal delayed_serial_data : std_logic;
signal raw_tmds_word : std_logic_vector(9 downto 0);
signal half_words : std_logic_vector(4 downto 0);
begin
diff_input : IBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "TMDS_33")
port map (
O => serial_data,
I => tmds_p,
IB => tmds_n
);
--i_input_delay: input_delay GENERIC MAP(
-- fixed_delay => fixed_delay
-- ) PORT MAP(
-- bit_clock => clk_input,
-- data_in => serial_data,
-- data_out => delayed_serial_data,
-- control_clock => clk_fabric_x2,
-- adjust_delay => adjust_delay,
-- increase_delay => increase_delay,
-- reset_delay => reset_delay,
-- start_calibrate => start_calibrate,
-- calibrate_busy => calibrate_busy
-- );
i_input_serialiser: input_serialiser PORT MAP(
clk_fabric_x2 => clk_fabric_x2,
clk_input => clk_input,
strobe => strobe,
-- ser_input => delayed_serial_data,
ser_input => serial_data,
ser_data => half_words
);
i_gearbox: gearbox PORT MAP(
clk_fabric_x2 => clk_fabric_x2,
invert => invert,
framing => framing,
data_in => half_words,
data_out => raw_tmds_word
);
i_tmds_decode: tmds_decode PORT MAP(
clk => clk_fabric,
data_in => raw_tmds_word,
data_out => data_out,
c => control,
active_data => active_data
);
look_for_sync: process (clk_fabric)
begin
if rising_edge(clk_fabric) then
------------------------------------------------------------
-- Is the TMDS data one of two special sync codewords?
------------------------------------------------------------
if raw_tmds_word = "1101010100" or raw_tmds_word = "0010101011" then
sync_seen <= '1';
else
sync_seen <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 996c3d6bf9093b0b1b5fedfed7df48f7 | 0.491843 | 3.813375 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/plasma_config.vhd | 1 | 7,099 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package asip_config is
-- INSTRUCTION TYPE (000000)
constant ENABLE_SLL : integer := 1 ; -- "000000";
constant ENABLE_SRL : integer := 1 ; -- "000010";
constant ENABLE_SRA : integer := 1 ; -- "000011";
constant ENABLE_SLLV : integer := 1 ; -- "000100";
constant ENABLE_SRLV : integer := 1 ; -- "000110";
constant ENABLE_SRAV : integer := 1 ; -- "000111";
constant ENABLE_JR : integer := 1 ; -- "001000";
constant ENABLE_JALR : integer := 1 ; -- "001001";
constant ENABLE_MOVZ : integer := 1 ; -- "001010";
constant ENABLE_MOVN : integer := 1 ; -- "001011";
constant ENABLE_SYSCALL : integer := 1 ; -- "001100";
constant ENABLE_BREAK : integer := 1 ; -- "001101";
constant ENABLE_SYNC : integer := 1 ; -- "001111";
constant ENABLE_MFHI : integer := 1 ; -- "010000";
constant ENABLE_MTHI : integer := 1 ; -- "010001";
constant ENABLE_MFLO : integer := 1 ; -- "010010";
constant ENABLE_MTLO : integer := 1 ; -- "010011";
constant ENABLE_MULT : integer := 1 ; -- "011000";
constant ENABLE_MULTU : integer := 1 ; -- "011001";
constant ENABLE_DIV : integer := 1 ; -- "011010";
constant ENABLE_DIVU : integer := 1 ; -- "011011";
constant ENABLE_ADD : integer := 1 ; -- "100000";
constant ENABLE_ADDU : integer := 1 ; -- "100001";
constant ENABLE_SUB : integer := 1 ; -- "100010";
constant ENABLE_SUBU : integer := 1 ; -- "100011";
constant ENABLE_AND : integer := 1 ; -- "100100";
constant ENABLE_OR : integer := 1 ; -- "100101";
constant ENABLE_XOR : integer := 1 ; -- "100110";
constant ENABLE_NOR : integer := 1 ; -- "100111";
constant ENABLE_SLT : integer := 1 ; -- "101010";
constant ENABLE_SLTU : integer := 1 ; -- "101011";
constant ENABLE_DADDU : integer := 1 ; -- "101101";
constant ENABLE_TGEU : integer := 1 ; -- "110001";
constant ENABLE_TLT : integer := 1 ; -- "110010";
constant ENABLE_TLTU : integer := 1 ; -- "110011";
constant ENABLE_TEQ : integer := 1 ; -- "110100";
constant ENABLE_TNE : integer := 1 ; -- "110110";
-- INSTRUCTION TYPE (000001)
constant ENABLE_BLTZ : integer := 1 ; -- "00000";
constant ENABLE_BGEZ : integer := 1 ; -- "00001";
constant ENABLE_BLTZL : integer := 1 ; -- "00010";
constant ENABLE_BGEZL : integer := 1 ; -- "00011";
constant ENABLE_BLTZAL : integer := 1 ; -- "10000";
constant ENABLE_BGEZAL : integer := 1 ; -- "10001";
constant ENABLE_BLTZALL : integer := 1 ; -- "10010";
constant ENABLE_BGEZALL : integer := 1 ; -- "10011";
-- INSTRUCTION TYPE (000010)
constant ENABLE_J : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000011)
constant ENABLE_JAL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000100)
constant ENABLE_BEQ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000101)
constant ENABLE_BNE : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000110)
constant ENABLE_BLEZ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000111)
constant ENABLE_BGTZ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001000)
constant ENABLE_ADDI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001001)
constant ENABLE_ADDIU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001010)
constant ENABLE_SLTI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001011)
constant ENABLE_SLTIU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001100)
constant ENABLE_ANDI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001101)
constant ENABLE_ORI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001110)
constant ENABLE_XORI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001111)
constant ENABLE_LUI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010000)
constant ENABLE_COP0 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010001)
constant ENABLE_COP1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010010)
constant ENABLE_COP2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010011)
constant ENABLE_COP3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010100)
constant ENABLE_BEQL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010101)
constant ENABLE_BNEL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010110)
constant ENABLE_BLEZL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010111)
constant ENABLE_BGTZL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100000)
constant ENABLE_LB : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100001)
constant ENABLE_LH : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100010)
constant ENABLE_LWL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100011)
constant ENABLE_LW : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100100)
constant ENABLE_LBU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100101)
constant ENABLE_LHU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100110)
constant ENABLE_LWR : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101000)
constant ENABLE_SB : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101001)
constant ENABLE_SH : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101010)
constant ENABLE_SWL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101011)
constant ENABLE_SW : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101110)
constant ENABLE_SWR : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101111)
constant ENABLE_CACHE : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110000)
constant ENABLE_LL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110001)
constant ENABLE_LWC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110010)
constant ENABLE_LWC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110011)
constant ENABLE_LWC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110101)
constant ENABLE_LDC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110110)
constant ENABLE_LDC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110111)
constant ENABLE_LDC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111000)
constant ENABLE_SC : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111001)
constant ENABLE_SWC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111010)
constant ENABLE_SWC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111011)
constant ENABLE_SWC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111101)
constant ENABLE_SDC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111110)
constant ENABLE_SDC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111111)
constant ENABLE_SDC3 : integer := 1 ; -- "";
end;
package body asip_config is
-- NOTHING FOR NOW ;-)
end;
| gpl-3.0 | 83bb6fc564abc7808834b8553e73edd1 | 0.546838 | 3.728466 | false | false | false | false |
chibby0ne/vhdl-book | Chapter7/exercise7_9_dir/exercise7_9.vhd | 1 | 998 | --!
--! @file: exercise7_9.vhd
--! @brief: frequency divider with variable
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity freq_divider is
generic (M: integer := 4;);
port (
clkin: in std_logic;
clkout: out std_logic);
end entity freq_divider;
--------------------------------------
architecture circuit of freq_divider is
--signals and declarations
begin
proc: process (clk)
variable counter: integer range 0 to M := 0;
begin
if (clk'event and clk = '1') then
counter := counter + 1;
if (counter = M/2) then
clkout <= '1';
elsif (counter = M) then
counter := 0;
clkout <= '0';
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | c484df4e742e8984f5a4305688d3f755 | 0.473948 | 4.396476 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_MIN_MAX_8b.vhd | 1 | 2,579 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MIN_MAX_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR( 1 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MIN_MAX_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MIN RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
variable bTemp1 : STD_LOGIC;
variable bTemp2 : STD_LOGIC;
variable bTemp3 : STD_LOGIC;
variable bTemp4 : STD_LOGIC;
begin
IF( UNSIGNED(INPUT_1( 7 downto 0)) < UNSIGNED(INPUT_2( 7 downto 0)) ) THEN bTemp1 := 1; ELSE bTemp1 := 0; END IF;
IF( UNSIGNED(INPUT_1(15 downto 8)) < UNSIGNED(INPUT_2(15 downto 8)) ) THEN bTemp2 := 1; ELSE bTemp2 := 0; END IF;
IF( UNSIGNED(INPUT_1(23 downto 16)) < UNSIGNED(INPUT_2(23 downto 16)) ) THEN bTemp3 := 1; ELSE bTemp3 := 0; END IF;
IF( UNSIGNED(INPUT_1(31 downto 24)) < UNSIGNED(INPUT_2(31 downto 24)) ) THEN bTemp4 := 1; ELSE bTemp4 := 0; END IF;
bTemp1 := bTemp1 XOR FONCTION(0);
bTemp2 := bTemp2 XOR FONCTION(0);
bTemp3 := bTemp3 XOR FONCTION(0);
bTemp4 := bTemp4 XOR FONCTION(0);
CASE bTemp1 IS
WHEN '0' => rTemp1 := INPUT_1(7 downto 0);
WHEN '1' => rTemp1 := INPUT_2(7 downto 0);
WHEN OTHERS => null;
END CASE;
CASE bTemp2 IS
WHEN '0' => rTemp2 := INPUT_1(15 downto 8);
WHEN '1' => rTemp2 := INPUT_2(15 downto 8);
WHEN OTHERS => null;
END CASE;
CASE bTemp3 IS
WHEN '0' => rTemp3 := INPUT_1(23 downto 16);
WHEN '1' => rTemp3 := INPUT_2(23 downto 16);
WHEN OTHERS => null;
END CASE;
CASE bTemp4 IS
WHEN '0' => rTemp4 := INPUT_1(31 downto 24);
WHEN '1' => rTemp4 := INPUT_2(31 downto 24);
WHEN OTHERS => null;
END CASE;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 94f8fd2a151bfeb86a3c064c54b98209 | 0.557968 | 3.156671 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/simulation/Ram_tb.vhd | 1 | 4,426 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Ram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Ram_tb IS
END ENTITY;
ARCHITECTURE Ram_tb_ARCH OF Ram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Ram_synth_inst:ENTITY work.Ram_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | bfde3c4b015ccae138d2e8eb883d9f6a | 0.599187 | 4.461694 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/disassembler.vhd | 1 | 22,652 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity disassembler is
port(
clk : in std_logic;
reset : in std_logic;
pause : in std_logic;
opcode : in std_logic_vector(31 downto 0);
pc_addr : in std_logic_vector(31 downto 2)
);
end; --entity control
architecture logic of disassembler is
-- synthesis_off
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tohex( n : std_logic_vector(3 downto 0) ) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
function chr_one_zero(int: std_logic) return character is
variable c: character;
begin
case int is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
return c;
end chr_one_zero;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function bin_char(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
variable bitv : std_logic;
begin
r := 1;
for i in slv'range loop
bitv := slv(i);
result(r) := chr_one_zero( bitv );
r := r + 1;
end loop;
return result;
end bin_char;
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := to_integer( unsigned(v) );
s(1) := darr(val / 10);
s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
-----------------------------------------------------------------------------
function tostrd(n : integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
if( n < 0) then
tmp(len+1) := '-';
len := len + 1;
end if;
return(tmp(len+1 downto 1));
end;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
function tostrud(n : integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
-----------------------------------------------------------------------------
--
--
--
--function no_code return string is
--begin
-- return "XXXXXX";
--end;
--
--
--
function intr2_code(v, f:std_logic_vector) return string is
begin
return bin_char(v) & " " & bin_char(f) & " - ";
end;
--
--
--
function intr_code(v:std_logic_vector) return string is
begin
return bin_char(v) & " " & "XXXXXX" & " - ";
end;
--
--
--
function ins2st( opcode : std_logic_vector(31 downto 0) ) return string is
-- uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is "assembler.log";
variable hex_file_line : line;
variable hex_output_line : line; -- BLG
variable c : character;
variable index : natural;
variable line_length : natural := 0;
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable target : std_logic_vector(25 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable regA, regB, regC : integer;
variable re : std_logic_vector(4 downto 0);
variable vRE : integer;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
target := opcode(25 downto 0);
-- ON RECUEPERE LES NUMEROS DES REGISTRES CONCERNES
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
rtx := opcode(20 downto 16);
re := opcode(10 downto 6);
-- On recupere le numero des registres
regA := to_integer( unsigned(rd) );
regB := to_integer( unsigned(rt) );
regC := to_integer( unsigned(rs) );
vRE := to_integer( unsigned(re) );
case op is
when "000000" => --SPECIAL
case func is
when "000000" =>
if( (regC = 0) and (regB = 0) and (vRE = 0) )then
return intr2_code(op, func) & " NOP";
else
return intr2_code(op, func) & " SLL r[" & tostrd( regC ) & "] = r[" & tostrd( regB ) & "] << " & tostrd( vRE ) & ";";
end if;
-- when "000001" =>
when "000010" => return intr2_code(op, func) & " SRL r[" & tostrd( regC ) & "] = u[" & tostrd( regB ) & "] >> " & tostrd( vRE ) & ";";
when "000011" => return intr2_code(op, func) & " SRA r[" & tostrd( regC ) & "] = r[" & tostrd( regB ) & "] >> " & tostrd( vRE ) & ";";
when "000100" => return intr2_code(op, func) & " SLLV r[" & tostrd( regC ) & "] = r[" & tostrd( regB ) & "] << r[" & tostrd( regC ) & "];";
-- when "000101" =>
when "000110" => return intr2_code(op, func) & " SRLV r[" & tostrd( regC ) & "] = u[" & tostrd( regB ) & "] >> r[" & tostrd( regC ) & "];";
when "000111" => return intr2_code(op, func) & " SRAV r[" & tostrd( regC ) & "] = r[" & tostrd( regB ) & "] >> r[" & tostrd( regC ) & "];";
when "001000" => return intr2_code(op, func) & " JR s->pc_next=r[" & tostrd( regC ) & "];";
when "001001" => return intr2_code(op, func) & " JALR r[" & tostrd( regC ) & "]=s->pc_next; s->pc_next=r[" & tostrd( regC ) & "];";
when "001010" => return intr2_code(op, func) & " MOVZ if(!r[" & tostrd( regB ) & "]) r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "]; /*IV*/";
when "001011" => return intr2_code(op, func) & " MOVN if( r[" & tostrd( regB ) & "]) r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "]; /*IV*/";
when "001100" => return intr2_code(op, func) & " SYSCALL";
when "001101" => return intr2_code(op, func) & " BREAK (code = " & tostrd ( to_integer(unsigned(opcode(25 downto 6))) ) & ")"; -- s->wakeup=1;";
when "001111" => return intr2_code(op, func) & " SYNC s->wakeup=1;";
when "010000" => return intr2_code(op, func) & " MFHI r[" & tostrd( regC ) & "] = s->hi;";
when "010001" => return intr2_code(op, func) & " MTHI s->hi = r[" & tostrd( regC ) & "];";
when "010010" => return intr2_code(op, func) & " MFLO r[" & tostrd( regC ) & "] = s->lo;";
when "010011" => return intr2_code(op, func) & " MTLO s->lo = r[" & tostrd( regC ) & "];";
-- when "010100" =>
-- when "010101" =>
-- when "010110" =>
-- when "010111" =>
when "011000" => return intr2_code(op, func) & " MULT s->lo = r[" & tostrd( regC ) & "] * r[" & tostrd( regB ) & "]; s->hi=0;\n";
when "011001" => return intr2_code(op, func) & " MULTU s->lo = r[" & tostrd( regC ) & "] * r[" & tostrd( regB ) & "]; s->hi=0;\n";
when "011010" => return intr2_code(op, func) & " DIV s->lo = r[" & tostrd( regC ) & "] / r[" & tostrd( regB ) & "]; s->hi=r[" & tostrd( regC ) & "]%r[" & tostrd( regB ) & "];";
when "011011" => return intr2_code(op, func) & " DIVU s->lo = r[" & tostrd( regC ) & "] / r[" & tostrd( regB ) & "]; s->hi=r[" & tostrd( regC ) & "]%r[" & tostrd( regB ) & "];";
-- when "011100" =>
-- when "011101" =>
-- when "011110" =>
-- when "011111" =>
when "100000" => return intr2_code(op, func) & " ADD r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] + r[" & tostrd( regB ) & "];";
when "100001" => return intr2_code(op, func) & " ADDU r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] + r[" & tostrd( regB ) & "];";
when "100010" => return intr2_code(op, func) & " SUB r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] - r[" & tostrd( regB ) & "];";
when "100011" => return intr2_code(op, func) & " SUBU r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] - r[" & tostrd( regB ) & "];";
when "100100" => return intr2_code(op, func) & " AND r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] & r[" & tostrd( regB ) & "];";
when "100101" => return intr2_code(op, func) & " OR r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] | r[" & tostrd( regB ) & "];";
when "100110" => return intr2_code(op, func) & " XOR r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] ^ r[" & tostrd( regB ) & "];";
when "100111" => return intr2_code(op, func) & " NOR r[" & tostrd( regC ) & "] = ~(r[" & tostrd( regC ) & "] | r[" & tostrd( regB ) & "]);";
-- when "101000" =>
-- when "101001" =>
when "101010" => return intr2_code(op, func) & " SLT r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] < r[" & tostrd( regB ) & "];";
when "101011" => return intr2_code(op, func) & " SLTU r[" & tostrd( regC ) & "] = u[" & tostrd( regC ) & "] < u[" & tostrd( regB ) & "];";
-- when "101100" =>
when "101101" => return intr2_code(op, func) & " DADDU r[" & tostrd( regC ) & "] = r[" & tostrd( regC ) & "] + u[" & tostrd( regB ) & "];";
-- when "101110" =>
-- when "101111" =>
-- when "110000" =>
when "110001" => return intr2_code(op, func) & " TGEU";
when "110010" => return intr2_code(op, func) & " TLT";
when "110011" => return intr2_code(op, func) & " TLTU";
when "110100" => return intr2_code(op, func) & " TEQ ";
-- when "110101" =>
when "110110" => return intr2_code(op, func) & " TNE ";
-- when "110111" =>
-- when "111000" =>
-- when "111001" =>
-- when "111010" =>
-- when "111011" =>
-- when "111100" =>
-- when "111101" =>
-- when "111110" =>
-- when "111111" =>
when others => return intr2_code(op, func) & " UNKNOW INSTRUCTION (1)";
ASSERT false REPORT "ON LANCE UN CRASH VOLONTAIRE (INSTR = CRASH)" SEVERITY FAILURE;
end case;
when "000001" => --REGIMM
case rtx is
when "10000" => return intr2_code(op, rtx) & " BLTZAL r[31] = s->pc_next; branch=r[" & tostrd( regC ) & "] < 0;";
when "00000" => return intr2_code(op, rtx) & " BLTZ branch=r[" & tostrd( regC ) & "]<0;";
when "10001" => return intr2_code(op, rtx) & " BGEZAL r[31] = s->pc_next; branch=r[" & tostrd( regC ) & "] >= 0;";
when "00001" => return intr2_code(op, rtx) & " BGEZ branch=r[" & tostrd( regC ) & "]>=0;";
when "10010" => return intr2_code(op, rtx) & " BLTZALL r[31] = s->pc_next; lbranch=r[" & tostrd( regC ) & "] < 0;";
when "00010" => return intr2_code(op, rtx) & " BLTZL lbranch = r[" & tostrd( regC ) & "]<0;";
when "10011" => return intr2_code(op, rtx) & " BGEZALL r[31] = s->pc_next; lbranch=r[" & tostrd( regC ) & "] >= 0;";
when "00011" => return intr2_code(op, rtx) & " BGEZL lbranch = r[" & tostrd( regC ) & "] >= 0;";
when others => return intr2_code(op, rtx) & " UNKNOW INSTRUCTION (2)";
ASSERT false REPORT "ON LANCE UN CRASH VOLONTAIRE (INSTR = CRASH)" SEVERITY FAILURE;
end case;
when "000010" => return intr_code(op) & " J s->pc_next=(s->pc&0xf0000000)| " & tostrd ( to_integer(unsigned(target)) ) & ";"; --target;";
when "000011" => return intr_code(op) & " JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)| "& tostrd ( to_integer(unsigned(target)) ) & ";"; --target;";
when "000100" => return intr_code(op) & " BEQ branch = r[" & tostrd( regC ) & "] == r[" & tostrd( regB ) & "];";
when "000101" => return intr_code(op) & " BNE branch = r[" & tostrd( regC ) & "] != r[" & tostrd( regB ) & "];";
when "000110" => return intr_code(op) & " BLEZ branch = r[" & tostrd( regC ) & "] <= 0;";
when "000111" => return intr_code(op) & " BGTZ branch = r[" & tostrd( regC ) & "] > 0;";
when "001000" => return intr_code(op) & " ADDI r[" & tostrd( regB ) & "] = r[" & tostrd( regC ) & "] + (short)" & tostrd ( to_integer(signed(imm)) ) & ";";
when "001001" => return intr_code(op) & " ADDIU u[" & tostrd( regB ) & "] = u[" & tostrd( regC ) & "] + (short)" & tostrud( to_integer(signed(imm)) ) & ";";
when "001010" => return intr_code(op) & " SLTI r[" & tostrd( regB ) & "] = r[" & tostrd( regC ) & "] < (short)" & tostrd ( to_integer(signed(imm)) ) & ";";
when "001011" => return intr_code(op) & " SLTIU u[" & tostrd( regB ) & "] = u[" & tostrd( regC ) & "] < (unsigned long)(short)" & tostrud( to_integer(signed(imm)) ) & ";";
when "001100" => return intr_code(op) & " ANDI r[" & tostrd( regB ) & "] = r[" & tostrd( regC ) & "] & " & tostrud( to_integer(signed(imm)) ) & ";";
when "001101" => return intr_code(op) & " ORI r[" & tostrd( regB ) & "] = r[" & tostrd( regC ) & "] | " & tostrud( to_integer(signed(imm)) ) & ";";
when "001110" => return intr_code(op) & " XORI r[" & tostrd( regB ) & "] = r[" & tostrd( regC ) & "] ^ " & tostrud( to_integer(signed(imm)) ) & ";";
when "001111" => return intr_code(op) & " LUI r[" & tostrd( regB ) & "] = (" & tostrud( to_integer(signed(imm)) ) & " << 16);";
when "010000" => return intr_code(op) & " COP0";
when "010001" => return intr_code(op) & " COP1";
when "010010" => return intr_code(op) & " COP2";
when "010011" => return intr_code(op) & " COP3";
when "010100" => return intr_code(op) & " BEQL lbranch=r[" & tostrd( regC ) & "] == r[" & tostrd( regB ) & "];";
when "010101" => return intr_code(op) & " BNEL lbranch=r[" & tostrd( regC ) & "] != r[" & tostrd( regB ) & "];";
when "010110" => return intr_code(op) & " BLEZL lbranch=r[" & tostrd( regC ) & "] <= 0;";
when "010111" => return intr_code(op) & " BGTZL lbranch=r[" & tostrd( regC ) & "] > 0;";
-- when "011000" =>
-- when "011001" =>
-- when "011010" =>
-- when "011011" =>
-- when "011100" =>
-- when "011101" =>
-- when "011110" =>
-- when "011111" =>
when "100000" => return intr_code(op) & " LB r[" & tostrd( regB ) & "] =* (signed char*)ptr;";
when "100001" => return intr_code(op) & " LH r[" & tostrd( regB ) & "] =* (signed short*)ptr;";
when "100010" => return intr_code(op) & " LWL //Not Implemented";
when "100011" => return intr_code(op) & " LW r[" & tostrd( regB ) & "] =* (long*)ptr;";
when "100100" => return intr_code(op) & " LBU r[" & tostrd( regB ) & "] =* (unsigned char*)ptr;";
when "100101" => return intr_code(op) & " LHU r[" & tostrd( regB ) & "] =* (unsigned short*)ptr;";
when "100110" => return intr_code(op) & " LWR //Not Implemented";
-- when "100111" =>
when "101000" => return intr_code(op) & " SB *(char*) ptr = (char)r[" & tostrd( regB ) & "];";
when "101001" => return intr_code(op) & " SH *(short*)ptr = (short)r[" & tostrd( regB ) & "];";
when "101010" => return intr_code(op) & " SWL //Not Implemented";
-- when "101011" => return intr_code(op) & " SW *(long*) ptr = r[" & tostrd( regB ) & "];";
when "101011" => return intr_code(op) & " SW *(long*) r[" & tostrd( regC ) & "] + (" & tostrd ( to_integer(signed(imm)) ) & ") = r[" & tostrd( regB ) & "];";
when "101110" => return intr_code(op) & " SWR //Not Implemented";
when "101111" => return intr_code(op) & " CACHE";
when "110000" => return intr_code(op) & " LL r[" & tostrd( regB ) & "]=*(long*)ptr;";
when "110001" => return intr_code(op) & " LWC1";
when "110010" => return intr_code(op) & " LWC2";
when "110011" => return intr_code(op) & " LWC3";
when "110101" => return intr_code(op) & " LDC1";
when "110110" => return intr_code(op) & " LDC2";
when "110111" => return intr_code(op) & " LDC3";
when "111000" => return intr_code(op) & " SC *(long*)ptr=r[" & tostrd( regB ) & "]; r[" & tostrd( regB ) & "]=1;";
when "111001" => return intr_code(op) & " SWC1";
when "111010" => return intr_code(op) & " SWC2";
when "111011" => return intr_code(op) & " SWC3";
when "111101" => return intr_code(op) & " SDC1";
when "111110" => return intr_code(op) & " SDC2";
when "111111" => return intr_code(op) & " SDC3";
when others => return intr_code(op) & " UNKNOW INSTRUCTION (3) " & bin_char(op);
end case;
return "- UNKNOW INSTRUCTION (4)";
end;
-- synthesis_on
SIGNAL last_pc_addr : std_logic_vector(31 downto 2);
begin
-- synthesis_off
control_logger: process( clk )
file store_file : text open write_mode is "assembler.log";
variable hex_file_line : line;
variable hex_output_line : line; -- BLG
variable l: line;
variable comment: string(1 to 1024);
begin
if (clk'event) and (clk='1') then
if pause = '0' then
last_pc_addr <= pc_addr;
if reset = '0' then
write(l, now, right, 15);
write(l, " : " & "@dr = " & tostf(last_pc_addr & "00") & " - " & ins2st( opcode ));
WRITEline(output, l);
end if;
end if;
else
-- NOTHING TO DO...
end if;
end process;
-- synthesis_on
end; --architecture logic
| gpl-3.0 | 2e5c402f6c6f5e2a7b139242c55fb0cb | 0.500795 | 3.066468 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_RAM_576s.vhd | 1 | 2,820 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_RAM_576s is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture aQ16_8_RAM_576s of Q16_8_RAM_576s is
type ram_type is array (0 to 576-1) of STD_LOGIC_VECTOR (15 downto 0);
signal RAM : ram_type;
SIGNAL READ_C : UNSIGNED(9 downto 0);
SIGNAL WRITE_C : UNSIGNED(9 downto 0);
BEGIN
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(9 downto 0);
begin
if reset = '0' then
WRITE_C <= TO_UNSIGNED(0, 10);
elsif clock'event and clock = '1' then
if write_en = '1' AND holdn = '1' then
TEMP := WRITE_C + TO_UNSIGNED(1, 10);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 10);
END IF;
WRITE_C <= TEMP;
else
WRITE_C <= WRITE_C;
end if;
end if;
end process;
--
-- COMPTEUR EN CHARGE DE LA GENERATION DE L'ADRESSE DES DONNEES
-- A LIRE DANS LA MEMOIRE (ACCES LINAIRE DE 0 => 575)
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(9 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 10);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
-- synthesis translate_off
-- printmsg("(Q16_8_RAM_576s) ===> READING (" & to_int_str( STD_LOGIC_VECTOR( RAM( to_integer(TEMP) ) ), 6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(TEMP),6) );
-- synthesis translate_on
TEMP := TEMP + TO_UNSIGNED(1, 10);
IF TEMP = 576 THEN
TEMP := TO_UNSIGNED(0, 10);
END IF;
end if;
READ_C <= TEMP;
OUTPUT_1 <= STD_LOGIC_VECTOR(RESIZE( SIGNED(RAM( to_integer(TEMP) )), 32));
end if;
end process;
--
--
--
process(clock)
VARIABLE AR : INTEGER RANGE 0 to 575;
VARIABLE AW : INTEGER RANGE 0 to 575;
begin
if clock'event and clock = '1' then
--AR := to_integer( READ_C );
if WRITE_EN = '1' AND holdn = '1' then
AW := to_integer( WRITE_C );
RAM( AW ) <= INPUT_1(15 downto 0);
-- synthesis translate_off
-- printmsg("(Q16_8_RAM_576s) ===> WRITING (" & to_int_str( STD_LOGIC_VECTOR(INPUT_1(15 downto 0)),6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(WRITE_C),6) );
-- synthesis translate_on
end if;
end if;
end process;
END aQ16_8_RAM_576s; | gpl-3.0 | 374fb53bb08a2d330b71f40df0c9af36 | 0.556738 | 2.955975 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/REVERSE_BIT_32b.vhd | 1 | 3,378 | -------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity REVERSE_BIT_32b is
port (
INPUT_1 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end REVERSE_BIT_32b;
architecture synthesis of REVERSE_BIT_32b is
SIGNAL n : std_logic_vector(4 downto 0);
FUNCTION bit_reverse(s1:std_logic_vector) return std_logic_vector is
variable rr : std_logic_vector(s1'high downto s1'low);
begin
for ii in s1'high downto s1'low loop
rr(ii) := s1(s1'high-ii);
end loop;
return rr;
end bit_reverse;
begin
-- Reverse bit order in an integer
-- #include <stdio.h>
-- static unsigned long reverse(unsigned long x) {
-- unsigned long h = 0;
-- int i = 0;
-- for(h = i = 0; i < 32; i++) {
-- h = (h << 1) + (x & 1);
-- x >>= 1;
-- }
-- return h;
-- }
OUTPUT_1(31 downto 0) <= bit_reverse(INPUT_1);
end synthesis;
| gpl-3.0 | 5654b05cd0dedf3d0bd4725a418162d9 | 0.384251 | 4.902758 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_6.vhd | 1 | 4,951 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--use ims.conversion.all;
entity RESOURCE_CUSTOM_6 is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in async32_in_type;
outp : out async32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_6 is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal wBuffer : std_logic_vector(1 downto 0);
signal rBuffer : std_logic_vector(1 downto 0);
COMPONENT ASYNC_RGB_2_YUV
PORT(
rst : IN std_logic;
clk : IN std_logic;
flush : IN std_logic;
holdn : IN std_logic;
INPUT_1 : IN std_logic_vector(31 downto 0);
write_en : IN std_logic;
in_full : OUT std_logic;
OUTPUT_1 : OUT std_logic_vector(31 downto 0);
read_en : IN std_logic;
out_empty : OUT std_logic;
Next_Empty : OUT std_logic
);
END COMPONENT;
COMPONENT CUSTOM_FIFO
PORT(
rst : IN std_logic;
clk : IN std_logic;
flush : IN std_logic;
holdn : IN std_logic;
INPUT_1 : IN std_logic_vector(31 downto 0);
write_en : IN std_logic;
in_full : OUT std_logic;
OUTPUT_1 : OUT std_logic_vector(31 downto 0);
read_en : IN std_logic;
out_empty : OUT std_logic;
Next_Empty : OUT std_logic
);
END COMPONENT;
signal INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal write_en : std_logic;
signal read_en : std_logic;
signal in_full : std_logic;
signal OUTPUT_1 : std_logic_vector(31 downto 0);
signal out_empty : std_logic;
signal Next_Empty : std_logic;
begin
write_en <= (wBuffer(0) AND holdn);
read_en <= (rBuffer(1) AND holdn);
--uut: CUSTOM_FIFO PORT MAP (
uut: ASYNC_RGB_2_YUV PORT MAP (
rst => rst,
clk => clk,
flush => '0',
holdn => '0',
INPUT_1 => inp.op1(31 downto 0),
write_en => write_en,
in_full => in_full,
OUTPUT_1 => outp.result,
read_en => read_en,
out_empty => out_empty,
Next_Empty => Next_Empty
);
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_6 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-- type async32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- signed : std_logic;
-- write_data : std_logic;
-- read_data : std_logic;
-- end record;
-- type async32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
-- end record;
-------------------------------------------------------------------------
reg : process(clk)
variable vready : std_logic;
variable vnready : std_logic;
begin
vready := '0';
vnready := '0';
if rising_edge(clk) then
if (rst = '0') then
--assert false report "STATE XXX => RESET";
--elsif (inp.flush = '1') then
--assert false report "STATE XXX => (inp.flush = '1')";
--state <= "000";
elsif (holdn = '0') then
--assert false report "STATE XXX => (holdn = '1')";
--state <= state;
rBuffer <= rBuffer;
wBuffer <= wBuffer;
else
rBuffer <= rBuffer(0) & inp.read_data;
wBuffer <= wBuffer(0) & inp.write_data;
if( wBuffer(0) = '1' ) then
--printmsg("(IOs) DATA ARE SENDED TO THE INTERFACE (1)");
--printmsg("(IOs) - COMPUTATION INPUT_A IS (" & to_int_str(inp.op1(31 downto 0),6) & " )");
--printmsg("(IOs) - COMPUTATION INPUT_B IS (" & to_int_str(inp.op2(31 downto 0),6) & " )");
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
end if;
if( rBuffer(1) = '1' ) then
--printmsg("(IOs) DATA READ FROM THE INTERFACE");
--printmsg("(IOs) - COMPUTATION INPUT_A IS (" & to_int_str(A,6) & " )");
--printmsg("(IOs) - COMPUTATION INPUT_B IS (" & to_int_str(B,6) & " )");
A <= "00000000000000000000000000000000";
end if;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
-------------------------------------------------------------------------
--outp.result <= A;
outp.icc <= "0000";
end;
| gpl-3.0 | cd9edbe91930b8fbde1dfa1f5bce2c91 | 0.50818 | 3.283156 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_spi/src/vvc_context.vhd | 1 | 1,396 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_spi;
use bitvis_vip_spi.vvc_cmd_pkg.all;
use bitvis_vip_spi.vvc_methods_pkg.all;
use bitvis_vip_spi.td_vvc_framework_common_methods_pkg.all;
end context; | mit | b857878847b31dbe7690a8653f51e6cf | 0.525788 | 5.496063 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_18.vhd | 5 | 3,027 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_18 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_18 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | 65d12a4f667aca17ed195870693c8488 | 0.562934 | 3.319079 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/slow_0_to_9_counter_with_ssd_dir/slow_0_to_9_counter_with_ssd.vhd | 1 | 1,999 | -- author: Antonio Gutierrez
-- date: 08/10/13
-- description: ssd display and ssd driver
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity slow_counter is
generic (fclk: integer := 50_000_000;); ---- 50Mhz
port (
clk, rst: in bit;
ssd: out bit_vector(6 downto 0);
end entity slow_counter;
--------------------------------------
architecture counter of slow_counter is
--signals and declarations
begin
counter: process (clk, rst)
variable counter1: natural range 0 to fclk := 0;
variable counter2: natural range 0 to 10 := 0;
begin
-------------------
---- counter
-------------------
if (rst = '1') then
counter1 := 0;
counter2 := 0;
elsif (clk'event and clk = '1') then
counter1 := counter1 + 1;
if (counter1 = fclk) then
counter1 := 0;
counter2 := counter2 + 1;
if (counter2 = 10) then
counter2 := 0;
end if;
end if;
end if;
-------------------
---- SSD driver:
-------------------
ssddriver: case counter2 is
when 0 => ssd <= "0000000"; ---- "0" in SSD
when 1 => ssd <= "1001111"; ---- "1' in SSD
when 2 => ssd <= "0010010"; ---- "2' in SSD
when 3 => ssd <= "0000110"; ---- "3' in SSD
when 4 => ssd <= "1001100"; ---- "4' in SSD
when 5 => ssd <= "0100100"; ---- "5' in SSD
when 6 => ssd <= "0100000"; ---- "6' in SSD
when 7 => ssd <= "0001111"; ---- "7' in SSD
when 8 => ssd <= "0000000"; ---- "8' in SSD
when 9 => ssd <= "0000100"; ---- "9' in SSD
when others => ssd <= "0110000"; ---- "E' in SSD
end case ssddriver;
end process counter;
end architecture counter;
--------------------------------------
| gpl-3.0 | ec1093ef9cfd614401c1db13172c4a55 | 0.422711 | 4.432373 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/xilinx/RAM16X1D.vhd | 1 | 2,372 | -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/RAM16X1D.vhd,v 1.1 2008/06/19 16:59:25 vandanad Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Description : Xilinx Functional Simulation Library Component
-- / / Static Dual Port Synchronous RAM 16-Deep by 1-Wide
-- /___/ /\ Filename : RAM16X1D.vhd
-- \ \ / \ Timestamp : Thu Apr 8 10:56:47 PDT 2004
-- \___\/\___\
--
-- Revision:
-- 03/23/04 - Initial version.
----- CELL RAM16X1D -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM16X1D is
generic (
INIT : bit_vector(15 downto 0) := X"0000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM16X1D;
architecture RAM16X1D_V of RAM16X1D is
signal MEM : std_logic_vector( 16 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
Variable Index_SP : integer := 16 ;
Variable Index_DP : integer := 16 ;
begin
Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
Index_DP := DECODE_ADDR4(ADDRESS => (DPRA3, DPRA2, DPRA1, DPRA0));
SPO <= MEM(Index_SP);
DPO <= MEM(Index_DP);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index_SP : integer := 16;
variable Index_DP : integer := 16;
begin
Index_SP := DECODE_ADDR4(ADDRESS => (A3, A2, A1, A0));
if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
MEM(Index_SP) <= D after 100 ps;
end if;
end process VITALWriteBehavior;
end RAM16X1D_V;
| gpl-3.0 | d0eb6cb3d5fae8b1987f1e6759030b0e | 0.518128 | 3.276243 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb.vhd | 1 | 4,325 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Font_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Font_tb IS
END ENTITY;
ARCHITECTURE Font_tb_ARCH OF Font_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Font_tb_synth_inst:ENTITY work.Font_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | efbd94345d784db2b848880d9e9c584e | 0.603699 | 4.399797 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_scoreboard/src/predefined_sb.vhd | 1 | 3,108 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string;
end package local_pkg;
package body local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string is
begin
return to_string(value, HEX, KEEP_LEADING_0, INCL_RADIX);
end function;
end package body local_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.generic_sb_pkg;
use work.local_pkg.all;
------------------------------------------------------------------------------------------
-- Package declarations
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
--
-- slv_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector. Vector length is defined by
-- the constant C_SB_SLV_WIDTH located under scoreboard adaptions in adaptions_pkg.
--
------------------------------------------------------------------------------------------
package slv_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(C_SB_SLV_WIDTH-1 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- int_sb_pkg
--
-- Predefined scoreboard package for integer.
--
------------------------------------------------------------------------------------------
package int_sb_pkg is new work.generic_sb_pkg
generic map (t_element => integer,
element_match => "=",
to_string_element => to_string); | mit | ac521c755745954bc539303ad502a730 | 0.484878 | 5.120264 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_stim_gen ([email protected] 2015-09-19-15-43-09).vhd | 1 | 11,029 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (16383 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"Instruction_Memory.mif",
DEFAULT_DATA,
32,
16384);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| mit | c3d0de32502e1059b893693fd74c1a5c | 0.576571 | 3.761596 | false | false | false | false |
ryos36/polyphony-tutorial | Xorshift/xorshift.vhdl | 1 | 2,748 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xorshift is
port(
clk : in std_logic;
rst_n : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(3 downto 0)
);
end xorshift;
architecture RTL of xorshift is
signal y: std_logic_vector(31 downto 0) := X"92d68ca2";
signal state: std_logic_vector(3 downto 0) := "0000";
begin
process(clk)
begin
if clk'event and clk = '1' then
if rst_n = '0' then
d_en_n <= '1';
state <= "0000";
else
case state is
when "0000" =>
if kick_n = '0' then
y <= y xor
(y((31 - 13) downto 0) & "0000000000000");
state <= "0001";
end if;
when "0001" =>
y <= y xor
("00000000000000000" & y(31 downto 17));
state <= "0011";
when "0011" =>
y <= y xor
(y((31 - 5) downto 0) & "00000");
state <= "0010";
when "0010" =>
state <= "0110";
d_en_n <= '0';
data <= y(3 downto 0);
when "0110" =>
state <= "0111";
data <= y(7 downto 4);
when "0111" =>
state <= "0101";
data <= y(11 downto 8);
when "0101" =>
state <= "0100";
data <= y(15 downto 12);
when "0100" =>
state <= "1100";
data <= y(19 downto 16);
when "1100" =>
state <= "1101";
data <= y(23 downto 20);
when "1101" =>
state <= "1111";
data <= y(27 downto 24);
when "1111" =>
state <= "1110";
data <= y(31 downto 28);
when "1110" =>
state <= "1010";
d_en_n <= '1';
when "1010" =>
state <= "1000";
when "1000" =>
state <= "0000";
when others =>
null;
end case;
end if;
end if;
end process;
end RTL;
| mit | 04b7bcba2bf0560ea9df4ed8ae856e7e | 0.314774 | 4.924731 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/string_methods_pkg.vhd | 1 | 51,719 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.math_real.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural;
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function replace_backslash_r_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
function add_msg_delimiter(
msg : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
elsif (width <= val'length) then
return val(1 to width);
else
v_result := (others => char);
if side = LEFT then
v_result(1 to val'length) := val;
else
v_result(v_result'length-val'length+1 to v_result'length) := val;
end if;
end if;
return v_result;
end pad_string;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := pad_string(remove_initial_chars(val,v_num_leading_space),' ',v_formatted_val'length,LEFT);
v_val_length := remove_initial_chars(val,v_num_leading_space)'length;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val(1 to v_val_length);
end if;
end if;
-- Justify if string is within the width specifications
if justified = left then
v_result(1 to v_val_length) := v_formatted_val(1 to v_val_length);
elsif justified = right then
v_result(width - v_val_length + 1 to width) := v_formatted_val(1 to v_val_length);
end if;
return v_result;
end function;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_start_pos : natural;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := pad_string(remove_initial_chars(val,v_num_leading_space),' ',v_formatted_val'length,LEFT);
v_val_length := remove_initial_chars(val,v_num_leading_space)'length;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val(1 to v_val_length);
end if;
end if;
-- Justify if string is within the width specifications
v_start_pos := natural(ceil((real(width)-real(v_val_length))/real(2))) + 1;
v_result(v_start_pos to v_start_pos + v_val_length-1) := v_formatted_val(1 to v_val_length);
return v_result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()");
for i in a_vector'right downto a_vector'left loop
if a_vector(i) /= ' ' then
return i;
end if;
end loop;
return result_if_not_found;
end;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural is
begin
return pos_of_leftmost(NUL, vector, vector'length) - 1;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string is
begin
if return_val then
return val1;
else
return val2;
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function replace_backslash_r_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_R_AS_LF then
loop
if (source(v_source_idx to v_source_idx+1) = "\r") then
v_dest_idx := v_dest_idx + 1;
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 2;
else
exit;
end if;
end loop;
else
return "";
end if;
end if;
return v_dest(1 to v_dest_idx);
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26 * val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
elsif val'length = 1 then
-- Value length is 1
-- Return the single value it contains
return to_string(val(val'low), radix, format, prefix);
else
-- Value length more than 1
-- Comma-separate all array members and return
write(v_line, string'("("));
for i in val'range loop
write(v_line, to_string(val(i), radix, format, prefix));
if i < val'right and val'ascending then
write(v_line, string'(", "));
elsif i > val'right and not val'ascending then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), justified, width));
end;
-- function to_string(
-- dummy : t_void
-- ) return string is
-- begin
-- return "VOID";
-- end function;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_more_than_expected_alerts : boolean := false;
variable v_less_than_expected_alerts : boolean := false;
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** INTERMEDIATE SUMMARY OF ALL ALERTS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
else -- order=FINAL
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** FINAL SUMMARY OF ALL ALERTS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
end if;
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok" & LF);
else
write(v_line, " *** " & to_string(i,0) & " ***" & LF);
if (i > MANUAL_CHECK) then
if (val(i)(REGARD) < val(i)(EXPECT)) then
v_less_than_expected_alerts := true;
else
v_more_than_expected_alerts := true;
end if;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequencer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_more_than_expected_alerts then
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
elsif v_less_than_expected_alerts then
write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed.
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
function add_msg_delimiter(
msg : string
) return string is
begin
if msg'length /= 0 then
if valid_length(msg) /= 1 then
if msg(1) = C_MSG_DELIMITER then
return msg;
else
return C_MSG_DELIMITER & msg & C_MSG_DELIMITER;
end if;
end if;
end if;
return "";
end;
end package body string_methods_pkg;
| mit | 64c96d7c71bbd5b7e0ec0300c948c1d5 | 0.581469 | 3.774558 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_A.vhd | 1 | 9,995 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_A is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_A is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(2 downto 0);
signal gated_clock : std_logic;
signal nIdle : std_logic;
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_1 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
process(clk)
variable gated : std_logic;
begin
if clk'event and clk = '1' then
gated := '0';
--IF ( (inp.dInstr(31 downto 30) & inp.dInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
--gated := '1';
--END IF;
IF ( (inp.aInstr(31 downto 30) & inp.aInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
gated := '1';
END IF;
IF ( (inp.eInstr(31 downto 30) & inp.eInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXECUTION PIPELINE STAGE";
gated := '1';
END IF;
--IF ( (inp.mInstr(31 downto 30) & inp.mInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE MEMORY PIPELINE STAGE";
-- gated := '1';
--END IF;
--IF ( (inp.xInstr(31 downto 30) & inp.xInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXCEPTION PIPELINE STAGE";
--gated := '1';
--END IF;
-- synthesis translate_off
IF ( (nIdle = '0') AND (gated = '1') ) THEN
--printmsg( "(PGDC) ENABLING THE PGDC CLOCK GENERATION" );
ELSIF( (nIdle = '1') AND (gated = '0') ) THEN
--printmsg( "(PGDC) DISABLING THE PGDC CLOCK GENERATION" );
END IF;
-- synthesis translate_on
nIdle <= gated;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
gated_clock <= clk AND nIdle;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.op1, inp.op2)
--begin
--At <= inp.op1(31 downto 0);
--Bt <= inp.op2(31 downto 0);
--if( nIdle = '1' )then
-- REPORT "(PGDC) (At, Bt) MEMORISATION PROCESS";
-- if ( (At(30) /= '-') AND (At(30) /= 'X') AND (At(30) /= 'U')) then
-- printmsg("(PGDC) =====> (At) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
-- end if;
-- if ( (Bt(30) /= '-') AND (Bt(30) /= 'X') AND (Bt(30) /= 'U')) then
-- printmsg("(PGDC) =====>(Bt) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
-- end if;
-- --printmsg("(PGDC) (At, Bt) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & " & " & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.start)
--begin
-- if (inp.start = '1') then
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME UP";
-- else
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME DOWN";
-- end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- DESCRIPTION ORIGINALE QUI FONCTIONNE TRES TRES BIEN
-- reg : process(clk)
-- variable vready, vnready : std_logic;
-- begin
-- vready := '0';
-- vnready := '0';
-- if clk'event and clk = '1' then
-- if (rst = '0') then
-- state <= "000";
-- elsif (inp.flush = '1') then
-- state <= "000";
-- elsif (holdn = '0') then
-- state <= state;
-- else
-- case state is
--ON ATTEND LA COMMANDE DE START
-- when "000" =>
-- if (inp.start = '1') then
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "001";
-- else
-- state <= "000";
-- A <= A;
-- B <= B;
-- end if;
--ON COMMENCE LE CALCUL
-- when "001" =>
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "011";
--ON COMMENCE LE CALCUL
-- when "010" =>
-- if( SIGNED(A) > SIGNED(B) ) then
-- A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
-- else
-- B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
-- end if;
-- state <= "011";
--ON TEST LES DONNEES (FIN D'ITERATION)
-- when "011" =>
-- if(SIGNED(A) = SIGNED(B)) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
-- A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
-- state <= "100";
-- vnready := '1';
-- else
-- state <= "010";
-- end if;
-- when "100" =>
--ON INDIQUE QUE LE RESULTAT EST PRET
-- vready := '1';
--ON RETOURNE DANS L'ETAT INTIAL
-- state <= "000";
-- when others =>
-- state <= "000";
-- end case;
-- outp.ready <= vready;
-- outp.nready <= vnready;
-- end if; -- if reset
-- end if; -- if clock
-- end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
reg : process(clk, rst)
variable vready, vnready : std_logic;
begin
vready := '0';
vnready := '0';
if (rst = '0') then
state <= "000";
outp.ready <= vready;
outp.nready <= vnready;
elsif clk'event and clk = '1' then
if (inp.flush = '1') then
state <= "000";
elsif (holdn = '0') then
state <= state;
else
case state is
-- ON ATTEND LA COMMANDE DE START
when "000" =>
if (inp.start = '1') then
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "001";
--printmsg("(PGDC) THE START SIGNAL IS UP");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
else
state <= "000";
A <= A;
B <= B;
end if;
-- ON COMMENCE LE CALCUL
when "001" =>
--printmsg("(PGDC) INPUT DATA READING");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "011";
-- ON COMMENCE LE CALCUL
when "010" =>
if( SIGNED(A) > SIGNED(B) ) then
A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
else
B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
end if;
state <= "011";
-- ON TEST LES DONNEES (FIN D'ITERATION)
when "011" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "100";
vnready := '1';
elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
state <= "100";
vnready := '1';
elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
state <= "100";
vnready := '1';
else
state <= "010";
end if;
when "100" =>
--printmsg("(PGDC) ===> COMPUTATION IS NOW FINISHED (" & to_int_str(A,6) & ")");
-- ON INDIQUE QUE LE RESULTAT EST PRET
vready := '1';
-- ON RETOURNE DANS L'ETAT INTIAL
state <= "000";
when others =>
state <= "000";
end case;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
-------------------------------------------------------------------------
outp.result <= A;
outp.icc <= "0000";
end; | gpl-3.0 | 3d5c8c9ff745857eae6103ecf1c8c128 | 0.441821 | 3.312894 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/mult.vhd | 1 | 8,584 | ---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0;
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0);
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <=
-- BEGIN ENABLE_(MFLO)
lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO and negate_reg = '1' else
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
upper_reg when mult_func = MULT_READ_HI else
-- END ENABLE_(MFHI)
ZERO;
pause_out <=
-- BEGIN ENABLE_(MFLO)
'1' when (count_reg /= "000000") and (mult_func = MULT_READ_LO) else
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
'1' when (count_reg /= "000000") and (mult_func = MULT_READ_HI) else
-- END ENABLE_(MFHI)
'0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
--multiplication / division unit
--mult_proc: process(clk, reset_in, a, b, mult_func,
-- a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
-- count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
mult_proc: process(clk, reset_in)
variable count : std_logic_vector(2 downto 0);
begin
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
else
if rising_edge(clk) then
count := "001"; -- FOR DESIGN COMPILER (ASIC)
case mult_func is
-- BEGIN ENABLE_(MTLO)
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
-- END ENABLE_(MTLO)
-- BEGIN ENABLE_(MTHI)
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
-- END ENABLE_(MTHI)
-- BEGIN ENABLE_(MULTU)
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
-- END ENABLE_(MULTU)
-- BEGIN ENABLE_(MULT)
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
else
aa_reg <= a_neg;
bb_reg <= b_neg;
end if;
sign_reg <= a(31) xor b(31);
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
-- END ENABLE_(MULT)
-- BEGIN ENABLE_(DIVU)
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
-- END ENABLE_(DIVU)
-- BEGIN ENABLE_(DIV)
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
-- END ENABLE_(DIV)
when others =>
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
if count_reg /= "000000" then
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
if mode_reg = MODE_MULT then
-- BEGIN ENABLE_(MULT,MULTU)
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
count_reg(5 downto 2) /= "0000" then
upper_reg <= "0000" & upper_reg(31 downto 4);
lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
count := "100";
bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
-- END ENABLE_(MULT,MULTU)
else
-- BEGIN ENABLE_(DIV,DIVU)
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
-- END ENABLE_(DIV,DIVU)
end if;
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
count_reg <= count_reg - count;
end if;
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
end case;
end if;
end if;
end process;
end; --architecture logic
| gpl-3.0 | 8805af59626d2a2a9a23bca6e9bcb845 | 0.45212 | 3.655877 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/plasma_3e.vhd | 1 | 11,354 | ---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 9/15/07
-- FILENAME: plasma_3e.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity divides the clock by two and interfaces to the
-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--use work.mlite_pack.all;
entity plasma_3e is
port(CLK_50MHZ : in std_logic;
RS232_DCE_RXD : in std_logic;
RS232_DCE_TXD : out std_logic;
SD_CK_P : out std_logic; --DDR SDRAM clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); -- bank_address
SD_A : out std_logic_vector(12 downto 0); -- address(row or col)
SD_CS : out std_logic; -- chip_select
SD_RAS : out std_logic; -- row_address_strobe
SD_CAS : out std_logic; -- column_address_strobe
SD_WE : out std_logic; -- write_enable
SD_DQ : inout std_logic_vector(15 downto 0); -- data
SD_UDM : out std_logic; -- upper_byte_enable
SD_UDQS : inout std_logic; -- upper_data_strobe
SD_LDM : out std_logic; -- low_byte_enable
SD_LDQS : inout std_logic; -- low_data_strobe
E_MDC : out std_logic; --Ethernet PHY
E_MDIO : inout std_logic; --management data in/out
E_RX_CLK : in std_logic; --receive clock
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0);
E_TX_CLK : in std_logic; --transmit clock
E_TX_EN : out std_logic; --data valid
E_TXD : out std_logic_vector(3 downto 0);
SF_CE0 : out std_logic; --NOR flash
SF_OE : out std_logic;
SF_WE : out std_logic;
SF_BYTE : out std_logic;
SF_STS : in std_logic; --status
SF_A : out std_logic_vector(24 downto 0);
SF_D : inout std_logic_vector(15 downto 1);
SPI_MISO : inout std_logic;
VGA_VSYNC : out std_logic; --VGA port
VGA_HSYNC : out std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
PS2_CLK : in std_logic; --Keyboard
PS2_DATA : in std_logic;
LED : out std_logic_vector(7 downto 0);
ROT_CENTER : in std_logic;
ROT_A : in std_logic;
ROT_B : in std_logic;
BTN_EAST : in std_logic;
BTN_NORTH : in std_logic;
BTN_SOUTH : in std_logic;
BTN_WEST : in std_logic;
SW : in std_logic_vector(3 downto 0));
end; --entity plasma_if
architecture logic of plasma_3e is
component plasma
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '1';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
signal clk_reg : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal data_r_ddr : std_logic_vector(31 downto 0);
signal byte_we : std_logic_vector(3 downto 0);
signal write_enable : std_logic;
signal pause_ddr : std_logic;
signal pause : std_logic;
signal no_ddr_start : std_logic;
signal no_ddr_stop : std_logic;
signal ddr_active : std_logic;
signal flash_active : std_logic;
signal flash_cnt : std_logic_vector(1 downto 0);
signal flash_we : std_logic;
signal reset : std_logic;
signal gpio0_out : std_logic_vector(31 downto 0);
signal gpio0_in : std_logic_vector(31 downto 0);
begin --architecture
--Divide 50 MHz clock by two
clk_div: process(reset, CLK_50MHZ, clk_reg)
begin
if reset = '1' then
clk_reg <= '0';
elsif rising_edge(CLK_50MHZ) then
clk_reg <= not clk_reg;
end if;
end process; --clk_div
reset <= ROT_CENTER;
E_TX_EN <= gpio0_out(28); --Ethernet
E_TXD <= gpio0_out(27 downto 24);
E_MDC <= gpio0_out(23);
E_MDIO <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';
VGA_VSYNC <= gpio0_out(20);
VGA_HSYNC <= gpio0_out(19);
VGA_RED <= gpio0_out(18);
VGA_GREEN <= gpio0_out(17);
VGA_BLUE <= gpio0_out(16);
LED <= gpio0_out(7 downto 0);
gpio0_in(31 downto 21) <= (others => '0');
gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;
gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;
gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
BTN_SOUTH & BTN_WEST & SW;
ddr_active <= '1' when address(31 downto 28) = "0001" else '0';
flash_active <= '1' when address(31 downto 28) = "0011" else '0';
write_enable <= '1' when byte_we /= "0000" else '0';
u1_plama: plasma
generic map (memory_type => "XILINX_16X",
log_file => "UNUSED",
eUart => '1',
ethernet => '1',
use_cache => '1')
--generic map (memory_type => "DUAL_PORT_",
-- log_file => "output2.txt",
-- ethernet => '1')
PORT MAP (
clk => clk_reg,
reset => reset,
uart_write => RS232_DCE_TXD,
uart_read => RS232_DCE_RXD,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => gpio0_out,
gpioA_in => gpio0_in);
u2_ddr: ddr_ctrl
port map (
clk => clk_reg,
clk_2x => CLK_50MHZ,
reset_in => reset,
address => address(25 downto 2),
byte_we => byte_we,
data_w => data_write,
data_r => data_r_ddr,
active => ddr_active,
no_start => no_ddr_start,
no_stop => no_ddr_stop,
pause => pause_ddr,
SD_CK_P => SD_CK_P, --clock_positive
SD_CK_N => SD_CK_N, --clock_negative
SD_CKE => SD_CKE, --clock_enable
SD_BA => SD_BA, --bank_address
SD_A => SD_A, --address(row or col)
SD_CS => SD_CS, --chip_select
SD_RAS => SD_RAS, --row_address_strobe
SD_CAS => SD_CAS, --column_address_strobe
SD_WE => SD_WE, --write_enable
SD_DQ => SD_DQ, --data
SD_UDM => SD_UDM, --upper_byte_enable
SD_UDQS => SD_UDQS, --upper_data_strobe
SD_LDM => SD_LDM, --low_byte_enable
SD_LDQS => SD_LDQS); --low_data_strobe
--Flash control (only lower 16-bit data lines connected)
flash_ctrl: process(reset, clk_reg, flash_active, write_enable,
flash_cnt, pause_ddr)
begin
if reset = '1' then
flash_cnt <= "00";
flash_we <= '1';
elsif rising_edge(clk_reg) then
if flash_active = '0' then
flash_cnt <= "00";
flash_we <= '1';
else
if write_enable = '1' and flash_cnt(1) = '0' then
flash_we <= '0';
else
flash_we <= '1';
end if;
if flash_cnt /= "11" then
flash_cnt <= flash_cnt + 1;
end if;
end if;
end if; --rising_edge(clk_reg)
if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then
pause <= '1';
else
pause <= '0';
end if;
end process; --flash_ctrl
SF_CE0 <= not flash_active;
SF_OE <= write_enable or not flash_active;
SF_WE <= flash_we;
SF_BYTE <= '1'; --16-bit access
SF_A <= address(25 downto 2) & '0' when flash_active = '1' else
"0000000000000000000000000";
SF_D <= data_write(15 downto 1) when
flash_active = '1' and write_enable = '1'
else "ZZZZZZZZZZZZZZZ";
SPI_MISO <= data_write(0) when
flash_active = '1' and write_enable = '1'
else 'Z';
data_read(31 downto 16) <= data_r_ddr(31 downto 16);
data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0'
else SF_D & SPI_MISO;
end; --architecture logic
| gpl-3.0 | 00e5da18c315220d46d7456303fa0319 | 0.502906 | 3.416792 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_5a_dir/exercise8_5a.vhd | 1 | 1,804 | --!
--! @file: synchronous_counter.vhd
--! @brief: synchronous counter cell
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity sync_counter is
--generic declarations
port (
a, b, clk: in std_logic;
andq, q: out std_logic);
end entity sync_counter;
--------------------------------------
architecture circuit of sync_counter is
signal temp: std_logic;
begin
temp <= a and b;
ff: process (clk)
variable q_ff: std_logic;
begin
if (clk'event and clk = '1') then
q_ff := q_ff xor temp;
end if;
end process ff;
q <= q_ff;
andq <= temp;
end architecture circuit;
--------------------------------------
-- Main code
--------------------------------------
entity exercise8_5a is
--generic declarations
port (
a, b, clk: in std_logic;
q: out std_logic_vector(2 downto 0));
end entity exercise8_5a;
--------------------------------------
architecture circuit of exercise8_5a is
--signals and declarations
component sync_counter is
port (
a, b, clk: in std_logic;
andq, q: out std_logic);
end component sync_counter;
begin
sync_cell0: sync_counter port map (
a => a
b => b,
clk => clk,
q => q(0),
andq => andq(0),
);
sync_cell1: sync_counter port map (
a => andq(0),
b => q(0),
clk => clk,
q => q(1)
);
sync_cell2: sync_counter port map (
a => andq(1)
b => q(1),
clk => clk,
q => q(2)
);
end architecture circuit;
| gpl-3.0 | ef7b0decf06604dcfc3acf0cee2e1984 | 0.459534 | 4 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q8_4_ADD.vhd | 1 | 1,030 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q8_4_ADD is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q8_4_ADD is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(8 downto 0);
VARIABLE OP2 : SIGNED(8 downto 0);
VARIABLE OP3 : SIGNED(8 downto 0);
begin
OP1 := SIGNED( INPUT_1(7) & INPUT_1(7 downto 0) );
OP2 := SIGNED( INPUT_2(7) & INPUT_2(7 downto 0) );
OP3 := OP1 + OP2;
if( OP3 > TO_SIGNED(127, 8) ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR(TO_SIGNED( 127, 32));
elsif( OP3 < TO_SIGNED(-128, 8) ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR(TO_SIGNED(-128, 32));
else
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE( OP3(7 downto 0), 32) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 39be4dcfe51c81970550e52f7705dc4c | 0.526214 | 3.029412 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/eth_dma.vhd | 1 | 6,974 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector( 3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
| gpl-3.0 | e2ad67e69b18c765775bb8f9e029b4b2 | 0.505305 | 3.561798 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd | 1 | 24,677 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_vvc_framework_support_pkg is
constant C_VVC_NAME_MAX_LENGTH : natural := 20;
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Inputs vvc_name and channel are truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH
-- are to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string;
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Input vvc_name is truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH
-- is to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string;
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag");
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay, scope => scope);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout, scope);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg, scope => scope);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)") is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(proc_call) & ": " & add_msg_delimiter(to_string(msg))
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", scope);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command" & format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_CHANNEL_STR : string := to_upper(to_string(channel));
constant C_SCOPE_LENGTH : natural := vvc_name'length + C_INSTANCE_IDX_STR'length + C_CHANNEL_STR'length + 2; -- +2 because of the two added commas
variable v_vvc_name_truncation_value : integer;
variable v_channel_truncation_value : integer;
variable v_vvc_name_truncation_idx : integer;
variable v_channel_truncation_idx : integer;
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_MINIMUM_CHANNEL_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 2) > C_LOG_SCOPE_WIDTH then -- +2 because of the two added commas
alert(TB_WARNING, "The combined width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 2.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If C_SCOPE_LENGTH is greater than allowed width
-- Check if vvc_name is greater than minimum width to truncate
elsif vvc_name'length <= C_MINIMUM_VVC_NAME_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to (C_CHANNEL_STR'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)));
-- Check if channel is greater than minimum width to truncate
elsif C_CHANNEL_STR'length <= C_MINIMUM_CHANNEL_SCOPE_WIDTH then
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If both vvc_name and channel is to be truncated
else
-- Calculate linear scaling of truncation between vvc_name and channel: (a*x)/(a+b), (b*x)/(a+b)
v_vvc_name_truncation_idx := integer(round(real(vvc_name'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
v_channel_truncation_value := integer(round(real(C_CHANNEL_STR'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
-- In case division ended with .5 and both rounded up
if (v_vvc_name_truncation_idx + v_channel_truncation_value) > (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH) then
v_channel_truncation_value := v_channel_truncation_value - 1;
end if;
-- Character index to truncate
v_vvc_name_truncation_idx := vvc_name'length - v_vvc_name_truncation_idx;
v_channel_truncation_idx := C_CHANNEL_STR'length - v_channel_truncation_value;
-- If bellow minimum name width
while v_vvc_name_truncation_idx < C_MINIMUM_VVC_NAME_SCOPE_WIDTH loop
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx + 1;
v_channel_truncation_idx := v_channel_truncation_idx - 1;
end loop;
-- If bellow minimum channel width
while v_channel_truncation_idx < C_MINIMUM_CHANNEL_SCOPE_WIDTH loop
v_channel_truncation_idx := v_channel_truncation_idx + 1;
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx - 1;
end loop;
return vvc_name(1 to v_vvc_name_truncation_idx) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to v_channel_truncation_idx);
end if;
end function;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_SCOPE_LENGTH : integer := vvc_name'length + C_INSTANCE_IDX_STR'length + 1; -- +1 because of the added comma
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 1) > C_LOG_SCOPE_WIDTH then -- +1 because of the added comma
alert(TB_WARNING, "The width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 1.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR;
-- If C_SCOPE_LENGTH is greater than allowed width truncate vvc_name
else
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR;
end if;
end function;
end package body ti_vvc_framework_support_pkg;
| mit | 3e7ab1480e817a4bb36764dc47881722 | 0.5604 | 4.191067 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_20_dir/exercise5_20.vhd | 1 | 1,401 | --!
--! @file: exercise5_20.vhd
--! @brief: Generic Multiplexer
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
use work.my_data_types.all;
--------------------------------------
entity gen_mux is
generic (N: integer := 5;
M: integer := 4);
port (
x: in oneDoneD (0 to M-1, N-1 downto 0);
sel: in integer range 0 to M-1 ;
y: out bit_vector(N-1 downto 0));
end entity gen_mux;
--------------------------------------
architecture circuit of gen_mux is
--signals and declarations
begin
gen: for i in N-1 downto 0 generate
y(i) <= x(sel, i);
end generate gen;
-- maybe this one as well
-- with sel select
-- y <= x(0) when 0,
-- x(sel) when others;
end architecture circuit;
--------------------------------------
entity gen_mux1 is
generic (N: integer := 5;
M: integer := 4);
port (
x: in bit_vector(M*N-1 downto 0);
sel: in integer range 0 to M-1;
y: out bit_vector(N-1 downto 0));
end entity gen_mux1;
--------------------------------------
architecture circuit2 of gen_mux1 is
--signals and declarations
begin
gen1: for i in N-1 downto 0 generate
y(i) <= x(sel*N + i);
end generate gen1;
end architecture circuit2;
--------------------------------------
| gpl-3.0 | 68432e24d1212bbcc991e2b782131d58 | 0.505353 | 3.657963 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/CUSTOM_FIFO.vhd | 1 | 3,511 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CUSTOM_FIFO is
generic (
ADD_WIDTH : integer := 4; -- FIFO word width
WIDTH : integer := 32
); -- Address Width
port (
rst : in std_logic; -- System global Reset
clk : in std_logic; -- System Clock
flush : in STD_LOGIC;
holdn : in STD_LOGIC;
INPUT_1 : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
write_en : in STD_LOGIC;
in_full : OUT STD_LOGIC;
OUTPUT_1 : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
read_en : in STD_LOGIC;
out_empty : OUT STD_LOGIC;
Next_Empty : out std_logic
);
end CUSTOM_FIFO;
architecture ARCH_CUSTOM_FIFO of CUSTOM_FIFO is
-- constant values
constant MAX_ADDR : UNSIGNED(ADD_WIDTH -1 downto 0) := (others => '1');
signal R_ADD : UNSIGNED(ADD_WIDTH - 1 downto 0); -- Read Address
signal W_ADD : UNSIGNED(ADD_WIDTH - 1 downto 0); -- Write Address
signal D_ADD : UNSIGNED(ADD_WIDTH - 1 downto 0); -- Diff Address
--signal WEN_INT : std_logic; -- Internal Write Enable
signal sFull : std_logic; -- Full Flag
signal sEmpty : std_logic; -- Empty Flag
-- DECLARATION DE LA MEMOIRE
TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0);
SIGNAL data : data_array(0 to (2** add_width) ); -- Local data
begin
-- PROCESSUS DECRIVANT LE COMPORTEMENT DE LA MEMOIRE RAM
PROCESS (clk, rst)
VARIABLE COUNTER : UNSIGNED(ADD_WIDTH-1 downto 0); -- Diff Address
VARIABLE NextReadAdress : UNSIGNED(ADD_WIDTH-1 downto 0); -- Diff Address
VARIABLE a : integer := 0;
BEGIN
IF rst = '0' THEN
W_ADD <= (others =>'0');
R_ADD <= (others =>'0');
D_ADD <= (others =>'0');
FOR a IN 0 TO (2** add_width) LOOP
data( a ) <= (others => '0');
END LOOP;
ELSIF clk'event AND clk = '1' THEN
COUNTER := UNSIGNED( D_ADD );
if WRITE_EN = '1' and ( sFULL = '0') then
W_ADD <= W_ADD + 1;
COUNTER := COUNTER + 1;
end if;
NextReadAdress := R_ADD;
if READ_EN = '1' and ( sEMPTY = '0') then
--REPORT "FIFO DATA READ ACTION";
NextReadAdress := NextReadAdress + 1;
COUNTER := COUNTER - 1;
end if;
R_ADD <= NextReadAdress;
D_ADD <= COUNTER;
IF WRITE_EN = '1' THEN
--REPORT "FIFO DATA WRITE ACTION";
data( to_integer( W_add ) ) <= INPUT_1;
END IF;
-- AFFECTATION DIRECTE DE LA SORTIE DE LA FIFO
END IF;
END PROCESS;
OUTPUT_1 <= data( to_integer( R_ADD ) );
--OUTPUT_1 <= data( to_integer( NextReadAdress ) );
--FULL <= '1' when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
-- ON REGARDE SI LA FIFO EST FULL
sFULL <= '1' when (D_ADD = MAX_ADDR) else '0';
in_FULL <= sFULL;
-- ON REGARDE SI LA FIFO EST EMPTY
sEMPTY <= '1' when UNSIGNED(D_ADD) = TO_UNSIGNED(0, ADD_WIDTH) else '0';
out_EMPTY <= sEMPTY;
--wen_int <= '1' when (WRITE_EN = '1' and ( sFULL = '0')) else '0';
-- ON REAGRDE SI LA FIFO SERA EMPTY AU PROCHAIN CYCLE D'HORLOGE
process(D_ADD, READ_EN, WRITE_EN, sEMPTY)
begin
IF (UNSIGNED(D_ADD) = TO_UNSIGNED(1, ADD_WIDTH)) AND (READ_EN = '1' AND WRITE_EN = '0') THEN
Next_Empty <= '1';
ELSIF (UNSIGNED(D_ADD) = TO_UNSIGNED(0, ADD_WIDTH)) AND (READ_EN = '1' AND WRITE_EN = '1') THEN
Next_Empty <= '1';
ELSIF (sEMPTY = '1') AND (WRITE_EN = '1' AND READ_EN = '0') THEN
Next_Empty <= '0';
ELSE
Next_Empty <= sEMPTY;
END IF;
end process;
end ARCH_CUSTOM_FIFO;
| gpl-3.0 | 8187f16ae2c5b66373a83b7c38ab481d | 0.592993 | 2.833737 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_15.vhd | 5 | 1,963 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_15 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_15 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(7 downto 0);
variable rTemp2 : SIGNED(7 downto 0);
variable rTemp3 : SIGNED(7 downto 0);
variable rTemp4 : SIGNED(7 downto 0);
variable sTemp1 : STD_LOGIC;
variable sTemp2 : STD_LOGIC;
variable sTemp3 : STD_LOGIC;
variable sTemp4 : STD_LOGIC;
begin
rTemp1 := SIGNED( INPUT_1( 7 downto 0) );
rTemp2 := SIGNED( INPUT_1(15 downto 8) );
rTemp3 := SIGNED( INPUT_1(23 downto 16) );
rTemp4 := SIGNED( INPUT_1(31 downto 24) );
IF rTemp1 <= TO_SIGNED(0, 8) THEN sTemp1 := INPUT_2( 0); ELSE sTemp1 := '0'; END IF;
IF rTemp2 <= TO_SIGNED(0, 8) THEN sTemp2 := INPUT_2( 8); ELSE sTemp2 := '0'; END IF;
IF rTemp3 <= TO_SIGNED(0, 8) THEN sTemp3 := INPUT_2(16); ELSE sTemp3 := '0'; END IF;
IF rTemp4 <= TO_SIGNED(0, 8) THEN sTemp4 := INPUT_2(24); ELSE sTemp4 := '0'; END IF;
OUTPUT_1 <= "0000000" & sTemp4 & "0000000" & sTemp3 & "0000000" & sTemp2 & "0000000" & sTemp1;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | e13d0e08546d1634443e8852ff678ba7 | 0.564952 | 3.378657 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/tuto_plasma/coproc_4.vhd | 1 | 4,858 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
clock_vga : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0);
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end; --comb_alu_1
architecture logic of coproc_4 is
component VGA_bitmap_640x480 is
generic(bit_per_pixel : integer range 1 to 12:=1; -- number of bits per pixel
grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
clk_VGA : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
ADDR : in std_logic_vector(18 downto 0);
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end component;
SIGNAL mem : UNSIGNED(31 downto 0);
signal tmp_addr : std_logic_vector(18 downto 0);
signal pixel : std_logic_vector(7 downto 0);
--signal tmp_out : std_logic_vector(10 downto 0);
signal data_write : std_logic;
signal counter : integer range 0 to 307199:= 0;
begin
--tmp_addr <= INPUT_1(31 downto 13);
--pixel <= INPUT_1(7 downto 0);
--
process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSE
IF INPUT_1_valid = '1' THEN
IF counter < 307199 THEN
counter <= counter + 1;
ELSE
counter <= 0;
END IF;
END IF;
END IF;
END IF;
end process;
--
--
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- tmp_addr <= (others => '1');
-- pixel <= (others => '0');
-- data_write <= '0';
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- tmp_addr <= INPUT_1(31 downto 13);
-- pixel <= INPUT_1(7 downto 0);
-- data_write <= '1';
-- else
-- data_write <= '0';
-- END IF;
-- END IF;
-- END IF;
-- end process;
--
tmp_addr <= std_logic_vector(to_signed(counter, 19));
--
vga : VGA_bitmap_640x480 generic map(12, false) -- should data be displayed in grayscale
port map(
clk => clock,
clk_vga => clock_vga,
reset => reset,
VGA_hs => VGA_hs,
VGA_vs => VGA_vs,
VGA_red => VGA_red,
VGA_green => VGA_green,
VGA_blue => VGA_blue,
ADDR => tmp_addr,
data_in => INPUT_1(11 downto 0),
data_write => INPUT_1_valid,
data_out => open);
OUTPUT_1 <= "0000000000000"&tmp_addr;
-- process (clock)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
---- assert INPUT_1_valid /= '1' severity failure;
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-------------------------------------------------------------------------
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
-------------------------------------------------------------------------
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-- -------------------------------------------------------------------------
--
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 | 2b88f706fc654d07bfa50135b277dc97 | 0.520585 | 3.152498 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/test/mux.vhd | 1 | 1,998 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:20 05/21/2016
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use work.CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.CONSTANTS.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity muxperso is
Port ( ADDR1 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write1 : in STD_LOGIC;
data_in1 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR2 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write2 : in STD_LOGIC;
data_in2 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR3 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write3 : in STD_LOGIC;
-- data_in3 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR4 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write4 : in STD_LOGIC;
-- data_in4 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR : out STD_LOGIC_vector(ADDR_BIT-1 downto 0);
data_write : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0));
end muxperso;
architecture Behavioral of muxperso is
begin
ADDR<= std_logic_vector( unsigned("00" & ADDR1) + to_unsigned(38400, ADDR_BIT)) when (data_write1 = '1') else std_logic_vector(unsigned("00" & ADDR2) + to_unsigned(38400, ADDR_BIT)) ;
data_out<=data_in1 when(data_write1 = '1') else data_in2;
data_write<='1' when (data_write1 = '1') else data_write2;
end Behavioral;
| gpl-3.0 | 2d3897687d972f0b30beb8250dd37e84 | 0.630631 | 3.201923 | false | false | false | false |
makestuff/swled | templates/fx2min/vhdl/top_level.vhdl | 1 | 4,638 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2FifoSel_out : out std_logic; -- select FIFO: "0" for EP2OUT, "1" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
begin
-- CommFPGA module
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => open,
-- FX2LP interface
fx2FifoSel_out => fx2FifoSel_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => fx2Clk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
| gpl-3.0 | 41d62f18d8df563c1eff6dff79ff8ce8 | 0.590987 | 3.497738 | false | false | false | false |
siam28/neppielight | dvid_in/dvid_in.vhd | 2 | 12,134 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: dvi_in.vhd - Behavioral
--
-- Description: Design to capture raw DVI-D input
--
-- I've also got do do some work to automatically adjust the phase of the
-- bit clocks, at the moment it needs to be manually tuned to match your source
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity dvid_in is
Port ( -- DVI-D/HDMI signals
tmds_in_p : in STD_LOGIC_VECTOR(3 downto 0);
tmds_in_n : in STD_LOGIC_VECTOR(3 downto 0);
-- debug
leds : out std_logic_vector(7 downto 0) := (others => '0');
-- VGA signals
clk_pixel : out std_logic;
red_p : out std_logic_vector(7 downto 0) := (others => '0');
green_p : out std_logic_vector(7 downto 0) := (others => '0');
blue_p : out std_logic_vector(7 downto 0) := (others => '0');
hsync : out std_logic := '0';
vsync : out std_logic := '0';
blank : out std_logic := '0'
);
end dvid_in;
architecture Behavioral of dvid_in is
signal dvid_clk : std_logic;
signal dvid_clk_buffered : std_logic;
signal ioclock : std_logic;
signal serdes_strobe : std_logic;
signal clock_x1 : std_logic;
signal clock_x2 : std_logic;
signal clock_x10 : std_logic;
signal clock_x10_unbuffered : std_logic;
signal clock_x2_unbuffered : std_logic;
signal clock_x1_unbuffered : std_logic;
signal clk_feedback : std_logic;
signal pll_locked : std_logic;
signal sync_seen : std_logic;
signal c0_d : std_logic_vector(7 downto 0);
signal c0_c : std_logic_vector(1 downto 0);
signal c0_active : std_logic;
signal c1_d : std_logic_vector(7 downto 0);
signal c1_c : std_logic_vector(1 downto 0);
signal c1_active : std_logic;
signal c2_d : std_logic_vector(7 downto 0);
signal c2_c : std_logic_vector(1 downto 0);
signal c2_active : std_logic;
signal led_count : unsigned( 2 downto 0) := (others => '0');
signal framing : std_logic_vector(3 downto 0) := (others => '0');
signal since_sync : unsigned(14 downto 0) := (others => '0');
signal start_calibrate : std_logic;
signal reset_delay : std_logic;
signal cal_start_count : unsigned(7 downto 0) := (others => '0');
COMPONENT input_channel
GENERIC(
fixed_delay : in natural
);
PORT(
clk_fabric : IN std_logic;
clk_fabric_x2 : IN std_logic;
clk_input : IN std_logic;
strobe : IN std_logic;
tmds_p : in STD_LOGIC;
tmds_n : in STD_LOGIC;
invert : IN std_logic;
framing : IN std_logic_vector(3 downto 0);
data_out : OUT std_logic_vector(7 downto 0);
control : OUT std_logic_vector(1 downto 0);
active_data : OUT std_logic;
sync_seen : OUT std_logic;
adjust_delay : IN std_logic;
increase_delay : IN std_logic;
reset_delay : IN std_logic;
start_calibrate : IN std_logic;
calibrate_busy : OUT std_logic
);
END COMPONENT;
signal x : unsigned(12 downto 0) := (others => '0');
signal y : unsigned(12 downto 0) := (others => '0');
begin
----------------------------------
-- Output the decoded VGA signals
----------------------------------
clk_pixel <= clock_x1;
blue_p <= c0_d;
green_p <= c1_d;
red_p <= c2_d;
hsync <= c0_c(0); --c2
vsync <= c0_c(1); --c2
blank <= not c2_active;
----------------------------------
-- Debug
----------------------------------
leds <= c2_c & (not c2_c) & framing;
------------------------------------------
-- Receive the differential clock
------------------------------------------
clk_diff_input : IBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "TMDS_33")
port map (
O => dvid_clk,
I => tmds_in_p(3),
IB => tmds_in_n(3)
);
------------------------------------------
-- Buffer it before the PLL
------------------------------------------
BUFG_clk : BUFG port map ( I => dvid_clk, O => dvid_clk_buffered);
------------------------------------------
-- Generate the bit clocks for the serdes
--
-- Adjust the phase in a 10:2:1 ratio (e.g. 50:10:5)
------------------------------------------
PLL_BASE_inst : PLL_BASE
generic map (
CLKFBOUT_MULT => 10,
-- Almost works with Western Digital Live @ 720p/60 -Noise on blue channel.
--CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 200.0, -- Output 10x original frequency
--CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 40.0, -- Output 2x original frequency
--CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 20.0, -- Output 1x original frequency
-- Works with Western Digital Live @ 640x480/60Hz
CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
CLK_FEEDBACK => "CLKFBOUT", -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
CLKIN_PERIOD => 10.0, -- IMPORTANT! Approx 77 MHz
DIVCLK_DIVIDE => 1 -- Division value for all output clocks (1-52)
)
port map (
CLKFBOUT => clk_feedback,
CLKOUT0 => clock_x10_unbuffered,
CLKOUT1 => clock_x2_unbuffered,
CLKOUT2 => clock_x1_unbuffered,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pll_locked,
CLKFBIN => clk_feedback,
CLKIN => dvid_clk_buffered,
RST => '0' -- 1-bit input: Reset input
);
BUFG_pclockx2 : BUFG port map ( I => clock_x2_unbuffered, O => clock_x2);
BUFG_pclock : BUFG port map ( I => clock_x1_unbuffered, O => clock_x1);
BUFG_pclockx10 : BUFG port map ( I => clock_x10_unbuffered, O => clock_x10 );
------------------------------------------------
-- Buffer the clocks ready to go the serialisers
------------------------------------------------
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8) !!!! IMPORTANT TO CHANGE THIS AS NEEDED !!!!
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- should be true
)
port map (
IOCLK => ioclock, -- Clock used to receive bits
LOCK => open,
SERDESSTROBE => serdes_strobe, -- Clock use to load data into SERDES
GCLK => clock_x2, -- Global clock use as a reference for serdes_strobe
LOCKED => pll_locked, -- When the upstream PLL is locked
PLLIN => clock_x10_unbuffered -- Clock to use for bit capture - this must be unbuffered
);
----------------------------------------
-- c0 channel input - Carries the RED channel
----------------------------------------
input_channel_c0: input_channel GENERIC MAP(
fixed_delay => 30
) PORT MAP(
clk_fabric => clock_x1,
clk_fabric_x2 => clock_x2,
clk_input => ioclock,
strobe => serdes_strobe,
tmds_p => tmds_in_p(0),
tmds_n => tmds_in_n(0),
invert => '0',
framing => framing,
data_out => c0_d,
control => c0_c,
active_data => c0_active,
sync_seen => open,
adjust_delay => '0',
increase_delay => '0',
reset_delay => reset_delay,
start_calibrate => start_calibrate,
calibrate_busy => open
);
----------------------------------------
-- c1 channel input - Carries the BLUE channel
----------------------------------------
input_channel_c1: input_channel GENERIC MAP(
fixed_delay => 40
) PORT MAP(
clk_fabric => clock_x1,
clk_fabric_x2 => clock_x2,
clk_input => ioclock,
strobe => serdes_strobe,
tmds_p => tmds_in_p(1),
tmds_n => tmds_in_n(1),
invert => '0',
framing => framing,
data_out => c1_d,
control => c1_c,
active_data => c1_active,
sync_seen => open,
adjust_delay => '0',
increase_delay => '0',
reset_delay => reset_delay,
start_calibrate => start_calibrate,
calibrate_busy => open
);
----------------------------------------
-- c2 channel input - Carries the GREEN channel and syncs
----------------------------------------
input_channel_c2: input_channel GENERIC MAP(
fixed_delay => 30
) PORT MAP(
clk_fabric => clock_x1,
clk_fabric_x2 => clock_x2,
clk_input => ioclock,
strobe => serdes_strobe,
tmds_p => tmds_in_p(2),
tmds_n => tmds_in_n(2),
invert => '0',
framing => framing,
data_out => c2_d,
control => c2_c,
active_data => c2_active,
sync_seen => sync_seen,
adjust_delay => '0',
increase_delay => '0',
reset_delay => reset_delay,
start_calibrate => start_calibrate,
calibrate_busy => open
);
calibrate_process: process (clock_x2)
begin
if rising_edge(clock_x2) then
if cal_start_count = "10000000" then
start_calibrate <= '0';
else
start_calibrate <= '0';
end if;
if cal_start_count = "11111100" then
reset_delay <= '0';
else
reset_delay <= '0';
end if;
if cal_start_count /= "11111111" then
cal_start_count <= cal_start_count + 1;
end if;
end if;
end process;
process(clock_x1)
begin
if rising_edge(clock_x1) then
-- Work out what we need to do to frame the TMDS data correctly
if sync_seen = '1' then
------------------------------------------------------------
-- We've just seen a sync codeword, so restart the counter
-- This means that we are in sync
------------------------------------------------------------
since_sync <= (others => '0');
elsif since_sync = "111111111111111" then
------------------------------------------------------------
-- We haven't seen a sync in 16383 pixel cycles, so it can't
-- be in sync. By incrementing 'framing' we bitslip one bit.
--
-- The 16k number is special, as they two sync codewords
-- being looked for will not be seen during the VSYNC period
-- (assuming that you are looking in the channel that
-- includes the encoded HSYNC/VSYNC signals
------------------------------------------------------------
if framing = "1001" then
framing <= (others =>'0');
else
framing <= std_logic_vector(unsigned(framing) + 1);
end if;
since_sync <= since_sync + 1;
else
------------------------------------------------------------
-- Keep counting and hoping for a sync codeword
------------------------------------------------------------
since_sync <= since_sync + 1;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | 64c4f589bf427af0257e4f0b821f63d8 | 0.47165 | 4.050067 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/leading_zeros_dir/leading_zeros.vhd | 1 | 891 | -- author: Antonio Gutierrez
-- date: 08/10/13
-- description: design tha t counts the number of leading zeros
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity leading_zeros is
--generic declarations
port (
data: in std_logic_vector(7 downto 0);
zeros: out integer range 0 to 8);
end entity leading_zeros;
--------------------------------------
architecture circuit of leading_zeros is
--signals and declarations
begin
proc: process (data)
variable count: integer range 0 to 8;
begin
count := 0;
loop1: for i in data'range loop
case data(i) is
when '0' => count := count + 1;
when others => exit;
end case;
end loop loop1;
zeros <= count;
end process proc;
end architecture circuit;
| gpl-3.0 | 08e8d355d37a8931a1617b18607829f8 | 0.536476 | 4.569231 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_11_dir/exercise6_11.vhd | 1 | 3,949 | --!
--! @file: exercise6_11.vhd
--! @brief: Frequency Meter with SSDs
--! @author: Antonio Gutierrez
--! @date: 2013-10-28
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity frequency_meter is
generic (fclk: positive := 50_000_000;
clk_divider: positive := 50_000);
port (
input: in std_logic; -- signal to measure
clk: in std_logic; -- clk
ssd1: out std_logic_vector(6 downto 0);
ssd2: out std_logic_vector(6 downto 0);
ssd3: out std_logic_vector(6 downto 0));
end entity frequency_meter;
--------------------------------------
architecture circuit of frequency_meter is
signal one_sec: std_logic;
signal output1: integer range 0 to 10;
signal output2: integer range 0 to 10;
signal output3: integer range 0 to 10;
begin
-- create one second window
proc: process (clk)
variable one_sec: integer range 0 to fclk+1 := 0;
begin
if (clk'event and clk = '1') then
count := count + 1;
if (count = fclk + 1) then
count := 0;
one_sec <= '1';
else
one_sec <= '0';
end if;
end if;
end process proc;
-- count number of input pulses in that time window
proc1: process (input, one_sec)
variable count1: integer range 0 to 10;
variable count2: integer range 0 to 10;
variable count3: integer range 0 to 10;
variable count4: integer range 0 to 10;
variable count5: integer range 0 to 10;
begin
if (one_sec = '1') then
count1 := 0;
count2 := 0;
count3 := 0;
count4 := 0;
count5 := 0;
elsif (input'event and input = '1') then
count1 := count1 + 1;
if (count1 = 10) then
count1 := 0;
count2 := count2 + 1;
if (count2 = 10) then
count2 := 0;
count3 := count3 + 1;
if (count3 = 10) then
count3 := 0;
count4 := count4 + 1;
if (count4 = 10) then
count4 := 0;
count5 := count5 + 1;
end if;
end if;
end if;
end if;
end if;
-- store outputs to SSD
if (one_sec'event and one_sec = '1') then
output1 <= count5;
output2 <= count4;
output3 <= count3;
end if;
end process proc1;
-- SSD circuits
with output1 select
ssd1 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
with output2 select
ssd2 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
with output3 select
ssd3 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
end architecture circuit;
--------------------------------------
| gpl-3.0 | e8c50ee6de345430c9d1d40a2b49a6cf | 0.438339 | 4.417226 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_spi/src/vvc_methods_pkg.vhd | 1 | 65,299 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.spi_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SPI VVC
--===============================================================================================
constant C_VVC_NAME : string := "SPI_VVC";
signal SPI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is SPI_VVCT;
alias t_bfm_config is t_spi_bfm_config;
constant C_SPI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_spi_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_SPI_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_SPI_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_SPI_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
tx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
rx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
tx_data => (others => (others => '0')),
rx_data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_spi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_SPI_VVC_CONFIG_DEFAULT);
shared variable shared_spi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_spi_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
-- Single-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
-- Single-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Single-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Multi-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
-- Single-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := RELEASE_LINE_BETWEEN_WORDS;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE_ONLY);
shared_vvc_cmd.num_words := num_words;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp'length;
variable v_num_words : natural := 1;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp(0)'length;
variable v_num_words : natural := data_exp'length;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY);
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
-- Single-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE_ONLY);
shared_vvc_cmd.num_words := num_words;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Single-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp'length;
variable v_num_words : natural := 1;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize to t_slv_array
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY);
--shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- Multi-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp(0)'length;
variable v_num_words : natural := data_exp'length;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
begin
-- normalize
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY);
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
end package body vvc_methods_pkg;
| mit | 29b1e3db86f13f06a6eebc473a1b580b | 0.533929 | 4.175929 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_SEQUE_1.vhd | 1 | 9,992 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_A is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_A is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(2 downto 0);
signal gated_clock : std_logic;
signal nIdle : std_logic;
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_1 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
process(clk)
variable gated : std_logic;
begin
if clk'event and clk = '1' then
gated := '0';
--IF ( (inp.dInstr(31 downto 30) & inp.dInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
--gated := '1';
--END IF;
IF ( (inp.aInstr(31 downto 30) & inp.aInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
gated := '1';
END IF;
IF ( (inp.eInstr(31 downto 30) & inp.eInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXECUTION PIPELINE STAGE";
gated := '1';
END IF;
--IF ( (inp.mInstr(31 downto 30) & inp.mInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE MEMORY PIPELINE STAGE";
-- gated := '1';
--END IF;
--IF ( (inp.xInstr(31 downto 30) & inp.xInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXCEPTION PIPELINE STAGE";
--gated := '1';
--END IF;
-- synthesis translate_off
IF ( (nIdle = '0') AND (gated = '1') ) THEN
--printmsg( "(PGDC) ENABLING THE PGDC CLOCK GENERATION" );
ELSIF( (nIdle = '1') AND (gated = '0') ) THEN
--printmsg( "(PGDC) DISABLING THE PGDC CLOCK GENERATION" );
END IF;
-- synthesis translate_on
nIdle <= gated;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
gated_clock <= clk AND nIdle;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.op1, inp.op2)
--begin
--At <= inp.op1(31 downto 0);
--Bt <= inp.op2(31 downto 0);
--if( nIdle = '1' )then
-- REPORT "(PGDC) (At, Bt) MEMORISATION PROCESS";
-- if ( (At(30) /= '-') AND (At(30) /= 'X') AND (At(30) /= 'U')) then
-- printmsg("(PGDC) =====> (At) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
-- end if;
-- if ( (Bt(30) /= '-') AND (Bt(30) /= 'X') AND (Bt(30) /= 'U')) then
-- printmsg("(PGDC) =====>(Bt) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
-- end if;
-- --printmsg("(PGDC) (At, Bt) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & " & " & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.start)
--begin
-- if (inp.start = '1') then
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME UP";
-- else
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME DOWN";
-- end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- DESCRIPTION ORIGINALE QUI FONCTIONNE TRES TRES BIEN
-- reg : process(clk)
-- variable vready, vnready : std_logic;
-- begin
-- vready := '0';
-- vnready := '0';
-- if clk'event and clk = '1' then
-- if (rst = '0') then
-- state <= "000";
-- elsif (inp.flush = '1') then
-- state <= "000";
-- elsif (holdn = '0') then
-- state <= state;
-- else
-- case state is
--ON ATTEND LA COMMANDE DE START
-- when "000" =>
-- if (inp.start = '1') then
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "001";
-- else
-- state <= "000";
-- A <= A;
-- B <= B;
-- end if;
--ON COMMENCE LE CALCUL
-- when "001" =>
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "011";
--ON COMMENCE LE CALCUL
-- when "010" =>
-- if( SIGNED(A) > SIGNED(B) ) then
-- A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
-- else
-- B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
-- end if;
-- state <= "011";
--ON TEST LES DONNEES (FIN D'ITERATION)
-- when "011" =>
-- if(SIGNED(A) = SIGNED(B)) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
-- A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
-- state <= "100";
-- vnready := '1';
-- else
-- state <= "010";
-- end if;
-- when "100" =>
--ON INDIQUE QUE LE RESULTAT EST PRET
-- vready := '1';
--ON RETOURNE DANS L'ETAT INTIAL
-- state <= "000";
-- when others =>
-- state <= "000";
-- end case;
-- outp.ready <= vready;
-- outp.nready <= vnready;
-- end if; -- if reset
-- end if; -- if clock
-- end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
reg : process(clk)
variable vready, vnready : std_logic;
begin
vready := '0';
vnready := '0';
if (rst = '0') then
state <= "000";
outp.ready <= vready;
outp.nready <= vnready;
else
if clk'event and clk = '1' then
elsif (inp.flush = '1') then
state <= "000";
elsif (holdn = '0') then
state <= state;
else
case state is
-- ON ATTEND LA COMMANDE DE START
when "000" =>
if (inp.start = '1') then
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "001";
--printmsg("(PGDC) THE START SIGNAL IS UP");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
else
state <= "000";
A <= A;
B <= B;
end if;
-- ON COMMENCE LE CALCUL
when "001" =>
--printmsg("(PGDC) INPUT DATA READING");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "011";
-- ON COMMENCE LE CALCUL
when "010" =>
if( SIGNED(A) > SIGNED(B) ) then
A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
else
B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
end if;
state <= "011";
-- ON TEST LES DONNEES (FIN D'ITERATION)
when "011" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "100";
vnready := '1';
elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
state <= "100";
vnready := '1';
elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
state <= "100";
vnready := '1';
else
state <= "010";
end if;
when "100" =>
--printmsg("(PGDC) ===> COMPUTATION IS NOW FINISHED (" & to_int_str(A,6) & ")");
-- ON INDIQUE QUE LE RESULTAT EST PRET
vready := '1';
-- ON RETOURNE DANS L'ETAT INTIAL
state <= "000";
when others =>
state <= "000";
end case;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
-------------------------------------------------------------------------
outp.result <= A;
outp.icc <= "0000";
end;
| gpl-3.0 | 37205dd97859968e213048e1ce04cbc8 | 0.442054 | 3.311899 | false | false | false | false |
8l/soc | backends/small1/hw/soc/logipi/3rdparty/SDRAM_Controller.vhd | 2 | 24,876 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 14:09:12 09/15/2013
-- Module Name: SDRAM_Controller - Behavioral
-- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
-- or Micron 48LC4M16A2-7E @ 100MHz
-- Revision:
-- Revision 0.1 - Initial version
-- Revision 0.2 - Removed second clock signal that isn't needed.
-- Revision 0.3 - Added back-to-back reads and writes.
-- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
-- Unless they get really, really delayed. If a delay occurs multiple
-- refreshes might get pushed out, but it will have avioded about
-- 50% of the refresh overhead
-- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
-- Papilio Pro and Logi-Pi
--
-- Worst case performance (single accesses to different rows or banks) is:
-- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
-- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
--
-- For 1:1 mixed reads and writes into the same row it is around 88MB/s
-- For reads or wries to the same it is can be as high as 184MB/s
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.NUMERIC_STD.ALL;
entity SDRAM_Controller is
generic (
sdram_address_width : natural;
sdram_column_bits : natural;
sdram_startup_cycles: natural;
cycles_per_refresh : natural ;
very_low_speed : natural := 0
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Interface to issue reads or write data
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC; -- is new data ready?
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
end SDRAM_Controller;
architecture Behavioral of SDRAM_Controller is
-- From page 37 of MT48LC16M16A2 datasheet
-- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
-- COMMAND INHIBIT (NOP) H X X X X X X
-- NO OPERATION (NOP) L H H H X X X
-- ACTIVE L L H H X Bank/row X
-- READ L H L H L/H Bank/col X
-- WRITE L H L L L/H Bank/col Valid
-- BURST TERMINATE L H H L X X Active
-- PRECHARGE L L H L X Code X
-- AUTO REFRESH L L L H X X X
-- LOAD MODE REGISTER L L L L X Op-code X
-- Write enable X X X X L X Active
-- Write inhibit X X X X H X High-Z
-- Here are the commands mapped to constants
constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
constant MODE_REG : std_logic_vector(12 downto 0) :=
-- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
"000" & "0" & "00" & "010" & "0" & "001";
signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
signal iob_cke : std_logic := '0';
signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
attribute IOB: string;
attribute IOB of iob_command: signal is "true";
attribute IOB of iob_address: signal is "true";
attribute IOB of iob_dqm : signal is "true";
attribute IOB of iob_cke : signal is "true";
attribute IOB of iob_bank : signal is "true";
attribute IOB of iob_data : signal is "true";
signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
signal sdram_din : std_logic_vector(15 downto 0);
attribute IOB of captured_data : signal is "true";
type fsm_state is (s_startup,
s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
s_idle,
s_open_in_2, s_open_in_1,
s_write_1, s_write_2, s_write_3,
s_read_1, s_read_2, s_read_3, s_read_4,
s_precharge
);
signal state : fsm_state := s_startup;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE-HOT";
-- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
-- logic to decide when to refresh
signal pending_refresh : std_logic := '0';
signal forcing_refresh : std_logic := '0';
-- The incoming address is split into these three values
signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
-- signals to hold the requested transaction before it is completed
signal save_wr : std_logic := '0';
signal save_row : std_logic_vector(12 downto 0);
signal save_bank : std_logic_vector( 1 downto 0);
signal save_col : std_logic_vector(12 downto 0);
signal save_data_in : std_logic_vector(31 downto 0);
signal save_byte_enable : std_logic_vector( 3 downto 0);
-- control when new transactions are accepted
signal ready_for_new : std_logic := '0';
signal got_transaction : std_logic := '0';
signal can_back_to_back : std_logic := '0';
-- signal to control the Hi-Z state of the DQ bus
signal iob_dq_hiz : std_logic := '1';
-- signals for when to read the data off of the bus
signal data_ready_delay : std_logic_vector( 4 - (very_low_speed) downto 0);
-- bit indexes used when splitting the address into row/colum/bank.
constant start_of_col : natural := 0;
constant end_of_col : natural := sdram_column_bits-2;
constant start_of_bank : natural := sdram_column_bits-1;
constant end_of_bank : natural := sdram_column_bits;
constant start_of_row : natural := sdram_column_bits+1;
constant end_of_row : natural := sdram_address_width-2;
constant prefresh_cmd : natural := 10;
begin
-- Indicate the need to refresh when the counter is 2048,
-- Force a refresh when the counter is 4096 - (if a refresh is forced,
-- multiple refresshes will be forced until the counter is below 2048
pending_refresh <= startup_refresh_count(11);
forcing_refresh <= startup_refresh_count(12);
-- tell the outside world when we can accept a new transaction;
cmd_ready <= ready_for_new;
----------------------------------------------------------------------------
-- Seperate the address into row / bank / address
----------------------------------------------------------------------------
addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 22:10
addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 9:8
addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 8:0 <= 7:0 & '0'
-----------------------------------------------------------
-- Forward the SDRAM clock to the SDRAM chip - 180 degress
-- out of phase with the control signals (ensuring setup and holdup
-----------------------------------------------------------
sdram_clk_forward : ODDR2
generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")
port map (Q => sdram_clk, C0 => clk, C1 => not clk, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');
-----------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--!! Ensure that all outputs are registered. !!
--!! Check the pinout report to be sure !!
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-----------------------------------------------
sdram_cke <= iob_cke;
sdram_CS <= iob_command(3);
sdram_RAS <= iob_command(2);
sdram_CAS <= iob_command(1);
sdram_WE <= iob_command(0);
sdram_dqm <= iob_dqm;
sdram_ba <= iob_bank;
sdram_addr <= iob_address;
---------------------------------------------------------------
-- Explicitly set up the tristate I/O buffers on the DQ signals
---------------------------------------------------------------
iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map ( O => sdram_din(i), IO => sdram_data(i), I => iob_data(i), T => iob_dq_hiz);
end generate;
capture_proc: process(clk)
begin
if rising_edge(clk) then
captured_data <= sdram_din;
end if;
end process;
main_proc: process(clk)
begin
if rising_edge(clk) then
captured_data_last <= captured_data;
------------------------------------------------
-- Default state is to do nothing
------------------------------------------------
iob_command <= CMD_NOP;
iob_address <= (others => '0');
iob_bank <= (others => '0');
------------------------------------------------
-- countdown for initialisation & refresh
------------------------------------------------
startup_refresh_count <= startup_refresh_count+1;
-------------------------------------------------------------------
-- It we are ready for a new tranasction and one is being presented
-- then accept it. Also remember what we are reading or writing,
-- and if it can be back-to-backed with the last transaction
-------------------------------------------------------------------
if ready_for_new = '1' and cmd_enable = '1' then
if save_bank = addr_bank and save_row = addr_row then
can_back_to_back <= '1';
else
can_back_to_back <= '0';
end if;
save_row <= addr_row;
save_bank <= addr_bank;
save_col <= addr_col;
save_wr <= cmd_wr;
save_data_in <= cmd_data_in;
save_byte_enable <= cmd_byte_enable;
got_transaction <= '1';
ready_for_new <= '0';
end if;
------------------------------------------------
-- Handle the data coming back from the
-- SDRAM for the Read transaction
------------------------------------------------
data_out_ready <= '0';
if data_ready_delay(0) = '1' then
data_out <= captured_data & captured_data_last;
data_out_ready <= '1';
end if;
----------------------------------------------------------------------------
-- update shift registers used to choose when to present data to/from memory
----------------------------------------------------------------------------
data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
iob_dqm <= dqm_sr(1 downto 0);
dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
case state is
when s_startup =>
------------------------------------------------------------------------
-- This is the initial startup state, where we wait for at least 100us
-- before starting the start sequence
--
-- The initialisation is sequence is
-- * de-assert SDRAM_CKE
-- * 100us wait,
-- * assert SDRAM_CKE
-- * wait at least one cycle,
-- * PRECHARGE
-- * wait 2 cycles
-- * REFRESH,
-- * tREF wait
-- * REFRESH,
-- * tREF wait
-- * LOAD_MODE_REG
-- * 2 cycles wait
------------------------------------------------------------------------
iob_CKE <= '1';
-- All the commands during the startup are NOPS, except these
if startup_refresh_count = startup_refresh_max-31 then
-- ensure all rows are closed
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- all banks
iob_bank <= (others => '0');
elsif startup_refresh_count = startup_refresh_max-23 then
-- these refreshes need to be at least tREF (66ns) apart
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-15 then
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-7 then
-- Now load the mode register
iob_command <= CMD_LOAD_MODE_REG;
iob_address <= MODE_REG;
end if;
------------------------------------------------------
-- if startup is coomplete then go into idle mode,
-- get prepared to accept a new command, and schedule
-- the first refresh cycle
------------------------------------------------------
if startup_refresh_count = 0 then
state <= s_idle;
ready_for_new <= '1';
got_transaction <= '0';
startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
end if;
when s_idle_in_6 => state <= s_idle_in_5;
when s_idle_in_5 => state <= s_idle_in_4;
when s_idle_in_4 => state <= s_idle_in_3;
when s_idle_in_3 => state <= s_idle_in_2;
when s_idle_in_2 => state <= s_idle_in_1;
when s_idle_in_1 => state <= s_idle;
when s_idle =>
-- Priority is to issue a refresh if one is outstanding
if pending_refresh = '1' or forcing_refresh = '1' then
------------------------------------------------------------------------
-- Start the refresh cycle.
-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
------------------------------------------------------------------------
state <= s_idle_in_6;
iob_command <= CMD_REFRESH;
startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
elsif got_transaction = '1' then
--------------------------------
-- Start the read or write cycle.
-- First task is to open the row
--------------------------------
state <= s_open_in_2;
iob_command <= CMD_ACTIVE;
iob_address <= save_row;
iob_bank <= save_bank;
end if;
--------------------------------------------
-- Opening the row ready for reads or writes
--------------------------------------------
when s_open_in_2 => state <= s_open_in_1;
when s_open_in_1 =>
-- still waiting for row to open
if save_wr = '1' then
state <= s_write_1;
iob_dq_hiz <= '0';
iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
else
iob_dq_hiz <= '1';
state <= s_read_1;
end if;
-- we will be ready for a new transaction next cycle!
ready_for_new <= '1';
got_transaction <= '0';
----------------------------------
-- Processing the read transaction
----------------------------------
when s_read_1 =>
state <= s_read_2;
iob_command <= CMD_READ;
iob_address <= save_col;
iob_bank <= save_bank;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
-- Schedule reading the data values off the bus
data_ready_delay(data_ready_delay'high) <= '1';
-- Set the data masks to read all bytes
iob_dqm <= (others => '0');
dqm_sr(1 downto 0) <= (others => '0');
when s_read_2 =>
state <= s_read_3;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_3 =>
state <= s_read_4;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_4 =>
state <= s_precharge;
-- can we do back-to-back read?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
else
state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
end if;
end if;
------------------------------------------------------------------
-- Processing the write transaction
-------------------------------------------------------------------
when s_write_1 =>
state <= s_write_2;
iob_command <= CMD_WRITE;
iob_address <= save_col;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
iob_bank <= save_bank;
iob_dqm <= NOT save_byte_enable(1 downto 0);
dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
iob_data <= save_data_in(15 downto 0);
iob_data_next <= save_data_in(31 downto 16);
when s_write_2 =>
state <= s_write_3;
iob_data <= iob_data_next;
-- can we do a back-to-back write?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
end if;
-- Although it looks right in simulation you can't go write-to-read
-- here due to bus contention, as iob_dq_hiz takes a few ns.
end if;
when s_write_3 => -- must wait tRDL, hence the extra idle state
-- back to back transaction?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
else
-- write-to-read switch?
state <= s_read_1;
iob_dq_hiz <= '1';
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
else
iob_dq_hiz <= '1';
state <= s_precharge;
end if;
-------------------------------------------------------------------
-- Closing the row off (this closes all banks)
-------------------------------------------------------------------
when s_precharge =>
state <= s_idle_in_3;
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
-------------------------------------------------------------------
-- We should never get here, but if we do then reset the memory
-------------------------------------------------------------------
when others =>
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end case;
if reset = '1' then -- Sync reset
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end if;
end if;
end process;
end Behavioral;
| mit | dee25a972577ceb5eae9019d851226e4 | 0.449148 | 4.35428 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/INTERFACE_COMB_1.vhd | 1 | 4,194 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
ENTITY INTERFACE_COMB_1 IS
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_1 IS
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
COMPONENT Q16_8_DECISION
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_FullXorMin
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT START_32b
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT STOP_32b
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
SIGNAL sINPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sINPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) INTERFACE_COMB_1 : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
sINPUT_1 <= inp.op1(31 downto 0);
sINPUT_2 <= inp.op2(31 downto 0);
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- synthesis translate_off
-- PROCESS(inp.instr, inp.op1(31 downto 0), sINPUT_2, RESULT_7)
-- variable op : std_logic_vector(1 downto 0);
-- variable op2 : std_logic_vector(2 downto 0);
-- variable op3 : std_logic_vector(5 downto 0);
-- BEGIN
-- op := inp.instr(31 downto 30);
-- op2 := inp.instr(24 downto 22);
-- op3 := inp.instr(24 downto 19);
-- if( op = "10" ) THEN
-- if( op3 = "001001" ) THEN
-- if( inp.instr(13 downto 5) = "001000000" ) THEN
-- printmsg("(PGDC) ===> FIXED POINT SUB A : (" & to_int_str(inp.op1 (15 downto 0),6) & ")...");
-- printmsg("(PGDC) ===> FIXED POINT SUB B : (" & to_int_str(RESULT_7(15 downto 0),6) & ")...");
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
RESOURCE_1 : Q16_8_DECISION PORT MAP (inp.op1(31 downto 0), RESULT_1);
RESOURCE_2 : Q16_8_FullXorMin PORT MAP (inp.op1(31 downto 0), inp.op2(31 downto 0), RESULT_2);
RESOURCE_3 : START_32b PORT MAP (inp.op1(31 downto 0), RESULT_3);
RESOURCE_4 : STOP_32b PORT MAP (inp.op1(31 downto 0), RESULT_4);
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
WITH inp.instr(13 downto 5) SELECT
outp.result <=
RESULT_1 WHEN "000000001",
RESULT_2 WHEN "000000010",
RESULT_3 WHEN "000000100",
RESULT_4 WHEN OTHERS;
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
end;
| gpl-3.0 | b0ca70cfd264ec1b63eb149c056ca7ea | 0.462566 | 3.886932 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_2_dir/exercise6_2.vhd | 1 | 1,443 | -- author: Antonio Gutierrez
-- date: 09/10/13
-- description: gray counter
--------------------------------------
entity gray_counter is
generic (maxnumbits: integer := 4;);
port (
clk: in std_logic;
count: out std_logic_vector(maxnumbits-1 downto 0);
end entity gray_counter;
--------------------------------------
architecture circuit of gray_counter is
begin
proc: process (clk)
variable binary: std_logic_vector(maxnumbits-1 downto 0) := (others => '0');
variable temp: std_logic_vector(maxnumbits-1 downto 0) := (others => '0');
begin
if (clk'event and clk = '1') then
if (binary = (others => '0')) then ---- if count starts then don't increment so as to have first elelemnt in count all zeros
binary := binary;
elsif (binary = 2**(maxnumofbits-1) - 1) then ---- if max reached then reset count to zero
binary := (others => '0');
else ---- if not 0 and not max then increment count
binary := binary + 1;
end if;
end if;
if (binary = '0') then
count <= (others => '0');
else
count <= (binary srl 1) xor binary; ---- according to wikipedia (converting binary to gray code)
end if;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | bed82d06065cc0d0e57b4d98e7934188 | 0.507277 | 4.509375 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/uart.vhd | 1 | 7,912 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(10 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(10 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(6 downto 0);
signal uart_read2 : std_logic;
signal reg_debug : std_logic_vector(7 downto 0);
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(10 downto 0) :=
-- "01010110110"; -- 80MHz / 11520Hz
-- "01010001011"; -- 75MHz / 11520Hz
-- "01001011111"; -- 70MHz / 11520Hz
-- "01000111100"; -- 66MHz / 11520Hz
-- "01000110100"; -- 65MHz / 11520Hz
-- "01000010010"; -- 60MHz / 11520Hz
-- "00111101110"; -- 57MHz / 11520Hz
-- "00111011101"; -- 55MHz / 11520Hz
"00110110010"; -- 50MHz / 11520Hz
-- "0100011110"; -- 33MHz / 2/57600Hz = 0x11e
-- "10101101101"; -- 80MHz / 57600Hz = 0x56D
-- "1101100100"; -- 50MHz / 57600Hz = 0x364
-- "00110110010"; -- 25MHz / 57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; -- 12.5MHz /57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(10 downto 0);
read_value_reg <= ONES(read_value_reg'length-1 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(10 downto 0);
data_save_reg <= ZERO(17 downto 0);
reg_debug <= ZERO(7 downto 0); -- FOR DEBUGGING PURPOSE ONLY
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(10 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
reg_debug <= data_in; -- FOR DEBUGGING PURPOSE ONLY
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(10 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(10 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(10 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or (enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synopsys synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable hex_output_line : line; -- BLG
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
write(hex_output_line, c); -- BLG
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(output, hex_output_line); -- BLG
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; -- uart_sel
end if; -- rising_edge(clk)
end process; -- uart_proc
end generate; -- uart_logger
-- synopsys synthesis_on
end; --architecture logic
| gpl-3.0 | 88fc6ccc0162c5c7bd087d9448978252 | 0.546385 | 3.507092 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example1_dir/vending_machine_tb.vhd | 1 | 1,365 | --------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine_tb is
end entity vending_machine_tb;
--------------------------------------
architecture circuit of vending_machine_tb is
-- dut declaration
component vending_machine is
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;
candy_out, nickel_out, dime_out: out std_logic);
end component vending_machine;
-- signal declaration
signal clk_tb: std_logic := '0';
signal rst_tb: std_logic := '1';
signal nickel_in_tb, dime_in_tb, quarter_in_tb: boolean;
signal candy_out_tb, nickel_out_tb, dime_out_tb: std_logic;
begin
-- dut instantiation
dut: vending_machine port map (
clk_tb, rst_tb, nickel_in_tb, dime_in_tb, quarter_in_tb, candy_out_tb, nickel_out_tb, dime_out_tb
);
-- stimuli generation
-- clock
clk_tb <= not clk_tb after 20 ns;
-- rst
rst_tb <= '0' after 40 ns;
-- nickel_in
nickel_in_tb <= false, true after 120 ns, false after 160 ns;
-- dime_in
dime_in_tb <= false, true after 200 ns, false after 240 ns;
-- quarter_in
quarter_in_tb <= false, true after 280 ns, false after 320 ns;
end architecture circuit;
| gpl-3.0 | 38f59fcafad9d3a0b526bbda87d40026 | 0.577289 | 3.649733 | false | false | false | false |
siam28/neppielight | dvid_out/dvid_out.vhd | 2 | 6,152 | --------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Description: Converts VGA signals into DVID bitstreams.
--
-- 'blank' must be asserted during the non-display
-- portions of the frame
--
-- NOTE due to the PLL frequency limits, changes are needed in dvid_out_clocking
-- to select pixel rates between 40 and 100 Mhz pixel clocks, or between 20 and
-- 50 MHz.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dvid_out is
Port ( -- Clocking
clk_pixel : IN std_logic;
-- Pixel data
red_p : in STD_LOGIC_VECTOR (7 downto 0);
green_p : in STD_LOGIC_VECTOR (7 downto 0);
blue_p : in STD_LOGIC_VECTOR (7 downto 0);
blank : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
-- TMDS outputs
tmds_out_p : out STD_LOGIC_VECTOR(3 downto 0);
tmds_out_n : out STD_LOGIC_VECTOR(3 downto 0));
end dvid_out;
architecture Behavioral of dvid_out is
COMPONENT dvid_out_clocking
PORT(
clk_pixel : IN std_logic;
clk_x1 : OUT std_logic;
clk_x2 : OUT std_logic;
clk_x10 : OUT std_logic;
serdes_strobe : OUT std_logic
);
END COMPONENT;
COMPONENT TMDS_encoder
PORT(
clk : IN std_logic;
data : IN std_logic_vector(7 downto 0);
c : IN std_logic_vector(1 downto 0);
blank : IN std_logic;
encoded : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
COMPONENT tmds_out_fifo
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(29 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT output_serialiser
PORT(
clk_load : IN std_logic;
clk_output : IN std_logic;
strobe : IN std_logic;
ser_data : IN std_logic_vector(4 downto 0);
ser_output : OUT std_logic
);
END COMPONENT;
signal clk_x1 : std_logic;
signal clk_x2 : std_logic;
signal clk_x10 : std_logic;
signal serdes_strobe : std_logic;
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal ser_in_red, ser_in_green, ser_in_blue, ser_in_clock : std_logic_vector(4 downto 0) := (others => '0');
signal rd_enable : std_logic := '0';
signal toggle : std_logic;
signal toggle_save : std_logic_vector(1 downto 0);
signal red_save, green_save, blue_save : std_logic_vector(9 downto 0) := (others => '0');
constant c_red : std_logic_vector(1 downto 0) := (others => '0');
constant c_green : std_logic_vector(1 downto 0) := (others => '0');
signal c_blue : std_logic_vector(1 downto 0) := (others => '0');
signal red_s : STD_LOGIC;
signal green_s : STD_LOGIC;
signal blue_s : STD_LOGIC;
signal clock_s : STD_LOGIC;
begin
-- Send the pixels to the encoder
c_blue <= vsync & hsync;
TMDS_encoder_red: TMDS_encoder PORT MAP(clk => clk_pixel, data => red_p, c => c_red, blank => blank, encoded => encoded_red);
TMDS_encoder_blue: TMDS_encoder PORT MAP(clk => clk_pixel, data => blue_p, c => c_blue, blank => blank, encoded => encoded_blue);
TMDS_encoder_green: TMDS_encoder PORT MAP(clk => clk_pixel, data => green_p, c => c_green, blank => blank, encoded => encoded_green);
-- Then to a small FIFO
-- fifo_in <= encoded_red & encoded_green & encoded_blue;
Inst_dvid_out_clocking: dvid_out_clocking PORT MAP(
clk_pixel => clk_pixel,
clk_x1 => clk_x1,
clk_x2 => clk_x2,
clk_x10 => clk_x10,
serdes_strobe => serdes_strobe
);
process(clk_pixel)
begin
if rising_edge(clk_pixel) then
toggle <= not toggle;
end if;
end process;
-- Now at a x2 clock, send the data from the fifo to the serialisers
process(clk_x2)
begin
if rising_edge(clk_x2) then
if toggle_save(1) = toggle_save(0) then
ser_in_red <= red_save(9 downto 5);
ser_in_green <= green_save(9 downto 5);
ser_in_blue <= blue_save(9 downto 5);
ser_in_clock <= "11111";
else
ser_in_red <= red_save(4 downto 0);
ser_in_green <= green_save(4 downto 0);
ser_in_blue <= blue_save(4 downto 0);
ser_in_clock <= "00000";
end if;
toggle_save <= toggle_save(0) & toggle;
red_save <= encoded_red;
green_save <= encoded_green;
blue_save <= encoded_blue;
end if;
end process;
-- The Seraialisers
output_serialiser_r: output_serialiser PORT MAP(clk_load => clk_x2, clk_output => clk_x10, strobe => serdes_strobe, ser_data => ser_in_red, ser_output => red_s);
output_serialiser_b: output_serialiser PORT MAP(clk_load => clk_x2, clk_output => clk_x10, strobe => serdes_strobe, ser_data => ser_in_blue, ser_output => blue_s);
output_serialiser_g: output_serialiser PORT MAP(clk_load => clk_x2, clk_output => clk_x10, strobe => serdes_strobe, ser_data => ser_in_green, ser_output => green_s);
output_serialiser_c: output_serialiser PORT MAP(clk_load => clk_x2, clk_output => clk_x10, strobe => serdes_strobe, ser_data => ser_in_clock, ser_output => clock_s);
-- The output buffers/drivers
OBUFDS_blue : OBUFDS port map ( O => tmds_out_p(0), OB => tmds_out_n(0), I => blue_s);
OBUFDS_green : OBUFDS port map ( O => tmds_out_p(1), OB => tmds_out_n(1), I => green_s);
OBUFDS_red : OBUFDS port map ( O => tmds_out_p(2), OB => tmds_out_n(2), I => red_s);
OBUFDS_clock : OBUFDS port map ( O => tmds_out_p(3), OB => tmds_out_n(3), I => clock_s);
end Behavioral; | gpl-2.0 | 8adb1b8a1bffe54cb9083d2e4aec9413 | 0.56762 | 3.281067 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/example8_5_dir/example8_5.vhd | 1 | 1,314 | --!
--! @file: example8_5.vhd
--! @brief: adder with compoenet and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.pkg_adder.all;
--------------------------------------
entity adder is
generic (N: integer := 8);
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(N-1 downto 0);
cout: out std_logic);
end entity adder;
--------------------------------------
architecture circuit of adder is
signal cin_cout: std_logic_vector(N-1 downto 0);
begin
-- first adder has cin as cin of entity
add0: full_adder port map (
a => a(0),
b => b(0),
cin => cin,
s => s(0)
cout => cin_cout(0)
);
-- middle adder have cin as cout of previous and cout as next cin
gen1: for i in 1 to N-1 generate
add1: full_adder port map (
a => a(i),
b => b(i),
cin => cin_cout(i-1),
s => s(i)
cout => cout_cout(i)
);
end generate gen1;
-- last adder's cout is cout of entity
cout <= cout_cout(N-1);
end architecture circuit;
| gpl-3.0 | ba08e5af4631a377a747c9a36387fbc4 | 0.489346 | 3.660167 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_uart/tb/uart_vvc_demo_th.vhd | 1 | 4,928 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
library bitvis_vip_uart;
library bitvis_uart;
library bitvis_vip_clock_generator;
-- Test harness entity
entity uart_vvc_demo_th is
end entity;
-- Test harness architecture
architecture struct of uart_vvc_demo_th is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
constant C_CLOCK_GEN : natural := 1;
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity work.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => 3,
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_DATA_WIDTH => 8,
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Clock Generator VVC
-----------------------------------------------------------------------------
i_clock_generator_vvc : entity bitvis_vip_clock_generator.clock_generator_vvc
generic map(
GC_INSTANCE_IDX => C_CLOCK_GEN,
GC_CLOCK_NAME => "Clock",
GC_CLOCK_PERIOD => C_CLK_PERIOD,
GC_CLOCK_HIGH_TIME => C_CLK_PERIOD / 2
)
port map(
clk => clk
);
end struct;
| mit | 888d2227804b41f98c9a4a4505fc50cf | 0.44724 | 4.697807 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/DIVIDER_32b.vhd | 1 | 4,818 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
entity DIVIDER_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end DIVIDER_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of DIVIDER_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
signal start_delay : std_logic;
begin
-------------------------------------------------------------------------
-- synthesis translate_off
-- process
-- begin
-- wait for 1 ns;
-- ASSERT false REPORT "(IMS) DIVIDER_32b : ALLOCATION OK !";
-- wait;
-- end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
start_delay <= '0';
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
start_delay <= '0';
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
start_delay <= start_delay;
-- Sinon on déroule l'execution de la division
else
start_delay <= start;
case sm is
-- Etat d'attente du signal start
when 0 =>
--buf1 <= (others => '0');
--buf2 <= INPUT_1;
--dbuf <= INPUT_2;
OUTPUT_1 <= buf2;
if start_delay = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
-- printmsg("(mDIV) ===> (000) THE START SIGNAL HAS BEEN RECEIVED !");
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(mDIV) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
else
--printmsg("(mDIV) ===> (000) WAITING FOR THE START SIGNAL...");
sm <= sm;
end if;
-- when 1 =>
-- printmsg("(mDIV) ===> (001) READING THE INPUT DATA");
-- buf1 <= (others => '0');
-- buf2 <= INPUT_1;
-- dbuf <= INPUT_2;
-- sm <= sm + 1; -- le calcul est en cours
-- if ( (INPUT_1(30) /= '-') AND (INPUT_1(30) /= 'X') AND (INPUT_1(30) /= 'U')) then
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- end if;
-- if ( (INPUT_2(30) /= '-') AND (INPUT_2(30) /= 'X') AND (INPUT_2(30) /= 'U')) then
-- printmsg("(mDIV) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- end if;
-- when 34 =>
-- OUTPUT_1 <= buf2;
-- snready := '1'; -- le resultat du calcul est disponible
-- sm <= 0;
-- printmsg("(mDIV) ===> (010) THE COMPUTATION IS FINISHED :-)");
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
--OUTPUT_1 <= buf2(30 downto 0) & '1';
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(buf2(30 downto 0) & '1',6) & ")");
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
| gpl-3.0 | 0a49121950fca7775a00b4e7413f92ce | 0.50851 | 3.205589 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_5b_dir/exercise8_5b.vhd | 1 | 1,113 | --!
--! @file: exercise8_5b.vhd
--! @brief: synchronous counter using component
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.pkg_sync_counter.all;
--------------------------------------
entity synchronous_counter is
port (
a, b, clk: in std_logic;
q: out std_logic_vector(2 downto 0));
end entity synchronous_counter;
--------------------------------------
architecture circuit of synchronous_counter is
signal andq: std_logic_vector(1 to 0);
begin
sync_cell0: sync_counter port map (
a => a
b => b,
clk => clk,
q => q(0),
andq => andq(0),
);
sync_cell1: sync_counter port map (
a => andq(0),
b => q(0),
clk => clk,
q => q(1)
);
sync_cell2: sync_counter port map (
a => andq(1)
b => q(1),
clk => clk,
q => q(2)
);
end architecture circuit;
| gpl-3.0 | fe587dd0e7dc470112df38546fd67fcd | 0.455526 | 3.919014 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_avalon_mm/src/avalon_mm_bfm_pkg.vhd | 1 | 37,752 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package avalon_mm_bfm_pkg is
----------------------------------------------------
-- Types for Avalon BFM
----------------------------------------------------
constant C_SCOPE : string := "AVALON MM BFM";
-- Avalon Interface signals
type t_avalon_mm_if is record
-- Avalon MM BFM to DUT signals
reset : std_logic;
address : std_logic_vector;
begintransfer : std_logic; -- optional, Altera recommends not to use
byte_enable : std_logic_vector;
chipselect : std_logic;
write : std_logic;
writedata : std_logic_vector;
read : std_logic;
lock : std_logic;
-- Avalon MM DUT to BFM signals
readdata : std_logic_vector;
response : std_logic_vector(1 downto 0); -- Set use_response_signal to false if not in use
waitrequest : std_logic;
readdatavalid : std_logic; -- might be used, might not.. If not used, fixed latency is a given
-- (same for read and write), unless waitrequest is used.
irq : std_logic;
end record;
-- Configuration record to be assigned in the test harness.
type t_avalon_mm_bfm_config is
record
max_wait_cycles : integer; -- Sets the maximum number of wait cycles before an alert occurs when waiting for readdatavalid or stalling because of waitrequest
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period accuracy margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
num_wait_states_read : natural; -- use_waitrequest = false -> this controls the (fixed) latency for read
num_wait_states_write : natural; -- use_waitrequest = false -> this controls the (fixed) latency for write
use_waitrequest : boolean; -- slave uses waitrequest
use_readdatavalid : boolean; -- slave uses readdatavalid (variable latency)
use_response_signal : boolean; -- Whether or not to check the response signal on read
use_begintransfer : boolean; -- Whether or not to assert begintransfer on start of transfer (Altera recommends not to use)
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the Avalon BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the Avalon BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the Avalon BFM
end record;
constant C_AVALON_MM_BFM_CONFIG_DEFAULT : t_avalon_mm_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => 10 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 2.5 ns,
hold_time => 2.5 ns,
num_wait_states_read => 0,
num_wait_states_write => 0,
use_waitrequest => true,
use_readdatavalid => false,
use_response_signal => true,
use_begintransfer => false,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
type t_avalon_mm_response_status is (OKAY, RESERVED, SLAVEERROR, DECODEERROR);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_avalon_mm_if_signals(
addr_width : natural;
data_width : natural;
lock_value : std_logic := '0'
) return t_avalon_mm_if;
-- This procedure could be called from an a simple testbench or
-- from an executor where there are concurrent BFMs - where
-- all BFMs could have different configs and msg_id_panels.
-- From a simplified testbench it is not necessary to use arguments
-- where defaults are given, e.g.:
-- avalon_mm_write(addr, data, msg, clk, avalon_mm_if);
-- avalon_mm_write overload without byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
-- avalon_mm_write with byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant byte_enable : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read" -- overwrite if called from other procedure like avalon_mm_check
);
procedure avalon_mm_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_reset (
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_read_request (
constant addr_value : in unsigned;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like avalon_mm_check
);
procedure avalon_mm_read_response (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read_response" -- overwrite if called from other procedure like avalon_mm_check
);
procedure avalon_mm_check_response (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_lock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_unlock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
end package avalon_mm_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body avalon_mm_bfm_pkg is
function init_avalon_mm_if_signals(
addr_width : natural;
data_width : natural;
lock_value : std_logic := '0'
) return t_avalon_mm_if is
variable result : t_avalon_mm_if(address(addr_width - 1 downto 0),
byte_enable((data_width/8) - 1 downto 0),
writedata(data_width - 1 downto 0),
readdata(data_width-1 downto 0));
begin
-- BFM to DUT signals
result.reset := '0';
result.address := (result.address'range => '0');
result.begintransfer := '0';
result.byte_enable := (result.byte_enable'range => '1');
result.chipselect := '0';
result.write := '0';
result.writedata := (result.writedata'range => '0');
result.read := '0';
result.lock := lock_value;
-- DUT to BFM signals
result.readdata := (result.readdata'range => 'Z');
result.response := (result.response'range => 'Z');
result.waitrequest := 'Z';
result.readdatavalid := 'Z';
result.irq := 'Z';
return result;
end function;
function to_avalon_mm_response_status(
constant response : in std_logic_vector(1 downto 0);
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return t_avalon_mm_response_status is
begin
case response is
when "00" =>
return OKAY;
when "10" =>
return RESERVED;
when "11" =>
return SLAVEERROR;
when others =>
return DECODEERROR;
end case;
end function;
-- avalon_mm_write overload without byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := "avalon_mm_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "address", "avalon_mm_if.address", msg);
variable v_normalized_data : std_logic_vector(avalon_mm_if.writedata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.writedata, ALLOW_NARROWER, "data", "avalon_mm_if.writedata", msg);
variable v_byte_enable : std_logic_vector((avalon_mm_if.writedata'length/8) - 1 downto 0) := (others => '1');
variable timeout : boolean := false;
begin
avalon_mm_write(addr_value, data_value, msg, clk, avalon_mm_if, v_byte_enable, scope, msg_id_panel, config);
end procedure;
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant byte_enable : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := "avalon_mm_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "address", "avalon_mm_if.address", msg);
variable v_normalized_data : std_logic_vector(avalon_mm_if.writedata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.writedata, ALLOW_NARROWER, "data", "avalon_mm_if.writedata", msg);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable timeout : boolean := false;
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
-- check if enough room for setup_time if clk is in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event)) then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
avalon_mm_if.writedata <= v_normalized_data;
avalon_mm_if.byte_enable <= byte_enable;
avalon_mm_if.write <= '1';
avalon_mm_if.chipselect <= '1';
avalon_mm_if.address <= v_normalized_addr;
if config.use_begintransfer then
avalon_mm_if.begintransfer <= '1';
end if;
wait until rising_edge(clk); -- wait for DUT update of signal
v_last_rising_edge := now; -- time stamp for clk period checking
-- Release the begintransfer signal after one clock cycle, if waitrequest is in use
if config.use_begintransfer then
avalon_mm_if.begintransfer <= '0' after config.clock_period/4;
end if;
-- use wait request?
if config.use_waitrequest then
for cycle in 1 to config.max_wait_cycles loop
if avalon_mm_if.waitrequest = '1' then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout waiting for waitrequest " & add_msg_delimiter(msg), scope);
end if;
else -- not waitrequest. num_wait_states_write will be used as number of wait cycles in fixed wait-states
for cycle in 1 to config.num_wait_states_write loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
end loop;
end if;
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length, avalon_mm_if.lock);
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure avalon_mm_write;
function is_readdatavalid_active(
signal avalon_mm_if : in t_avalon_mm_if;
constant config : in t_avalon_mm_bfm_config
) return boolean is
begin
if (config.use_readdatavalid and avalon_mm_if.readdatavalid = '1') then
return true;
end if;
return false;
end function is_readdatavalid_active;
function is_waitrequest_active(
signal avalon_mm_if : in t_avalon_mm_if;
constant config : in t_avalon_mm_bfm_config
) return boolean is
begin
if (config.use_waitrequest and avalon_mm_if.waitrequest = '1') then
return true;
end if;
return false;
end function is_waitrequest_active;
procedure avalon_mm_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read" -- overwrite if called from other procedure like avalon_mm_check
) is
begin
avalon_mm_read_request(addr_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
avalon_mm_read_response(addr_value, data_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
end procedure avalon_mm_read;
procedure avalon_mm_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_check";
constant proc_call : string := "avalon_mm_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_exp, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_data_value : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
avalon_mm_read_request(addr_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_call);
avalon_mm_check_response(addr_value, data_exp, msg, clk, avalon_mm_if, alert_level, scope, msg_id_panel, config);
end procedure avalon_mm_check;
procedure avalon_mm_reset (
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_reset(num_rst_cycles=" & to_string(num_rst_cycles) & ")";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length);
avalon_mm_if.reset <= '1';
for i in 1 to num_rst_cycles loop
wait until rising_edge(clk);
end loop;
avalon_mm_if.reset <= '0';
wait until rising_edge(clk);
end procedure avalon_mm_reset;
-- NOTE: This procedure returns as soon as the read command has been accepted. To retreive the response, use
-- avalon_mm_read_response or avalon_mm_check_response.
procedure avalon_mm_read_request (
constant addr_value : in unsigned;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like avalon_mm_check
) is
-- local_proc_* used if called from sequencer or VVC
constant local_proc_name : string := "avalon_mm_read_request";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
variable timeout : boolean := false;
variable v_proc_call : line; -- Current proc_call, external or local
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "addr", "avalon_mm_if.address", msg);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
if ext_proc_call = "" then
-- called from sequencer/VVC, show 'avalon_mm_read_request...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like axistream_expect, log 'avalon_mm_check() while executing avalon_mm_read_request...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event)) then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, local_proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Setup time
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
-- start the read
avalon_mm_if.address <= v_normalized_addr;
avalon_mm_if.read <= '1';
avalon_mm_if.byte_enable(avalon_mm_if.byte_enable'length - 1 downto 0) <= (others => '1'); -- always all bytes for reads
avalon_mm_if.chipselect <= '1';
wait until rising_edge(clk); -- wait for DUT update of signal
v_last_rising_edge := now; -- time stamp for clock_period checking
-- Handle read with waitrequests
if config.use_waitrequest then
for cycle in 1 to config.max_wait_cycles loop
if is_waitrequest_active(avalon_mm_if, config) then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout waiting for waitrequest" & add_msg_delimiter(msg), scope);
end if;
else -- not waitrequest - issue read, wait num_wait_states_read before finishing the read
for cycle in 1 to config.num_wait_states_read loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
end loop;
end if;
if ext_proc_call = "" then -- proc_name = "avalon_mm_read_request"
log(ID_BFM, v_proc_call.all & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length, avalon_mm_if.lock) after config.clock_period/4;
end procedure avalon_mm_read_request;
procedure avalon_mm_read_response (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read_response" -- overwrite if called from other procedure like avalon_mm_check
) is
constant proc_call : string := "avalon_mm_read_response(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_last_rising_edge : time := -1 ns; -- time stamp for clock_period checking
variable timeout : boolean := false;
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
-- Handle read with readdatavalid.
if config.use_readdatavalid then
for cycle in 1 to config.max_wait_cycles loop
-- Check for readdatavalid
if is_readdatavalid_active(avalon_mm_if, config) then
log(config.id_for_bfm, "readdatavalid was active after " & to_string(cycle) & " clock cycles", scope, msg_id_panel);
exit;
else
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- take a new time stamp for clk period checking
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout waiting for readdatavalid" & add_msg_delimiter(msg), scope);
end if;
end if;
if config.use_response_signal = true and to_avalon_mm_response_status(avalon_mm_if.response) /= OKAY then
error("Avalon MM read response was not OKAY, got " & to_string(avalon_mm_if.response), scope);
end if;
v_normalized_data := avalon_mm_if.readdata;
data_value := v_normalized_data(data_value'length-1 downto 0);
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
if proc_name = "avalon_mm_read_response" then
log(config.id_for_bfm, proc_call & "=> " & to_string(data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure avalon_mm_read_response;
procedure avalon_mm_check_response (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_check_response";
constant proc_call : string := proc_name&"(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_exp, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_data_value : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
avalon_mm_read_response(addr_value, v_data_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
v_check_ok := true;
for i in 0 to (v_normalized_data'length)-1 loop
if v_normalized_data(i) = '-' or v_normalized_data(i) = v_data_value(i) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
alert(alert_level, proc_call & "=> Failed. slv Was " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure avalon_mm_check_response;
procedure avalon_mm_lock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_lock()";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if.lock <= '1';
end procedure avalon_mm_lock;
procedure avalon_mm_unlock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_unlock()";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if.lock <= '0';
end procedure avalon_mm_unlock;
end package body avalon_mm_bfm_pkg;
| mit | 05737f94171f294988cdf6826c690974 | 0.597425 | 3.728593 | false | true | false | false |
makestuff/swled | templates/fx2all/vhdl/top_level.vhdl | 1 | 5,119 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => fx2Clk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
| gpl-3.0 | 0fbd0bb9ca7a5e8969a4909d4fe5d365 | 0.598359 | 3.383344 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_agen.vhd | 1 | 4,486 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END Instruction_Memory_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit | 6ce61f31e9816bfd2f0c4916e0c3f640 | 0.58337 | 4.280534 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/config_pkg.vhd | 1 | 3,976 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : config_pkg.vhd
-- Design name : config_pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package config_pkg is
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
constant CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
constant CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
constant CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2;
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_pkg;
| lgpl-3.0 | 94cb430864ea6d91cc562ec40e9c3d00 | 0.52666 | 5.177083 | false | true | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/memory_64k.vhd | 1 | 3,719 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:23 07/17/2011
-- Design Name:
-- Module Name: memory_64k - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY memory_64k IS
PORT (
clk : IN STD_LOGIC;
addr_in : IN STD_LOGIC_VECTOR (31 DOWNTO 2);
data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enable : IN STD_LOGIC;
we_select : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END memory_64k;
ARCHITECTURE Behavioral OF memory_64k IS
CONSTANT ADDRESS_WIDTH : NATURAL := 7; -- 2**X = NOMBRE D'OCTETS DE LA MEMOIRE
-- 14 => 16ko of memory
-- 15 => 32ko of memory
-- 16 => 64ko of memory
-- 17 => 128ko of memory
TYPE ptorage_array IS ARRAY(NATURAL RANGE 0 TO (2 ** ADDRESS_WIDTH) / 4 - 1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL memBank1 : ptorage_array;
SIGNAL memBank2 : ptorage_array;
SIGNAL memBank3 : ptorage_array;
SIGNAL memBank4 : ptorage_array;
attribute RAM_STYLE : string;
attribute RAM_STYLE of memBank1: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank2: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank3: signal is "DISTRIBUTED";
attribute RAM_STYLE of memBank4: signal is "DISTRIBUTED";
BEGIN
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(0) = '1' then
memBank1(index) <= data_in(7 DOWNTO 0);
end if;
data_out(7 DOWNTO 0) <= memBank1(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(1) = '1' then
memBank2(index) <= data_in(15 DOWNTO 8);
end if;
data_out(15 DOWNTO 8) <= memBank2(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(2) = '1' then
memBank3(index) <= data_in(23 DOWNTO 16);
end if;
data_out(23 DOWNTO 16) <= memBank3(index);
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(3) = '1' then
memBank4(index) <= data_in(31 DOWNTO 24);
end if;
data_out(31 DOWNTO 24) <= memBank4(index);
end if;
end if;
end process;
END Behavioral;
| gpl-3.0 | 2e5425c9fbea6371b2a7ad6c3c1c2f9e | 0.522183 | 3.707876 | false | false | false | false |
mohamed/tdm-hw-arbiter | tdm_arbiter_tb.vhd | 1 | 1,592 | -- Testbench
-- Author: Mohamed A. Bamakhrama <[email protected]>
-- Copyrights (c) 2009-2014 by Leiden University, The Netherlands
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library work;
use work.tdm_arbiter_pkg.all;
entity tdm_arbiter_tb is
end tdm_arbiter_tb;
architecture behav of tdm_arbiter_tb is
constant clock_frequency : natural := 400_000_000;
constant clock_period : time := 1000 ms /clock_frequency;
signal tb_clock : std_logic := '0';
signal tb_reset_n : std_logic := '0';
signal tb_hold : std_logic := '0';
signal tb_exists : std_logic_vector(NUM_OF_FIFOS-1 downto 0) := (others => '0');
signal tb_read : std_logic_vector(NUM_OF_FIFOS-1 downto 0) := (others => '0');
begin
tb_clock <= not tb_clock after clock_period/2;
uut: tdm_arbiter
port map
(
clk => tb_clock,
reset_n => tb_reset_n,
hold => tb_hold,
exists => tb_exists,
read => tb_read
);
tb: process
begin
tb_reset_n <= '0';
wait for 2*clock_period;
tb_reset_n <= '1';
tb_hold <= '0';
tb_exists <= "0100101000101010";
wait for 20*clock_period;
tb_exists <= "1101110000101011";
wait for 20*clock_period;
tb_exists <= "1111111111111111";
wait for 20*clock_period;
tb_exists <= "1000000000000000";
wait for 20*clock_period;
tb_exists <= "0000000000000000";
wait for 20*clock_period;
assert false report "Simulation stopped" severity failure;
end process;
end behav;
| bsd-3-clause | c02d228f543e4a74130a003c9202a0be | 0.641332 | 2.975701 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/example8_4_dir/example8_4_tb.vhd | 1 | 4,099 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: example8_4_tb.vhd
--! @brief: testbench of shift register with component and generate
--! @author: Antonio Gutierrez
--! @date: 2014-04-10
--!
--!
--------------------------------------
library ieee;
-- library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
--------------------------------------
--------------------------------------
entity shift_register_tb is
generic (M: positive := 4; -- num. of stages
N: positive := 8); -- bits per stage
end entity shift_register_tb;
--------------------------------------
--------------------------------------
architecture circuit of shift_register_tb is
-- dut declarations
component shift_register is
port (
clk, load: in std_logic;
x: in std_logic_vector(N-1 downto 0);
d: in twoD(0 to M-1, N-1 downto 0);
y: out std_logic_vector(N-1 downto 0));
end component shift_register;
-- signal declaration
signal clk_tb: std_logic := '0';
signal load_tb: std_logic := '0';
signal x_tb: std_logic_vector(N-1 downto 0);
signal d_tb: twoD(0 to M-1, N-1 downto 0);
signal y_tb: std_logic_vector(N-1 downto 0);
constant x_const: integer := 44;
constant d_tb0: std_logic_vector := std_logic_vector(to_unsigned(55, N));
constant d_tb1: std_logic_vector := std_logic_vector(to_unsigned(66, N));
constant d_tb2: std_logic_vector := std_logic_vector(to_unsigned(77, N));
constant d_tb3: std_logic_vector := std_logic_vector(to_unsigned(88, N));
type array_of_std_logic_vector is array (natural range <>) of std_logic_vector(N-1 downto 0);
constant d_tb_all: array_of_std_logic_vector(M-1 downto 0) := ( d_tb3, d_tb2, d_tb1, d_tb0 );
begin
-- dut ins
dut: shift_register port map (
clk => clk_tb,
load => load_tb,
x => x_tb,
d => d_tb,
y => y_tb
);
-- stimuli generation
-- clk
clk_tb <= not clk_tb after 20 ns;
-- x
x_tb <= std_logic_vector(to_unsigned(44, N)), std_logic_vector(to_unsigned(33,N)) after 170 ns, std_logic_vector(to_unsigned(0, N)) after 210 ns;
-- load
load_tb <= '1' after 50 ns, '0' after 61 ns;
-- uncomment and comment other part
-- d
-- initialize each d to each one
-- gen: for i in N-1 downto 0 generate
-- d_tb(3, i) <= d_tb3(i);
-- d_tb(2, i) <= d_tb2(i);
-- d_tb(1, i) <= d_tb1(i);
-- d_tb(0, i) <= d_tb0(i);
-- end generate gen;
gen1: for j in M-1 downto 0 generate
gen2: for i in N-1 downto 0 generate
d_tb(j, i) <= d_tb_all(j)(i);
end generate gen2;
end generate gen1;
-- output verification
process
--declarative part
begin
wait for 61 ns;
assert y_tb = std_logic_vector(to_unsigned(88, N))
report "error not expected value at 61 ns"
severity failure;
wait for 40 ns; -- 101
assert y_tb = std_logic_vector(to_unsigned(77, N))
report "error not expected value at 101 ns"
severity failure;
wait for 40 ns;
assert y_tb = std_logic_vector(to_unsigned(66, N))
report "error not expected value at 141 ns"
severity failure;
wait for 40 ns;
assert y_tb = std_logic_vector(to_unsigned(55, N))
report "error not expected value at 181 ns"
severity failure;
wait for 40 ns;
assert y_tb = std_logic_vector(to_unsigned(44, N))
report "error not expected value at 221 ns"
severity failure;
wait for 80 ns;
assert y_tb = std_logic_vector(to_unsigned(33, N))
report "error not expected value at 261 ns"
severity failure;
wait for 40 ns;
assert y_tb = std_logic_vector(to_unsigned(0, N))
report "error not expected value at 301 ns"
severity failure;
assert false
report "no errors"
severity note;
end process;
end architecture circuit;
| gpl-3.0 | cd1ac48db71879a644583d3fe4ae92aa | 0.557209 | 3.473729 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/methods_pkg.vhd | 1 | 266,289 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.global_signals_and_shared_variables_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) ;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean ;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean ;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_slv_array;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array;
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Adjustable clock generators
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
);
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := WARNING;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status: file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
variable v_idx : natural := 1;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), LEFT, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF then
loop
if (msg(v_idx to v_idx+1) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
v_idx := v_idx + 2;
else
write(v_msg, remove_initial_chars(msg, v_idx-1));
exit;
end if;
end loop;
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
end if;
end if;
end;
-- Calls overloaded log procedure with default msg_id
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
begin
log(C_TB_MSG_ID_DEFAULT, msg, scope, msg_id_panel, log_destination, log_file_name, open_mode);
end procedure log;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
msg_id_panel(ID_LOG_MSG_CTRL) := ENABLED; -- keep
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
if C_USE_STD_STOP_ON_ALERT_STOP_LIMIT then
std.env.stop(1);
else
assert false report "This single Failure line has been provoked to stop the simulation. See alert-message above" severity failure;
end if;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT" & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT, KEEP_LEADING_SPACE) & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", LEFT, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_upper(to_string(shared_msg_id_panel(i))) & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_ERROR,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (WARNING, TB_WARNING, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
alias found_unexpected_simulation_warnings_or_worse is shared_uvvm_status.found_unexpected_simulation_warnings_or_worse;
alias found_unexpected_simulation_errors_or_worse is shared_uvvm_status.found_unexpected_simulation_errors_or_worse;
alias mismatch_on_expected_simulation_warnings_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_warnings_or_worse;
alias mismatch_on_expected_simulation_errors_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= NOTE) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
found_unexpected_simulation_warnings_or_worse := 0; -- default
found_unexpected_simulation_errors_or_worse := 0; -- default
mismatch_on_expected_simulation_warnings_or_worse := 0; -- default
mismatch_on_expected_simulation_errors_or_worse := 0; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) /= get_alert_counter(alert_check_array(i), EXPECT)) then
-- MISMATCH
-- warning or worse
mismatch_on_expected_simulation_warnings_or_worse := 1;
-- error or worse
if not(alert_check_array(i) = WARNING) and not(alert_check_array(i) = TB_WARNING) then
mismatch_on_expected_simulation_errors_or_worse := 1;
end if;
-- FOUND UNEXPECTED ALERT
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
found_unexpected_simulation_warnings_or_worse := 1;
-- error and worse
if not(alert_check_array(i) = WARNING) and not(alert_check_array(i) = TB_WARNING) then
found_unexpected_simulation_errors_or_worse := 1;
end if;
end if;
end if;
end loop;
end if;
end if;
end;
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_alert_stop_limit : natural := get_alert_stop_limit(alert_level);
begin
increment_expected_alerts(alert_level, number, msg, scope);
set_alert_stop_limit(alert_level, v_alert_stop_limit + number);
end ;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, RIGHT, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", RIGHT, 100) then
deprecated_subprogram_list(i) := justify(caller_name, RIGHT, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1 : std_logic_vector;
value2 : std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0) and
a_value1'left >= maximum( idx_leftmost_p1_in_p2('H', a_value2), 0) and
a_value1'left >= maximum( idx_leftmost_p1_in_p2('Z', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0) and
a_value2'left >= maximum( idx_leftmost_p1_in_p2('H', a_value1), 0) and
a_value2'left >= maximum( idx_leftmost_p1_in_p2('Z', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
case match_strictness is
when MATCH_STD =>
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
when MATCH_STD_INCL_Z =>
for i in v_min_length-1 downto 0 loop
if not(std_match(a_value1(i), a_value2(i)) or (a_value1(i) = 'Z' and a_value2(i) = 'Z')) then
v_match := false;
exit;
end if;
end loop;
when others =>
if a_value1(v_min_length-1 downto 0) /= a_value2(v_min_length-1 downto 0) then
v_match := false;
end if;
end case;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
variable v_failed : boolean := false;
begin
case match_strictness is
when MATCH_STD =>
if std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when MATCH_STD_INCL_Z =>
if (value = 'Z' and exp = 'Z') or std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when others =>
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
end case;
if v_failed = true then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
else
return true;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format,INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format,INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
variable v_trigger_alert : boolean := false; -- trigger alert and log message
-- Match length of short string with long string
function pad_short_string(short, long : string) return string is
variable v_padding : string(1 to (long'length - short'length)) := (others => '0');
begin
-- Include leading 'x"'
return short(1 to 2) & v_padding & short(3 to short'length);
end function pad_short_string;
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp, match_strictness);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
v_trigger_alert := true; -- alert and log
end if;
end if;
else
v_trigger_alert := true; -- alert and log
end if;
-- trigger alert and log message
if v_trigger_alert then
if v_value_str'length > v_exp_str'length then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & pad_short_string(v_exp_str,v_value_str) & "." & LF & msg, scope);
elsif v_value_str'length < v_exp_str'length then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & pad_short_string(v_value_str,v_exp_str) & ". Expected " & v_exp_str & "." & LF & msg, scope);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
end if;
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
begin
for idx in exp'range loop
if not(check_value(value(idx), exp(idx), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
return true;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
begin
for idx in exp'range loop
if not(check_value(std_logic_vector(value(idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
return true;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
begin
for idx in exp'range loop
if not(check_value(std_logic_vector(value(idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
return true;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(value(idx + v_adj_idx), exp(idx), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end loop;
end if;
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end loop;
end if;
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end loop;
end if;
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
variable v_rand : integer;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
random(0,1, v_seed1, v_seed2, v_rand);
v_target(i downto i) := std_logic_vector(to_unsigned(v_rand,1));
end loop;
end;
-- Set target to a random SL, using overload for the SLV version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
random(v_seed1, v_seed2, v_random_slv);
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_slv_array is
variable v_slv_array : t_slv_array(0 to (byte_array'length/bytes_in_word)-1)((8*bytes_in_word)-1 downto 0);
variable v_byte_idx : integer := 0;
variable v_num_bytes : integer := byte_array'length/bytes_in_word;
begin
for idx in 0 to v_num_bytes-1 loop
if byte_endianness = FIRST_BYTE_LEFT then
for byte_in_word in bytes_in_word downto 1 loop
v_slv_array(idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
else -- FIRST_BYTE_RIGHT
for byte_in_word in 1 to bytes_in_word loop
v_slv_array(idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
return v_slv_array;
end function;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array is
variable v_bytes_in_word : integer := (slv_array(slv_array'low)'length/8);
variable v_byte_array_length : integer := (slv_array'length * v_bytes_in_word);
variable v_ascending_array : t_byte_array(0 to v_byte_array_length-1);
variable v_descending_array : t_byte_array(v_byte_array_length-1 downto 0);
variable v_ascending_vector : boolean := false;
variable v_byte_number : integer := 0;
variable v_offset : natural := 0;
begin
-- The ascending parameter should match the array direction. We could also just remove the ascending
-- parameter and use the t'ascending attribute.
bitvis_assert((slv_array'ascending and ascending) or (not(slv_array'ascending) and not(ascending)), ERROR,
"convert_slv_array_to_byte_array()", "slv_array direction doesn't match ascending parameter");
v_ascending_vector := slv_array(slv_array'low)'ascending;
-- Use this offset in case the slv_array doesn't start at 0
v_offset := slv_array'low;
if byte_endianness = FIRST_BYTE_LEFT then
for slv_idx in 0 to slv_array'length-1 loop
for byte in v_bytes_in_word downto 1 loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
else -- FIRST_BYTE_RIGHT
for slv_idx in 0 to slv_array'length-1 loop
for byte in 1 to v_bytes_in_word loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
end if;
if ascending then
return v_ascending_array;
else -- descending
return v_descending_array;
end if;
end function;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if pulse_value(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for clock_high_time;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Adjustable clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end procedure;
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
) is
constant v_clock_name : string := "";
begin
adjustable_clock_generator(clock_signal, clock_ena, clock_period, v_clock_name, clock_high_percentage);
end procedure;
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end procedure;
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- Local type used in synchronization methods
type t_flag_array_idx_and_status_record is record
flag_idx : integer;
flag_is_new : boolean;
flag_array_full : boolean;
end record;
-- Local function used in synchronization methods to search through shared_flag_array for flag_name or available index
-- Returns:
-- Flag index in the shared array
-- If the flag is new or already in the array
-- If the array is full, and the flag can not be added (alerts an error).
impure function find_or_add_sync_flag(
constant flag_name : string
) return t_flag_array_idx_and_status_record is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
for i in shared_flag_array'range loop
-- Search for empty index. If found add a new flag
if (shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => NUL)) then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_is_new := true;
end if;
-- Check if flag exists in the array
if (shared_flag_array(i).flag_name(flag_name'range) = flag_name) then
v_idx := i;
v_is_array_full := false;
exit;
end if;
end loop;
return (v_idx, v_is_new, v_is_array_full);
end;
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := WARNING;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Block flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
-- Check if the flag to be blocked already is blocked
if (shared_flag_array(v_idx).is_blocked = true) then
alert(already_blocked_severity, "The flag " & flag_name & " was already blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Blocking flag. " & add_msg_delimiter(msg), scope);
end if;
end if;
shared_flag_array(v_idx).is_blocked := true;
end if;
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Unblock flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New unblocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Unblocking flag. " & add_msg_delimiter(msg), scope);
end if;
shared_flag_array(v_idx).is_blocked := false;
-- Triggers a signal to allow await_unblock_flag() to detect unblocking.
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
variable v_flag_is_blocked : boolean := true;
constant start_time : time := now;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Waits only if the flag is found and is blocked. Will wait when a new flag is added, as it is default blocked.
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if (flag_returning = RETURN_TO_BLOCK) then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
log(ID_BLOCKING, flag_name & ": Was already unblocked. Returned to blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Was already unblocked. " & add_msg_delimiter(msg), scope);
end if;
else -- Flag is blocked (or a new flag was added), starts waiting. log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
end if;
end if;
-- Waiting for flag to be unblocked
while v_flag_is_blocked = true loop
if (timeout /= 0 ns) then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out. " & add_msg_delimiter(msg), scope, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if flag_returning = KEEP_UNBLOCKED then
log(ID_BLOCKING, flag_name & ": Has been unblocked. ", scope);
else
log(ID_BLOCKING, flag_name & ": Has been unblocked. Returned to blocked. ", scope);
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
end if;
end if;
end loop;
end if;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), scope);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), scope);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
end package body methods_pkg;
| mit | ac8574aecfaf9c5cef011599767970cb | 0.571218 | 3.762845 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_pc.vhd | 1 | 1,580 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:52 05/21/2017
-- Design Name:
-- Module Name: mux_pc1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_pc is
Port(
pcsrc : in STD_LOGIC_VECTOR (2 downto 0);
input1 : in STD_LOGIC_VECTOR (15 downto 0);--pc+2
input2 : in STD_LOGIC_VECTOR (15 downto 0);--¼Ä´æÆ÷
input3 : in STD_LOGIC_VECTOR (15 downto 0);--ALU
output : out STD_LOGIC_VECTOR (15 downto 0)
);
end mux_pc;
architecture Behavioral of mux_pc is
begin
process(pcsrc)
begin
case pcsrc is
when "000"=>output<=input1;
when "001"=>output<=input2;
when "010"=>
if input2="0000000000000000"then
output<=input3;
else
output<=input1;
end if;
when "011"=>
if input2="0000000000000000"then
output<=input1;
else
output<=input3;
end if;
when "100"=>
output<=input3;
when others => null;
end case;
end process;
end Behavioral;
| apache-2.0 | ec7e0f6389ed3e66d7a707727cd53413 | 0.591772 | 3.607306 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_i2c/src/vvc_methods_pkg.vhd | 1 | 32,091 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.i2c_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the I2C VVC
--===============================================================================================
constant C_VVC_NAME : string := "I2C_VVC";
signal I2C_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is I2C_VVCT;
alias t_bfm_config is t_i2c_bfm_config;
constant C_I2C_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_i2c_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_I2C_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_I2C_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_I2C_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0);
data : t_byte_array(0 to C_VVC_CMD_DATA_MAX_LENGTH-1);
num_bytes : natural;
action_when_transfer_is_done : t_action_when_transfer_is_done;
exp_ack : boolean;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
addr => (others => '0'),
data => (others => (others => '0')),
num_bytes => 0,
operation => NO_OPERATION,
msg => (others => ' '),
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
exp_ack => true
);
shared variable shared_i2c_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_I2C_VVC_CONFIG_DEFAULT);
shared variable shared_i2c_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_i2c_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
-- *****************************************************************************
--
-- master transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- single byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- *****************************************************************************
--
-- slave transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- single byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- *****************************************************************************
--
-- master receive
--
-- *****************************************************************************
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- *****************************************************************************
--
-- master check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- single byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- *****************************************************************************
--
-- slave receive
--
-- *****************************************************************************
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- *****************************************************************************
--
-- slave check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- single byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
-- master transmit
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_transmit(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, scope);
end procedure;
-- slave transmit
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_transmit(VVCT, vvc_instance_idx, v_byte_array, msg, scope);
end procedure;
-- master receive
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE);
shared_vvc_cmd.num_bytes := num_bytes;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- master check
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_check(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, alert_level, scope);
end procedure;
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_QUICK_CMD);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.exp_ack := exp_ack;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_byte_array, msg, alert_level, rw_bit, scope);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_dummy_byte_array : t_byte_array(0 to -1); -- Empty byte array to indicate that data is not checked
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_dummy_byte_array, msg, alert_level, rw_bit, scope);
end procedure;
end package body vvc_methods_pkg;
| mit | bdcd89201f99fc206c7bcbbb85ae2b40 | 0.545823 | 4.178516 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_synth.vhd | 1 | 7,280 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END Instruction_Memory_tb_synth;
ARCHITECTURE Instruction_Memory_synth_ARCH OF Instruction_Memory_tb_synth IS
COMPONENT Instruction_Memory_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
Instruction_Memory_TB_STIM_GEN_INST:ENTITY work.Instruction_Memory_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: Instruction_Memory_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| mit | 63fd768ef1c2d03bcc6118a34e8dde2d | 0.563462 | 3.79562 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_agen.vhd | 1 | 4,430 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Font_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END Font_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF Font_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit | 228a4dacef826ed7b508a30297c2dd74 | 0.579007 | 4.259615 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_19.vhd | 5 | 3,027 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | b11e44bc03dd8deed1b2297290a0bc72 | 0.562934 | 3.319079 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_11_dir/exercise5_11.vhd | 1 | 2,140 | --!
--! @file: exercise5_11.vhd
--! @brief: arithmeric circuit with std_logic
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mini_alu is
generic
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
opcode: in std_logic_vector(2 downto 0) ;
y: out std_logic_vector(N-1 downto 0);
cout: out std_logic);
end entity mini_alu;
--------------------------------------
architecture circuit of mini_alu is
-- signed
signal a_sig: signed(N-1 downto 0) ;
signal b_sig: signed(N-1 downto 0) ;
signal y_sig: signed(N downto 0);
-- unsigned
signal a_unsig: unsigned(N-1 downto 0) ;
signal b_unsig: unsigned(N-1 downto 0) ;
signal y_unsig: unsigned(N downto 0);
signal small_int: integer range 0 to 1;
begin
-- type casting
a_sig <= signed(a);
a_sig <= signed(a);
b_unsig <= unsigned(b);
b_unsig <= unsigned(b);
-- signed
with opcode(1 downto 0) select
y_sig <= (a_sig(N-1) & a_sig) + (b_sig(N-1) & b_sig) when "00",
(a_sig(N-1) & a_sig) - (b_sig(N-1) & b_sig) when "01".
(b_sig(N-1) & b_sig) - (a_sig(N-1) & a_sig) when "10",
(a_sig(N-1) & a_sig) + (b_sig(N-1) & b_sig) + ('0' & cin) when others;
-- unsigned
with opcode(1 downto 0) select
y_unsig <= ('0' & a_unsig) + ('0' & b_unsig) when "00",
('0' & a_unsig) - ('0' & b_unsig) when "01".
('0' & b_unsig) - ('0' & a_unsig) when "10",
('0' & a_unsig) + ('0' & b_unsig) + ('0' & cin) when others;
-- mux
with opcode(2) select
y <= std_logic_vector(y_unsig(N-1 downto 0)) when '0',
std_logic_vector(y_sig(N-1 downto 0)) when others;
-- cout
with opcode(2) select
y <= std_logic_vector(y_unsig(N)) when '0',
std_logic_vector(y_sig(N)) when others;
end architecture circuit;
--------------------------------------
| gpl-3.0 | faf7b3b7d936b3872e59222c61887010 | 0.492991 | 3.105951 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_3.vhd | 4 | 1,548 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff : UNSIGNED(7 downto 0);
variable mult : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data := UNSIGNED( INPUT_1(7 downto 0) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff := data - mini; -- 8
mult := diff * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult(15 downto 8));
OUTPUT_1(31 downto 8) <= (others => '0');
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | 2a345d2ee7966465936a65032d426dd5 | 0.547158 | 3.748184 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/Colorgen.vhd | 1 | 3,426 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Colorgen is
Port ( iter : in STD_LOGIC_VECTOR (7 downto 0);
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0)); -- blue output
end Colorgen;
architecture Behavioral of Colorgen is -- TODO : Améliorer colorgen (comparaison OpenGL)
type rom_type is array (0 to ITER_MAX-1) of std_logic_vector (bit_per_pixel-1 downto 0);
constant color_scheme : rom_type := (
x"000",
x"000",
x"001",
x"001",
x"002",
x"002",
x"002",
x"003",
x"003",
x"004",
x"004",
x"005",
x"005",
x"005",
x"006",
x"006",
x"006",
x"007",
x"017",
x"018",
x"018",
x"018",
x"018",
x"019",
x"019",
x"019",
x"02A",
x"02A",
x"02A",
x"02A",
x"02A",
x"02B",
x"02B",
x"03B",
x"03B",
x"03B",
x"03C",
x"03C",
x"03C",
x"04C",
x"04C",
x"04C",
x"04D",
x"04D",
x"04D",
x"05D",
x"05D",
x"05D",
x"05D",
x"05D",
x"05D",
x"06D",
x"06D",
x"16D",
x"16E",
x"16E",
x"17E",
x"17E",
x"17E",
x"17E",
x"17E",
x"17E",
x"18E",
x"18E",
x"18E",
x"18E",
x"18E",
x"18E",
x"19E",
x"29E",
x"29E",
x"29E",
x"29E",
x"29E",
x"2AE",
x"2AE",
x"2AD",
x"2AD",
x"2AD",
x"2AD",
x"3BD",
x"3BD",
x"3BD",
x"3BD",
x"3BD",
x"3BD",
x"3BD",
x"3CD",
x"3CD",
x"3CD",
x"4CC",
x"4CC",
x"4CC",
x"4CC",
x"4CC",
x"4DC",
x"4DC",
x"4DC",
x"5DC",
x"5DC",
x"5DB",
x"5DB",
x"5DB",
x"5DB",
x"5DB",
x"5EB",
x"6EB",
x"6EB",
x"6EA",
x"6EA",
x"6EA",
x"6EA",
x"6EA",
x"6EA",
x"7EA",
x"7EA",
x"7E9",
x"7E9",
x"7E9",
x"7E9",
x"7E9",
x"8E9",
x"8E9",
x"8E9",
x"8E8",
x"8E8",
x"8E8",
x"8E8",
x"9E8",
x"9E8",
x"9E8",
x"9E8",
x"9E7",
x"9E7",
x"9E7",
x"AE7",
x"AE7",
x"AE7",
x"AE7",
x"AE6",
x"AE6",
x"AE6",
x"AE6",
x"BE6",
x"BE6",
x"BE6",
x"BE6",
x"BE5",
x"BE5",
x"BE5",
x"CE5",
x"CD5",
x"CD5",
x"CD5",
x"CD5",
x"CD4",
x"CD4",
x"CD4",
x"CD4",
x"DD4",
x"DD4",
x"DC4",
x"DC4",
x"DC4",
x"DC3",
x"DC3",
x"DC3",
x"DC3",
x"DC3",
x"EB3",
x"EB3",
x"EB3",
x"EB3",
x"EB3",
x"EB2",
x"EB2",
x"EA2",
x"EA2",
x"EA2",
x"EA2",
x"EA2",
x"EA2",
x"E92",
x"E92",
x"F92",
x"F92",
x"F91",
x"F91",
x"F81",
x"F81",
x"F81",
x"F81",
x"F81",
x"F81",
x"F71",
x"F71",
x"F71",
x"F71",
x"F71",
x"E71",
x"E61",
x"E61",
x"E60",
x"E60",
x"E60",
x"E50",
x"E50",
x"E50",
x"E50",
x"E50",
x"E50",
x"E40",
x"D40",
x"D40",
x"D40",
x"D40",
x"D40",
x"D30",
x"D30",
x"C30",
x"C30",
x"C30",
x"C30",
x"C20",
x"B20",
x"B20",
x"B20",
x"B20",
x"A20",
x"A20",
x"A10",
x"A10",
x"910",
x"910",
x"910",
x"810",
x"810",
x"810",
x"700",
x"700",
x"700",
x"600",
x"600",
x"500",
x"500",
x"400",
x"400",
x"400",
x"300",
x"300",
x"200",
x"200",
x"100",
x"100",
x"000",
x"000");
begin
process(iter)
begin
--color <= not iters;
VGA_red <= color_scheme(to_integer(unsigned(iter)))(11 downto 8);
VGA_green <= color_scheme(to_integer(unsigned(iter)))( 7 downto 4);
VGA_blue <= color_scheme(to_integer(unsigned(iter)))( 3 downto 0);
end process;
end Behavioral;
--Cut and paste following lines into Shared.vhd.
-- constant ITER_MAX : integer := 4095;
-- constant ITER_RANGE : integer := 12;
| gpl-3.0 | b7c41c562b2014931d451e4ce73b86d1 | 0.514302 | 1.632984 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/TRIGO/COSINUS_SINUS_32b.vhd | 1 | 30,141 | -------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Cordic Top --
-- --
-- Simple SIN/COS Cordic example --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc. --
-- angle input +/-0.5phi --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity COSINUS_SINUS_32b is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
angle : in std_logic_vector(31 downto 0); -- input radian
sin : out std_logic_vector(31 downto 0); -- THIS OUTPUT ¨PROVIDES THE SINUS RESULT
cos : out std_logic_vector(31 downto 0);
start : in std_logic;
done : out std_logic);
end COSINUS_SINUS_32b;
architecture synthesis of COSINUS_SINUS_32b is
constant xinit_c : std_logic_vector(31 downto 0):=X"26dd3b44";
constant yinit_c : std_logic_vector(31 downto 0):=X"00000000";
component addsub is
port(abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end component;
component shiftn is
port(ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end component;
component atan32 is --ARCTAN(x) lut
port (ZA : in Std_Logic_Vector(4 downto 0);
ZData : out Std_Logic_Vector(31 downto 0));
end component;
component fsm is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
start : in std_logic;
cnt : in std_logic_vector(4 downto 0);
init : out std_logic;
load : out std_logic;
done : out std_logic);
end component;
signal cnt_s : std_logic_vector(4 downto 0); -- bit counter, 2^5
signal newx_s : std_logic_vector(31 downto 0);
signal newy_s : std_logic_vector(31 downto 0);
signal newz_s : std_logic_vector(31 downto 0);
signal xreg_s : std_logic_vector(31 downto 0);
signal yreg_s : std_logic_vector(31 downto 0);
signal zreg_s : std_logic_vector(31 downto 0);
signal sxreg_s: std_logic_vector(31 downto 0);
signal syreg_s: std_logic_vector(31 downto 0);
signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT
signal init_s : std_logic;
signal load_s : std_logic;
signal as_s : std_logic;
signal nas_s : std_logic;
begin
SHIFT1: shiftn port map (xreg_s,sxreg_s,cnt_s);
SHIFT2: shiftn port map (yreg_s,syreg_s,cnt_s);
nas_s <= not as_s;
ADD1 : addsub port map (xreg_s,syreg_s,newx_s,as_s); -- xreg
ADD2 : addsub port map (yreg_s,sxreg_s,newy_s,nas_s); -- yreg
LUT : atan32 port map(cnt_s,atan_s);
ADD3 : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s); -- zreg
FSM1 : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done);
-- COS(X) Register
process (clk,newx_s)
begin
if (rising_edge(clk)) then
if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607
elsif load_s='1' then xreg_s <= newx_s;
end if;
end if;
end process;
-- SIN(Y) Register
process (clk,newy_s)
begin
if (rising_edge(clk)) then
if init_s='1' then yreg_s <= yinit_c; -- 0.0000 fails in vh2sc yinit_c(31 downto 0)
elsif load_s='1' then yreg_s <= newy_s;
end if;
end if;
end process;
-- Z Register
process (clk,newz_s,angle)
begin
if (rising_edge(clk)) then
if init_s='1' then zreg_s <= angle; -- x
elsif load_s='1' then zreg_s <= newz_s;
end if;
end if;
end process;
as_s <= zreg_s(31); -- MSB=Sign bit
process (clk,load_s,init_s) -- bit counter
begin
if (rising_edge(clk)) then
if init_s='1' then cnt_s<=(others=> '0');
elsif (load_s='1') then cnt_s <= cnt_s + '1';
end if;
end if;
end process;
sin <= yreg_s;
cos <= xreg_s;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Adder/Subtracter --
-- no overflow. --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port (abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end addsub;
architecture synthesis of addsub is
begin
process(as,abus,bbus)
begin
if as='1' then
obus <= abus + bbus;
else
obus <= abus - bbus;
end if;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity atan32 is
port ( za : in std_logic_vector(4 downto 0);
zdata : out std_logic_vector(31 downto 0));
end atan32;
Architecture synthesis of atan32 Is
Begin
process(ZA)
begin
Case ZA is
when "00000" => ZData <= X"3243f6a8";
when "00001" => ZData <= X"1dac6705";
when "00010" => ZData <= X"0fadbafc";
when "00011" => ZData <= X"07f56ea6";
when "00100" => ZData <= X"03feab76";
when "00101" => ZData <= X"01ffd55b";
when "00110" => ZData <= X"00fffaaa";
when "00111" => ZData <= X"007fff55";
when "01000" => ZData <= X"003fffea";
when "01001" => ZData <= X"001ffffd";
when "01010" => ZData <= X"000fffff";
when "01011" => ZData <= X"0007ffff";
when "01100" => ZData <= X"0003ffff";
when "01101" => ZData <= X"0001ffff";
when "01110" => ZData <= X"0000ffff";
when "01111" => ZData <= X"00007fff";
when "10000" => ZData <= X"00003fff";
when "10001" => ZData <= X"00001fff";
when "10010" => ZData <= X"00000fff";
when "10011" => ZData <= X"000007ff";
when "10100" => ZData <= X"000003ff";
when "10101" => ZData <= X"000001ff";
when "10110" => ZData <= X"000000ff";
when "10111" => ZData <= X"0000007f";
when "11000" => ZData <= X"0000003f";
when "11001" => ZData <= X"0000001f";
when "11010" => ZData <= X"0000000f";
when "11011" => ZData <= X"00000007";
when "11100" => ZData <= X"00000003";
when "11101" => ZData <= X"00000001";
when "11110" => ZData <= X"00000000";
when "11111" => ZData <= X"00000000";
When others => ZData <= "--------------------------------";
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsm IS
PORT(
clk : IN std_logic;
reset : IN std_logic; -- Active low reset
start : IN std_logic;
cnt : IN std_logic_vector (4 DOWNTO 0);
init : OUT std_logic;
load : OUT std_logic;
done : OUT std_logic);
END fsm ;
architecture synthesis of fsm is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
begin
Process (clk,reset) -- Process to create current state variables
begin
if (reset='0') then -- Reset State
state <= s0;
elsif (rising_edge(clk)) then
state <= nextstate; -- Set Current state
end if;
end process;
process(state,start,cnt)
begin
case state is
when s0 => -- Step 1 load regs
if start='1' then nextstate <= s1;
else nextstate <= s0; -- Wait for start signal
end if;
when s1 => -- latch result register
if cnt="11111" then nextstate <= s2; -- done
else nextstate <= s1; -- wait
end if;
when s2 =>
if start='0' then nextstate <= s0;
else nextstate <= s2; -- Wait for start signal
end if;
when others => nextstate <= s0;
end case;
end process;
process(state)
begin
case state is
when s0 =>done <= '0'; init <= '1'; load <= '0';
when s1 =>done <= '0'; init <= '0'; load <= '1';
when s2 =>done <= '1'; init <= '0'; load <= '0';
when others => done <= '-'; init <= '-'; load <= '-';
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiftn is
port (ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end shiftn;
architecture synthesis of shiftn is
begin
process(n,ibus)
begin
case n is
when "00000" => obus <= ibus(31)&ibus(30 downto 0); -- ibus
when "00001" => obus <= ibus(31)&ibus(31)&ibus(30 downto 1);
when "00010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 2);
when "00011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 3);
when "00100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 4);
when "00101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 5);
when "00110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 6);
when "00111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 7);
when "01000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 8);
when "01001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 9);
when "01010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 10);
when "01011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 11);
when "01100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 12);
when "01101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 13);
when "01110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 14);
when "01111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 15);
when "10000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 16);
when "10001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 17);
when "10010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 18);
when "10011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 19);
when "10100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 20);
when "10101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 21);
when "10110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 22);
when "10111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 23);
when "11000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 24);
when "11001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 25);
when "11010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 26);
when "11011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 27);
when "11100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 28);
when "11101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 29);
when "11110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30);
when others => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31);
end case;
end process;
end synthesis;
| gpl-3.0 | 94d0cb8b40ace982a0b7ee3298ef8183 | 0.409376 | 4.300942 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/ASYNC_RGB_2_YUV.vhd | 1 | 7,731 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity ASYNC_RGB_2_YUV is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
write_en : in std_logic;
in_full : out std_logic;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0);
read_en : in std_logic;
out_empty : out std_logic;
Next_Empty : out std_logic
);
end ASYNC_RGB_2_YUV;
architecture rtl of ASYNC_RGB_2_YUV is
COMPONENT CUSTOM_FIFO
PORT(
rst : IN std_logic;
clk : IN std_logic;
flush : IN std_logic;
holdn : IN std_logic;
INPUT_1 : IN std_logic_vector(31 downto 0);
write_en : IN std_logic;
in_full : OUT std_logic;
OUTPUT_1 : OUT std_logic_vector(31 downto 0);
read_en : IN std_logic;
out_empty : OUT std_logic;
Next_Empty : OUT std_logic
);
END COMPONENT;
constant s_rgb_30 : UNSIGNED(24 downto 0) := "0010011001000101101000011";
constant s_rgb_59 : UNSIGNED(24 downto 0) := "0100101100100010110100001";
constant s_rgb_11 : UNSIGNED(24 downto 0) := "0000111010010111100011010";
constant s_rgb_17 : UNSIGNED(24 downto 0) := "0001010110011001010001011";
constant s_rgb_33 : UNSIGNED(24 downto 0) := "0010101001100110101110100";
constant s_rgb_50 : UNSIGNED(24 downto 0) := "0100000000000000000000000";
constant s_rgb_42 : UNSIGNED(24 downto 0) := "0011010110010111101000100";
constant s_rgb_08 : UNSIGNED(24 downto 0) := "0000101001101000010111011";
constant s_rgb_128 : UNSIGNED(31 downto 0) := "10000000000000000000000000000000"; -- TO_UNSIGNED(128, 32); --"10000000000000000000000000000000";
signal PIPE_START : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL INPUT_R : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_G : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_B : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_Y : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_U : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_V : STD_LOGIC_VECTOR(7 downto 0);
signal AFTER_FIFO : STD_LOGIC_VECTOR(31 downto 0);
signal READ_INP : STD_LOGIC;
signal INPUT_EMPTY : STD_LOGIC;
signal INPUT_nEMPTY : STD_LOGIC;
signal BEFORE_FIFO : STD_LOGIC_VECTOR(31 downto 0);
signal WRITE_OUTP : STD_LOGIC;
signal OUTPUT_FULL : STD_LOGIC;
signal START_COMPUTE : STD_LOGIC;
SIGNAL s_rgb_out_y : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cb : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cr : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL rgb_in_r_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
begin
inFifo: CUSTOM_FIFO PORT MAP (
rst => rst,
clk => clk,
flush => '0',
holdn => '0',
INPUT_1 => INPUT_1,
write_en => write_en,
in_full => in_full,
OUTPUT_1 => AFTER_FIFO,
read_en => READ_INP,
out_empty => INPUT_EMPTY,
Next_Empty => INPUT_nEMPTY
);
ouFIFO: CUSTOM_FIFO PORT MAP (
rst => rst,
clk => clk,
flush => '0',
holdn => '0',
INPUT_1 => BEFORE_FIFO,
write_en => WRITE_OUTP,
in_full => OUTPUT_FULL,
OUTPUT_1 => OUTPUT_1,
read_en => read_en,
out_empty => out_empty,
Next_Empty => Next_Empty
);
-- ON MAPPE LES E/S DU CIRCUIT SUR LES E/S DES FIFOS
INPUT_R <= AFTER_FIFO( 7 downto 0);
INPUT_G <= AFTER_FIFO(15 downto 8);
INPUT_B <= AFTER_FIFO(23 downto 16);
BEFORE_FIFO <= "00000000" & INPUT_V & INPUT_U & INPUT_Y;
WRITE_OUTP <= PIPE_START(2);
process(rst, clk)
begin
if rst = '0' then
--REPORT "RESET";
INPUT_Y <= (others => '0');
INPUT_U <= (others => '0');
INPUT_V <= (others => '0');
PIPE_START <= "0000";
START_COMPUTE <= '0';
READ_INP <= '0';
elsif clk'event and clk = '1' then
START_COMPUTE <= not INPUT_nEMPTY;
READ_INP <= not INPUT_nEMPTY; --START_COMPUTE;
PIPE_START <= PIPE_START(2 downto 0) & START_COMPUTE;
-- ON MULTIPLIE LES DONNEES ENTRANTES PAR LES CONSTANTES
-- CODEES EN VIRGULE FIXE
if START_COMPUTE = '1' then
--REPORT "RUNNING FIRST SLICE...";
--printmsg("(PGDC) ===> (001) DATA ARE (" & to_int_str(INPUT_B,6) & ", " & to_int_str(INPUT_G,6) & ", " & to_int_str(INPUT_R,6) & ")");
rgb_in_r_reg_Y <= s_rgb_30 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Y <= s_rgb_59 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Y <= s_rgb_11 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cb <= s_rgb_17 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cb <= s_rgb_33 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cb <= s_rgb_50 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cr <= s_rgb_50 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cr <= s_rgb_42 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cr <= s_rgb_08 * UNSIGNED(INPUT_B);
end if;
if PIPE_START(0) = '1' then
--REPORT "RUNNING SECOND SLICE...";
s_rgb_out_y <= rgb_in_r_reg_Y + (rgb_in_g_reg_Y + rgb_in_b_reg_Y);
s_rgb_out_cb <= (s_rgb_128 - rgb_in_r_reg_Cb) - (rgb_in_g_reg_Cb + rgb_in_b_reg_Cb);
s_rgb_out_cr <= (s_rgb_128 + rgb_in_r_reg_Cr) - (rgb_in_g_reg_Cr - rgb_in_b_reg_Cr);
end if;
if PIPE_START(1) = '1' then
--REPORT "RUNNING THIRD SLICE...";
if (s_rgb_out_y(23)='1') then
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24) + 1);
else
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24));
end if;
if (s_rgb_out_cb(23)='1') then
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24) + 1);
else
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24));
end if;
if (s_rgb_out_cr(23)='1') then
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24) + 1);
else
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24));
end if;
--printmsg("(PGDC) ===> (011) DATA Y = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_y (31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA U = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA V = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24)),6) & ")");
else
INPUT_Y <= INPUT_Y;
INPUT_U <= INPUT_U;
INPUT_V <= INPUT_V;
end if;
end if;
end process;
--process(INPUT_Y, INPUT_U, INPUT_V)
--BEGIN
-- printmsg("(PGDC) ===> (111) DATA ARE (" & to_int_str(INPUT_V,6) & ", " & to_int_str(INPUT_U,6) & ", " & to_int_str(INPUT_Y,6) & ")");
--END PROCESS;
end rtl;
| gpl-3.0 | 7b6254c96f2a934ee1d865b09bfd4a0e | 0.55077 | 2.925085 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_pkg.vhd | 1 | 6,033 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Font_TB_PKG;
PACKAGE BODY Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Font_TB_PKG;
| mit | bcc8cb2a9a1a3a6d0f816324fd606bac | 0.575501 | 4.413314 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/MODULUS_2x_32b.vhd | 1 | 3,336 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity MODULUS_2x_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture behav of MODULUS_2x_32b is
constant SIZE : INTEGER := 32;
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to SIZE;
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
BEGIN
process(rst, clk)
variable sready, snready : std_logic;
variable tbuf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable xx1 : std_logic;
variable xx2 : std_logic;
variable yy : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
OUTPUT_1 <= buf1;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
else
sm <= sm;
end if;
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
-- ON TRAITE LE PREMIER BIT DE L'ITERATION
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
else
tbuf := buf((2 * SIZE - 2) downto 0) & '0';
end if;
-- ON TRAITE LE SECOND BIT DE L'ITERATION
if tbuf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1 <= '0' & (tbuf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2 <= tbuf((SIZE - 2) downto 0) & '1';
else
buf <= tbuf((2 * SIZE - 2) downto 0) & '0';
end if;
-- EN FONCTION DE LA VALEUR DU COMPTEUR ON CHOISI NOTRE DESTIN
if sm /= 16 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if;
end if;
end process;
end behav;
| gpl-3.0 | 28388f27b7dd5099d5b593ca0ab8733c | 0.541966 | 3.021739 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_stim_gen.vhd | 1 | 14,805 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For Dual Port RAM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_DRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_DRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_DRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_TB_STIM_GEN IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
D : OUT STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0');
DPRA : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
WE : OUT STD_LOGIC := '0';
DATA_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
DATA_IN_B : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
CHECK_DATA : OUT STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0')
);
END Video_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Video_Memory_TB_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:=1;
CONSTANT DATA_PART_CNT_B: INTEGER:=1;
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ_REG_A : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_INT_A : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_INT_B : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 8;
CONSTANT READ_CNT_A : integer := 8;
CONSTANT WRITE_CNT_B : integer := 8;
CONSTANT READ_CNT_B : integer := 8;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
READ_ADDR_INT_B(11 DOWNTO 0) <= READ_ADDR_B(11 DOWNTO 0);
A <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A);
D <= IF_THEN_ELSE(DO_WRITE_A='1',D_INT_A,D_INT_B);
DPRA <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B);
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
DO_WRITE <= DO_WRITE_A OR DO_WRITE_B;
RD_GEN_INST_A:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_AGEN_INST_A:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
WR_DGEN_INST_A:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE_A,
DATA_OUT => D_INT_A
);
RD_AGEN_INST_B:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_AGEN_INST_B:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DGEN_INST_B:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_B,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE_B,
DATA_OUT => D_INT_B
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_A(0),
CLK => CLK,
RST => RST,
D => DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_A(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_B(0),
CLK => CLK,
RST => RST,
D => DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_B(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
WE <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | 984ce741a0c5689a5dcceb88ea0e4dee | 0.548801 | 3.205933 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/txt_util.vhd | 1 | 14,512 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| gpl-3.0 | 9fe33a07c5f190ad1dba04a0fcf79957 | 0.472988 | 3.818947 | false | false | false | false |
siam28/neppielight | dvid_in/serialiser_in.vhd | 2 | 4,703 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: input_serialiser
--
-- Description: A 5-bits per cycle SDR input serialiser
--
-- Maybe in the future the 'bitslip' funciton can be implemented.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity input_serialiser is
Port ( clk_fabric_x2 : in STD_LOGIC;
clk_input : in STD_LOGIC;
strobe : in STD_LOGIC;
ser_data : out STD_LOGIC_VECTOR (4 downto 0);
ser_input : in STD_LOGIC);
end input_serialiser;
architecture Behavioral of input_serialiser is
signal clk0, clk1, clkdiv : std_logic;
signal cascade : std_logic;
constant bitslip : std_logic := '0';
begin
clkdiv <= clk_fabric_x2;
clk0 <= clk_input;
clk1 <= '0';
ISERDES2_master : ISERDES2
generic map (
BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "MASTER" -- "NONE", "MASTER" or "SLAVE"
)
port map (
CFB0 => open, -- 1-bit output: Clock feed-through route output
CFB1 => open, -- 1-bit output: Clock feed-through route output
DFB => open, -- 1-bit output: Feed-through clock output
FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output
INCDEC => open, -- 1-bit output: Phase detector output
-- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
Q1 => ser_data(1),
Q2 => ser_data(2),
Q3 => ser_data(3),
Q4 => ser_data(4),
SHIFTOUT => cascade, -- 1-bit output: Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output: Output status of the phase detector
BITSLIP => bitslip , -- 1-bit input: Bitslip enable input
CE0 => '1', -- 1-bit input: Clock enable input
CLK0 => clk0, -- 1-bit input: I/O clock network input
CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input
CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input
D => ser_input, -- 1-bit input: Input data
IOCE => strobe, -- 1-bit input: Data strobe input
RST => '0', -- 1-bit input: Asynchronous reset input
SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O
);
ISERDES2_slave : ISERDES2
generic map (
BITSLIP_ENABLE => TRUE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "SLAVE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
CFB0 => open, -- 1-bit output: Clock feed-through route output
CFB1 => open, -- 1-bit output: Clock feed-through route output
DFB => open, -- 1-bit output: Feed-through clock output
FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output
INCDEC => open, -- 1-bit output: Phase detector output
-- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
Q1 => open,
Q2 => open,
Q3 => open,
Q4 => ser_data(0),
SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output: Output status of the phase detector
BITSLIP => bitslip, -- 1-bit input: Bitslip enable input
CE0 => '1', -- 1-bit input: Clock enable input
CLK0 => clk0, -- 1-bit input: I/O clock network input
CLK1 => clk1, -- 1-bit input: Secondary I/O clock network input
CLKDIV => clkdiv, -- 1-bit input: FPGA logic domain clock input
D => '0', -- 1-bit input: Input data
IOCE => '1', -- 1-bit input: Data strobe input
RST => '0', -- 1-bit input: Asynchronous reset input
SHIFTIN => cascade -- 1-bit input: Cascade input signal for master/slave I/O
);
end Behavioral;
| gpl-2.0 | 58ee4f4ed0f86057cb7496eabcb9b472 | 0.53519 | 3.848609 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_gpio/src/vvc_methods_pkg.vhd | 1 | 12,541 | --========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.gpio_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the GPIO VVC
--========================================================================================================================
constant C_VVC_NAME : string := "GPIO_VVC";
signal GPIO_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is GPIO_VVCT;
alias t_bfm_config is t_gpio_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_GPIO_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay;
cmd_queue_count_max : natural;
cmd_queue_count_threshold_severity : t_alert_level;
cmd_queue_count_threshold : natural;
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_gpio_bfm_config;
msg_id_panel : t_msg_id_panel;
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_GPIO_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_GPIO_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_GPIO_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
data => (others => '0'),
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_gpio_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_GPIO_VVC_CONFIG_DEFAULT);
shared variable shared_gpio_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_gpio_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure gpio_set(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_get(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_check(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_expect(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant timeout : in time := 1 us;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
procedure gpio_set(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_set";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & ", " & to_string(data, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, SET);
shared_vvc_cmd.operation := SET;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_get(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_get";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, GET);
shared_vvc_cmd.operation := GET;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_check(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_check";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & to_string(data_exp, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data_exp'length-1 downto 0) :=
normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.data_exp := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.operation := CHECK;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_expect(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant timeout : in time := 1 us;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_expect";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & to_string(data_exp, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data_exp'length-1 downto 0) :=
normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, EXPECT);
shared_vvc_cmd.data_exp := v_normalised_data;
shared_vvc_cmd.timeout := timeout;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVC, scope => scope);
end procedure;
end package body vvc_methods_pkg;
| mit | 3ad00c8552164731fe57e2eda7c1c650 | 0.566701 | 4.055951 | false | true | false | false |
chibby0ne/vhdl-book | Chapter9/exercise9_6_dir/exercise9_6.vhd | 1 | 1,506 | --!
--! @file: exercise9_6.vhd
--! @brief: function bcd_to_ssd
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package exercise9_6 is
function bcd_to_ssd(bcd : std_logic_vector) return std_logic_vector
end package exercise9_6;
------------------------------
package body exercise9_6 is
function bcd_to_ssd(bcd : std_logic_vector) return std_logic_vector is
variable bcd_uns: unsigned range 0 to (2**std_logic_vector'length)-1
variable ssd: std_logic_vector(6 downto 0);
begin
bcd_uns := unsigned(bcd);
-- check for bcd code = 4
assert (bcd'length = 4)
report "not bcd code in input!"
severity failure;
-- bcd to ssd conversion
case1: case bcd_uns is
when 0 => ssd := "0000001";
when 1 => ssd := "1001111";
when 2 => ssd := "0010010";
when 3 => ssd := "0000110";
when 4 => ssd := "1001100";
when 5 => ssd := "0100100";
when 6 => ssd := "0100000";
when 7 => ssd := "0001111";
when 8 => ssd := "0000000";
when 9 => ssd := "0000100";
when others => ssd := "0110000"; -- 'E' on SSD for Error
end case case1;
return ssd;
end function bcd_to_ssd;
end package body exercise9_6;
--------------------------------------
| gpl-3.0 | 3d1f0bb81df8fc00db408100725659b0 | 0.499336 | 4.026738 | false | false | false | false |
ryos36/polyphony-tutorial | Xorshift/xorshift16.vhdl | 1 | 2,076 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity xorshift16 is
port(
clk : in std_logic;
rst_n : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(3 downto 0)
);
end xorshift16;
architecture RTL of xorshift16 is
signal y: std_logic_vector(15 downto 0) := X"8ca2";
signal state: std_logic_vector(3 downto 0) := "0000";
begin
process(clk)
begin
if clk'event and clk = '1' then
if rst_n = '0' then
d_en_n <= '1';
state <= "0000";
else
case state is
when "0000" =>
if kick_n = '0' then
y <= y xor
(y((15 - 2) downto 0) & "00");
state <= "0001";
end if;
when "0001" =>
y <= y xor
("00000" & y(15 downto 5));
state <= "0011";
when "0011" =>
y <= y xor
(y((15 - 8) downto 0) & "00000000");
state <= "0010";
when "0010" =>
state <= "0110";
d_en_n <= '0';
data <= y(3 downto 0);
when "0110" =>
state <= "0111";
data <= y(7 downto 4);
when "0111" =>
state <= "0101";
data <= y(11 downto 8);
when "0101" =>
state <= "0100";
data <= y(15 downto 12);
when "0100" =>
d_en_n <= '1';
state <= "0000";
when others =>
null;
end case;
end if;
end if;
end process;
end RTL;
| mit | 8fd59c90260c771c07d45ffa8e7e0268 | 0.328998 | 4.603104 | false | false | false | false |
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