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1995parham/FPGA-Homework | HW-4/src/p9/vending-machine.vhd | 1 | 3,252 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: vending-machine.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vending_machine is
port(coin_in : in std_logic;
coin_in_1 : in std_logic;
coin_in_10 : in std_logic;
coin_in_100 : in std_logic;
buy_in : in std_logic;
price : in std_logic_vector(7 downto 0);
coin_return : out std_logic;
coin_return_1 : out std_logic_vector(7 downto 0);
coin_return_10 : out std_logic_vector(7 downto 0);
coin_return_100 : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
architecture rtl of vending_machine is
type state is (COIN_IN_S, COIN_RETURN_100_S, COIN_RETURN_10_S, COIN_RETURN_1_S);
signal current_state, next_state : state;
begin
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process (coin_in, buy_in, current_state)
variable coin_return_total : std_logic_vector(7 downto 0);
variable coin_return_100_var : std_logic_vector(7 downto 0);
variable coin_return_10_var : std_logic_vector(7 downto 0);
variable coin_return_1_var : std_logic_vector(7 downto 0);
variable coin_in_total : std_logic_vector(7 downto 0);
begin
case current_state is
when COIN_IN_S =>
if coin_in = '1' then
coin_return <= '0';
next_state <= COIN_IN_S;
if coin_in_1 = '1' and coin_in_10 = '0' and coin_in_100 = '0' then
coin_in_total := coin_in_total + "00000001";
elsif coin_in_1 = '0' and coin_in_10 = '1' and coin_in_100 = '0' then
coin_in_total := coin_in_total + "00001010";
elsif coin_in_1 = '0' and coin_in_10 = '0' and coin_in_100 = '1' then
coin_in_total := coin_in_total + "01100100";
end if;
end if;
if buy_in = '1' then
coin_return_total := coin_in_total - price;
coin_return_100_var := "00000000";
coin_return_10_var := "00000000";
coin_return_1_var := "00000000";
next_state <= COIN_RETURN_100_S;
end if;
when COIN_RETURN_100_S =>
if coin_return_total >= "01100100" then
coin_return_total := coin_return_total - "01100100";
coin_return_100_var := coin_return_100_var + "00000001";
next_state <= COIN_RETURN_100_S;
else
next_state <= COIN_RETURN_10_S;
end if;
when COIN_RETURN_10_S =>
if coin_return_total >= "00001010" then
coin_return_total := coin_return_total - "00001010";
coin_return_10_var := coin_return_10_var + "00000001";
next_state <= COIN_RETURN_10_S;
else
next_state <= COIN_RETURN_1_S;
end if;
when COIN_RETURN_1_S =>
if coin_return_total >= "00000001" then
coin_return_total := coin_return_total - "00000001";
coin_return_1_var := coin_return_1_var + "00000001";
next_state <= COIN_RETURN_1_S;
else
next_state <= COIN_IN_S;
coin_return <= '1';
coin_return_1 <= coin_return_1_var;
coin_return_10 <= coin_return_10_var;
coin_return_100 <= coin_return_100_var;
end if;
end case;
end process;
end architecture;
| gpl-3.0 | 91e8ba3d9fc0013b50e957e5c2738605 | 0.604244 | 2.900981 | false | false | false | false |
1995parham/FPGA-Homework | HW-3/src/p9/p9.vhd | 1 | 1,299 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity robot is
port (key1, key2, key3, clk : in std_logic);
end entity;
architecture rtl of robot is
type state is (stop, move_forward_slowly, move_forward_fast,
move_backward_fast, move_backward_slowly, turn_right,
turn_left);
signal current_state, next_state : state;
signal command : std_logic_vector (2 downto 0);
begin
command <= key1 & key2 & key3;
process (command)
begin
case command is
when "000" => next_state <= stop;
when "001" => next_state <= move_forward_slowly;
when "010" => next_state <= move_forward_fast;
when "011" => next_state <= move_backward_slowly;
when "100" => next_state <= move_backward_fast;
when "101" => next_state <= turn_right;
when "110" => next_state <= turn_left;
when "111" => next_state <= current_state;
when others => next_state <= stop;
end case;
end process;
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
end architecture;
| gpl-3.0 | 82b537be857aa41a80eb696886b67de3 | 0.580446 | 3.305344 | false | false | false | false |
lukehsiao/FPGA_Flappy_Bird | src/seven_segment_display.vhd | 1 | 2,463 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; --need to use for unsigned
entity seven_segment_display is
generic(COUNTER_BITS: natural := 15); --Indicates number of bits on segment counter to count up to (determines speed)
port(
clk: in std_logic;
data_in: in std_logic_vector(15 downto 0); --Data to display
dp_in: in std_logic_vector(3 downto 0); --Value of 4 decimal points
blank: in std_logic_vector(3 downto 0); --Tells which digits are blank
seg: out std_logic_vector(6 downto 0); --Segment control signals
dp: out std_logic; --Digit point control signal
an: out std_logic_vector(3 downto 0) --Segment anode control signals
);
end seven_segment_display;
architecture arch of seven_segment_display is
signal counter_value: std_logic_vector(COUNTER_BITS-1 downto 0) := (others=>'0'); --sets the initial value to 0
signal anode_select: std_logic_vector(1 downto 0);
signal decode: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
counter_value <= std_logic_vector(unsigned(counter_value) + 1);
end if;
end process;
anode_select <= counter_value(COUNTER_BITS-1 downto COUNTER_BITS-2);
with anode_select select
an <=
"111" & blank(0) when "00", --Determines when the display should be blank (1 is blank)
"11" & blank(1) & '1' when "01",
'1' & blank(2) & "11" when "10",
blank(3) & "111" when others;
with anode_select select --Determines which data set to send to the seven segment decoder
decode <=
data_in(3 downto 0) when "00",
data_in(7 downto 4) when "01",
data_in(11 downto 8) when "10",
data_in(15 downto 12) when others;
with anode_select select --Determines which decimal point to light up
dp <=
not dp_in(0) when "00",
not dp_in(1) when "01",
not dp_in(2) when "10",
not dp_in(3) when others;
with decode select --determines which parts to light up
seg <= "1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0010000" when "1001", -- 9
"0001000" when "1010", -- A
"0000011" when "1011", -- B
"1000110" when "1100", -- C
"0100001" when "1101", -- D
"0000110" when "1110", -- E
"0001110" when others; -- F
end arch; | mit | 71edb50ed99e09a75b6f6c9f8faa9a11 | 0.64596 | 2.963899 | false | false | false | false |
1995parham/FPGA-Homework | HW-4/src/p4/p4-2.vhd | 1 | 1,148 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 07-05-2016
-- Module Name: p4-2.vhd
--------------------------------------------------------------------------------
-- next state logic for a FSM
process (state, a, b, c, d, e)
begin
case state is
when IDLE =>
if a = '0' then
next_state <= INITIAL;
-- preventing from transparent latch creation
else
next_state <= IDLE;
end if;
when INITIAL =>
if a = '1' then
next_state <= ERROR_FLAG;
else
next_state <= SCANNING;
end if;
when SCANNING =>
if b = '1' then
next_state <= LOCKED;
elsif b = '0' then
if c = '0' then
next_state <= TIME_OUT;
else
next_state <= RELEASE;
end if;
-- following statement never happening ...
else
next_state <= CAPTURE;
end if;
when CAPTURE =>
next_state <= ...
when LOCKED =>
next_state <= ...
when TIME_OUT =>
next_state <= ...
when RELEASE =>
next_state <= ...
when ERROR_FLAG =>
next_state <= some_function(a, d, e);
end case;
end process;
| gpl-3.0 | a7cd40c0baa03ab03fc28757b48c3afe | 0.493031 | 3.406528 | false | false | false | false |
Project-Bonfire/EHA | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_with_checkers.vhd | 3 | 28,312 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
-- Signal(s) required for checker(s)
signal packet_drop_order_sig: std_logic;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
begin
packet_drop_order <= packet_drop_order_sig;
-- LBDR packet drop routing part checkers instantiation
LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers
generic map (cur_addr_rst => cur_addr_rst, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
dst_addr => dst_addr,
faulty => faulty,
Cx => Cx,
Rxy => Rxy,
packet_drop => packet_drop,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
grants => grants,
packet_drop_order => packet_drop_order_sig,
packet_drop_in => packet_drop_in,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => err_grants_onehot,
err_grants_mismatch => err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => err_packet_drop_order
);
-- LBDR packet drop Cx Reconfiguration module checkers instantiation
Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in,
Cx => Cx,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal
);
-- LBDR packet drop Rxy Reconfiguration checkers instantiation
Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers
port map (
ReConf_FF_out => ReConf_FF_out,
Rxy => Rxy,
Rxy_tmp => Rxy_tmp,
Reconfig_command => Reconfig_command,
flit_type => flit_type,
grants => grants,
empty => empty,
Rxy_reconf_PE => Rxy_reconf_PE,
Rxy_in => Rxy_in,
Rxy_tmp_in => Rxy_tmp_in,
ReConf_FF_in => ReConf_FF_in,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
Rxy_tmp <= (others => '0');
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Rxy_tmp <= Rxy_tmp_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty) begin
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_tmp_in <= Rxy_tmp;
Rxy_in <= Rxy_tmp;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig_command = '1'then
Rxy_tmp_in <= Rxy_reconf_PE;
ReConf_FF_in <= '1';
else
Rxy_tmp_in <= Rxy_tmp;
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
elsif Reconfig_command = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= Cx_reconf_PE;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, faulty) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= '0';
end if;
if faulty = '1' or (((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) = '0') and
((((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) = '0') and
((((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) = '0') and
((((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr)) then
packet_drop_in <= '1';
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order_sig <= packet_drop;
END; | gpl-3.0 | 110f9869449ce1e27f1c0b76aa2b6954 | 0.524513 | 3.343805 | false | true | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/ua_narrow.vhd | 1 | 18,160 | -------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer := 1; -- range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
| mit | 451ee6203cc1377604cd67e434c96043 | 0.49554 | 4.173753 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/xip_cross_clk_sync.vhd | 1 | 58,092 | -------------------------------------------------------------------------------
-- $Id: xip_cross_clk_sync.vhd
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Filename: xip_cross_clk_sync.vhd
-- Version: v3.0
-- Description: This is the CDC file for XIP mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_quad_spi.vhd
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Created second version of the core.
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity xip_cross_clk_sync is
generic (
C_S_AXI4_DATA_WIDTH : integer;
C_SPI_MEM_ADDR_BITS : integer;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESET : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
mst_modf_err_cdc_from_spi : in std_logic;
mst_modf_err_cdc_to_axi : out std_logic;
mst_modf_err_cdc_to_axi4 : out std_logic;
----------------------------
one_byte_xfer_cdc_from_axi : in std_logic;
one_byte_xfer_cdc_to_spi : out std_logic;
----------------------
two_byte_xfer_cdc_from_axi : in std_logic;
two_byte_xfer_cdc_to_spi : out std_logic;
----------------------
four_byte_xfer_cdc_from_axi : in std_logic;
four_byte_xfer_cdc_to_spi : out std_logic;
----------------------
Transmit_Addr_cdc_from_axi : in std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
Transmit_Addr_cdc_to_spi : out std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
----------------------
load_cmd_cdc_from_axi : in std_logic;
load_cmd_cdc_to_spi : out std_logic;
--------------------------
CPOL_cdc_from_axi : in std_logic;
CPOL_cdc_to_spi : out std_logic;
--------------------------
CPHA_cdc_from_axi : in std_logic;
CPHA_cdc_to_spi : out std_logic;
--------------------------
SS_cdc_from_axi : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_cdc_to_spi : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
--------------------------
type_of_burst_cdc_from_axi : in std_logic;-- _vector(1 downto 0);
type_of_burst_cdc_to_spi : out std_logic;-- _vector(1 downto 0);
--------------------------
axi_length_cdc_from_axi : in std_logic_vector(7 downto 0);
axi_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
dtr_length_cdc_from_axi : in std_logic_vector(7 downto 0);
dtr_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
load_axi_data_cdc_from_axi : in std_logic;
load_axi_data_cdc_to_spi : out std_logic;
------------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
Rx_FIFO_Full_cdc_to_axi4 : out std_logic;
------------------------------
wb_hpm_done_cdc_from_spi : in std_logic;
wb_hpm_done_cdc_to_axi : out std_logic
);
end entity xip_cross_clk_sync;
-------------------------------------------------------------------------------
architecture imp of xip_cross_clk_sync is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
signal size_length_cdc_to_spi_d1 : std_logic_vector(1 downto 0);
signal size_length_cdc_to_spi_d2 : std_logic_vector(1 downto 0);
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2 : std_logic;
signal spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal byte_xfer_cdc_from_axi_d1 : std_logic;
signal byte_xfer_cdc_from_axi_d2 : std_logic;
signal hw_xfer_cdc_from_axi_d1 : std_logic;
signal hw_xfer_cdc_from_axi_d2 : std_logic;
signal word_xfer_cdc_from_axi_d1 : std_logic;
signal word_xfer_cdc_from_axi_d2 : std_logic;
signal SS_cdc_from_spi_d1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_cdc_from_spi_d2 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal mst_modf_err_d1 : std_logic;
signal mst_modf_err_d2 : std_logic;
signal mst_modf_err_d3 : std_logic;
signal mst_modf_err_d4 : std_logic;
signal dtr_length_cdc_from_axi_d1 : std_logic_vector(7 downto 0);
signal dtr_length_cdc_from_axi_d2 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d1 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d2 : std_logic_vector(7 downto 0);
signal CPOL_cdc_to_spi_d1 : std_logic;
signal CPOL_cdc_to_spi_d2 : std_logic;
signal CPHA_cdc_to_spi_d1 : std_logic;
signal CPHA_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d1 : std_logic;
signal load_axi_data_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d3 : std_logic;
signal Transmit_Addr_cdc_from_axi_d1 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal Transmit_Addr_cdc_from_axi_d2 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal type_of_burst_cdc_to_spi_d1 : std_logic;-- _vector(1 downto 0);
signal type_of_burst_cdc_to_spi_d2 : std_logic;-- _vector(1 downto 0);
signal load_cmd_cdc_from_axi_d1 : std_logic;
signal load_cmd_cdc_from_axi_d2 : std_logic;
signal load_cmd_cdc_from_axi_d3 : std_logic;
signal load_cmd_cdc_from_axi_int_2 : std_logic;
signal rx_fifo_full_d1 : std_logic;
signal rx_fifo_full_d2 : std_logic;
signal rx_fifo_full_d3 : std_logic;
signal rx_fifo_full_d4 : std_logic;
signal ld_axi_data_cdc_from_axi_int_2 : std_logic;
signal wb_hpm_done_cdc_from_spi_d1 : std_logic;
signal wb_hpm_done_cdc_from_spi_d2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of XFER_DONE_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of BYTE_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of HW_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of WORD_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of TYP_OF_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_AXI_DATA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_CMD_SYNC_AXI2SPI : label is "TRUE";
-- -- attribute ASYNC_REG of TRANSMIT_DATA_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of CPOL_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of CPHA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of WB_HPM_DONE_SYNC_SPI2AXI : label is "TRUE";
attribute KEEP : string;
attribute KEEP of SS_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d3 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of type_of_burst_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of rx_fifo_full_d2 : signal is "TRUE";
attribute KEEP of CPHA_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of CPOL_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of Transmit_Addr_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d3 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of word_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of hw_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of byte_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d4 : signal is "TRUE";
attribute KEEP of spiXfer_done_d2 : signal is "TRUE";
attribute KEEP of spiXfer_done_d3 : signal is "TRUE";
attribute KEEP of axi_length_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of dtr_length_cdc_from_axi_d2 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE = 0) generate
-----
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => S_AXI4_ACLK,
D => spiXfer_done_cdc_from_spi_int_2,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => S_AXI4_ACLK,
D => spiXfer_done_d1,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => S_AXI4_ACLK,
D => spiXfer_done_d2,
R => S_AXI4_ARESET
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d1,
C => S_AXI_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI_ARESETN
);
MST_MODF_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d2,
C => S_AXI_ACLK,
D => mst_modf_err_d1,
R => S_AXI_ARESETN
);
mst_modf_err_cdc_to_axi <= mst_modf_err_d2;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d3,
C => S_AXI4_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI4_ARESET
);
MST_MODF_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d4,
C => S_AXI4_ACLK,
D => mst_modf_err_d3,
R => S_AXI4_ARESET
);
mst_modf_err_cdc_to_axi4 <= mst_modf_err_d4;
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => one_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
BYTE_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => byte_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
one_byte_xfer_cdc_to_spi <= byte_xfer_cdc_from_axi_d2;
------------------------------------------------
HW_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => two_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
HW_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => hw_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
two_byte_xfer_cdc_to_spi <= hw_xfer_cdc_from_axi_d2;
------------------------------------------------
WORD_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => four_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
WORD_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => word_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
four_byte_xfer_cdc_to_spi <= word_xfer_cdc_from_axi_d2;
------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
-------------------------------------
-- from AXI4 to SPI
LD_CMD_SYNC_AXI2SPI: component FDR
port map (
Q => load_cmd_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_1: component FDR
port map (
Q => load_cmd_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_2: component FDR
port map (
Q => load_cmd_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
--------------------------------------------------------------------------
-- from AXI4 to SPI
TRANS_ADDR_SYNC_GEN: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TRANS_ADDR_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TRANS_ADDR_SYNC_GEN;
-- Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2; -- 4/19/2013
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d1; -- 4/19/2013
------------------------------------------------
-- from AXI4 Lite to SPI
CPOL_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPOL_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPOL_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPOL_cdc_to_spi <= CPOL_cdc_to_spi_d2;
------------------------------------------------
-- from AXI4 Lite to SPI
CPHA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPHA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPHA_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPHA_cdc_to_spi <= CPHA_cdc_to_spi_d2;
------------------------------------------------
LD_AXI_DATA_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
-------------------------------------
LD_AXI_DATA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => ld_axi_data_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_2: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d3,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
------------------------------------------------
SS_SYNC_AXI_SPI_GEN: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
SS_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d1(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SS_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d2(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SS_SYNC_AXI_SPI_GEN;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
TYP_OF_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
--end generate TYP_OF_XFER_GEN;
------------------------------
type_of_burst_cdc_to_spi <= type_of_burst_cdc_to_spi_d2;
------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
AXI_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d1(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
AXI_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d2(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_to_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
DTR_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
-- from SPI to AXI Lite
Rx_FIFO_Full_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d1,
C => S_AXI_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d2,
C => S_AXI_ACLK,
D => rx_fifo_full_d1,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_cdc_to_axi <= rx_fifo_full_d2;
-------------------------------------------------------------------------------
-- from SPI to AXI4
Rx_FIFO_Full_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d3,
C => S_AXI4_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d4,
C => S_AXI4_ACLK,
D => rx_fifo_full_d3,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_cdc_to_axi4 <= rx_fifo_full_d4;
-------------------------------------------------------------------------------
-- from SPI to AXI4
WB_HPM_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d1,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi,
R => S_AXI4_ARESET
);
WB_HPM_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d2,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi_d1,
R => S_AXI4_ARESET
);
wb_hpm_done_cdc_to_axi <= wb_hpm_done_cdc_from_spi_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (LOGIC_CHANGE = 1) generate
-------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
--spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor spiXfer_done_cdc_from_spi_int_2;
--spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
spiXfer_done_d3 <= '0';
else
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI_ARESETN ,
scndry_out => mst_modf_err_cdc_to_axi
);
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => mst_modf_err_cdc_to_axi4
);
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => one_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => one_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
HW_XFER_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => two_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => two_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
WORD_XFER_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => four_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => four_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
--load_cmd_cdc_from_axi_d1 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
--load_cmd_cdc_from_axi_d1 <= load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH_CDC;
LD_CMD_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => load_cmd_cdc_from_axi_int_2,--load_cmd_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_cmd_cdc_from_axi_d2
);
LD_CMD_cdc_from_AXI_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_cmd_cdc_from_axi_d3 <= '0';
else
load_cmd_cdc_from_axi_d3 <= load_cmd_cdc_from_axi_d2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
-------------------------------------------------------------------------------
TRANS_ADDR_SYNC_GEN_CDC: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => Transmit_Addr_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => Transmit_Addr_cdc_from_axi_d2(i)
);
end generate TRANS_ADDR_SYNC_GEN_CDC;
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2;
-------------------------------------------------------------------------------
CPOL_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPOL_cdc_to_spi
);
-------------------------------------------------------------------------------
CPHA_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPHA_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_AXI_DATA_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
--load_axi_data_cdc_to_spi_d1 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
-- load_axi_data_cdc_to_spi_d1 <= ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH_CDC;
LD_AXI_DATA_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => ld_axi_data_cdc_from_axi_int_2,--load_axi_data_cdc_to_spi_d1 ,
prmry_vect_in => (others => '0' ),
scndry_aclk => EXT_SPI_CLK ,
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_axi_data_cdc_to_spi_d2
);
LD_AXI_DATA_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_axi_data_cdc_to_spi_d3 <= '0';
else
load_axi_data_cdc_to_spi_d3 <= load_axi_data_cdc_to_spi_d2 ;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
SS_SYNC_AXI_SPI_GEN_CDC: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
SS_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => SS_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
scndry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => (others => '0' ),
scndry_out => SS_cdc_from_spi_d2(i)
);
end generate SS_SYNC_AXI_SPI_GEN_CDC;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => type_of_burst_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => type_of_burst_cdc_to_spi
);
---------------------------------------------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-------------
AXI_LEN_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => axi_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => axi_length_cdc_to_spi_d2(i)
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN_CDC;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => dtr_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => dtr_length_cdc_from_axi_d2(i)
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN_CDC;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI_ACLK ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI4_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => Rx_FIFO_Full_cdc_to_axi4
);
-------------------------------------------------------------------------------
WB_HPM_DONE_SYNC_SPI2AXI_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => wb_hpm_done_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => wb_hpm_done_cdc_to_axi
);
-------------------------------------------------------------------------------
byte_xfer_cdc_from_axi_d2 <= '0' ;
hw_xfer_cdc_from_axi_d2 <= '0' ;
word_xfer_cdc_from_axi_d2 <= '0' ;
mst_modf_err_d2 <= '0' ;
mst_modf_err_d4 <= '0' ;
CPOL_cdc_to_spi_d2 <= '0' ;
CPHA_cdc_to_spi_d2 <= '0' ;
type_of_burst_cdc_to_spi_d2 <= '0' ;
rx_fifo_full_d2 <= '0' ;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
---------------------
| mit | 878cda5a6bbdaa0ab06e01ad02bf046f | 0.41961 | 3.880043 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/correct_one_bit_64.vhd | 7 | 8,400 | -------------------------------------------------------------------------------
-- correct_one_bit_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit_64.vhd
--
-- Description: Identifies single bit to correct in 64-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit_64 is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 7));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 7);
DCorr : out std_logic);
end entity Correct_One_Bit_64;
architecture IMP of Correct_One_Bit_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 7)) return natural is
begin -- function find_one
for I in 0 to 7 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 6);
signal lut_corr_val : std_logic_vector(0 to 6);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 7);
lut_corr_val <= Correct_Value(1 to 7);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 6);
lut_corr_val <= Correct_Value(0 to 6);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| mit | 8bc06bf5d7c27280cff29b5b9b7d99eb | 0.485595 | 4.416404 | false | false | false | false |
lukehsiao/FPGA_Flappy_Bird | src/vga_timing.vhd | 1 | 2,111 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_timing is
port(
clk, rst: in std_logic;
HS, VS: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0);
last_column, last_row, blank: out std_logic
);
end vga_timing;
architecture arch of vga_timing is
signal pixel_en: std_logic;
signal horizontal_pixel_counter: unsigned(9 downto 0); --to count to 800
signal horizontal_pixel_counter_next: unsigned(9 downto 0);
signal vertical_pixel_counter: unsigned(9 downto 0); --to count to 521
signal vertical_pixel_counter_next: unsigned(9 downto 0);
begin
process(clk, rst)
begin
if (rst='1') then
pixel_en <= '0';
horizontal_pixel_counter <= (others=>'0');
vertical_pixel_counter <= (others=>'0');
elsif (clk'event and clk='1') then
pixel_en <= not pixel_en;
horizontal_pixel_counter <= horizontal_pixel_counter_next;
vertical_pixel_counter <= vertical_pixel_counter_next;
end if;
end process;
horizontal_pixel_counter_next <= (others=>'0') when (horizontal_pixel_counter = 799 and pixel_en='1') else --0 is first pixel 639 is last pixel
horizontal_pixel_counter + 1 when pixel_en='1' else
horizontal_pixel_counter;
vertical_pixel_counter_next <= (others=>'0') when (vertical_pixel_counter = 520 and pixel_en='1' and horizontal_pixel_counter = 799) else --0 is first row 479 is last row
vertical_pixel_counter + 1 when (pixel_en='1' and horizontal_pixel_counter = 799) else
vertical_pixel_counter;
HS <= '0' when (horizontal_pixel_counter > 639+16 and horizontal_pixel_counter < 800-48) else '1';
VS <= '0' when (vertical_pixel_counter > 479+10 and vertical_pixel_counter < 521-29) else '1';
pixel_x <= std_logic_vector(horizontal_pixel_counter);
pixel_y <= std_logic_vector(vertical_pixel_counter);
last_column <= '1' when horizontal_pixel_counter = 639 else '0';
last_row <= '1' when vertical_pixel_counter = 479 else '0';
blank <= '1' when (horizontal_pixel_counter >= 640 or vertical_pixel_counter >= 480) else '0';
end arch; | mit | 044b12d6e6c198342d642215b7c5ab8f | 0.678825 | 3.21309 | false | false | false | false |
sorgelig/SAMCoupe_MIST | sid/wave_map.vhd | 6 | 7,491 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wave_map is
generic (
g_num_voices : integer := 8; -- 8 or 16, clock should then be 8 or 16 MHz, too!
g_sample_bits : integer := 8 );
port (
clock : in std_logic;
reset : in std_logic;
osc_val : in unsigned(23 downto 0);
carry_20 : in std_logic;
msb_other: in std_logic := '0';
ring_mod : in std_logic := '0';
test : in std_logic := '0';
voice_i : in unsigned(3 downto 0);
comb_mode: in std_logic;
enable_i : in std_logic;
wave_sel : in std_logic_vector(3 downto 0);
sq_width : in unsigned(11 downto 0);
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
wave_out : out unsigned(g_sample_bits-1 downto 0) );
end wave_map;
architecture Gideon of wave_map is
type noise_array_t is array (natural range <>) of unsigned(22 downto 0);
signal noise_reg : noise_array_t(0 to g_num_voices-1) := (others => (0 => '1', others => '0'));
type voice_array_t is array (natural range <>) of unsigned(g_sample_bits-1 downto 0);
signal voice_reg : voice_array_t(0 to g_num_voices-1) := (others => (others => '0'));
type t_byte_array is array(natural range <>) of unsigned(7 downto 0);
constant c_wave_TP : t_byte_array(0 to 255) := (
16#FF# => X"FF", 16#F7# => X"F7", 16#EF# => X"EF", 16#E7# => X"E0",
16#FE# => X"FE", 16#F6# => X"F0", 16#EE# => X"E0", 16#E6# => X"00",
16#FD# => X"FD", 16#F5# => X"FD", 16#ED# => X"E0", 16#E5# => X"00",
16#FC# => X"F8", 16#F4# => X"80", 16#EC# => X"00", 16#E4# => X"00",
16#FB# => X"FB", 16#F3# => X"F0", 16#EB# => X"E0", 16#E3# => X"00",
16#FA# => X"F8", 16#F2# => X"08", 16#EA# => X"00", 16#E2# => X"00",
16#F9# => X"F0", 16#F1# => X"00", 16#E9# => X"00", 16#E1# => X"00",
16#F8# => X"80", 16#F0# => X"00", 16#E8# => X"00", 16#E0# => X"00",
16#DF# => X"DF", 16#DE# => X"D0", 16#DD# => X"C0", 16#DB# => X"C0",
16#D7# => X"C0", 16#CF# => X"C0", 16#BF# => X"BF", 16#BE# => X"B0",
16#BD# => X"A0", 16#B9# => X"80", 16#B7# => X"80", 16#AF# => X"80",
16#7F# => X"7F", 16#7E# => X"70", 16#7D# => X"70", 16#7B# => X"60",
16#77# => X"40", others => X"00" );
constant c_wave_TS : t_byte_array(0 to 255) := (
16#7F# => X"1E", 16#FE# => X"18", 16#FF# => X"3E", others => X"00" );
begin
process(clock)
variable noise_tmp : unsigned(22 downto 0);
variable voice_tmp : unsigned(g_sample_bits-1 downto 0);
variable triangle : unsigned(g_sample_bits-1 downto 0);
variable square : unsigned(g_sample_bits-1 downto 0);
variable sawtooth : unsigned(g_sample_bits-1 downto 0);
variable out_tmp : unsigned(g_sample_bits-1 downto 0);
variable new_bit : std_logic;
begin
if rising_edge(clock) then
-- take top of list
voice_tmp := voice_reg(0);
noise_tmp := noise_reg(0);
if reset='1' or test='1' then
noise_tmp := (others => '1'); -- seed not equal to zero
elsif carry_20='1' then
new_bit := noise_tmp(22) xor noise_tmp(21) xor noise_tmp(20) xor noise_tmp(15);
noise_tmp := noise_tmp(21 downto 0) & new_bit;
end if;
if osc_val(23)='1' then
triangle := not osc_val(22 downto 23-g_sample_bits);
else
triangle := osc_val(22 downto 23-g_sample_bits);
end if;
if ring_mod='1' and msb_other='0' then
triangle := not triangle;
end if;
sawtooth := osc_val(23 downto 24-g_sample_bits);
if osc_val(23 downto 12) < sq_width then
square := (others => '0');
else
square := (others => '1');
end if;
out_tmp := (others => '0');
case wave_sel is
when X"0" =>
out_tmp := voice_tmp;
when X"1" =>
out_tmp := triangle;
when X"2" =>
out_tmp := sawtooth;
when X"3" =>
if comb_mode='0' then
out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
c_wave_TS(to_integer(osc_val(23 downto 23-g_sample_bits)));
else -- 8580
out_tmp := triangle and sawtooth;
end if;
when X"4" =>
out_tmp := square;
when X"5" => -- combined triangle and square
if comb_mode='0' then
if square(0)='1' then
out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
c_wave_TP(to_integer(triangle(g_sample_bits-1 downto g_sample_bits-8)));
end if;
else -- 8580
out_tmp := triangle and square;
end if;
when X"6" => -- combined saw and pulse
if comb_mode='1' then
out_tmp := sawtooth and square;
end if;
when X"7" => -- combined triangle, saw and pulse
if comb_mode='1' then
out_tmp := triangle and sawtooth and square;
end if;
when X"8" =>
out_tmp(g_sample_bits-1) := noise_tmp(22); -- unsure.. 21?
out_tmp(g_sample_bits-2) := noise_tmp(20);
out_tmp(g_sample_bits-3) := noise_tmp(16);
out_tmp(g_sample_bits-4) := noise_tmp(13);
out_tmp(g_sample_bits-5) := noise_tmp(11);
out_tmp(g_sample_bits-6) := noise_tmp(7);
out_tmp(g_sample_bits-7) := noise_tmp(4);
out_tmp(g_sample_bits-8) := noise_tmp(2);
-- when X"9"|X"A"|X"B"|X"C"|X"D"|X"E"|X"F" =>
-- out_tmp := noise_tmp(20 downto 21-g_sample_bits);
-- noise_tmp := (others => '0');
when others =>
null;
end case;
if enable_i='1' then
noise_reg(g_num_voices-1) <= noise_tmp;
noise_reg(0 to g_num_voices-2) <= noise_reg(1 to g_num_voices-1);
voice_reg(g_num_voices-1) <= out_tmp;
voice_reg(0 to g_num_voices-2) <= voice_reg(1 to g_num_voices-1);
end if;
--out_tmp(out_tmp'high) := not out_tmp(out_tmp'high);
wave_out <= unsigned(out_tmp);
voice_o <= voice_i;
enable_o <= enable_i;
end if;
end process;
end Gideon;
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`protect end_protected
| gpl-3.0 | 543bded0206f54d073068e1ec751a159 | 0.934101 | 1.913019 | false | false | false | false |
6769/VHDL | Lab_4/Part2/__report_code.vhd | 1 | 10,464 |
--------------------------------------------------------------
------------------------------------------------------------
-- clock_signal_per_second.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end entity clock_signal_per_second;
architecture behavior of clock_signal_per_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
constant Terminator:integer:=25000000;--25*1000*1000
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal<Terminator then counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second_output<=not second_output;
end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- H24_Min60_Sec60.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60 is
port(Clk,Ldn:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60;
architecture Behavior of H24_Min60_Sec60 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
begin
Qout<=Q;
process(Clk,Ldn,Din)
begin
if(Ldn='0') then min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
elsif(Clk'event and Clk='1') then
if(second_count=59) then second_count<=0;
if(min_count=59) then min_count<=0;
if(hour_count=23) then hour_count<=0;
else hour_count<=hour_count+1;
end if;
--carry_from_min<='1';
else min_count<=min_count+1;
end if;
--carry_from_second<='1';
else second_count<=second_count+1;
end if;
end if;
end process;
Second_low<=to_unsigned(second_count mod 10,4);
Second_hig<=to_unsigned(second_count/10,4);
Min_low<=to_unsigned(min_count mod 10,4);
Min_hig<=to_unsigned(min_count/10,4);
Hour_low<=to_unsigned(hour_count mod 10,4);
Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- H24_Min60_Sec60_v2.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
-- signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
-- signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
constant CLs:unsigned(3 downto 0):="0000";
begin
Qout<=Q;
process(Clk,Ldn,Reset)
begin
if(Reset='0') then --min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
-- Min_low <=Din(4 downto 1);
-- Min_hig <=Din(8 downto 5);
-- Hour_low<=Din(12 downto 9);
-- Hour_hig<=Din(16 downto 13);
Q<=(others=>'0');
elsif(Ldn='0' and Reset='1') then Q(23 downto 8)<=Din;
elsif(Clk'event and Clk='1') then
if(Second_low=9) then Second_low<=CLs;
if(Second_hig=5) then Second_hig<=CLs;
if(Min_low=9) then Min_low<=CLs;
if(Min_hig=5) then Min_hig<=CLs;
if(Hour_hig<2)then
if(Hour_low=9) then Hour_low<=CLs;Hour_hig<=Hour_hig+1;
else Hour_low<=Hour_low+1;
end if;
else --Hour_hig==2
if(Hour_low=3) then Hour_low<=CLs;Hour_hig<=CLs;
else Hour_low<=Hour_low+1;
end if;
end if;
else Min_hig<=Min_hig+1;
end if;
else Min_low<=Min_low+1;
end if;
else Second_hig<=Second_hig+1;
end if;
else Second_low<=Second_low+1;
end if;
-------------------------------------------old design,too much latchs...--------------------------
-- if(second_count=59) then second_count<=0;
-- if(min_count=59) then min_count<=0;
-- if(hour_count=23) then hour_count<=0;
-- else hour_count<=hour_count+1;
-- end if;
-- --carry_from_min<='1';
-- else min_count<=min_count+1;
-- end if;
-- --carry_from_second<='1';
-- else second_count<=second_count+1;
-- end if;
end if;
end process;
-- Second_low<=to_unsigned(second_count mod 10,4);
-- Second_hig<=to_unsigned(second_count/10,4);
-- Min_low<=to_unsigned(min_count mod 10,4);
-- Min_hig<=to_unsigned(min_count/10,4);
-- Hour_low<=to_unsigned(hour_count mod 10,4);
-- Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Segment7Decoder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library IEEE;
use ieee.numeric_bit.all;
entity Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral;
--------------------------------------------------------------
------------------------------------------------------------
-- View.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity View is
port(Clk_original,Reset,Ldn:in bit;
Din:in unsigned(15 downto 0);
hex0,hex1,hex2,hex3,hex4,hex5:out unsigned(7 downto 0));
end entity View;
architecture Behave of View is
component clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end component;
component Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end component;
component H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end component;
signal mid_second:bit;
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
begin
hex0(0)<='1';
hex1(0)<='1';
hex2(0)<='1';
hex3(0)<='1';
hex4(0)<='1';
hex5(0)<='1';
High50Mhz:clock_signal_per_second port map(Clk_original,mid_second);
Core:H24_Min60_Sec60_v2 port map(mid_second,Ldn,Reset,Din,Q);
Hex0_display:Segment7Decoder port map(Second_low,hex0(7 downto 1));
Hex1_display:Segment7Decoder port map(Second_hig,hex1(7 downto 1));
Hex2_display:Segment7Decoder port map(Min_low, hex2(7 downto 1));
Hex3_display:Segment7Decoder port map(Min_hig,hex3(7 downto 1));
Hex4_display:Segment7Decoder port map(Hour_low,hex4(7 downto 1));
Hex5_display:Segment7Decoder port map(Hour_hig,hex5(7 downto 1));
end architecture Behave;
| gpl-2.0 | a086ec866cf84a53a99958c8fab65a54 | 0.509461 | 3.747851 | false | false | false | false |
6769/VHDL | Lab_4/Part2/H24_Min60_Sec60_v2.vhd | 2 | 3,374 | library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
-- signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
-- signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
constant CLs:unsigned(3 downto 0):="0000";
begin
Qout<=Q;
process(Clk,Ldn,Reset)
begin
if(Reset='0') then --min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
-- Min_low <=Din(4 downto 1);
-- Min_hig <=Din(8 downto 5);
-- Hour_low<=Din(12 downto 9);
-- Hour_hig<=Din(16 downto 13);
Q<=(others=>'0');
elsif(Ldn='0' and Reset='1') then Q(23 downto 8)<=Din;
elsif(Clk'event and Clk='1') then
if(Second_low=9) then Second_low<=CLs;
if(Second_hig=5) then Second_hig<=CLs;
if(Min_low=9) then Min_low<=CLs;
if(Min_hig=5) then Min_hig<=CLs;
if(Hour_hig<2)then
if(Hour_low=9) then Hour_low<=CLs;Hour_hig<=Hour_hig+1;
else Hour_low<=Hour_low+1;
end if;
else --Hour_hig==2
if(Hour_low=3) then Hour_low<=CLs;Hour_hig<=CLs;
else Hour_low<=Hour_low+1;
end if;
end if;
else Min_hig<=Min_hig+1;
end if;
else Min_low<=Min_low+1;
end if;
else Second_hig<=Second_hig+1;
end if;
else Second_low<=Second_low+1;
end if;
-------------------------------------------old design,too much latchs...--------------------------
-- if(second_count=59) then second_count<=0;
-- if(min_count=59) then min_count<=0;
-- if(hour_count=23) then hour_count<=0;
-- else hour_count<=hour_count+1;
-- end if;
-- --carry_from_min<='1';
-- else min_count<=min_count+1;
-- end if;
-- --carry_from_second<='1';
-- else second_count<=second_count+1;
-- end if;
end if;
end process;
-- Second_low<=to_unsigned(second_count mod 10,4);
-- Second_hig<=to_unsigned(second_count/10,4);
-- Min_low<=to_unsigned(min_count mod 10,4);
-- Min_hig<=to_unsigned(min_count/10,4);
-- Hour_low<=to_unsigned(hour_count mod 10,4);
-- Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior; | gpl-2.0 | 64888c03acff615de6d23810b55d906f | 0.49259 | 3.608556 | false | false | false | false |
6769/VHDL | Lab_0/light.vhd | 1 | 341 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY light IS
PORT ( x1, x2 : IN STD_LOGIC ;
f: OUT STD_LOGIC ) ;
END light ;
ARCHITECTURE LogicFunction OF light IS
signal tmp:std_logic :='0';
BEGIN
f <= (x1 AND NOT x2) OR (NOT x1 AND x2);
--process(x1)
--begin
--g<=x1;
--tmp<= x1 or x2;
--h<=tmp;
--end process;
END LogicFunction ;
| gpl-2.0 | ef854004b37a551481a473b6078158b6 | 0.645161 | 2.544776 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/rom/rom.vhd | 1 | 24,764 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16592)
`protect data_block
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`protect end_protected
| mit | 5384300ddc96432ca50d7e7bc0c353a3 | 0.942861 | 1.864478 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/coregen_comp_defs.vhd | 1 | 13,913 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_1
-- Component declaration for blk_mem_gen_v8_1 pulled from the blk_mem_gen_v8_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_1
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_1
END coregen_comp_defs;
| mit | 89ecb9ca081e71b2df975aad7b9936e6 | 0.426867 | 4.512812 | false | false | false | false |
gregani/la16fw | test_sample.vhd | 1 | 4,347 | --
-- This file is part of the lafw16 project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_sample is
end test_sample;
architecture behavior of test_sample is
-- component declaration for the unit under test (uut)
component sample
port(
sample_run : in std_logic;
sample_clk : in std_logic;
sample_rate_divisor : in std_logic_vector(7 downto 0);
channel_select : in std_logic_vector(15 downto 0);
logic_data : in std_logic_vector(15 downto 0);
fifo_reset : out std_logic;
fifo_data : out std_logic_vector(15 downto 0);
fifo_write : out std_logic;
fifo_full : in std_logic;
fifo_almost_full : in std_logic
);
end component;
--Inputs
signal sample_run : std_logic := '0';
signal sample_clk : std_logic := '0';
signal sample_rate_divisor : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(1, 8));
signal channel_select : std_logic_vector(15 downto 0) := (others => '1');
signal logic_data : std_logic_vector(15 downto 0) := "0101010101010101";
signal fifo_full : std_logic := '1';
signal fifo_almost_full : std_logic := '1';
--Outputs
signal fifo_reset : std_logic;
signal fifo_data : std_logic_vector(15 downto 0);
signal fifo_write : std_logic;
-- Clock period definitions
constant sample_clk_period : time := 10 ns;
signal do_count : std_logic := '0';
signal count2 : unsigned(7 downto 0) := (others=>'0');
signal count : unsigned(15 downto 0) := (others=>'0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sample PORT MAP (
sample_run => sample_run,
sample_clk => sample_clk,
sample_rate_divisor => sample_rate_divisor,
channel_select => channel_select,
logic_data => logic_data,
fifo_reset => fifo_reset,
fifo_data => fifo_data,
fifo_write => fifo_write,
fifo_full => fifo_full,
fifo_almost_full => fifo_almost_full
);
-- Clock process definitions
sample_clk_process :process
begin
if (do_count = '1') then
count2 <= count2 - 1;
if (count2 = to_unsigned(0, count2'length)) then
count2 <= unsigned(sample_rate_divisor);
count <= count + 1;
for i in 0 to 15
loop
logic_data(i) <= to_unsigned(i + 1, 8)(to_integer(7 - count(2 downto 0)));
if (count(2 downto 0) = to_unsigned(0, count'length)) then
logic_data(i) <= count(4);
end if;
end loop;
end if;
end if;
sample_clk <= '0';
wait for sample_clk_period/2;
sample_clk <= '1';
wait for sample_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
--channel_select <= "0101010101010101";
--channel_select <= "1010101010101010";
--channel_select <= "0000000011111111";
--channel_select <= "1111111100000000";
channel_select <= "1111111111111111";
--channel_select <= "1111000000000000";
-- channel_select <= "1111000000000000";
sample_run <= '0';
wait for sample_clk_period*5;
sample_run <= '1';
wait for sample_clk_period*(3+to_integer(unsigned(sample_rate_divisor)));
fifo_full <= '0';
fifo_almost_full <= '0';
do_count <= '1';
wait;
end process;
END;
| gpl-2.0 | 8a08e61f008c2b6ed85df3724e4442e3 | 0.596273 | 3.898655 | false | false | false | false |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/new/axis_buffer.vhd | 1 | 2,734 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity axis_buffer is
generic (
DATAWIDTH : integer := 64;
BUFFER_SIZE : positive := 1
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end axis_buffer;
architecture rtl of axis_buffer is
signal reg_tdata : STD_LOGIC_VECTOR (((BUFFER_SIZE + 1) * DATAWIDTH) - 1 downto 0) := ( others => '0' );
signal reg_tkeep : STD_LOGIC_VECTOR (((BUFFER_SIZE + 1) * DATAWIDTH/8) - 1 downto 0) := ( others => '1' );
signal reg_tlast : STD_LOGIC_VECTOR (BUFFER_SIZE downto 0) := ( others => '0' );
signal reg_tvalid : STD_LOGIC_VECTOR (BUFFER_SIZE downto 0) := ( others => '0' );
signal tready : STD_LOGIC := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if (tready = '1') then
reg_tdata(((BUFFER_SIZE + 1) * DATAWIDTH) - 1 downto BUFFER_SIZE * DATAWIDTH) <= s_axis_data_tdata;
reg_tkeep(((BUFFER_SIZE + 1) * DATAWIDTH/8) - 1 downto BUFFER_SIZE * DATAWIDTH/8) <= s_axis_data_tkeep;
reg_tlast(BUFFER_SIZE) <= s_axis_data_tlast;
reg_tvalid(BUFFER_SIZE) <= s_axis_data_tvalid;
end if;
if (m_axis_data_tready = '1') then
tready <= '1';
reg_tdata((BUFFER_SIZE * DATAWIDTH) - 1 downto 0) <= reg_tdata(((BUFFER_SIZE + 1) * DATAWIDTH) - 1 downto DATAWIDTH);
reg_tkeep((BUFFER_SIZE * DATAWIDTH/8) - 1 downto 0) <= reg_tkeep(((BUFFER_SIZE + 1) * DATAWIDTH/8) - 1 downto DATAWIDTH/8);
reg_tlast(BUFFER_SIZE - 1 downto 0) <= reg_tlast(BUFFER_SIZE downto 1);
reg_tvalid(BUFFER_SIZE - 1 downto 0) <= reg_tvalid(BUFFER_SIZE downto 1);
else
tready <= '0';
end if;
end if;
end process;
m_axis_data_tdata <= reg_tdata(DATAWIDTH - 1 downto 0);
m_axis_data_tkeep <= reg_tkeep(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tlast <= reg_tlast(0);
m_axis_data_tvalid <= reg_tvalid(0);
s_axis_data_tready <= tready;
end architecture; | mit | 6398c73444162a62e6bce725d29be908 | 0.579737 | 3.35049 | false | false | false | false |
quicky2000/IP_clock_divider | clk_divider.vhd | 1 | 1,781 | --
-- This file is part of clock_divider
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_divider is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
input : in std_logic;
output : out STD_LOGIC);
end clk_divider;
architecture Behavioral of clk_divider is
constant max_value : positive := 2;
begin
process (clk,rst)
variable counter : natural range 0 to max_value := 0;
begin
if rst = '1' then
counter := 0;
elsif rising_edge(clk) then
if input = '1' then
if counter = max_value then
counter := 0;
output <= '1';
else
output <= '0';
counter := counter + 1;
end if;
else
output <= '0';
end if;
end if ;
end process;
end Behavioral;
| gpl-3.0 | fdd6508a8a74ca7b5e909d918d266947 | 0.677709 | 3.702703 | false | false | false | false |
gregani/la16fw | spi.vhd | 1 | 5,270 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
----------------------------------------------------------------------------------
--
-- state machine for receiving data from the spi interface
--
-- first byte of packet is the address and r/w bit, second is the data
-- when data is written it is put onto data_out bus and enable_write is strobed
-- when data is read enable_read is strobed and data must be put onto data_in
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi is
port(
clk : in std_logic; -- system clock (48MHz)
reset : in std_logic; -- reset (sync)
-- spi interface signals
ss_n : in std_logic; -- slave select (inverted)
sclk : in std_logic; -- serial clock
mosi : in std_logic; -- master out slave in
miso : out std_logic; -- master in slave out
-- communication with other logic
enable_write : out std_logic; -- write data to address
enable_read : out std_logic; -- laod data from address
addr : out std_logic_vector(6 downto 0); -- address
data_out : out std_logic_vector(7 downto 0); -- data to write
data_in : in std_logic_vector(7 downto 0) -- loaded data
);
end spi;
architecture behavioral of spi is
type state_t is(
idle, -- slave select inactive
recv_addr, -- receiving address and r/w bit
recv_addr_done, -- address received
load_data, -- if read: load data from address
load_data_wait, -- if read: wait for data
recv_send_data, -- recv/send data
recv_send_data_done -- if write: store data to address
);
signal state : state_t;
signal bit_count : unsigned(2 downto 0); -- bit counter
signal bits : unsigned(7 downto 0); -- data
signal ss_n_last : std_logic;
signal sclk_last : std_logic;
signal read_flag : std_logic; -- 0: write, 1: read
begin
-- FIXME: increase address after read/write?
process(clk)
begin
if rising_edge(clk) then
enable_write <= '0';
enable_read <= '0';
if (reset = '1') then
state <= idle;
elsif (state = idle) then
if (ss_n_last = '1' and ss_n = '0') then -- slave select
state <= recv_addr;
bit_count <= (others=>'0');
bits <= (others=>'0');
read_flag <= '1';
miso <= '0';
end if;
elsif (state = recv_addr or state = recv_send_data) then
if (ss_n = '1') then
state <= idle;
elsif (sclk_last = '0' and sclk = '1') then -- rising edge
-- shift in/out one bit
miso <= bits(7);
bits <= bits(6 downto 0) & mosi;
if (bit_count = 7) then -- byte received
if (state = recv_addr) then
state <= recv_addr_done;
elsif (state = recv_send_data) then
state <= recv_send_data_done;
end if;
end if;
bit_count <= bit_count + 1;
end if;
elsif (state = recv_addr_done) then
read_flag <= bits(7);
addr <= std_logic_vector(bits(6 downto 0));
if (bits(7) = '1') then -- read
state <= load_data;
enable_read <= '1';
else -- write
state <= recv_send_data;
bits <= (others=>'0');
end if;
elsif (state = load_data) then
state <= load_data_wait;
enable_read <= '1';
elsif (state = load_data_wait) then
bits <= unsigned(data_in);
state <= recv_send_data;
elsif (state = recv_send_data_done) then
state <= recv_send_data;
if (read_flag = '0') then -- write
data_out <= std_logic_vector(bits);
enable_write <= '1';
end if;
end if;
ss_n_last <= ss_n;
sclk_last <= sclk;
end if;
end process;
end behavioral;
| gpl-2.0 | bacf8f9a6ba669015baeb9f7f150a3d3 | 0.503985 | 4.323216 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/synth/zynq_1_axi_quad_spi_0_0.vhd | 1 | 18,081 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_1;
USE axi_quad_spi_v3_1.axi_quad_spi;
ENTITY zynq_1_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END zynq_1_axi_quad_spi_0_0;
ARCHITECTURE zynq_1_axi_quad_spi_0_0_arch OF zynq_1_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
Async_Clk : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_1_axi_quad_spi_0_0_arch : ARCHITECTURE IS "zynq_1_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "zynq_1_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_S_AXI4_BASEADDR=0x41E00000,C_S_AXI4_HIGHADDR=0x41E00FFF,C_FAMILY=virtex7,C_SUB_FAMILY=virtex7,C_INSTANCE=axi_quad_spi_inst,C_TYPE_OF_AXI4_INTERFACE=1,C_XIP_MODE=0,C_SPI_MEM_ADDR_BITS=24,C_FIFO_DEPTH=256,C_SCK_RATIO=128,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=12,Async_Clk=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 full_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 full_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
C_S_AXI4_BASEADDR => X"41E00000",
C_S_AXI4_HIGHADDR => X"41E00FFF",
C_FAMILY => "virtex7",
C_SUB_FAMILY => "virtex7",
C_INSTANCE => "axi_quad_spi_inst",
C_TYPE_OF_AXI4_INTERFACE => 1,
C_XIP_MODE => 0,
C_SPI_MEM_ADDR_BITS => 24,
C_FIFO_DEPTH => 256,
C_SCK_RATIO => 128,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 12,
Async_Clk => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => '0',
s_axi_aresetn => '0',
s_axi4_aclk => s_axi4_aclk,
s_axi4_aresetn => s_axi4_aresetn,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 7)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 7)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi4_awid => s_axi4_awid,
s_axi4_awaddr => s_axi4_awaddr,
s_axi4_awlen => s_axi4_awlen,
s_axi4_awsize => s_axi4_awsize,
s_axi4_awburst => s_axi4_awburst,
s_axi4_awlock => s_axi4_awlock,
s_axi4_awcache => s_axi4_awcache,
s_axi4_awprot => s_axi4_awprot,
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_awready => s_axi4_awready,
s_axi4_wdata => s_axi4_wdata,
s_axi4_wstrb => s_axi4_wstrb,
s_axi4_wlast => s_axi4_wlast,
s_axi4_wvalid => s_axi4_wvalid,
s_axi4_wready => s_axi4_wready,
s_axi4_bid => s_axi4_bid,
s_axi4_bresp => s_axi4_bresp,
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_bready => s_axi4_bready,
s_axi4_arid => s_axi4_arid,
s_axi4_araddr => s_axi4_araddr,
s_axi4_arlen => s_axi4_arlen,
s_axi4_arsize => s_axi4_arsize,
s_axi4_arburst => s_axi4_arburst,
s_axi4_arlock => s_axi4_arlock,
s_axi4_arcache => s_axi4_arcache,
s_axi4_arprot => s_axi4_arprot,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_arready => s_axi4_arready,
s_axi4_rid => s_axi4_rid,
s_axi4_rdata => s_axi4_rdata,
s_axi4_rresp => s_axi4_rresp,
s_axi4_rlast => s_axi4_rlast,
s_axi4_rvalid => s_axi4_rvalid,
s_axi4_rready => s_axi4_rready,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt
);
END zynq_1_axi_quad_spi_0_0_arch;
| mit | 41fecb7437ab651c91b2455b0ecd8a2c | 0.668436 | 2.935704 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/axi_qspi_enhanced_mode.vhd | 1 | 41,943 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_qspi_enhanced_mode.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- enhanced mode with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of xps_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- SK 12/12/11
-- 1. First introduction of AXI4 full in v3_1 version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.srl_fifo_f;
library interrupt_control_v3_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
entity axi_qspi_enhanced_mode is
generic (
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_AXI4_CLK_PS : integer := 10000;--AXI clock period
C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
C_SPI_MEM_ADDR_BITS : integer -- newly added
);
port (
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESETN : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
--Bus2IP_Addr : out std_logic_vector
-- (C_S_AXI4_ADDR_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
---------------------------------
burst_tr : out std_logic;
rready : out std_logic
);
end entity axi_qspi_enhanced_mode;
architecture imp of axi_qspi_enhanced_mode is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant ACTIVE_LOW_RESET : std_logic := '0';
-- local type declarations
type STATE_TYPE is (
IDLE,
AXI_SINGLE_RD,
AXI_RD,
AXI_SINGLE_WR,
AXI_WR,
CHECK_AXI_LENGTH_ERROR,
AX_WRONG_BURST_TYPE,
WR_RESP_1,
WR_RESP_2,
RD_RESP_1,RD_LAST,
RD_RESP_2,
ERROR_RESP,
RD_ERROR_RESP
);
-- Signal Declaration
-----------------------------
signal axi_full_sm_ps : STATE_TYPE;
signal axi_full_sm_ns : STATE_TYPE;
-- function declaration
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
-- code coverage -- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
-- code coverage -- variable i : integer := 0;
-- code coverage -- begin
-- code coverage -- for i in 31 downto 0 loop
-- code coverage -- if y(i)='1' then
-- code coverage -- return (i);
-- code coverage -- end if;
-- code coverage -- end loop;
-- code coverage -- return -1;
-- code coverage -- end function Get_Addr_Bits;
-- constant declaration
constant C_ADDR_DECODE_BITS : integer := 6; -- Get_Addr_Bits(C_S_AXI_SPI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector(31 downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-- type decode_bit_array_type is Array(natural range 0 to (
-- (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
-- integer;
-- type short_addr_array_type is Array(natural range 0 to
-- C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
-- std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
-- signal declaration
signal axi_size_reg : std_logic_vector(2 downto 0);
signal axi_size_cmb : std_logic_vector(2 downto 0);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(31 downto 0); -- (31 downto 0); -- 8/18/2013
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal arready_i : std_logic;
signal awready_i, s_axi_wready_i : std_logic;
signal S_AXI4_RID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal S_AXI4_BID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector(2 downto 0);
signal axi_full_sm_ps_IDLE_cmb : std_logic;
signal s_axi_mem_bvalid_reg : std_logic;
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
signal axi_length_cmb : std_logic_vector(7 downto 0);
signal axi_length_reg : std_logic_vector(7 downto 0);
signal burst_transfer_cmb : std_logic;
signal burst_transfer_reg : std_logic;
signal axi_burst_cmb : std_logic_vector(1 downto 0);
signal axi_burst_reg : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(7 downto 0);
signal last_data_cmb : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal pr_state_idle : std_logic;
signal length_error : std_logic;
signal rnw_reg, rnw_cmb : std_logic;
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal wready_cmb : std_logic;
signal store_axi_signal_cmb : std_logic;
signal combine_ack, start, temp_i, response : std_logic;
signal s_axi4_rdata_i : std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
signal s_axi4_rresp_i : std_logic_vector(1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal S_AXI4_BRESP_i : std_logic_vector(1 downto 0);
signal s_axi_bvalid_i : std_logic;
signal pr_state_length_chk : std_logic;
signal axi_full_sm_ns_IDLE_cmb : std_logic;
signal last_data_reg: std_logic;
signal rst_en : std_logic;
signal s_axi_rvalid_cmb, last_data, burst_tr_i,rready_i, store_data : std_logic;
signal Bus2IP_Reset_i : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
-- REGISTERING_RESET_P: Invert the reset coming from AXI4
-----------------------
REGISTERING_RESET_P : process (S_AXI4_ACLK) is
-----
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
Bus2IP_Reset_i <= not S_AXI4_ARESETN;
end if;
end process REGISTERING_RESET_P;
Bus2IP_Reset <= Bus2IP_Reset_i;
Bus2IP_Clk <= S_AXI4_ACLK;
--Bus2IP_Resetn <= S_AXI4_ARESETN;
--bus2ip_rnw_i <= rnw_reg;-- '1' when S_AXI4_ARVALID='1' else '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_Data <= S_AXI4_WDATA;
--Bus2IP_Addr <= bus2ip_addr_i;
wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
bus2ip_addr_i <= ZEROS & S_AXI4_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI4_ARVALID='1')
else
ZEROS & S_AXI4_AWADDR(C_ADDR_DECODE_BITS downto 0);
--S_AXI4_ARADDR(C_ADDR_DECODE_BITS+1 downto 0) when (S_AXI4_ARVALID='1')
--else
--S_AXI4_AWADDR(C_ADDR_DECODE_BITS+1 downto 0);
-- read and write transactions should be separate
-- preferencec of read over write
-- only narrow transfer of 8-bit are supported
-- for 16-bit and 32-bit transactions error should be generated - dont provide these signals to internal logic
--wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
--wr_addr_transaction <= S_AXI4_AWVALID and (not S_AXI4_WVALID);
-------------------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
arready_i <='0';
else
arready_i <= arready_cmb;
end if;
end if;
end process AXI_ARREADY_P;
--------------------------
S_AXI4_ARREADY <= arready_i; -- arready_i;--IP2Bus_RdAck; --arready_i;
--------------------------
AXI_AWREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
awready_i <='0';
else
awready_i <= awready_cmb;
end if;
end if;
end process AXI_AWREADY_P;
--------------------------
S_AXI4_AWREADY <= awready_i;
--------------------------
S_AXI4_BRESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
S_AXI4_BRESP_i <= (others => '0');
elsif (axi_full_sm_ps = AXI_WR) or (axi_full_sm_ps = AXI_SINGLE_WR) then
S_AXI4_BRESP_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI4_BRESP_P;
---------------------------
S_AXI4_BRESP <= S_AXI4_BRESP_i;
-------------------------------
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_bvalid_i <= '0';
elsif(axi_full_sm_ps = WR_RESP_1)then
s_axi_bvalid_i <= '1';
elsif(S_AXI4_BREADY = '1')then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------
S_AXI4_BVALID <= s_axi_bvalid_i;
--------------------------------
----S_AXI_WREADY_I_P: below process provides logic for valid write response signal
---------------------
S_AXI_WREADY_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_wready_i <= '0';
else
s_axi_wready_i <= wready_cmb;
end if;
end if;
end process S_AXI_WREADY_I_P;
-------------------------------
S_AXI4_WREADY <= s_axi_wready_i;
--------------------------------
-------------------------------------------------------------------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
REG_BID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
S_AXI4_BID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_BID_reg <= S_AXI4_AWID;-- and pr_state_length_chk;
end if;
end if;
end process REG_BID_P;
-----------------------
S_AXI4_BID <= S_AXI4_BID_reg;
------------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI4_ACLK) is
------------
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if ((Bus2IP_Reset_i = RESET_ACTIVE)) then
bus2ip_BE_reg <= (others => '0');
else
if (rnw_cmb = '0'-- and
--(wready_cmb = '1')
) then
bus2ip_BE_reg <= S_AXI4_WSTRB;
else -- if(rnw_cmb = '1') then
bus2ip_BE_reg <= (others => '1');
end if;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
Bus2IP_BE <= bus2ip_BE_reg;
axi_length_cmb <= S_AXI4_ARLEN when (rnw_cmb = '1')
else
S_AXI4_AWLEN;
burst_transfer_cmb <= (or_reduce(axi_length_cmb));
BURST_LENGTH_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_length_reg <= (others => '0');
burst_transfer_reg <= '0';
elsif((store_axi_signal_cmb = '1'))then
axi_length_reg <= axi_length_cmb;
burst_transfer_reg <= burst_transfer_cmb;
end if;
end if;
end process BURST_LENGTH_REG_P;
-----------------------
burst_tr_i <= burst_transfer_reg;
burst_tr <= burst_tr_i;
-------------------------------------------------------------------------------
axi_size_cmb <= S_AXI4_ARSIZE(2 downto 0) when (rnw_cmb = '1')
else
S_AXI4_AWSIZE(2 downto 0);
SIZE_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_size_reg <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
axi_size_reg <= axi_size_cmb;
end if;
end if;
end process SIZE_REG_P;
-----------------------
axi_burst_cmb <= S_AXI4_ARBURST when (rnw_cmb = '1')
else
S_AXI4_AWBURST;
BURST_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
axi_burst_reg <= (others => '0');
elsif(store_axi_signal_cmb = '1')then
axi_burst_reg <= axi_burst_cmb;
end if;
end if;
end process BURST_REG_P;
-----------------------
combine_ack <= IP2Bus_WrAck or IP2Bus_RdAck;
--------------------------------------------
LENGTH_CNTR_P:process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
length_cntr <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
length_cntr <= axi_length_cmb;
elsif (wready_cmb = '1' and S_AXI4_WVALID = '1') or
(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then -- burst length error
length_cntr <= length_cntr - '1';
end if;
end if;
end process LENGTH_CNTR_P;
--------------------------
--last_data_cmb <= or_reduce(length_cntr(7 downto 1)) and length_cntr(1);
rready <= rready_i;
last_bt_one_data_cmb <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0) and S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(length_cntr(7 downto 0)));
--temp_i <= (combine_ack and last_data_reg)or rst_en;
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(axi_full_sm_ps_IDLE_cmb = '1') then
last_data_acked <= '0';
elsif(burst_tr_i = '0')then
if(S_AXI4_RREADY = '1' and last_data_acked = '1')then
last_data_acked <= '0';
else
last_data_acked <= last_data_cmb and s_axi_rvalid_cmb;
end if;
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then
last_data_acked <= '1';
else
last_data_acked <= last_data and s_axi_rvalid_i and S_AXI4_RREADY;
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
-- S_AXI4_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
elsif(S_AXI4_RREADY = '1' )or(store_data = '1') then --if --((axi_full_sm_ps = AXI_SINGLE_RD) or (axi_full_sm_ps = AXI_BURST_RD)) then
S_AXI4_RRESP_i <= (IP2Bus_Error) & '0';
S_AXI4_RDATA_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= s_axi_rvalid_cmb;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
-- Addr_int <= S_AXI_ARADDR when(rnw_cmb_dup = '1')
-- else
-- S_AXI_AWADDR;
axi_full_sm_ns_IDLE_cmb <= '1' when (axi_full_sm_ns = IDLE) else '0';
axi_full_sm_ps_IDLE_cmb <= '1' when (axi_full_sm_ps = IDLE) else '0';
pr_state_idle <= '1' when axi_full_sm_ps = IDLE else '0';
pr_state_length_chk <= '1' when axi_full_sm_ps = CHECK_AXI_LENGTH_ERROR
else
'0';
REGISTER_LOWER_ADDR_BITS_P:process(S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (axi_full_sm_ps_IDLE_cmb = '1') then
length_error <= '0';
elsif(burst_transfer_cmb = '1')then -- means its a burst
--if (bus2ip_addr_i (7 downto 3) = "01101")then
if (bus2ip_addr_i (6 downto 3) = "1101")then
length_error <= '0';
else
length_error <= '1';
end if;
end if;
end if;
end process REGISTER_LOWER_ADDR_BITS_P;
---------------------------------------
-- length_error <= '0';
---------------------------
REG_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
axi_full_sm_ps <= IDLE;
last_data_reg <= '0';
else
axi_full_sm_ps <= axi_full_sm_ns;
last_data_reg <= last_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
STORE_SIGNALS_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
rnw_reg <= '0';
else-- if(store_axi_signal_cmb = '1')then
rnw_reg <= rnw_cmb;
end if;
end if;
end process STORE_SIGNALS_P;
-------------------------------------------------------
AXI_FULL_STATE_MACHINE_P:process(
axi_full_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_AWVALID ,
S_AXI4_WVALID ,
S_AXI4_BREADY ,
S_AXI4_RREADY ,
wr_transaction ,
wr_addr_transaction ,
length_error ,
IP2Bus_WrAck ,
last_data_cmb ,
IP2Bus_RdAck ,
IP2Bus_Error ,
burst_transfer_cmb ,
last_bt_one_data_cmb ,
rnw_reg ,
length_cntr
)is
-----
begin
-----
arready_cmb <= '0';
awready_cmb <= '0';
wready_cmb <= '0';
start <= '0';
rst_en <= '0';
temp_i <= '0';
store_axi_signal_cmb <= '0';
s_axi_rvalid_cmb <= '0';
rready_i <= '0';
rnw_cmb <= '0';
last_data <= '0';
store_data <= '0';
case axi_full_sm_ps is
when IDLE => if(S_AXI4_ARVALID = '1') then
start <= '1';
store_axi_signal_cmb <= '1';
arready_cmb <= '1';
if(burst_transfer_cmb = '1') then
axi_full_sm_ns <= AXI_RD;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
elsif(wr_transaction = '1')then
start <= '1';
store_axi_signal_cmb <= '1';
if(burst_transfer_cmb = '1') then
awready_cmb <= '1';
wready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
else
axi_full_sm_ns <= IDLE;
end if;
rnw_cmb <= S_AXI4_ARVALID and (not S_AXI4_AWVALID);
------------------------------
when CHECK_AXI_LENGTH_ERROR => if (length_error = '0') then
if(rnw_reg = '1')then
arready_cmb <= '1';
axi_full_sm_ns <= AXI_RD;
else
awready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
end if;
start <= '1';
else
axi_full_sm_ns <= ERROR_RESP;
end if;
---------------------------------------------------------
when AXI_SINGLE_RD => --arready_cmb <= IP2Bus_RdAck;
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error;
temp_i <= IP2Bus_RdAck or IP2Bus_Error;
rready_i <= '1';
if(IP2Bus_RdAck = '1')or (IP2Bus_Error = '1') then
store_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
rnw_cmb <= rnw_reg;
when AXI_RD =>
rready_i <= S_AXI4_RREADY and not last_data_cmb;
last_data <= last_bt_one_data_cmb;
if(last_data_cmb = '1') then
if(S_AXI4_RREADY = '1')then
temp_i <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
axi_full_sm_ns <= IDLE;
else
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
last_data <= not S_AXI4_RREADY;
temp_i <= '1';
axi_full_sm_ns <= RD_LAST;
end if;
else
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error; -- not last_data_cmb;
axi_full_sm_ns <= AXI_RD;
end if;
rnw_cmb <= rnw_reg;
----------------------------------------------------------
when AXI_SINGLE_WR => awready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
wready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
temp_i <= IP2Bus_WrAck or IP2Bus_Error;
if(IP2Bus_WrAck = '1')or (IP2Bus_Error = '1')then
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
rnw_cmb <= rnw_reg;
when AXI_WR => --if(IP2Bus_WrAck = '1')then
wready_cmb <= '1';--IP2Bus_WrAck;
if(last_data_cmb = '1') then
wready_cmb <= '0';
temp_i <= '1';--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_WrAck;
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_WR;
end if;
rnw_cmb <= rnw_reg;
-----------------------------------------------------------
when WR_RESP_1 => --if(S_AXI4_BREADY = '1') then
-- axi_full_sm_ns <= IDLE;
--else
axi_full_sm_ns <= WR_RESP_2;
-- end if;
-----------------------------------------------------------
when WR_RESP_2 => if(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= WR_RESP_2;
end if;
-----------------------------------------------------------
when RD_LAST => if(S_AXI4_RREADY = '1') then -- and (TX_FIFO_Empty = '1') then
last_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= IDLE;
else
last_data <= not S_AXI4_RREADY;
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
temp_i <= '1';
end if;
-----------------------------------------------------------
when RD_RESP_2 => if(S_AXI4_RREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= RD_RESP_2;
end if;
-----------------------------------------------------------
when ERROR_RESP => if(length_cntr = "00000000") and
(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= ERROR_RESP;
end if;
response <= '1';
when others => axi_full_sm_ns <= IDLE;
end case;
end process AXI_FULL_STATE_MACHINE_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
I_DECODER : entity axi_quad_spi_v3_1.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK,
Bus_rst => S_AXI4_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), -- (C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI4_ARVALID,
Bus_RNW_Erly => S_AXI4_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
end architecture imp;
------------------------------------------------------------------------------
| mit | 5da9ddd9eed20861313f1008416cbbd8 | 0.444699 | 3.875 | false | false | false | false |
sunoc/vhdl-lz4-variation | lz4_pkg.vhdl | 1 | 4,830 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library IKWZM_SECURE_HASH;
--use IKWZM_SECURE_HASH.SHA1.all;
package lz4_pkg is
-- constants for the SHA-1
constant SYMBOL_BITS : integer := 8;
constant SYMBOLS : integer := 4;
constant REVERSE : integer := 1;
constant WORDS : integer := 1;
constant BLOCK_GAP : integer := 1;
-- Clock period definitions
constant clk_period : time := 10 ns;
component lz4_top
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end component;
component lz4_entryBuffer is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
toUTVal_o : out std_logic_vector(31 downto 0);
buffPoint_o : out std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
eof : out std_logic;
-- data to the output level
pos_i : in std_logic_vector(12 downto 0);
len_i : in std_logic_vector(12 downto 0);
literal_o : out std_logic_vector(31 downto 0);
-- output to the hash
CLR_o : out std_logic;
I_DATA_o : out std_logic_vector(31 downto 0);
I_ENA_o : out std_logic_vector(3 downto 0);
I_DONE_o : out std_logic;
I_LAST_o : out std_logic;
I_VAL_o : out std_logic;
O_RDY_o : out std_logic
);
end component;
component lz4_utval is
port (
clk_i : in std_logic;
reset_i : in std_logic;
fromEntry_i : in std_logic_vector(31 downto 0);
length_o : out std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
-- output to the hash
CLR_o : out std_logic;
I_DATA_o : out std_logic_vector(31 downto 0);
I_ENA_o : out std_logic_vector(3 downto 0);
I_DONE_o : out std_logic;
I_LAST_o : out std_logic;
I_VAL_o : out std_logic;
O_RDY_o : out std_logic
);
end component;
component lz4_utline is
port (
clk_i : in std_logic;
reset_i : in std_logic;
length_i : in std_logic_vector(12 downto 0);
position_i : in std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
match : out std_logic;
-- output from the hash
O_DATA_i : in std_logic_vector(159 downto 0);
O_VAL_i : in std_logic;
I_RDY_i : in std_logic;
-- for the dict comp
startpars_o : out std_logic;
dictLine_i : in std_logic_vector(185 downto 0);
todictLine_o : out std_logic_vector(185 downto 0);
-- line used by the out level
lineToOut_o : out std_logic_vector(185 downto 0);
offset_o : out std_logic_vector(12 downto 0)
);
end component;
component lz4_fsm is
port (
clk_i : in std_logic;
reset_i : in std_logic;
match : in std_logic;
eof : in std_logic;
Fs : out std_logic_vector(2 downto 0)
);
end component;
component lz4_dictionary is
port (
clk_i : in std_logic;
reset_i : in std_logic;
-- for the dict comp
startpars_i : in std_logic;
dictLine_o : out std_logic_vector(185 downto 0);
todictLine_i : in std_logic_vector(185 downto 0)
);
end component;
component lz4_assembly is
port (
clk_i : in std_logic;
reset_i : in std_logic;
litLength_i : in std_logic_vector(9 downto 0);
offset_i : in std_logic_vector(9 downto 0);
matchLength_i : in std_logic_vector(9 downto 0);
internalStream_i : in std_logic;
-- main output
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end component;
component lz4_entryDict is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryBytes_i : in std_logic_vector(7 downto 0);
litLength_o : out std_logic_vector(9 downto 0);
offset_o : out std_logic_vector(9 downto 0);
matchLength_o : out std_logic_vector(9 downto 0);
internalStream_o : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | d40d1cf67a047830a65e25df5ff4f290 | 0.513458 | 3.57513 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 2 | 7,566 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | afc98e8ad79f378a4d5af10e890a117b | 0.557891 | 3.773566 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/reset_builtin.vhd | 9 | 18,883 | `protect begin_protected
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| gpl-3.0 | ff9fccd10eb73e3ddc6955c6bb4dd6d2 | 0.942011 | 1.879841 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top.vhd | 9 | 40,066 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| gpl-3.0 | 6b23c4144ff1364ca3f5427e0d76941a | 0.949009 | 1.844574 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/simulation/dist_mem_gen_v8_0.vhd | 1 | 27,885 | -------------------------------------------------------------------------------
--
-- Distributed Memory Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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--
-- DISCLAIMER
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename : dist_mem_gen_v8_0.vhd
--
-- Author : Xilinx
--
-- Description : Distributed Memory Simulation Model
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity dist_mem_gen_v8_0 is
generic (
C_FAMILY : STRING := "VIRTEX5";
C_ADDR_WIDTH : INTEGER := 6;
C_DEFAULT_DATA : STRING := "0";
C_ELABORATION_DIR : STRING := "0";
C_DEPTH : INTEGER := 64;
C_HAS_CLK : INTEGER := 1;
C_HAS_D : INTEGER := 1;
C_HAS_DPO : INTEGER := 0;
C_HAS_DPRA : INTEGER := 0;
C_HAS_I_CE : INTEGER := 0;
C_HAS_QDPO : INTEGER := 0;
C_HAS_QDPO_CE : INTEGER := 0;
C_HAS_QDPO_CLK : INTEGER := 0;
C_HAS_QDPO_RST : INTEGER := 0;
C_HAS_QDPO_SRST : INTEGER := 0;
C_HAS_QSPO : INTEGER := 0;
C_HAS_QSPO_CE : INTEGER := 0;
C_HAS_QSPO_RST : INTEGER := 0;
C_HAS_QSPO_SRST : INTEGER := 0;
C_HAS_SPO : INTEGER := 1;
C_HAS_WE : INTEGER := 1;
C_MEM_INIT_FILE : STRING := "NULL.MIF";
C_MEM_TYPE : INTEGER := 1;
C_PIPELINE_STAGES : INTEGER := 0;
C_QCE_JOINED : INTEGER := 0;
C_QUALIFY_WE : INTEGER := 0;
C_READ_MIF : INTEGER := 0;
C_REG_A_D_INPUTS : INTEGER := 0;
C_REG_DPRA_INPUT : INTEGER := 0;
C_SYNC_ENABLE : INTEGER := 0;
C_WIDTH : INTEGER := 16;
C_PARSER_TYPE : INTEGER := 1);
port (
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0));
end dist_mem_gen_v8_0;
architecture behavioral of dist_mem_gen_v8_0 is
-- Register delay
CONSTANT C_TCQ : time := 100 ps;
constant max_address : std_logic_vector(c_addr_width-1 downto 0) :=
std_logic_vector(to_unsigned(c_depth-1, c_addr_width));
constant c_rom : integer := 0;
constant c_sp_ram : integer := 1;
constant c_dp_ram : integer := 2;
constant c_sdp_ram : integer := 4;
type mem_type is array ((2**c_addr_width)-1 downto 0) of std_logic_vector(c_width-1 downto 0);
---------------------------------------------------------------------
-- Convert character to type std_logic.
---------------------------------------------------------------------
impure function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
---------------------------------------------------------------------
impure function read_mif (
filename : in string;
def_data : in std_logic_vector;
depth : in integer;
width : in integer)
return mem_type is
file meminitfile : text;
variable mif_status : file_open_status;
variable bitline : line;
variable bitsgood : boolean := true;
variable bitchar : character;
variable lines : integer := 0;
variable memory_content : mem_type;
begin
for i in 0 to depth-1 loop
memory_content(i) := def_data;
end loop; -- i
file_open(mif_status, meminitfile, filename, read_mode);
if mif_status /= open_ok then
assert false
report "Error: read_mem_init_file: could not open MIF."
severity failure;
end if;
lines := 0;
for i in 0 to depth-1 loop
if not(endfile(meminitfile)) and i < depth then
memory_content(i) := (others => '0');
readline(meminitfile, bitline);
for j in 0 to width-1 loop
read(bitline, bitchar, bitsgood);
if ((bitsgood = false) or
((bitchar /= ' ') and (bitchar /= cr) and
(bitchar /= ht) and (bitchar /= lf) and
(bitchar /= '0') and (bitchar /= '1') and
(bitchar /= 'x') and (bitchar /= 'z'))) then
assert false
report
"Warning: dist_mem_utils: unknown or illegal " &
"character encountered while reading mif - " &
"finishing file read." & cr &
"This could be due to an undersized mif file"
severity warning;
exit; -- abort the file read
end if;
memory_content(i)(width-1-j) := char_to_std_logic(bitchar);
end loop; -- j
else
exit;
end if;
lines := i + 1;
end loop;
file_close(meminitfile);
assert not(lines > depth)
report "MIF file contains more addresses than the memory."
severity failure;
assert lines = depth
report
"MIF file size does not match memory size." & cr &
"Remaining addresses in memory are padded with default data."
severity warning;
return memory_content;
end read_mif;
---------------------------------------------------------------------
impure function string_to_std_logic_vector (
the_string : string;
size : integer)
return std_logic_vector is
variable slv_tmp : std_logic_vector(1 to size) := (others => '0');
variable slv : std_logic_vector(size-1 downto 0) := (others => '0');
variable index : integer := 0;
begin
slv_tmp := (others => '0');
index := size;
if the_string'length > size then
for i in the_string'length downto the_string'length-size+1 loop
slv_tmp(index) := char_to_std_logic(the_string(i));
index := index - 1;
end loop; -- i
else
for i in the_string'length downto 1 loop
slv_tmp(index) := char_to_std_logic(the_string(i));
index := index - 1;
end loop; -- i
end if;
for i in 1 to size loop
slv(size-i) := slv_tmp(i);
end loop; -- i
return slv;
end string_to_std_logic_vector;
---------------------------------------------------------------------
-- Convert the content of a file and return an array of
-- std_logic_vectors.
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Function which initialises the memory from the c_default_data
-- string or the c_mem_init_file MIF file.
---------------------------------------------------------------------
impure function init_mem (
memory_type : in integer;
read_mif_file : in integer;
filename : in string;
default_data : in string;
depth : in integer;
width : in integer)
return mem_type is
variable memory_content : mem_type := (others => (others => '0'));
variable def_data : std_logic_vector(width-1 downto 0) := (others => '0');
constant all_zeros : std_logic_vector(width-1 downto 0) := (others => '0');
begin
def_data := string_to_std_logic_vector(default_data, width);
if read_mif_file = 0 then
-- If the memory is not initialised from a MIF file then fill the memory array with
-- default data.
for i in 0 to depth-1 loop
memory_content(i) := def_data;
end loop; -- i
else
--Initialise the memory from the MIF file.
memory_content := read_mif(filename, def_data, depth, width);
end if;
return memory_content;
end init_mem;
------------------------------------------------------------------
signal memory : mem_type :=
init_mem(
c_mem_type,
c_read_mif,
c_mem_init_file,
c_default_data,
c_depth,
c_width);
-- address signal connected to memory
signal a_int : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- address signal connected to memory, which has been registered.
signal a_reg : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
signal a_over : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- dual port read address signal connected to dual port memory
signal dpra_int : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- dual port read address signal connected to dual port memory, which
-- has been registered.
signal dpra_reg : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
signal dpra_over : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- input data signal connected to RAM
signal d_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- input data signal connected to RAM, which has been registered.
signal d_reg : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Write Enable signal connected to memory
signal we_int : std_logic := '0';
-- Write Enable signal connected to memory, which has been registered.
signal we_reg : std_logic := '0';
-- Internal Clock Enable for optional qspo output
signal qspo_ce_int : std_logic := '0';
-- Internal Clock Enable for optional qspo output, which has been
-- registered
signal qspo_ce_reg : std_logic := '0';
-- Internal Clock Enable for optional qdpo output
signal qdpo_ce_int : std_logic := '0';
-- Internal Clock Enable for optional qspo output, which has been
-- registered
signal qdpo_ce_reg : std_logic := '0';
-- Internal version of the spo output
signal spo_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Pipeline for the qspo output
signal qspo_pipe : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Internal version of the qspo output
signal qspo_int : std_logic_vector(c_width-1 downto 0) :=
string_to_std_logic_vector(c_default_data, c_width);
-- Internal version of the dpo output
signal dpo_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Pipeline for the qdpo output
signal qdpo_pipe : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Internal version of the qdpo output
signal qdpo_int : std_logic_vector(c_width-1 downto 0) :=
string_to_std_logic_vector(c_default_data, c_width);
-- Content of spo_int from address a
signal data_sp : std_logic_vector(c_width-1 downto 0);
-- Content of Dual Port Output at address dpra
signal data_dp : std_logic_vector(c_width-1 downto 0);
-- Content of spo_int from address a
signal data_sp_over : std_logic_vector(c_width-1 downto 0);
-- Content of Dual Port Output at address dpra
signal data_dp_over : std_logic_vector(c_width-1 downto 0);
signal a_is_over : std_logic;
signal dpra_is_over : std_logic;
begin
p_warn_behavioural : process
begin
assert false report "This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation." severity warning;
wait;
end process p_warn_behavioural;
---------------------------------------------------------------------
-- Infer any optional input registers, in the clk clock domain.
---------------------------------------------------------------------
p_optional_input_registers : process
begin
wait until c_reg_a_d_inputs = 1 and clk'event and clk = '1';
if c_mem_type = c_rom then
if (c_has_qspo_ce = 1) then
if (qspo_ce = '1') then
a_reg <= a after C_TCQ;
end if;
else
a_reg <= a after C_TCQ;
end if;
elsif c_has_i_ce = 0 then
we_reg <= we after C_TCQ;
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
elsif c_qualify_we = 0 then
we_reg <= we after C_TCQ;
if i_ce = '1' then
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
end if;
elsif c_qualify_we = 1 and i_ce = '1' then
we_reg <= we after C_TCQ;
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
end if;
qspo_ce_reg <= qspo_ce after C_TCQ;
end process p_optional_input_registers;
---------------------------------------------------------------------
-- If the inputs are registered, propogate those signals to the
-- internal versions that will be used by the memory construct.
---------------------------------------------------------------------
g_optional_input_regs : if c_reg_a_d_inputs = 1 generate
we_int <= we_reg;
d_int <= d_reg;
a_int <= a_reg;
qspo_ce_int <= qspo_ce_reg;
end generate g_optional_input_regs;
---------------------------------------------------------------------
-- Otherwise, just pass the ports directly to the internal signals
-- used by the memory construct.
---------------------------------------------------------------------
g_no_optional_input_regs : if c_reg_a_d_inputs = 0 generate
we_int <= we;
d_int <= d;
a_int <= a;
qspo_ce_int <= qspo_ce;
end generate g_no_optional_input_regs;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- In addition, there are inputs that can be registered, that can
-- have their own clock domain. This is best handled in a seperate
-- process for readability.
---------------------------------------------------------------------
p_optional_dual_port_regs : process
begin
if c_reg_dpra_input = 0 then
wait;
elsif c_has_qdpo_clk = 0 then
wait until clk'event and clk = '1';
else
wait until qdpo_clk'event and qdpo_clk = '1';
end if;
if c_qce_joined = 1 then
if c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce = '1') then
dpra_reg <= dpra after C_TCQ;
end if;
elsif c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce = '1') then
dpra_reg <= dpra after C_TCQ;
end if;
qdpo_ce_reg <= qdpo_ce after C_TCQ;
end process p_optional_dual_port_regs;
---------------------------------------------------------------------
-- If the inputs are registered, propogate those signals to the
-- internal versions that will be used by the memory construct.
---------------------------------------------------------------------
g_optional_dual_port_regs : if c_reg_dpra_input = 1 generate
dpra_int <= dpra_reg;
qdpo_ce_int <= qdpo_ce_reg;
end generate g_optional_dual_port_regs;
---------------------------------------------------------------------
-- Otherwise, just pass the ports directly to the internal signals
-- used by the memory construct.
---------------------------------------------------------------------
g_no_optional_dual_port_regs : if c_reg_dpra_input = 0 generate
dpra_int <= dpra;
qdpo_ce_int <= qdpo_ce;
end generate g_no_optional_dual_port_regs;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- For the Single Port RAM and Dual Port RAM memory types, define how
-- the RAM is written to.
---------------------------------------------------------------------
p_write_to_spram_dpram : process
begin -- process p_write_to_spram_dpram
wait until clk'event and clk = '1' and we_int = '1'
and c_mem_type /= c_rom;
if a_is_over = '1' then
assert false
report "Writing to out of range address." & cr &
"Max address is " & integer'image(c_depth-1) & "." &
cr & "Write ignored."
severity warning;
else
memory(to_integer(unsigned(a_int))) <= d_int after C_TCQ;
end if;
end process p_write_to_spram_dpram;
---------------------------------------------------------------------
-- Form the spo_int signal and the optional spo output. spo_int will
-- be used in assigning the optional qspo output.
---------------------------------------------------------------------
spo_int <= data_sp_over when a_is_over = '1' else data_sp;
a_is_over <= '1' when a_int > max_address else '0';
dpra_is_over <= '1' when dpra_int > max_address else '0';
g_dpra_over: for i in 0 to c_addr_width-1 generate
dpra_over(i) <= dpra_int(i) and max_address(i);
end generate g_dpra_over;
data_sp <= memory(to_integer(unsigned(a_int)));
data_sp_over <= (others => 'X');
data_dp <= memory(to_integer(unsigned(dpra_int)));
data_dp_over <= (others => 'X');
g_has_spo : if c_has_spo = 1 generate
spo <= spo_int;
end generate g_has_spo;
g_has_no_spo : if c_has_spo = 0 generate
spo <= (others => 'X');
end generate g_has_no_spo;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Form the dpo_int signal and the optional dpo output. dpo_int will
-- be used in assigning the optional qdpo output.
---------------------------------------------------------------------
g_dpram: if (c_mem_type = c_dp_ram or c_mem_type = c_sdp_ram) generate
dpo_int <= data_dp_over when dpra_is_over = '1' else data_dp;
end generate g_dpram;
g_not_dpram: if (c_mem_type /= c_dp_ram and c_mem_type /= c_sdp_ram) generate
dpo_int <= (others => 'X');
end generate g_not_dpram;
assert not((c_mem_type = c_dp_ram or c_mem_type = c_sdp_ram) and dpra_is_over = '1')
report "DPRA trying to read from out of range address." & cr &
"Max address is " & integer'image(c_depth-1)
severity warning;
g_has_dpo : if c_has_dpo = 1 generate
dpo <= dpo_int;
end generate g_has_dpo;
g_has_no_dpo : if c_has_dpo = 0 generate
dpo <= (others => 'X');
end generate g_has_no_dpo;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Form the QSPO output depending on the following:
---------------------------------------------------------------------
-- Generics
-- c_has_qspo
-- c_has_qspo_rst
-- c_sync_enable
-- c_has_qspo_ce
---------------------------------------------------------------------
-- Signals
-- clk
-- qspo_rst
-- qspo_srst
-- qspo_ce
-- spo_int
---------------------------------------------------------------------
p_has_qspo : process
begin
if c_has_qspo /= 1 then
qspo_int <= (others => 'X');
qspo_pipe <= (others => 'X');
wait;
end if;
wait until (clk'event and clk = '1') or (qspo_rst = '1' and c_has_qspo_rst = 1);
---------------------------------------------------------------------
if c_has_qspo_rst = 1 and qspo_rst = '1' then
qspo_pipe <= (others => '0');
qspo_int <= (others => '0');
elsif c_has_qspo_srst = 1 and qspo_srst = '1' then
if c_sync_enable = 0 then
qspo_pipe <= (others => '0') after C_TCQ;
qspo_int <= (others => '0') after C_TCQ;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
qspo_pipe <= (others => '0') after C_TCQ;
qspo_int <= (others => '0') after C_TCQ;
end if;
elsif c_has_qspo_ce = 0 or qspo_ce_int = '1' then
qspo_pipe <= spo_int after C_TCQ;
if c_pipeline_stages = 1 then
qspo_int <= qspo_pipe after C_TCQ;
else
qspo_int <= spo_int after C_TCQ;
end if;
end if;
end process p_has_qspo;
---------------------------------------------------------------------
qspo <= qspo_int;
---------------------------------------------------------------------
-- Form the QDPO output depending on the following:
---------------------------------------------------------------------
-- Generics
-- c_has_qdpo
-- c_qce_joined
-- c_has_qdpo_clk
-- c_has_qdpo_rst
-- c_has_qdpo_srst
-- c_has_qdpo_ce
-- c_has_qspo_ce
-- c_sync_enable
---------------------------------------------------------------------
-- Signals
-- clk
-- qdpo_clk
-- qdpo_rst
-- qdpo_srst
-- qdpo_ce
-- qspo_ce
-- dpo_int
---------------------------------------------------------------------
p_has_qdpo : process
begin
if c_has_qdpo /= 1 then
qdpo_pipe <= (others => 'X');
qdpo_int <= (others => 'X');
wait;
end if;
if c_has_qdpo_clk = 0 then
--Common clock enables used for qspo and qdpo outputs.
--Therefore we have one clock domain to worry about.
wait until (clk'event and clk = '1')
or (c_has_qdpo_rst = 1 and qdpo_rst = '1');
else
--The qdpo output is in a seperate clock domain from the rest
--of the dual port RAM.
wait until
(qdpo_clk'event and qdpo_clk = '1') or
(c_has_qdpo_rst = 1 and qdpo_rst = '1');
end if;
if c_has_qdpo_rst = 1 and qdpo_rst = '1' then
-- Async reset asserted.
qdpo_pipe <= (others => '0');
qdpo_int <= (others => '0');
elsif c_has_qdpo_srst = 1 and qdpo_srst = '1' then
if c_sync_enable = 0 then
--Synchronous reset asserted. Sync reset overrides the
--clock enable
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
elsif c_qce_joined = 0 then
-- Seperate qdpo_clk domain
if c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce_int = '1') then
-- Either the qdpo does not have a clock enable, or it
-- does, and it has been asserted permitting the sync
-- reset to act.
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
end if;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
-- Common clock domain so we monitor the common clock
-- enable to see if the a sync reset is permitted, or there
-- are no clock enables to block the sync reset.
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
end if;
elsif c_qce_joined = 0 then
-- qdpo is a seperate clock domain, so check to see if there
-- is a qdpo_ce clock enable, if it is there, assign qdpo when
-- qdpo_ce is active - if there is no clock enable just assign
-- it.
if c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce_int = '1') then
qdpo_pipe <= dpo_int after C_TCQ;
if c_pipeline_stages = 1 then
qdpo_int <= qdpo_pipe after C_TCQ;
else
qdpo_int <= dpo_int after C_TCQ;
end if;
end if;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
-- Common clock domain, check to see if there is a qspo_ce to
-- concern us.
qdpo_pipe <= dpo_int after C_TCQ;
if c_pipeline_stages = 1 then
qdpo_int <= qdpo_pipe after C_TCQ;
else
qdpo_int <= dpo_int after C_TCQ;
end if;
end if;
end process p_has_qdpo;
---------------------------------------------------------------------
qdpo <= qdpo_int;
end behavioral;
| mit | 192b1a5a9d2065a5f93d0d328a3121e6 | 0.495392 | 4.084517 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/sim/zynq_1_axi_gpio_0_0.vhd | 3 | 9,104 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY zynq_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_axi_gpio_0_0;
ARCHITECTURE zynq_1_axi_gpio_0_0_arch OF zynq_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 32,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_1_axi_gpio_0_0_arch;
| mit | 6417f54516bae56e42b7027ee929e736 | 0.678822 | 3.218098 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b_@f060/_primary.vhd | 3 | 9,695 | library verilog;
use verilog.vl_types.all;
entity MSS_AHB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHADDR : out vl_logic_vector(19 downto 0);
MSSHWDATA : out vl_logic_vector(31 downto 0);
MSSHTRANS : out vl_logic_vector(1 downto 0);
MSSHSIZE : out vl_logic_vector(1 downto 0);
MSSHLOCK : out vl_logic;
MSSHWRITE : out vl_logic;
MSSHRDATA : in vl_logic_vector(31 downto 0);
MSSHREADY : in vl_logic;
MSSHRESP : in vl_logic;
FABHADDR : in vl_logic_vector(31 downto 0);
FABHWDATA : in vl_logic_vector(31 downto 0);
FABHTRANS : in vl_logic_vector(1 downto 0);
FABHSIZE : in vl_logic_vector(1 downto 0);
FABHMASTLOCK : in vl_logic;
FABHWRITE : in vl_logic;
FABHSEL : in vl_logic;
FABHREADY : in vl_logic;
FABHRDATA : out vl_logic_vector(31 downto 0);
FABHREADYOUT : out vl_logic;
FABHRESP : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
ADC12 : in vl_logic;
ADC13 : in vl_logic;
ADC14 : in vl_logic;
ADC15 : in vl_logic;
ADC16 : in vl_logic;
ADC17 : in vl_logic;
ADC18 : in vl_logic;
ADC19 : in vl_logic;
ADC20 : in vl_logic;
ADC21 : in vl_logic;
ADC22 : in vl_logic;
ADC23 : in vl_logic;
ADC24 : in vl_logic;
ADC25 : in vl_logic;
SDD0 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
TM0 : in vl_logic;
CM0 : in vl_logic;
GNDTM0 : in vl_logic;
VAREF0 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_AHB_F060;
| gpl-3.0 | 7040f411c69a0d761007afb8c730f79e | 0.407117 | 3.661254 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/Flash/flashio.vhd | 1 | 5,802 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 20:30:32 11/30/2013
-- Design Name:
-- Module Name: flashio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity flashio is
port(
-- ×ÖģʽÏÂΪ22-1£¬×Ö½ÚģʽΪ22-0
KEY16_INPUT: in std_logic_vector(15 downto 0);
LED_output: out std_logic_vector(15 downto 0);
led1: out std_logic_vector(6 downto 0);
clk: in std_logic;
reset: in std_logic;
flash_byte : out std_logic;
flash_vpen : out std_logic;
flash_ce : out std_logic;
flash_oe : out std_logic;
flash_we : out std_logic;
flash_rp : out std_logic;
flash_addr : out std_logic_vector(22 downto 1);
flash_data : inout std_logic_vector(15 downto 0);
addr_ram1: out std_logic_vector(15 downto 0)
);
end flashio;
architecture Behavioral of flashio is
type flash_state is (
waiting,
write1, write2, write3, write4, write5,
read1, read2, read3, read4,
sr1, sr2, sr3, sr4, sr5,
erase1, erase2, erase3, erase4, erase5, erase6,
done
);
signal state : flash_state := waiting;
signal next_state : flash_state := waiting;
signal ctl_read_last, ctl_write_last, ctl_erase_last : std_logic;
signal dataout: std_logic_vector(15 downto 0);
signal addr: std_logic_vector(22 downto 1);
signal ctl_read : std_logic := '0';
signal ctl_write :std_logic:= '0';
signal ctl_erase :std_logic:= '0';
signal datain: std_logic_vector(15 downto 0);
component LED16
Port(
LED_output : out std_logic_vector(15 downto 0);
input : in std_logic_vector(15 downto 0)
);
end component;
component LED_seg7
Port(
input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
signal tmp : std_logic_vector(3 downto 0);
begin
l1: LED16 port map (LED_output => LED_output, input => dataout);
l3: LED16 port map (LED_output => addr_ram1, input => datain);
l2: LED_seg7 port map(input => addr(4 downto 1), output => led1);
tmp <= '0' & ctl_read & ctl_write & ctl_erase;
addr <= "000000000000000" & KEY16_INPUT(6 downto 0);
datain <= KEY16_INPUT(12 downto 7) & "0000000000";
ctl_read <= key16_input(15);
ctl_write <= key16_input(14);
ctl_erase <= key16_input(13);
-- always set 1 for ×Öģʽ
flash_byte <= '1';
-- write protect, always 1
flash_vpen <= '1';
-- ce is enable, 0 is selected, 1 is not.
flash_ce <= '0';
-- 0 is reset, 1 is work, always 1
flash_rp <= '1';
process(clk, reset)
begin
if (reset = '0') then
dataout <= (others => '0');
flash_oe <= '1';
flash_we <= '1';
state <= waiting;
next_state <= waiting;
ctl_read_last <= ctl_read;
ctl_write_last <= ctl_write;
ctl_erase_last <= ctl_erase;
flash_data <= (others => 'Z');
elsif (clk'event and clk = '1') then
case state is
-- wait(initial)
when waiting =>
-- store last so you can change the value
-- to triggle the action when necessary
if (ctl_read /= ctl_read_last) then
flash_we <= '0';
state <= read1;
ctl_read_last <= ctl_read;
elsif (ctl_write /= ctl_write_last) then
flash_we <= '0';
state <= write1;
ctl_write_last <= ctl_write;
elsif (ctl_erase /= ctl_erase_last) then
flash_we <= '0';
dataout(0) <= '0';
state <= erase1;
ctl_erase_last <= ctl_erase;
end if;
-- write
when write1 =>
flash_data <= x"0040";
state <= write2;
when write2 =>
flash_we <= '1';
state <= write3;
when write3 =>
flash_we <= '0';
state <= write4;
when write4 =>
flash_addr <= addr;
flash_data <= datain;
state <= write5;
when write5 =>
flash_we <= '1';
state <= sr1;
next_state <= done;
-- small loop CM in write
-- write 6 is sr1
when sr1 =>
flash_we <= '0';
flash_data <= x"0070";
state <= sr2;
when sr2 =>
flash_we <= '1';
state <= sr3;
when sr3 =>
flash_data <= (others => 'Z');
state <= sr4;
when sr4 =>
flash_oe <= '0';
state <= sr5;
when sr5 =>
flash_oe <= '1';
if flash_data(7) = '0' then
state <= sr1;
else
state <= next_state;
end if;
-- read
when read1 =>
flash_data <= x"00FF";
state <= read2;
when read2 =>
flash_we <= '1';
state <= read3;
when read3 =>
flash_oe <= '0';
flash_addr <= addr;
flash_data <= (others => 'Z');
state <= read4;
when read4 =>
dataout <= flash_data;
state <= done;
-- erase
when erase1 =>
flash_data <= x"0020";
state <= erase2;
when erase2 =>
flash_we <= '1';
state <= erase3;
when erase3 =>
flash_we <= '0';
state <= erase4;
when erase4 =>
flash_data <= x"00D0";
flash_addr <= addr;
state <= erase5;
when erase5 =>
flash_we <= '1';
next_state <= erase6;
state <= sr1;
-- jump to sr1
-- return back from sr5
when erase6 =>
state <= done;
dataout(0) <= '1';
when others =>
flash_oe <= '1';
flash_we <= '1';
flash_data <= (others => 'Z');
state <= waiting;
end case;
end if;
end process;
end Behavioral;
| mit | d397a0dcff5ab7810ca9ef6a1352b6f2 | 0.567391 | 2.952672 | false | false | false | false |
dsd-g05/lab5 | g05_minimum3.vhd | 1 | 840 | -- Descp. Compares two 3bit numbers and outputs the smallest one
--
-- entity name: g05_minimum3
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: October 5, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_minimum3 is
port (
N, M : in std_logic_vector(2 downto 0);
min : out std_logic_vector(2 downto 0)
);
end g05_minimum3;
architecture behavior of g05_minimum3 is
signal AltB, AeqB, AgtB : std_logic;
signal i : std_logic_vector(2 downto 0);
begin
i <= N xnor M;
AeqB <= i(0) and i(1) and i(2);
AgtB <= (N(2) and not M(2)) or
(N(1) and not M(1) and i(2)) or
(N(0) and not M(0) and i(2) and i(1));
AltB <= AeqB nor AgtB;
min <= M when AltB = '0' else N;
end behavior; | mit | 9b0758146ea6eec166c2bb5dd0b55c03 | 0.609524 | 2.978723 | false | false | false | false |
6769/VHDL | Lab_3/Part01/FSM_core.vhd | 1 | 1,288 | library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:bit_vector(3 downto 0);
alias Q0:bit is State(0);
alias Q1:bit is State(1);
alias Q2:bit is State(2);
alias Q3:bit is State(3);
begin
stateout<=to_integer(unsigned(State));
Z<=(Q3 or Q2 )and not Q1 and not Q0;
--Q0`=x(q0'q1'+q0q2+q1q0')+x'(q3'q2'+q2q0')
nextState(0)<=(X and ((not Q0 and not Q2) or (Q0 and Q2)or (Q1 and not Q0)))or (not X and ((not Q3 and not Q2)or (Q2 and not Q0 )));
nextState(1)<=(x and ((Q1 and not Q0 and not Q2)or (not Q1 and Q0 and not Q2)))or(not x and ((not Q1 and Q0 and Q2)or (Q1 and not Q0 and Q2) )) ;
nextState(2)<=(X and ( (not Q1 and not Q0 and Q2) or (Q1 and Q0 and not Q2) ))or(not X and ( (not Q3 and not Q2) or (Q1 and not Q0 ) or (not Q1 and Q2) ));
nextState(3)<=not X and ( (Q3 and not Q2) or (Q1 and Q0 and Q2) );
process(CLK,reset)
begin
if reset='0' then State<="0000";
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
| gpl-2.0 | 16bf9db3a66c2559a52f100794b705ed | 0.618012 | 2.661157 | false | false | false | false |
6769/VHDL | Lab_5/SingluarUnit/controller/controller.vhd | 1 | 1,077 | entity Controller_2 is
port(
Rb,Reset,Eq,D7,D711,D2312,CLK:in bit;
State_debug:out integer range 0 to 3;
Sp,Roll,Win,Lose,Clear:out bit:='0');
end entity Controller_2;
architecture Behavior of Controller_2 is
signal State,NextState:integer range 0 to 3:=0;
begin
State_debug<=State;
process(Rb,Reset,State,Eq,D7,D711,D2312)
begin
--Roll<=Rb;
case State is
when 0 =>
if(D711='1')then Win<='1';NextState<=2;
elsif(D2312='1') then Lose<='1';NextState<=3;
else NextState<=1;Sp<='1';
end if;
when 2=>
if(Reset='1') then Win<='0';Lose<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 3=>
if(Reset='1') then Lose<='0';Win<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 1=>
if(Eq='1')then Win<='1' ;NextState<=2;
elsif(D7='1')then Lose<='1';NextState<=3;
end if;
end case;
end process;
Roll<=Rb;
Clear<='1' when Reset='1' and (State=2 or State=3) else '0';
process(CLK)
begin
if CLK'event and CLK = '1' then
State <= NextState;
end if;
end process;
end architecture Behavior;
| gpl-2.0 | 15329fac0ffc26f0f563b48bcbae6b22 | 0.61467 | 2.672457 | false | false | false | false |
dsd-g05/lab5 | g05_mastermind_game.vhd | 1 | 7,142 | -- Descp.
--
-- entity name: g05_mastermind_game
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 26, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_game is
port (
start, ready : in std_logic;
sel, increment : in std_logic;
mode : in std_logic;
clk : in std_logic;
seg_1, seg_2, seg_3, seg_4, seg_5, seg_6 : out std_logic_vector(6 downto 0)
);
end g05_mastermind_game;
architecture behavior of g05_mastermind_game is
component g05_mastermind_controller is
port (
TM_OUT : in std_logic;
SC_CMP, TC_LAST : in std_logic;
START, READY : in std_logic;
MODE : in std_logic;
CLK : in std_logic;
START_MODE : out std_logic;
DEFAULT_SCORE : out std_logic;
SR_SEL, P_SEL, GR_SEL : out std_logic;
GR_LD, SR_LD : out std_logic;
TM_IN, TM_EN, TC_EN, TC_RST : out std_logic;
SOLVED : out std_logic
);
end component;
component g05_mastermind_datapath is
port (
P_SEL, GR_SEL, SR_SEL : in std_logic;
GR_LD, SR_LD : in std_logic;
TM_IN, TM_EN, TC_RST, TC_EN : in std_logic;
EXT_PATTERN : in std_logic_vector(11 downto 0);
EXT_SCORE : in std_logic_vector(3 downto 0);
MODE : in std_logic;
START_MODE : in std_logic;
CLK : in std_logic;
TM_OUT : out std_logic;
TC_LAST : out std_logic;
SC_CMP : out std_logic;
DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : out std_logic_vector(3 downto 0)
);
end component;
signal P_SEL, GR_SEL, SR_SEL : std_logic;
signal GR_LD, SR_LD : std_logic;
signal TM_IN, TM_OUT, TM_EN, TC_RST, TC_EN : std_logic;
signal TC_LAST : std_logic;
signal SC_CMP : std_logic;
signal SOLVED : std_logic;
signal tmp_P5, tmp_P6 : std_logic_vector(3 downto 0);
signal DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : std_logic_vector(3 downto 0);
signal START_MODE, DEFAULT_SCORE : std_logic;
component g05_pattern_input is
port (
increment, sel : in std_logic;
seg_code : out std_logic_vector(2 downto 0);
segment : out std_logic_vector(1 downto 0)
);
end component;
signal seg_code : std_logic_vector(2 downto 0);
signal segment : std_logic_vector(1 downto 0);
signal ext_p1, ext_p2, ext_p3, ext_p4 : std_logic_vector(2 downto 0);
signal ext_pattern : std_logic_vector(11 downto 0);
component g05_score_input is
port (
increment, sel : in std_logic;
score : out std_logic_vector(2 downto 0);
score_part : out std_logic
);
end component;
signal score : std_logic_vector(2 downto 0);
signal exact_matches, color_matches : std_logic_vector(2 downto 0);
signal score_part : std_logic;
component g05_score_encoder is
port (
score_code : out std_logic_vector(3 downto 0);
num_exact_matches : in std_logic_vector(2 downto 0);
num_color_matches : in std_logic_vector(2 downto 0)
);
end component;
signal encoded_score : std_logic_vector(3 downto 0);
component g05_7_segment_decoder is
port (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
end component;
begin
pattern_input : g05_pattern_input
port map (increment => increment, sel => sel,
seg_code => seg_code, segment => segment);
ext_p1 <= seg_code when segment = "00";
ext_p2 <= seg_code when segment = "01";
ext_p3 <= seg_code when segment = "10";
ext_p4 <= seg_code when segment = "11";
ext_pattern <= ext_p1 & ext_p2 & ext_p3 & ext_p4;
score_input : g05_score_input
port map (increment => increment, sel => sel,
score => score, score_part => score_part);
exact_matches <= score when score_part = '1';
color_matches <= score when score_part = '0';
encoder : g05_score_encoder
port map (num_exact_matches => exact_matches, num_color_matches => color_matches,
score_code => encoded_score);
controller : g05_mastermind_controller
port map (SC_CMP => SC_CMP, TC_LAST => TC_LAST, START => start, READY => ready,
MODE => mode, CLK => clk, SR_SEL => SR_SEL, P_SEL => P_SEL, GR_SEL => GR_SEL,
GR_LD => GR_LD, SR_LD => SR_LD, TM_IN => TM_IN, TM_EN => TM_EN, TC_EN => TC_EN,
TC_RST => TC_RST, SOLVED => SOLVED, TM_OUT => TM_OUT, START_MODE => START_MODE, DEFAULT_SCORE => DEFAULT_SCORE);
datapath : g05_mastermind_datapath
port map (P_SEL => P_SEL, GR_SEL => GR_SEL, SR_SEL => SR_SEL, GR_LD => GR_LD, SR_LD => SR_LD,
TM_IN => TM_IN, TM_OUT => TM_OUT, TM_EN => TM_EN, TC_RST => TC_RST, TC_EN => TC_EN, EXT_PATTERN => ext_pattern,
EXT_SCORE => encoded_score, MODE => mode, CLK => clk, TC_LAST => TC_LAST, SC_CMP => SC_CMP,
DIS_P1 => DIS_P1, DIS_P2 => DIS_P2, DIS_P3 => DIS_P3, DIS_P4 => DIS_P4, DIS_P5 => tmp_P5, DIS_P6 => tmp_P6, START_MODE => START_MODE);
process(clk, START_MODE)
begin
if START_MODE = '0' then
if rising_edge(clk) then
if DEFAULT_SCORE = '0' then
if MODE = '1' then
DIS_P5 <= tmp_P5;
DIS_P6 <= tmp_P6;
else
DIS_P5 <= '0' & color_matches;
DIS_P6 <= '0' & exact_matches;
end if;
else
DIS_P5 <= "0000";
DIS_P6 <= "0000";
end if;
end if;
else
DIS_P5 <= "0101"; -- S
DIS_P6 <= "0000"; --
end if;
end process;
segment1 : g05_7_segment_decoder
port map (code => DIS_P1, RippleBlank_In => '0', segments => seg_1);
segment2 : g05_7_segment_decoder
port map (code => DIS_P2, RippleBlank_In => '0', segments => seg_2);
segment3 : g05_7_segment_decoder
port map (code => DIS_P3, RippleBlank_In => '0', segments => seg_3);
segment4 : g05_7_segment_decoder
port map (code => DIS_P4, RippleBlank_In => '0', segments => seg_4);
segment5 : g05_7_segment_decoder
port map (code => DIS_P5, RippleBlank_In => '0', segments => seg_5);
segment6 : g05_7_segment_decoder
port map (code => DIS_P6, RippleBlank_In => '0', segments => seg_6);
end behavior; | mit | e5ca0132d4fe4c9cbb51af90305a4e8e | 0.522543 | 3.420498 | false | false | false | false |
frankvanbever/MIPS_processor | testbenches/ALU_Control_tb.vhd | 1 | 3,076 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:31 03/06/2013
-- Design Name:
-- Module Name: /home/steven/Documenten/Codes/pcarch/MIPSmodules/ALU_Control_tb.vhd
-- Project Name: MIPSmodules
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU_Control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_Control_tb IS
END ALU_Control_tb;
ARCHITECTURE behavior OF ALU_Control_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_Control
PORT(
ALU_OP : IN std_logic_vector(1 downto 0);
ALU_Funct_In : IN std_logic_vector(5 downto 0);
ALU_Control_out : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal ALU_OP : std_logic_vector(1 downto 0) := (others => '0');
signal ALU_Funct_In : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALU_Control_out : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
signal clk: std_logic;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_Control PORT MAP (
ALU_OP => ALU_OP,
ALU_Funct_In => ALU_Funct_In,
ALU_Control_out => ALU_Control_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
ALU_OP<="00";
ALU_Funct_In<="100000"; --test for add 0010
wait for clk_period*10;
ALU_Funct_In<="101010"; --test for add 2 0010
wait for clk_period*10;
ALU_Funct_In<="100000";
ALU_OP<="01"; --test for branch equal 0110
wait for clk_period*10;
ALU_OP<="10"; --test for add 0010
wait for clk_period*10;
ALU_Funct_In<="100010"; --test for substract 0110
wait for clk_period*10;
ALU_Funct_In<="100100"; --test for AND 0000
wait for clk_period*10;
ALU_Funct_In<="100101"; --test for OR 0001
wait for clk_period*10;
ALU_Funct_In<="101010"; --test for slt 0111
wait;
end process;
END;
| mit | 8f3e522dc7d4987036d8fb01b65eee16 | 0.611508 | 3.491487 | false | true | false | false |
6769/VHDL | Lab_5/__FromSaru/lab50/point_register.vhd | 1 | 501 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity point_register is
--latch the last value--
port(sp:in bit;
point:out std_logic_vector(3 downto 0):="0000";
sum:in std_logic_vector(3 downto 0));
end point_register;
architecture point of point_register is
--signal count:bit;
begin
process(sp,sum)
begin
if sp='0' then
--count<='0';
elsif sp='1' then
--count<='1';
point<=sum;
end if;
end process;
end point; | gpl-2.0 | 292d1f112e2d8873e090b182a2b656ea | 0.636727 | 3.211538 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/blk_mem_gen_wrapper.vhd | 12 | 33,638 | -------------------------------------------------------------------------------
-- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $
-------------------------------------------------------------------------------
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
-- Version: v1.00a
-- Description:
-- This wrapper file performs the direct call to Block Memory Generator
-- during design implementation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- blk_mem_gen_wrapper.vhd
-- |
-- |-- blk_mem_gen_v2_7
-- |
-- |-- blk_mem_gen_v6_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: MW
-- Revision: $Revision: 1.1.2.69 $
-- Date: $7/11/2008$
--
-- History:
-- MW 7/11/2008 Initial Version
-- MSH 2/26/2009 Add new blk_mem_gen version
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2 instance callout
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2
-- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3
-- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6.
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/27/2010 EDK 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6
-- and later build case.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated to blk_mem_gen V5.2.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated to blk_mem_gen V6.1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Regressed back to blk_mem_gen V5.2
-- ^^^^^^
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use blk_mem_gen_v6_2 for s6, v6, and later.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2
-- instance.
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--Library XilinxCoreLib;
-- synopsys translate_on
library blk_mem_gen_v8_1;
library proc_common_v4_0;
use blk_mem_gen_v8_1.all;
--use proc_common_v4_0.coregen_comp_defs.all;
use proc_common_v4_0.family_support.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex5";
-- "Virtex2"
-- "Virtex4"
-- "Virtex5"
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until clka = '1';
wait until clka = '0';
Wait until clka = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr <= '0' ; -- : out std_logic;
sbiterr <= '0' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_1.blk_mem_gen_v8_1
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
C_RST_TYPE => "SYNC" ,
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
| mit | d33131d277ea952dd62ef644299e763a | 0.362715 | 4.666759 | false | false | false | false |
fpgaddicted/car_taillights_animation-engine | signal_mux.vhd | 1 | 1,388 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: fpgaddicted (Stefan Naco)
--
-- Create Date: 22:38:28 05/16/2017
-- Design Name:
-- Module Name: signal_mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity signal_mux is
Port ( sel : in STD_LOGIC;
sig_out : out STD_LOGIC_VECTOR (2 downto 0);
sig_turn : in STD_LOGIC_VECTOR (2 downto 0);
sig_alarm : in STD_LOGIC_VECTOR (2 downto 0));
end signal_mux;
architecture Behavioral of signal_mux is
begin
process(sel,sig_turn,sig_alarm)
begin
case sel is
when '0' => sig_out <= sig_turn;
when '1' => sig_out <= sig_alarm;
when others => sig_out <= "XXX";
end case;
end process;
end Behavioral;
| gpl-3.0 | 050b312340caa3d49f2a9a32ace2ee6d | 0.557637 | 3.701333 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wrap_brst.vhd | 7 | 51,441 | -------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
| mit | 8129d07908f7da11d8092731ed656af5 | 0.409868 | 4.42351 | false | false | false | false |
1995parham/FPGA-Homework | HW-1/src/p4-1-2/p4-1.vhd | 1 | 1,507 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 04-03-2016
-- Module Name: p4-1.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity four_bit_comparator is
port (a, b : in std_logic_vector(3 downto 0);
l, g, e : in std_logic;
eq, gt, lt : out std_logic);
end entity four_bit_comparator;
architecture structural of four_bit_comparator is
signal a0_b0_eq, a0_b0_gt, a0_b0_lt : std_logic;
signal a1_b1_eq, a1_b1_gt, a1_b1_lt : std_logic;
signal a2_b2_eq, a2_b2_gt, a2_b2_lt : std_logic;
signal a3_b3_eq, a3_b3_gt, a3_b3_lt : std_logic;
begin
a0_b0_gt <= a(0) and (not b(0));
a0_b0_lt <= (not a(0)) and b(0);
a0_b0_eq <= a(0) xor b(0);
a1_b1_gt <= a(1) and (not b(1));
a1_b1_lt <= (not a(1)) and b(1);
a1_b1_eq <= a(1) xor b(1);
a2_b2_gt <= a(2) and (not b(2));
a2_b2_lt <= (not a(2)) and b(2);
a2_b2_eq <= a(2) xor b(2);
a3_b3_gt <= a(3) and (not b(3));
a3_b3_lt <= (not a(3)) and b(3);
a3_b3_eq <= a(3) xor b(3);
eq <= a3_b3_eq and a2_b2_eq and a1_b1_eq and a0_b0_eq;
gt <= a3_b3_gt or (a2_b2_gt and a3_b3_eq) or (a1_b1_gt and a2_b2_eq and a3_b3_eq)
or (a0_b0_gt and a1_b1_eq and a2_b2_eq and a3_b3_eq);
lt <= a3_b3_lt or (a2_b2_lt and a3_b3_eq) or (a1_b1_lt and a2_b2_eq and a3_b3_eq)
or (a0_b0_lt and a1_b1_eq and a2_b2_eq and a3_b3_eq);
end architecture structural;
| gpl-3.0 | 2ca44d735c2aa8ecfc143cf8859dc566 | 0.53351 | 2.075758 | false | false | false | false |
dsd-g05/lab5 | g05_mastermind_datapath.vhd | 1 | 6,713 | -- Descp. mastermind datapath
--
-- entity name: g05_mastermind_datapath
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 23, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_datapath is
port (
P_SEL, GR_SEL, SR_SEL : in std_logic;
GR_LD, SR_LD : in std_logic;
TM_IN, TM_EN, TC_RST, TC_EN : in std_logic;
EXT_PATTERN : in std_logic_vector(11 downto 0);
EXT_SCORE : in std_logic_vector(3 downto 0);
MODE : in std_logic;
START_MODE : in std_logic;
CLK : in std_logic;
TM_OUT : out std_logic;
TC_LAST : out std_logic;
SC_CMP : out std_logic;
DIS_P1, DIS_P2, DIS_P3, DIS_P4, DIS_P5, DIS_P6 : out std_logic_vector(3 downto 0)
);
end g05_mastermind_datapath;
architecture behavior of g05_mastermind_datapath is
component g05_mastermind_score is
port (
P1, P2, P3, P4 : in std_logic_vector(2 downto 0);
G1, G2, G3, G4 : in std_logic_vector(2 downto 0);
exact_match_score : out std_logic_vector(2 downto 0);
color_match_score : out std_logic_vector(2 downto 0);
score_code : out std_logic_vector(3 downto 0)
);
end component;
component g05_possibility_table is
port (
TC_EN : in std_logic;
TC_RST : in std_logic;
TM_IN : in std_logic;
TM_EN : in std_logic;
CLK : in std_logic;
TC_LAST : out std_logic;
TM_ADDR : out std_logic_vector(11 downto 0);
TM_OUT : out std_logic
);
end component;
component g05_comp6 is
port (
A : in std_logic_vector(5 downto 0);
B : in std_logic_vector(5 downto 0);
AeqB : out std_logic
);
end component;
component g05_color_decoder is
port (
color : in std_logic_vector(2 downto 0);
color_code : out std_logic_vector(3 downto 0)
);
end component;
component g05_score_decoder is
port (
score_code : in std_logic_vector(3 downto 0);
num_exact_matches, num_color_matches : out std_logic_vector(3 downto 0)
);
end component;
signal P1, P2, P3, P4 : std_logic_vector(2 downto 0);
signal G1, G2, G3, G4 : std_logic_vector(2 downto 0);
signal TM_ADDR : std_logic_vector(11 downto 0);
signal score, score_reg, SR : std_logic_vector(3 downto 0);
signal G1_code, G2_code, G3_code, G4_code, P1_code, P2_code, P3_code, P4_code : std_logic_vector(3 downto 0);
signal num_exact_matches, num_color_matches : std_logic_vector(3 downto 0);
begin
P4 <= EXT_PATTERN(2 downto 0) when P_SEL = '0' else TM_ADDR(2 downto 0);
P3 <= EXT_PATTERN(5 downto 3) when P_SEL = '0' else TM_ADDR(5 downto 3);
P2 <= EXT_PATTERN(8 downto 6) when P_SEL = '0' else TM_ADDR(8 downto 6);
P1 <= EXT_PATTERN(11 downto 9) when P_SEL = '0' else TM_ADDR(11 downto 9);
process(CLK)
begin
if (rising_edge(CLK)) then
if (GR_LD = '1') then
if (GR_SEL = '0') then
G1 <= TM_ADDR(2 downto 0);
G2 <= TM_ADDR(5 downto 3);
G3 <= TM_ADDR(8 downto 6);
G4 <= TM_ADDR(11 downto 9);
else
G1 <= "001";
G2 <= "001";
G3 <= "000";
G4 <= "000";
end if;
end if;
end if;
end process;
G1_decode : g05_color_decoder
port map (color => G1, color_code => G1_code);
G2_decode : g05_color_decoder
port map (color => G2, color_code => G2_code);
G3_decode : g05_color_decoder
port map (color => G3, color_code => G3_code);
G4_decode : g05_color_decoder
port map (color => G4, color_code => G4_code);
P1_decode : g05_color_decoder
port map (color => P1, color_code => P1_code);
P2_decode : g05_color_decoder
port map (color => P2, color_code => P2_code);
P3_decode : g05_color_decoder
port map (color => P3, color_code => P3_code);
P4_decode : g05_color_decoder
port map (color => P4, color_code => P4_code);
process(CLK, START_MODE, MODE)
begin
if (rising_edge(CLK)) then
if START_MODE = '0' then
if MODE = '0' then
DIS_P1 <= G1_code;
DIS_P2 <= G2_code;
DIS_P3 <= G3_code;
DIS_P4 <= G4_code;
DIS_P5 <= num_color_matches;
DIS_P6 <= num_exact_matches;
else
DIS_P1 <= P1_code;
DIS_P2 <= P2_code;
DIS_P3 <= P3_code;
DIS_P4 <= P4_code;
DIS_P5 <= num_color_matches;
DIS_P6 <= num_exact_matches;
end if;
else
DIS_P1 <= "0111"; -- T
DIS_P2 <= "1011"; -- R
DIS_P3 <= "1000"; -- A
DIS_P4 <= "0111"; -- T
DIS_P5 <= "0101"; -- S
DIS_P6 <= "0000"; --
end if;
end if;
end process;
mastermind_score : g05_mastermind_score
port map (P1 => P1, P2 => P2, P3 => P3, P4 => P4,
G1 => G1, G2 => G2, G3 => G3, G4 => G4,
score_code => score);
process(CLK)
begin
if rising_edge(CLK) then
if SR_LD = '1' then
if MODE = '0' then
score_reg <= EXT_SCORE;
else
score_reg <= score;
end if;
end if;
end if;
end process;
decode : g05_score_decoder
port map (score_code => score_reg, num_exact_matches => num_exact_matches, num_color_matches => num_color_matches);
SR <= score when SR_SEL = '0' else "0000";
score_comp : g05_comp6
port map (A(5 downto 4) => "00", A(3 downto 0) => score_reg,
B(5 downto 4) => "00", B(3 downto 0) => SR, AeqB => SC_CMP);
possibility_table : g05_possibility_table
port map (TC_EN => TC_EN, TC_RST => TC_RST, TM_IN => TM_IN,
TM_EN => TM_EN, CLK => CLK, TC_LAST => TC_LAST,
TM_ADDR => TM_ADDR, TM_OUT => TM_OUT);
end behavior; | mit | ac046eb1dd830d794a68c0b22b73b1ef | 0.485178 | 3.446099 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_lite.vhd | 7 | 95,564 | -------------------------------------------------------------------------------
-- axi_lite.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite.vhd
--
-- Description: This file is the top level module for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Update BRAM address mapping to lite_ecc_reg module. Corrected
-- signal size for XST detected unused bits in vector.
-- Plus minor code cleanup.
--
-- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add Hsiao ECC algorithm logic (similar to full_axi module HDL).
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move REG_RDATA register process out from C_ECC_TYPE generate block
-- to C_ECC generate block.
-- ^^^^^^
-- JLJ 3/22/2011 v1.03a
-- ~~~~~~
-- Add LUT level with reset signal to combinatorial outputs, AWREADY
-- and WREADY. This will ensure that the output remains LOW during reset,
-- regardless of AWVALID or WVALID input signals.
-- ^^^^^^
-- JLJ 3/28/2011 v1.03a
-- ~~~~~~
-- Remove combinatorial output paths on AWREADY and WREADY.
-- Combine AWREADY and WREADY registers.
-- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY
-- (but only for non ECC configurations).
-- Create 3-bit counter for BVALID response, seperate from AW/W channels.
--
-- Delay assertion of WREADY in ECC configurations to minimize register
-- resource utilization.
-- No pre-assertion of ARREADY in ECC configurations (due to write latency
-- with ECC enabled).
--
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Update Sl_CE and Sl_UE flag assertions to a single clock cycle.
-- Clean up comments.
-- ^^^^^^
-- JLJ 4/19/2011 v1.03a
-- ~~~~~~
-- Update BVALID assertion when ECC is enabled to match the implementation
-- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Modify FaultInjectClr signal assertion. With BVALID counter, delay
-- when fault inject register gets cleared.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 7/7/2011 v1.03a
-- ~~~~~~
-- Fix DV regression failure with reset.
-- Hold off BRAM enable output with active reset signal.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.lite_ecc_reg;
use work.parity;
use work.checkbit_handler;
use work.correct_one_bit;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_lite is
generic (
C_S_AXI_PROTOCOL : string := "AXI4LITE";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : integer := 1;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- Unused AW AXI-Lite Signals
-- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- AXI_AWLEN : in std_logic_vector(7 downto 0);
-- AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- AXI_AWBURST : in std_logic_vector(1 downto 0);
-- AXI_AWLOCK : in std_logic; -- Currently unused
-- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
-- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
-- *** AXI Write Data Channel Signals (W) ***
AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- Unused W AXI-Lite Signals
-- AXI_WLAST : in std_logic;
-- *** AXI Write Data Response Channel Signals (B) ***
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- Unused B AXI-Lite Signals
-- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- *** AXI Read Data Channel Signals (R) ***
AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- *** AXI-Lite ECC Register Interface Signals ***
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** BRAM Port A Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
-- Note: Remove BRAM_RdData_A port (unused in dual port mode)
-- Platgen will keep port open on BRAM block
-- *** BRAM Port B Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC
);
end entity axi_lite;
-------------------------------------------------------------------------------
architecture implementation of axi_lite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future implementation.
-- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8;
-- Internal data width based on C_S_AXI_DATA_WIDTH.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type LITE_SM_TYPE is ( IDLE,
SNG_WR_DATA,
RD_DATA,
RMW_RD_DATA,
RMW_MOD_DATA,
RMW_WR_DATA
);
signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE;
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_reg : std_logic := '0';
signal axi_arready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
signal axi_wready_cmb : std_logic := '0';
signal axi_wready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_set_r : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
signal axi_rlast_set_r : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0');
signal bram_en_a_cmb : std_logic := '0';
signal bram_en_b_cmb : std_logic := '0';
signal bram_en_a_int : std_logic := '0';
signal bram_en_b_int : std_logic := '0';
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC
-------------------------------------------------------------------------------
-- Internal ECC Signals
-------------------------------------------------------------------------------
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal UE_Q : std_logic := '0';
signal Enable_ECC : std_logic := '0';
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate
GEN_NO_REGS: if (C_ECC = 0) generate
begin
AXI_CTRL_AWREADY <= '0';
AXI_CTRL_WREADY <= '0';
AXI_CTRL_BRESP <= (others => '0');
AXI_CTRL_BVALID <= '0';
AXI_CTRL_ARREADY <= '0';
AXI_CTRL_RDATA <= (others => '0');
AXI_CTRL_RRESP <= (others => '0');
AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
BRAM_Addr_En <= '0';
-----------------------------------------------------------------------
-- Generate: GEN_DIS_ECC
-- Purpose: Disable ECC in read path when ECC is disabled in core.
-----------------------------------------------------------------------
GEN_DIS_ECC: if C_ECC = 0 generate
Enable_ECC <= '0';
end generate GEN_DIS_ECC;
-- For future implementation.
--
-- -----------------------------------------------------------------------
-- -- Generate: GEN_EN_ECC
-- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available.
-- -- ECC on/off control register is not accessible (so ECC is always
-- -- enabled in this configuraiton).
-- -----------------------------------------------------------------------
-- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate
-- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC
-- -- ECC registers are available. Therefore, ECC
-- -- is always enabled.
-- end generate GEN_EN_ECC;
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_CTRL_AWVALID => AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC
);
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0';
Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
end generate GEN_REGS;
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
-- AXI_AWREADY <= axi_awready_cmb;
-- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a
AXI_AWREADY <= axi_wready_int; -- v1.03a
-- AXI Write Data Channel Output Signals
-- AXI_WREADY <= axi_wready_cmb;
-- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a
AXI_WREADY <= axi_wready_int; -- v1.03a
-- AXI Write Response Channel Output Signals
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
-- AXI Read Address Channel Output Signals
-- AXI_ARREADY <= axi_arready_cmb; -- v1.03a
AXI_ARREADY <= axi_arready_int; -- v1.03a
-- AXI Read Data Channel Output Signals
-- AXI_RRESP <= axi_rresp_int;
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
-- AXI_RDATA <= axi_rdata_int;
-- Move assignment of RDATA to generate statements based on C_ECC.
AXI_RVALID <= axi_rvalid_int;
AXI_RLAST <= axi_rlast_int;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
-- Notes:
-- No address pipelining for AXI-Lite.
-- PDR feedback.
-- Remove address register stage to BRAM.
-- Rely on registers in AXI Interconnect.
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Generate all valid bits in the address(es) to BRAM.
-- If dual port, generate Port B address signal.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_SNG_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
-- Read takes priority over AWADDR
-- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i);
-- ISE should optimize away this mux when connected to the AXI Interconnect
-- as the AXI Interconnect duplicates the write or read address on both channels.
-- v1.03a
-- ARVALID may get asserted while handling ECC read-modify-write.
-- With the delay in assertion of AWREADY/WREADY, must add some logic to the
-- control on this mux select.
bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and
(lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or
(lite_sm_cs = RD_DATA))
else AXI_AWADDR (i);
end generate GEN_ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_DUAL_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_addr_a_int (i) <= AXI_AWADDR (i);
bram_addr_b_int (i) <= AXI_ARADDR (i);
end generate GEN_ADDR_DUAL_PORT;
end generate GEN_ADDR;
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY
-- Purpose: Only pre-assert ARREADY for non ECC designs.
-- With ECC, a write requires a read-modify-write and
-- will miss the address associated with the ARVALID
-- (due to the # of clock cycles).
---------------------------------------------------------------------------
GEN_ARREADY: if (C_ECC = 0) generate
begin
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- ARREADY is asserted until we detect the ARVALID.
-- Check for back-to-back ARREADY assertions (add axi_arready_int).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(AXI_ARVALID = '1' and axi_arready_int = '1') then
axi_arready_int <= '0';
-- Then ARREADY is asserted again when the read operation completes.
elsif (axi_aresetn_re = '1') or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_arready_int <= '1';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_ECC
-- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted
-- as in the non ECC configuration.
---------------------------------------------------------------------------
GEN_ARREADY_ECC: if (C_ECC = 1) generate
begin
axi_arready_int <= axi_arready_reg;
end generate GEN_ARREADY_ECC;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
-- No AXI_WLAST
---------------------------------------------------------------------------
-- Generate: GEN_WRDATA
-- Purpose: Generate BRAM port A write data. For AXI-Lite, pass
-- through from AXI bus. If ECC is enabled, merge with fault
-- inject vector.
-- Write data bits are in lower order bit lanes.
-- (31:0) or (63:0)
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-- Remove write data path register to BRAM
---------------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
bram_wrdata_a_int (i) <= AXI_WDATA (i);
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_W_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector).
-- (N:0)
---------------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- No BID support (wrap around in Interconnect)
-- In AXI-Lite, no WLAST assertion
-- Drive constant value out on BRESP
-- axi_bresp_int <= RESP_OKAY;
axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY;
---------------------------------------------------------------------------
-- Implement BVALID with counter regardless of IP configuration.
--
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bvalid_cnt = "001" and bvalid_cnt_dec = '1') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt /= "000") then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** AXI Read Data Channel Interface ***
---------------------------------------------------------------------------
-- For reductions on AXI-Lite, drive constant value on RESP
axi_rresp_int <= RESP_OKAY;
---------------------------------------------------------------------------
-- Generate: GEN_R
-- Purpose: Generate AXI R channel outputs when ECC is disabled.
-- No register delay on AXI_RVALID and AXI_RLAST.
---------------------------------------------------------------------------
GEN_R: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R;
---------------------------------------------------------------------------
-- Generate: GEN_R_ECC
-- Purpose: Generate AXI R channel outputs when ECC is enabled.
-- Must use registered delayed control signals for RLAST
-- and RVALID to align with register inclusion for corrected
-- read data in ECC logic.
---------------------------------------------------------------------------
GEN_R_ECC: if C_ECC = 1 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set_r = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set_r = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R_ECC;
---------------------------------------------------------------------------
--
-- Generate AXI bus read data. No register. Pass through
-- read data from BRAM. Determine source on single port
-- vs. dual port configuration.
--
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: RDATA_NO_ECC
-- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled.
-----------------------------------------------------------------------
RDATA_NO_ECC: if (C_ECC = 0) generate
begin
AXI_RDATA <= axi_rdata_int;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_SNG_PORT
-- Purpose: Source of read data: Port A in single port configuration.
-----------------------------------------------------------------------
GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_SNG_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_DUAL_PORT
-- Purpose: Source of read data: Port B in dual port configuration.
-----------------------------------------------------------------------
GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_DUAL_PORT;
end generate RDATA_NO_ECC;
-----------------------------------------------------------------------
-- Generate: RDATA_W_ECC
-- Purpose: Connect AXI_RDATA from ECC module when ECC enabled.
-----------------------------------------------------------------------
RDATA_W_ECC: if (C_ECC = 1) generate
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
begin
-- Logic common to either type of ECC encoding/decoding
-- Renove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0);
-- Remove GEN_RDATA that was doing bit reversal.
-- Read back data is registered prior to any single bit error correction.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rdata_int <= (others => '0');
else
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1);
end if;
end if;
end process REG_RDATA;
---------------------------------------------------------------------------
-- Generate: RDATA_W_HAMMING
-- Purpose: Add generate statement for Hamming Code ECC algorithm
-- specific logic.
---------------------------------------------------------------------------
RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate
begin
-- Move correct_one_bit logic to output side of AXI_RDATA output register.
-- Improves timing by balancing logic on both sides of pipeline stage.
-- Utilizing registers in AXI interconnect makes this feasible.
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table (i))
port map (
DIn => axi_rdata_int (31-i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i));
end generate GEN_CORR_32;
end generate RDATA_W_HAMMING;
-- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC)
end generate RDATA_W_ECC;
---------------------------------------------------------------------------
-- Main AXI-Lite State Machine
--
-- Description: Central processing unit for AXI-Lite write and read address
-- channel interface handling and handshaking.
-- Handles all arbitration between write and read channels
-- to utilize single port to BRAM
--
-- Outputs: axi_wready_int Registered
-- axi_arready_reg Registered (used in ECC configurations)
-- bvalid_cnt_inc Combinatorial
-- axi_rvalid_set Combinatorial
-- axi_rlast_set Combinatorial
-- bram_en_a_cmb Combinatorial
-- bram_en_b_cmb Combinatorial
-- bram_we_a_int Combinatorial
--
--
-- LITE_SM_CMB_PROCESS: Combinational process to determine next state.
-- LITE_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
LITE_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_WVALID,
AXI_WSTRB,
AXI_ARVALID,
AXI_RREADY,
bvalid_cnt,
axi_rvalid_int,
lite_sm_cs )
begin
-- assign default values for state machine outputs
lite_sm_ns <= lite_sm_cs;
axi_wready_cmb <= '0';
axi_arready_cmb <= '0';
bvalid_cnt_inc <= '0';
axi_rvalid_set <= '0';
axi_rlast_set <= '0';
bram_en_a_cmb <= '0';
bram_en_b_cmb <= '0';
bram_we_a_int <= (others => '0');
case lite_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- AXI Interconnect will only issue AWVALID OR ARVALID
-- at a time. In the case when the core is attached
-- to another AXI master IP, arbitrate between read
-- and write operation. Read operation will always win.
if (AXI_ARVALID = '1') then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and
(bvalid_cnt /= "111") then
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Always perform a read-modify-write sequence with ECC is enabled.
if (C_ECC = 1) then
lite_sm_ns <= RMW_RD_DATA;
-- Disable Port A write enables
bram_we_a_int <= (others => '0');
else
-- Non ECC operation or an ECC full 32-bit word write
-- Assert acknowledge of data & address on AXI.
-- Wait to assert AWREADY and WREADY in ECC designs.
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
bvalid_cnt_inc <= '1';
lite_sm_ns <= SNG_WR_DATA;
bram_we_a_int <= AXI_WSTRB;
end if;
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- With early assertion of ARREADY, the SM
-- must be able to accept a read address at any clock cycle.
-- Check here for active ARVALID and directly handle read
-- and do not proceed back to IDLE (no empty clock cycle in which
-- read address may be missed).
if (AXI_ARVALID = '1') and (C_ECC = 0) then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
-- Pre-assertion of ARREADY is only for non ECC configurations.
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
else
lite_sm_ns <= IDLE;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Data is presented to AXI bus
-- Wait for acknowledgment to process any next transfers
-- RVALID may not be asserted as we transition into this state.
if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then
lite_sm_ns <= IDLE;
end if;
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
lite_sm_ns <= RMW_MOD_DATA;
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
lite_sm_ns <= RMW_WR_DATA;
-- Hold off on assertion of WREADY and AWREADY until
-- here, so no pipeline registers necessary.
-- Assert acknowledge of data & address on AXI
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
-- Able to assert this signal early, then BVALID counter
-- will get incremented in the next clock cycle when WREADY
-- is asserted.
bvalid_cnt_inc <= '1';
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Enable all WEs to BRAM
bram_we_a_int <= (others => '1');
-- Complete write operation
lite_sm_ns <= IDLE;
--coverage off
------------------------------ Default ----------------------------
when others =>
lite_sm_ns <= IDLE;
--coverage on
end case;
end process LITE_SM_CMB_PROCESS;
---------------------------------------------------------------------------
LITE_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
lite_sm_cs <= IDLE;
axi_wready_int <= '0';
axi_arready_reg <= '0';
axi_rvalid_set_r <= '0';
axi_rlast_set_r <= '0';
else
lite_sm_cs <= lite_sm_ns;
axi_wready_int <= axi_wready_cmb;
axi_arready_reg <= axi_arready_cmb;
axi_rvalid_set_r <= axi_rvalid_set;
axi_rlast_set_r <= axi_rlast_set;
end if;
end if;
end process LITE_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0');
signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0);
signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0');
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Read on Port A
-- or any operation on Port B (it will be read only).
BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or
(bram_en_b_int = '1')
else '0';
-- BRAM_WE generated from SM
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
REG_RMW_SIGS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset values
if (S_AXI_AResetn = C_RESET_ACTIVE) then
RdModifyWr_Check <= '0';
RdModifyWr_Modify <= '0';
RdModifyWr_Write <= '0';
else
RdModifyWr_Check <= RdModifyWr_Read;
RdModifyWr_Modify <= RdModifyWr_Check;
RdModifyWr_Write <= RdModifyWr_Modify;
end if;
end if;
end process REG_RMW_SIGS;
-- v1.03a
-- Delay assertion of WREADY to minimize registers in core.
-- Use SM transition to RMW "read" to assert this signal.
RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
STORE_WRITE_DBUS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WDATA_Q <= (others => '0');
AXI_WSTRB_Q <= (others => '0');
-- v1.03a
-- With the delay assertion of WREADY, use WVALID
-- to register in WDATA and WSTRB signals.
elsif (AXI_WVALID = '1') then
AXI_WDATA_Q <= AXI_WDATA;
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process STORE_WRITE_DBUS;
wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_S_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0';
bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH)
<= WrECC xor FaultInjectECC;
------------------------------------------------------------------------
-- No need to use RdModifyWr_Write in the data path.
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
---------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
-- Bit swapping done at port level on checkbit_handler (31:0) & (6:0)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)]
CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic to use registered syndrome value.
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_S_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
end process HSIAO_ECC;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
-- Replicate BRAM read back data register for Hamming ECC
ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0);
end if;
end process REG_SYNDROME;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read.
-- Either during RMW of write operation or during BRAM read.
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' or
((Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- Register CE and UE flags to register block.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A
-- Purpose: Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HSIAO;
end generate GEN_DIN_A;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B
-- Purpose: Generate BRAM read data vector assignment in a dual port
-- configuration to be either from Port B, or from Port A in a
-- read-modify-write sequence.
-- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HSIAO;
end generate GEN_DIN_B;
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
-- With AXI-LITE no narrow operations are allowed.
-- AXI_WSTRB is ignored and all byte lanes are written.
bram_en_a_int <= bram_en_a_cmb;
-- BRAM_En_A <= bram_en_a_int;
-- DV regression failure with reset
-- 7/7/11
BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_DUAL_PORT
-- Purpose: Only generate Port B BRAM enable signal when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_en_b_int <= bram_en_b_cmb;
BRAM_En_B <= bram_en_b_int;
end generate GEN_BRAM_EN_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_En_B <= '0';
end generate GEN_BRAM_EN_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate
begin
BRAM_WE_A (i) <= bram_we_a_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A_i (i) <= '0';
BRAM_Addr_B_i (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A_i (i) <= bram_addr_a_int (i);
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_DUAL_PORT
-- Purpose: Only generate Port B BRAM address when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Addr_B_i (i) <= bram_addr_b_int (i);
end generate GEN_BRAM_ADDR_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Addr_B_i (i) <= '0';
end generate GEN_BRAM_ADDR_SNG_PORT;
end generate GEN_U_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data for Port A.
---------------------------------------------------------------------------
-- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL)
GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate
begin
BRAM_WrData_A (i) <= bram_wrdata_a_int (i);
end generate GEN_BRAM_WRDATA;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
end architecture implementation;
| mit | 99a54f4c00271a8a25ee29d29df86c57 | 0.427619 | 4.629142 | false | false | false | false |
dsd-g05/lab5 | g05_mastermind_controller.vhd | 1 | 5,824 | -- Descp. Controller of the Datapath/Controller architecture for solving Mastermind
--
-- entity name: g05_controller
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 23, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_mastermind_controller is
port (
TM_OUT : in std_logic;
SC_CMP, TC_LAST : in std_logic;
START, READY : in std_logic;
MODE : in std_logic;
CLK : in std_logic;
START_MODE : out std_logic;
DEFAULT_SCORE : out std_logic;
SR_SEL, P_SEL, GR_SEL : out std_logic;
GR_LD, SR_LD : out std_logic;
TM_IN, TM_EN, TC_EN, TC_RST : out std_logic;
SOLVED : out std_logic
);
end g05_mastermind_controller;
architecture behavior of g05_mastermind_controller is
type state is (s1, s2, s3, s4, s5, s6, s7, s8, s9,
s10, s11, s12, s13, s14);
signal s_present, s_next : state;
begin
process(SC_CMP, TC_LAST, START, READY, TM_OUT, MODE)
begin
if MODE = '0' then
DEFAULT_SCORE <= '0';
case s_present is
when s1 =>
if START = '1' then
s_next <= s1;
else
s_next <= s2;
end if;
when s2 =>
if START = '0' then
s_next <= s2;
else
s_next <= s3;
end if;
when s3 =>
if TC_LAST = '0' then
s_next <= s3;
else
s_next <= s4;
end if;
when s4 =>
if READY = '1' then
s_next <= s4;
else
s_next <= s5;
end if;
when s5 =>
if SC_CMP = '0' then
s_next <= s6;
else
s_next <= s9;
end if;
when s6 =>
if TC_LAST = '0' then
s_next <= s6;
else
s_next <= s7;
end if;
when s7 =>
if TM_OUT = '0' then
s_next <= s7;
else
s_next <= s8;
end if;
when s8 =>
if READY = '1' then
s_next <= s8;
else
s_next <= s5;
end if;
when s9 =>
if START = '1' then
s_next <= s9;
else
s_next <= s2;
end if;
when others =>
s_next <= s1;
end case;
else
case s_present is
when s10 =>
if START = '1' then
s_next <= s10;
DEFAULT_SCORE <= '1';
else
s_next <= s11;
end if;
when s11 =>
DEFAULT_SCORE <= '1';
if START = '0' then
s_next <= s11;
else
s_next <= s12;
end if;
when s12 =>
if READY = '1' then
s_next <= s12;
else
s_next <= s13;
end if;
when s13 =>
DEFAULT_SCORE <= '0';
if READY = '0' then
s_next <= s13;
elsif SC_CMP = '1' then
s_next <= s14;
else
s_next <= s12;
end if;
when s14 =>
if START = '1' then
s_next <= s14;
else
s_next <= s11;
end if;
when others =>
s_next <= s10;
end case;
end if;
end process;
process(CLK)
begin
if START = '0' then
if MODE = '0' then
s_present <= s2;
else
s_present <= s11;
end if;
elsif rising_edge(CLK) then
s_present <= s_next;
end if;
end process;
START_MODE <= '1' when s_present = s1 or s_present = s10 else '0';
SR_SEL <= '1' when s_present = s5 or MODE = '1' else '0';
P_SEL <= '1' when s_present = s6 else '0';
GR_SEL <= '1' when s_present = s4 else '0';
GR_LD <= '1' when s_present = s4 or s_present = s11 or s_present = s7 else '0';
SR_LD <= '1' when s_present = s5 or s_present = s8 or s_present = s10 or s_present = s11 or s_present = s13 or s_present = s14 else '0';
TM_IN <= '1' when s_present = s3 else
SC_CMP when s_present = s6 else '0';
TM_EN <= '1' when s_present = s3 else
TM_OUT when s_present = s6 else '0';
TC_EN <= '1' when s_present = s3 or s_present = s6 or s_present = s7 or MODE = '1' else '0';
TC_RST <= '1' when s_present = s1 or s_present = s4 or s_present = s8 else '0';
SOLVED <= '1' when s_present = s9 or s_present = s14 else '0';
end behavior; | mit | d1f566714fd95fd090808f81dc501140 | 0.354739 | 4.241806 | false | false | false | false |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/reg_bank_xilinx.vhd | 3 | 9,896 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
-- library UNISIM; --May need to uncomment for ModelSim
-- use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity reg_bank is
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
signal no_connect : std_logic_vector(127 downto 0);
begin
--------------------------------------
-- Implements register bank control --
--------------------------------------
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new, intr_enable_reg,
data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";--"01110" --"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
-----------------------
-- Implements memory --
-----------------------
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => no_connect(i) -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => no_connect(32+i) -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => no_connect(64+i) -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => no_connect(96+i) -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end; --architecture ram_block
| gpl-3.0 | fb9f54d88ac335656fc6c9a7e8bc28d8 | 0.480194 | 4.003236 | false | false | false | false |
1995parham/FPGA-Homework | HW-2/src/p2/p2.vhd | 1 | 1,472 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-03-2016
-- Module Name: p2.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity clk_dvdr is
port (clk : in std_logic;
clk_2, clk_5 : out std_logic);
end entity;
architecture BEHAVIORAL of clk_dvdr is
signal clk_2_tmp : std_logic := '0';
signal clk_5_tmp : std_logic := '0';
begin
-- divide clock by 2:
-- counter values: 0 ... 1;
process (clk)
variable clk_2_var : integer := 0;
begin
if clk'event and clk = '1' then
clk_2_var := clk_2_var + 1;
if clk_2_var = 1 then
clk_2_var := 0;
clk_2_tmp <= not clk_2_tmp;
end if;
end if;
end process;
-- divide clock by 5:
-- counter values: 0 ... 3; toggle: true;
-- counter values: 0 ... 2; toggle: false;
process (clk)
variable clk_5_var : integer := 0;
variable clk_5_toggle : boolean := false;
begin
if clk'event then
clk_5_var := clk_5_var + 1;
if clk_5_var = 3 and clk_5_toggle then
clk_5_var := 0;
clk_5_tmp <= not clk_5_tmp;
clk_5_toggle := not clk_5_toggle;
elsif clk_5_var = 2 and not clk_5_toggle then
clk_5_var := 0;
clk_5_tmp <= not clk_5_tmp;
clk_5_toggle := not clk_5_toggle;
end if;
end if;
end process;
clk_2 <= clk_2_tmp;
clk_5 <= clk_5_tmp;
end architecture BEHAVIORAL;
| gpl-3.0 | b1cb4fb097886a82db9b6d402c762d71 | 0.538723 | 2.869396 | false | false | false | false |
lukehsiao/FPGA_Flappy_Bird | src/flappy_top.vhd | 1 | 18,565 | ----------------------------------------------------------------------------------
-- Flappy Bird
--
-- Authors: Steve Hammon and Luke Hsiao
-- Brigham Young University - ECEn 320
-- Winter Semester 2014
-- Dr. Mike Wirthlin
--
--
-- Create Date: 12:39:00 03/26/2014
--
-- Revision History:
-- Revision 0.01 - File Created
-- Revision 1.00 - [27 March 2014] Flappy Bird Completed!
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flappy_top is
generic(
CLK_RATE: natural := 50_000_000;
DEBOUNCE_TIME: natural := 10 --In miliseconds
);
port(
clk: in std_logic;
btn: in std_logic_vector(3 downto 0);
sw: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
Hsync: out std_logic;
Vsync: out std_logic;
vgaRed: out std_logic_vector(2 downto 0);
vgaGreen: out std_logic_vector(2 downto 0);
vgaBlue: out std_logic_vector(1 downto 0);
an: out std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0);
dp: out std_logic
);
end flappy_top;
architecture arch of flappy_top is
-- Debounce
-------------------Function-------------------
function log2c(n: integer) return integer is
variable m, p: integer;
begin
m := 0;
p := 1;
while p < n loop
m := m + 1;
p := p * 2;
end loop;
return m;
end log2c;
---------------------------------------------
constant DEBOUNCE_TIMER_VALUE: natural := (DEBOUNCE_TIME * CLK_RATE) / 1000;
constant DEBOUNCE_TIMER_BITS: natural := log2c(DEBOUNCE_TIMER_VALUE);
signal debounce_counter_value, debounce_counter_value_next: unsigned(DEBOUNCE_TIMER_BITS-1 downto 0) := (others=>'0');
-- VGA Signals
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal pix_x, pix_y: unsigned(9 downto 0);
signal blank: std_logic;
signal last_column: std_logic;
signal last_row: std_logic;
signal rst: std_logic;
signal rgb: std_logic_vector(7 downto 0);
signal HS: std_logic;
signal VS: std_logic;
-- Seven Segment Display Signals
signal data_in: std_logic_vector(15 downto 0);
signal dp_in: std_logic_vector(3 downto 0);
signal blank_seg: std_logic_vector(3 downto 0);
signal left_seven_seg_data, left_seven_seg_data_next: std_logic_vector(7 downto 0) := (others=>'0');
signal right_seven_seg_data, right_seven_seg_data_next: std_logic_vector(7 downto 0) := (others=>'0');
-- Signals for Flappy Bird Graphics
signal bird_top, bird_top_next, bird_top_temp: unsigned(9 downto 0):= to_unsigned(200,10);
signal bird_left: unsigned(9 downto 0):= to_unsigned(100,10);
signal bird_outline_on, bird_lips_on, bird_white_on, bird_color_on, pipe_on, ground_on, ground_border_on: std_logic;
signal bird_outline_rgb, bird_lips_rgb, bird_white_rgb, bird_color_rgb, sky_rgb, pipe_rgb, ground_rgb, ground_border: std_logic_vector(7 downto 0);
-- Signals for column movement
signal col1_x, col1_x_next, col1_y, col1_y_next: unsigned (pixel_x'range) := (others => '1');
signal col2_x, col2_x_next, col2_y, col2_y_next: unsigned (pixel_x'range) := (others => '1');
signal col3_x, col3_x_next, col3_y, col3_y_next: unsigned (pixel_x'range) := (others => '1');
signal random, random_next, random_temp: unsigned (pixel_x'range) := (others => '0');
signal moveEN, col1_on, col2_on, col3_on: std_logic := '0'; -- to delay the movement
signal delay, delay_next: Natural := 0;
-- Signals for State Machine (necessary to have a "tap to start" type of behavior)
type state is (start, play);
signal state_reg, state_next: state;
signal crashed: std_logic;
-- Signals to Keep Score
signal scoreOnes, scoreOnes_next, scoreTens, scoreTens_next: unsigned (3 downto 0);
signal highscore, highscore_next: unsigned (left_seven_seg_data'range);
--Physics
signal button0, button0_next, button0Pulse: std_logic;
signal jump_reg, jump_reg_next: unsigned(4 downto 0) := "00000";
signal fall_reg, fall_reg_next: unsigned(3 downto 0) := "0000";
signal bird_delay, bird_delay_next: unsigned(20 downto 0):= to_unsigned(0,21);
begin
------------------------Component Declarations-----------------------------------------------------
vga_timer: entity work.vga_timing
port map(clk=>clk, rst=>rst, HS=>HS, VS=>VS, pixel_x=>pixel_x, pixel_y=>pixel_y, blank=>blank,
last_column=>last_column, last_row=>last_row);
display: entity work.seven_segment_display
port map(clk=>clk, data_in=>data_in, dp_in=>dp_in, blank=>blank_seg,
an=>an, seg=>seg, dp=>dp);
debouncer: entity work.btnpulse
port map (btn=>button0, clk=>clk, reset=>rst, btnpulse=>button0Pulse);
--==================================================================================================
process(clk,btn)
begin
rst <='0';
if btn(3)='1' then
rst <= '1';
bird_top <= to_unsigned(200,10);
bird_delay <= (others=>'0');
col1_x <= (others => '0');
col2_x <= (others => '0');
col3_x <= (others => '0');
delay <= 0;
state_reg <= start;
highscore <= (others => '0');
scoreOnes <= (others => '0');
scoreTens <= (others => '0');
elsif (clk'event and clk='1') then
Hsync <= HS;
Vsync <= VS;
vgaRed <= rgb(7 downto 5);
vgaGreen <= rgb(4 downto 2);
vgaBlue <= rgb(1 downto 0);
bird_top <= bird_top_next;
bird_delay <= bird_delay_next;
left_seven_seg_data <= left_seven_seg_data_next;
right_seven_seg_data <= right_seven_seg_data_next;
state_reg <= state_next;
debounce_counter_value <= debounce_counter_value_next;
button0 <= button0_next;
if button0Pulse='1' then
jump_reg <= "10111";
fall_reg <= "0000";
else
jump_reg <= jump_reg_next;
fall_reg <= fall_reg_next;
end if;
--signals for columns
col1_x <= col1_x_next;
col2_x <= col2_x_next;
col3_x <= col3_x_next;
col1_y <= col1_y_next;
col2_y <= col2_y_next;
col3_y <= col3_y_next;
delay <= delay_next;
--Signals for Score
highscore <= highscore_next;
scoreOnes <= scoreOnes_next;
scoreTens <= scoreTens_next;
end if;
end process;
--Debounce Logic
debounce_counter_value_next <= debounce_counter_value + 1;
button0_next <= '1' when (btn(0)='1' and debounce_counter_value = 0) else
'0' when (btn(0)='0' and debounce_counter_value = 0) else
button0;
--X 640
--Y 480
------------------------------------Bird Draw Logic----------------------------------------
pix_x <= unsigned(pixel_x);
pix_y <= unsigned(pixel_y);
bird_outline_on <= '1' when
((pix_y=bird_top or pix_y=bird_top+1) and (pix_x>=bird_left+12 and pix_x<=bird_left+25)) or --line 0
((pix_y=bird_top+2 or pix_y=bird_top+3) and ((pix_x>=bird_left+8 and pix_x<=bird_left+11) or pix_x=bird_left+20 or pix_x=bird_left+21 or pix_x=bird_left+26 or pix_x=bird_left+27)) or --line 1
((pix_y=bird_top+4 or pix_y=bird_top+5) and (pix_x=bird_left+6 or pix_x=bird_left+7 or pix_x=bird_left+18 or pix_x=bird_left+19 or pix_x=bird_left+28 or pix_x=bird_left+29)) or --line 2
((pix_y=bird_top+6 or pix_y=bird_top+7) and ((pix_x>=bird_left+2 and pix_x<=bird_left+11) or pix_x=bird_left+18 or pix_x=bird_left+19 or pix_x=bird_left+24 or pix_x=bird_left+25 or pix_x=bird_left+30 or pix_x=bird_left+31)) or --line 3
((pix_y=bird_top+8 or pix_y=bird_top+9) and (pix_x=bird_left or pix_x=bird_left+1 or pix_x=bird_left+12 or pix_x=bird_left+13 or pix_x=bird_left+18 or pix_x=bird_left+19 or pix_x=bird_left+24 or pix_x=bird_left+25 or pix_x=bird_left+30 or pix_x=bird_left+31)) or --line 4
((pix_y=bird_top+10 or pix_y=bird_top+11) and (pix_x=bird_left or pix_x=bird_left+1 or pix_x=bird_left+14 or pix_x=bird_left+15 or pix_x=bird_left+18 or pix_x=bird_left+19 or pix_x=bird_left+30 or pix_x=bird_left+31)) or --line 5
((pix_y=bird_top+12 or pix_y=bird_top+13) and (pix_x=bird_left or pix_x=bird_left+1 or pix_x=bird_left+14 or pix_x=bird_left+15 or pix_x=bird_left+20 or pix_x=bird_left+21 or pix_x=bird_left+30 or pix_x=bird_left+31)) or --line 6
((pix_y=bird_top+14 or pix_y=bird_top+15) and (pix_x=bird_left or pix_x=bird_left+1 or pix_x=bird_left+14 or pix_x=bird_left+15 or (pix_x>=bird_left+22 and pix_x<=bird_left+33))) or --line 7
((pix_y=bird_top+16 or pix_y=bird_top+17) and (pix_x=bird_left+2 or pix_x=bird_left+3 or pix_x=bird_left+12 or pix_x=bird_left+13 or pix_x=bird_left+20 or pix_x=bird_left+21 or pix_x=bird_left+34 or pix_x=bird_left+35)) or --line 8
((pix_y=bird_top+18 or pix_y=bird_top+19) and ((pix_x>=bird_left+4 and pix_x<=bird_left+11) or pix_x=bird_left+18 or pix_x=bird_left+19 or (pix_x>=bird_left+22 and pix_x<=bird_left+33))) or --line 9
((pix_y=bird_top+20 or pix_y=bird_top+21) and (pix_x=bird_left+4 or pix_x=bird_left+5 or pix_x=bird_left+20 or pix_x=bird_left+21 or pix_x=bird_left+32 or pix_x=bird_left+33)) or --line 10
((pix_y=bird_top+22 or pix_y=bird_top+23) and ((pix_x>=bird_left+6 and pix_x<=bird_left+11) or (pix_x>=bird_left+22 and pix_x<=bird_left+31))) or --line 11
((pix_y=bird_top+24 or pix_y=bird_top+25) and (pix_x>=bird_left+12 and pix_x<=bird_left+21)) --line 12
else '0';
bird_lips_on <= '1' when
((pix_y=bird_top+16 or pix_y=bird_top+17) and (pix_x>=bird_left+22 and pix_x<=bird_left+33)) or --line 8
((pix_y=bird_top+18 or pix_y=bird_top+19) and (pix_x=bird_left+20 or pix_x=bird_left+21)) or --line 9
((pix_y=bird_top+20 or pix_y=bird_top+21) and (pix_x>=bird_left+22 and pix_x<=bird_left+31)) --line 10
else '0';
bird_white_on <= '1' when
((pix_y=bird_top+2 or pix_y=bird_top+3) and (pix_x>=bird_left+22 and pix_x<=bird_left+25)) or --line 1
((pix_y=bird_top+4 or pix_y=bird_top+5) and (pix_x>=bird_left+20 and pix_x<=bird_left+27)) or --line 2
((pix_y=bird_top+6 or pix_y=bird_top+7) and ((pix_x>=bird_left+20 and pix_x<=bird_left+23) or (pix_x>=bird_left+26 and pix_x<=bird_left+29))) or --line 3
((pix_y=bird_top+8 or pix_y=bird_top+9) and ((pix_x>=bird_left+2 and pix_x<=bird_left+11) or (pix_x>=bird_left+20 and pix_x<=bird_left+23) or (pix_x>=bird_left+26 and pix_x<=bird_left+29))) or --line 4
((pix_y=bird_top+10 or pix_y=bird_top+11) and ((pix_x>=bird_left+2 and pix_x<=bird_left+13) or (pix_x>=bird_left+20 and pix_x<=bird_left+29))) or --line 5
((pix_y=bird_top+12 or pix_y=bird_top+13) and ((pix_x>=bird_left+2 and pix_x<=bird_left+13) or (pix_x>=bird_left+22 and pix_x<=bird_left+29))) or --line 6
((pix_y=bird_top+14 or pix_y=bird_top+15) and (pix_x>=bird_left+2 and pix_x<=bird_left+13)) or --line 7
((pix_y=bird_top+16 or pix_y=bird_top+17) and (pix_x>=bird_left+4 and pix_x<=bird_left+11)) --line 8
else '0';
bird_color_on <= '1' when
((pix_y=bird_top+2 or pix_y=bird_top+3) and (pix_x>=bird_left+12 and pix_x<=bird_left+19)) or --line 1
((pix_y=bird_top+4 or pix_y=bird_top+5) and (pix_x>=bird_left+8 and pix_x<=bird_left+17)) or --line 2
((pix_y=bird_top+6 or pix_y=bird_top+7) and (pix_x>=bird_left+12 and pix_x<=bird_left+17)) or --line 3
((pix_y=bird_top+8 or pix_y=bird_top+9) and (pix_x>=bird_left+14 and pix_x<=bird_left+17)) or --line 4
((pix_y=bird_top+10 or pix_y=bird_top+11) and (pix_x=bird_left+16 or pix_x=bird_left+17)) or --line 5
((pix_y=bird_top+12 or pix_y=bird_top+13) and (pix_x>=bird_left+16 and pix_x<=bird_left+19)) or --line 6
((pix_y=bird_top+14 or pix_y=bird_top+15) and (pix_x>=bird_left+16 and pix_x<=bird_left+21)) or --line 7
((pix_y=bird_top+16 or pix_y=bird_top+17) and (pix_x>=bird_left+14 and pix_x<=bird_left+19)) or --line 8
((pix_y=bird_top+18 or pix_y=bird_top+19) and (pix_x>=bird_left+12 and pix_x<=bird_left+17)) or --line 9
((pix_y=bird_top+20 or pix_y=bird_top+21) and (pix_x>=bird_left+6 and pix_x<=bird_left+19)) or --line 10
((pix_y=bird_top+22 or pix_y=bird_top+23) and (pix_x>=bird_left+12 and pix_x<=bird_left+21)) --line 11
else '0';
bird_outline_rgb <= "00000000"; --black outline
bird_lips_rgb <= "11101100"; --orange lips
bird_white_rgb <= "11111111";
bird_color_rgb <= sw; --You can change the color of the bird based on the switches
--=====================================================================================
------------------------------------Bird Movement-------------------------------------
-- (+ is down and - is up)
process(bird_delay, button0Pulse, jump_reg, fall_reg)
begin
if bird_delay=0 then
if jump_reg/="00000" then
jump_reg_next <= '0' & jump_reg(4 downto 1); --creates a shift register to add and subtract the heights
fall_reg_next <= fall_reg;
else
jump_reg_next <= jump_reg;
fall_reg_next <= fall_reg(2 downto 0) & '1';
end if;
else
jump_reg_next <= jump_reg;
fall_reg_next <= fall_reg;
end if;
end process;
bird_delay_next <= bird_delay+1;
bird_top_temp <= to_unsigned(200,10) when (state_reg=start and button0Pulse='1') else
(bird_top - jump_reg + fall_reg) when bird_delay=0 and state_reg/=start
else bird_top;
bird_top_next <= bird_top_temp when (bird_top_temp>=0 and bird_top_temp<425) else --This caps the level so the bird can't fly above it
(others=>'0');
bird_left <= to_unsigned(100,10);
--=====================================================================================
---------------Logic to generate a psuedorandom number between 15 and 255---------------
process(clk)
begin
if clk'event and clk='1' then
random <= random_next;
end if;
end process;
-- concatenated values keep it in the proper range
random_temp <= random(6 downto 5) & (pix_x(3 downto 1) xor pix_y(8 downto 6)) & random(7) & (pix_x(5 downto 2) xor pix_y(9 downto 6));
random_next <= "00" & random_temp(9 downto 6) & "1111";
--=======================================================================================
-----------------------------Column Draw Logic-------------------------------------------
pipe_rgb <= "00010100"; -- solid colored, light green pipes
ground_rgb <= "11110101"; -- orangish ground
ground_border <= "00001100"; --Border for the ground
ground_border_on <= '1' when (pix_y >= 425 and pix_y < 430) else '0';
ground_on <= '1' when pix_y >= 430 else '0';
--In order for columns to actually move off the the screen to the left, need to display them
--relative to their right edge, rather than their left edge.
-- Next State Logic
process (state_reg, button0Pulse, crashed, col1_x, col2_x, col3_x, moveEN, col1_on, col2_on, col3_on, random, col1_y, col2_y, col3_y)
begin
--Defaults
state_next <= state_reg;
col1_x_next <= col1_x;
col2_x_next <= col2_x;
col3_x_next <= col3_x;
col1_y_next <= col1_y;
col2_y_next <= col2_y;
col3_y_next <= col3_y;
--right_seven_seg_data_next <= right_seven_seg_data;
case state_reg is
when start =>
if (button0Pulse = '1') then
state_next <= play;
col1_x_next <= to_unsigned((638+80), 10); --start column 1s
col2_x_next <= (others => '1');
col3_x_next <= (others => '1');
col1_y_next <= random;
else
state_next <= start;
end if;
when play =>
if moveEN = '1' then
if col1_on = '1' then
col1_x_next <= col1_x - 1;
end if;
if col2_on = '1' then
col2_x_next <= col2_x - 1;
end if;
if col3_on = '1' then
col3_x_next <= col3_x - 1;
end if;
end if;
if col3_x = 450 then --defines space between columns
col1_x_next <= to_unsigned((638+80), 10);
col1_y_next <= random;
end if;
if col2_x = 450 then
col3_x_next <= to_unsigned((638+80), 10);
col3_y_next <= random;
end if;
if col1_x = 450 then
col2_x_next <= to_unsigned((638+80), 10);
col2_y_next <= random;
end if;
if crashed = '1' then
state_next <= start;
else
state_next <= play;
end if;
end case;
end process;
--Transition from start state to play state must turn col1 on.
col1_on <= '1' when col1_x <= (639+80) and col1_x > 0 else '0';
col2_on <= '1' when col2_x <= (639+80) and col2_x > 0 else '0';
col3_on <= '1' when col3_x <= (639+80) and col3_x > 0 else '0';
moveEN <= '1' when delay = 400000 else '0';
delay_next <= 0 when delay > 400000 else delay + 1;
--Logic to signal the pipe is on (80 is the width of the pipe, 100 is width of the gap)
pipe_on <= '1' when (col1_on='1' and ((pix_x >= col1_x - 80 and pix_x < col1_x) or (col1_x <= 80 and pix_x < col1_x)) and (pix_y <= col1_y or pix_y > col1_y+100)) or
(col2_on='1' and ((pix_x >= col2_x - 80 and pix_x < col2_x) or (col2_x <= 80 and pix_x < col2_x)) and (pix_y <= col2_y or pix_y > col2_y+100)) or
(col3_on='1' and ((pix_x >= col3_x - 80 and pix_x < col3_x) or (col3_x <= 80 and pix_x < col3_x)) and (pix_y <= col3_y or pix_y > col3_y+100))
else '0';
-- Calculate Crashes
crashed <= '1' when bird_outline_on='1' and (ground_border_on='1' or pipe_on='1') else '0';
--======================================================================================
-------------------------------------Calculate Scores-------------------------------------
scoreOnes_next <= scoreOnes + 1 when (bird_left = col1_x or bird_left = col2_x or bird_left = col3_x) and moveEN = '1' else
(others => '0') when (state_reg=start and button0Pulse='1') or scoreOnes = 9 else
scoreOnes;
scoreTens_next <= scoreTens + 1 when scoreOnes = 9 else
(others => '0') when (state_reg=start and button0Pulse='1') else
scoreTens;
highscore_next <= (scoreTens & scoreOnes) when ((scoreTens&scoreOnes) > highscore and crashed='1') else highscore;
left_seven_seg_data_next <= std_logic_vector(highscore);
right_seven_seg_data_next <= std_logic_vector(scoreTens & scoreOnes);
--=======================================================================================
-----------------------Output Logic----------------------------------------------------
sky_rgb <= "01011111";
rgb <= (others=>'0') when blank='1' else
ground_border when ground_border_on='1' else
ground_rgb when ground_on='1' else
pipe_rgb when pipe_on='1' else
bird_outline_rgb when bird_outline_on='1' else
bird_lips_rgb when bird_lips_on='1' else
bird_white_rgb when bird_white_on='1' else
bird_color_rgb when bird_color_on='1' else
sky_rgb;
data_in <= left_seven_seg_data & right_seven_seg_data;
blank_seg <= "0000"; --turn on all displays
dp_in <= "0100"; --turn off decimal points
led <= sw;
--=====================================================================================
end arch; | mit | d61328645ef285394e8976c7e9c4cfa4 | 0.590412 | 2.72774 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_address_decoder.vhd | 1 | 25,047 | -------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_address_decoder.vhd
-- Version: v3.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author:
--
-- History:
-- ~~~~~~
-- SK 11/12/211 --
-- 1. added for address decoding purpose.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.pselect_f;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI4_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI4_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex7" -- "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity qspi_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of qspi_address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI4_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity proc_common_v4_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity proc_common_v4_0.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture imp;
| mit | e72c21e1d89c9cba0dc2828dd8f75849 | 0.432667 | 4.606768 | false | false | false | false |
dsd-g05/lab5 | g05_pattern_input.vhd | 1 | 3,700 | -- Descp. Allow the user to choose a pattern
--
-- entity name: g05_pattern_input
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 26, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_pattern_input is
port (
increment, sel : in std_logic;
seg_code : out std_logic_vector(2 downto 0);
segment : out std_logic_vector(1 downto 0)
);
end g05_pattern_input;
architecture behavior of g05_pattern_input is
type segment_num is (s1, s2, s3, s4);
type color is (c1, c2, c3, c4, c5, c6);
signal s_present, s_next : segment_num;
signal c_present, c_next : color;
signal sd1, sd2, sd3, sd4 : color;
begin
selector: process(sel)
begin
case s_present is
when s1 =>
if sel = '0' then
s_next <= s2;
else
s_next <= s1;
end if;
when s2 =>
if sel = '0' then
s_next <= s3;
else
s_next <= s2;
end if;
when s3 =>
if sel = '0' then
s_next <= s4;
else
s_next <= s3;
end if;
when s4 =>
if sel = '0' then
s_next <= s1;
else
s_next <= s4;
end if;
when others =>
s_next <= s1;
end case;
end process;
process(sel)
begin
if rising_edge(sel) then
s_present <= s_next;
end if;
end process;
incrementor: process(increment)
begin
case c_present is
when c1 =>
if increment = '0' then
c_next <= c2;
else
c_next <= c1;
end if;
when c2 =>
if increment = '0' then
c_next <= c3;
else
c_next <= c2;
end if;
when c3 =>
if increment = '0' then
c_next <= c4;
else
c_next <= c3;
end if;
when c4 =>
if increment = '0' then
c_next <= c5;
else
c_next <= c4;
end if;
when c5 =>
if increment = '0' then
c_next <= c6;
else
c_next <= c5;
end if;
when c6 =>
if increment = '0' then
c_next <= c1;
else
c_next <= c6;
end if;
when others =>
c_next <= c1;
end case;
end process;
process(increment, sel)
begin
if rising_edge(increment) then
c_present <= c_next;
end if;
end process;
seg_code <= "000" when c_present = c1 else
"001" when c_present = c2 else
"010" when c_present = c3 else
"011" when c_present = c4 else
"100" when c_present = c5 else
"101" when c_present = c6 else
"000";
segment <= "00" when s_present = s1 else
"01" when s_present = s2 else
"10" when s_present = s3 else
"11" when s_present = s4 else
"00";
end behavior; | mit | 45ef00d974b0a6e2fa8d24c87e4fa711 | 0.39027 | 4.052574 | false | false | false | false |
zzhou007/161lab | lab04/alu_control.vhd | 1 | 1,058 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.cpu_constant_library.all;
entity alu_control is
port (
alu_op : in std_logic_vector(1 downto 0);
instruction_5_0 : in std_logic_vector(5 downto 0);
alu_out : out std_logic_vector(3 downto 0)
);
end alu_control;
architecture Behavioral of alu_control is
begin
process (alu_op, instruction_5_0)
begin
case alu_op is
when "00" => --lw and sw
alu_out <= "0010";
when "01" => --branch
alu_out <= "0110";
when "10" => --r type
case instruction_5_0 is
when "100000" => --add
alu_out <= "0010";
when "100010" => --sub
alu_out <= "0110";
when "100100" => --AND
alu_out <= "0000";
when "100101" => --OR
alu_out <= "0001";
when "101010" => --slt
alu_out <= "0111";
when "100111" => --NOR
alu_out <= "1100";
when others => --bad input
alu_out <= "XXXX";
end case;
when others => --bad input
alu_out <= "XXXX";
end case;
end process;
end Behavioral;
| gpl-2.0 | c5cb11e0ddf332c2a89144bad993a964 | 0.548204 | 2.997167 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/checkbit_handler.vhd | 7 | 25,695 | -------------------------------------------------------------------------------
-- checkbit_handler.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler.vhd
--
-- Description: Generates the ECC checkbits for the input vector of data bits.
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true
);
port (
DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code.
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Syndrome_4 : out std_logic_vector (0 to 1);
Syndrome_6 : out std_logic_vector (0 to 5);
Syndrome_Chk : in std_logic_vector (0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
architecture IMP of checkbit_handler is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6) := (others => '0');
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_0_to_2 : std_logic_vector (0 to 2);
signal syndrome_3_to_5 : std_logic_vector (3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- For improved timing, remove Enable_ECC signal in this LUT level
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
-- Set bit 4 output with default. Real ECC XOR value will be determined post register
-- stage.
syndrome_i (4) <= '0';
-- For improved timing, move last LUT level XOR to next side of pipeline
-- stage in read path.
Syndrome_4 <= chk4_1;
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
-- No internal use for MSB of syndrome (it is created after the
-- register stage, outside of this block)
syndrome_i(6) <= '0';
Syndrome <= syndrome_i;
-- (N:0) <= (0:N)
-- Bring out seperate output to do final XOR stage on Syndrome (6) after
-- the pipeline stage.
Syndrome_6 <= chk6_1 (0 to 5);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101")
else '0';
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0';
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi);
Use_LUT6: if (C_USE_LUT6) generate
begin
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => Syndrome_Chk(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
begin
UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
| mit | d56a6c9f302ddf3f60271af0e8f2cfc2 | 0.4439 | 3.882006 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/Common.vhd | 1 | 4,058 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package Common is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
subtype Int16 is std_logic_vector(15 downto 0);
subtype Int15 is std_logic_vector(14 downto 0);
subtype Int5 is std_logic_vector(4 downto 0);
subtype Int4 is std_logic_vector(3 downto 0);
subtype Int3 is std_logic_vector(2 downto 0);
subtype Int8 is std_logic_vector(7 downto 0);
constant Int16_Zero : Int16 := "0000000000000000";
constant Int15_Zero : Int15 := "000000000000000";
constant Int5_Zero : Int5 := "00000";
constant Int4_Zero : Int4 := "0000";
constant Int4_One : Int4 := "1111";
constant Int3_Zero : Int3 := "000";
constant Int8_Zero : Int8 := "00000000";
constant Int16_eight: Int16 := "0000000000001000";
constant Int16_Z : int16 := "ZZZZZZZZZZZZZZZZ";
constant Zero_Reg: Int4 := "1000";
constant PC_Reg: Int4 := "1010";
constant IH_reg: Int4 := "1011";
constant RA_reg: Int4 := "1100";
constant SP_reg: Int4 := "1101";
function sll_2(imm: Int16) return Int16;
function extend(imm: Int16; imm_n: Int4; sign: std_logic) return int16;
end Common;
package body Common is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
function sll_2(imm: Int16) return Int16 is
variable i : integer := 2;
variable n1: bit_vector(15 downto 0);
begin
i := 2;
n1 := TO_BITVECTOR(imm);
return TO_STDLOGICVECTOR(n1 sll i);
end sll_2;
function extend(imm: Int16; imm_n: Int4; sign: std_logic) return int16 is
variable re: int16 := int16_zero;
begin
if sign = '1' then --sign_extend
case imm_n is
when "0011" =>
re(15 downto 3) := (others => imm(2));
re(2 downto 0) := imm(2 downto 0);
when "1000" =>
re(15 downto 8) := (others => imm(7));
re(7 downto 0) := imm(7 downto 0);
when "0100" =>
re(15 downto 4) := (others => imm(3));
re(3 downto 0) := imm(3 downto 0);
when "0101" =>
re(15 downto 5) := (others => imm(4));
re(4 downto 0) := imm(4 downto 0);
when "1011" =>
re(15 downto 11) := (others => imm(10));
re(10 downto 0) := imm(10 downto 0);
when others => null;
end case;
else --zero_extend
case imm_n is
when "1000" =>
re(15 downto 8) := (others => '0');
re(7 downto 0) := imm(7 downto 0);
when "0011" =>
re(15 downto 3) := (others => '0');
re(2 downto 0) := imm(2 downto 0);
when others => null;
end case;
end if;
return re;
end extend;
end Common;
| mit | 002f21ff270e6da10058da31e57004c8 | 0.600542 | 2.999261 | false | false | false | false |
6769/VHDL | Lab_6/Modelsim_Project/proc.vhd | 1 | 5,870 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity proc is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : buffer STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end proc;
architecture Behavior of proc is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
component regn --usual register
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
end component;
component upcount
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component Addsub
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end component;
component multiplexers
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end component;
--declare signals
--
--
subtype regtype is std_logic_vector(15 downto 0);
signal Tstep_Q:std_logic_vector(1 downto 0);
signal High,Clear:std_logic;
signal IR:std_logic_vector(1 to 9);
signal Xreg,Yreg,Rin,Multiplexer_Reg:std_logic_vector(0 to 7);
signal Ain,Gin,IRin,AddSub_ALU,Multiplexer_Gout,Multiplexer_Dinout:std_logic;
signal R0,R1,A,ALU_result,G:regtype;
signal I,X,Y:std_LOGIC_vector(1 to 3);
begin
High <= '1';
process(Run,Resetn)
begin
if Resetn='0' then Clear <= '0';
else Clear<='1';
end if;
end process;
Tstep : upcount port map(Clear, Clock and Run, Tstep_Q);
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
decX : dec3to8 port map(X, High, Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, High, Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)
begin
--specify initial values
Done<='0';
Multiplexer_Dinout<='0';
Multiplexer_Gout<='0';
Multiplexer_Reg<=(others =>'0');
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub_ALU<='Z';
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Multiplexer_Reg<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
Multiplexer_Dinout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Multiplexer_Reg<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Multiplexer_Reg<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Multiplexer_Reg<=Yreg;
AddSub_ALU<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Multiplexer_Reg<=Yreg;
AddSub_ALU<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Multiplexer_Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Multiplexer_Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
end process;
-- Din, RinControl,Clk,ROut
reg_0 : regn port map(BusWires, Rin(0), Clock, R0);
reg_1 : regn port map(BusWires, Rin(1), Clock, R1);
reg_A : regn port map(BusWires, Ain, Clock, A );
reg_G : regn port map(ALU_result, Gin, Clock, G );
reg_IR: regn generic map(9) port map(DIN(15 downto 7),IRin,Clock,IR);
ALU_Unit:
Addsub port map(A, BusWires,AddSub_ALU, ALU_result);
--instantiate other registers and the adder/subtracter unit
Multiplexer_Unit:
multiplexers generic map(N=>2,n_multi=>16) port map(DIN,G,R0,R1,Multiplexer_Reg(0 to 1) ,Multiplexer_Gout&Multiplexer_Dinout,BusWires);
--define the bus
end Behavior; | gpl-2.0 | b237e723fed9efbf82657dacb50e37e9 | 0.48092 | 3.910726 | false | false | false | false |
1995parham/FPGA-Homework | Project-Phase2/hw/main.vhd | 1 | 3,616 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-05-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (DDR_addr : inout STD_LOGIC_VECTOR (14 downto 0);
DDR_ba : inout STD_LOGIC_VECTOR (2 downto 0);
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dq : inout STD_LOGIC_VECTOR (31 downto 0);
DDR_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR (53 downto 0);
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FSM_clk : in std_logic);
end entity;
architecture structural of main is
component FSM is
port (start_state : in std_logic_vector(3 downto 0);
end_state : out std_logic_vector(3 downto 0);
str : in std_logic_vector(31 downto 0);
enable, clk : in std_logic;
done : out std_logic);
end component;
component base_zynq_design_wrapper
port (DDR_addr : inout STD_LOGIC_VECTOR (14 downto 0);
DDR_ba : inout STD_LOGIC_VECTOR (2 downto 0);
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dq : inout STD_LOGIC_VECTOR (31 downto 0);
DDR_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR (53 downto 0);
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
gpio_rtl_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_rtl_1_i : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_rtl_1_o : out STD_LOGIC_VECTOR ( 9 downto 0 ));
end component;
signal gpio_rtl_1_i : std_logic_vector (9 downto 0);
signal gpio_rtl_1_o : std_logic_vector (9 downto 0);
signal gpio_rtl_0 : std_logic_vector (31 downto 0);
signal start_state, end_state : std_logic_vector (3 downto 0);
signal str : std_logic_vector (31 downto 0);
signal enable : std_logic;
signal done : std_logic;
begin
start_state <= gpio_rtl_1_o (3 downto 0);
gpio_rtl_1_i (8 downto 5) <= end_state;
str <= gpio_rtl_0;
enable <= gpio_rtl_1_o (4);
gpio_rtl_1_i (9) <= done;
FSM_i: component FSM
port map (start_state, end_state, str, enable, FSM_clk, done);
base_zynq_design_wrapper_i: component base_zynq_design_wrapper
port map (DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n,
DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n,
DDR_reset_n, DDR_we_n, FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp, FIXED_IO_mio,
FIXED_IO_ps_clk, FIXED_IO_ps_porb, FIXED_IO_ps_srstb, gpio_rtl_0, gpio_rtl_1_i, gpio_rtl_1_o);
end architecture;
| gpl-3.0 | 4e229e75cb45cec1116bd496107ea17e | 0.615597 | 2.831637 | false | false | false | false |
frankvanbever/MIPS_processor | Control.vhd | 1 | 3,653 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Steven Vanden Branden
--
-- Create Date: 15:23:25 03/13/2013
-- Design Name:
-- Module Name: Control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
--! use logic elements
use IEEE.STD_LOGIC_1164.ALL;
--! sends out control signals depending on the instruction first 6 bits (FUNCT field) and the instructions 26-31 bits(?)
entity Control is
Port ( Instruction : in STD_LOGIC_VECTOR (31 downto 26); --! last 6 bits of instruction (?)
Instruction_funct : in STD_LOGIC_VECTOR (5 downto 0); --! first 6 bits of instruction (FUNCT field)
RegDst : out STD_LOGIC; --! Register Destination selector
ALUSrc : out STD_LOGIC; --! ALU input Source selector
MemtoReg : out STD_LOGIC; --! write to register from memory
RegWrite : out STD_LOGIC; --! Write to register from ALU output
MemRead : out STD_LOGIC; --! read from memory
MemWrite : out STD_LOGIC; --! write to memory
Branch : out STD_LOGIC; --! branch if equal
Branch_ne : out STD_LOGIC; --! branch if not equal
ALUop : out STD_LOGIC_VECTOR (1 downto 0)); --! input for ALU_Control
end Control;
--! @brief This is the controller that sets the control variables
--! @details depending on function field sets (RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,Branch,ALUop):
--! @details 000000:(1,0,0,1,0,0,0,0,10) --> R-type instruction
--! @details 100011:(0,1,1,1,1,0,0,0,00) --> load word instruction
--! @details 101011:(0,1,0,0,0,1,0,0,00) --> save word instruction
--! @details 000100:(0,0,0,0,0,0,1/0,0/1,01)--> branch equal/branch not equal instruction
architecture Behavioral of Control is
begin
Control_out: process(Instruction,Instruction_funct)
begin
case Instruction is
when "000000" => --R-format instruction
RegDst<= '1';
ALUSrc<= '0';
MemtoReg<= '0';
RegWrite<= '1';
MemRead<='0';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
ALUop<="10";
when "000100" => -- branch on equal
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '1';
Branch_ne<= '0';
ALUop <= "01";
when "000101" => -- branch on not equal
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
Branch_ne<= '1';
ALUop <= "01";
when "001000" => -- add immediate
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '0';
RegWrite<= '1';
MemRead<='0';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
when "101011" => -- store word
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '0';
RegWrite<= '0';
MemRead<='0';
MemWrite<='1';
Branch<='0';
Branch_ne<='0';
ALUop <= "00";
when "100011" => -- load word
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '1';
RegWrite<= '1';
MemRead<='1';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
ALUop <= "00";
when others => --error
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
Branch_ne<='0';
ALUop <= "00";
end case;
end process Control_out;
end Behavioral;
| mit | df621c35af41761096ccf51442bf2d35 | 0.542568 | 3.22134 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/correct_one_bit.vhd | 7 | 8,861 | -------------------------------------------------------------------------------
-- correct_one_bit.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description: Identifies single bit to correct in 32-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| mit | e42079e583320f8e685c9925485d71ce | 0.471391 | 4.341499 | false | false | false | false |
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`protect end_protected
| mit | 4dd428657ff797b63b3a801177ce8072 | 0.947463 | 1.85095 | false | false | false | false |
dsd-g05/lab5 | g05_possibility_table.vhd | 1 | 1,814 | -- Descp. Generate the table of all the possible pattern
--
-- entity name: g05_possibility_table
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 2, 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity g05_possibility_table is
port (
TC_EN : in std_logic; -- table counter enable
TC_RST : in std_logic; -- table counter reset
TM_IN : in std_logic; -- table memory input data
TM_EN : in std_logic; -- table memory write enable
CLK : in std_logic;
TC_LAST : out std_logic; -- last count flag
TM_ADDR : out std_logic_vector(11 downto 0);
TM_OUT : out std_logic -- table memory output
);
end g05_possibility_table;
architecture behavior of g05_possibility_table is
signal TC : std_logic_vector(11 downto 0);
signal MT : std_logic_vector(4195 downto 0);
begin
-- Table memory counter
process(CLK, TC_RST)
begin
if(TC_RST = '1') then
TC <= "000000000000";
TC_LAST <= '0';
elsif(rising_edge(CLK)) then
if(TC_EN = '1') then
if(TC(2 downto 0) = "101") then
if(TC(5 downto 3) = "101") then
if(TC(8 downto 6) = "101") then
if(TC(11 downto 9) = "101") then
TC_LAST <= '1';
TC <= "000000000000";
else
TC <= TC + 147;
end if;
else
TC <= TC + 19;
end if;
else
TC <= TC + 3;
end if;
else
TC <= TC + 1;
end if;
end if;
end if;
end process;
TM_ADDR <= TC;
-- Write in the memory table at a specific memory address
process(CLK)
begin
if(rising_edge(CLK)) then
if(TM_EN = '1') then
MT(to_integer(unsigned(TC))) <= TM_IN;
end if;
end if;
end process;
TM_OUT <= MT(to_integer(unsigned(TC)));
end behavior;
| mit | 3eaec43b32ad774884d8686db3f2421b | 0.618523 | 2.879365 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/fifo_mem/simulation/bmg_stim_gen.vhd | 2 | 12,282 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((11 <= 11),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((11 <= 11),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(10 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(10 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 2048 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 2048,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
| mit | 5775b8c7216aa453767e9a9383efe9c6 | 0.542664 | 3.545612 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/char_mem/simulation/char_mem_synth.vhd | 2 | 6,828 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: char_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY char_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE char_mem_synth_ARCH OF char_mem_synth IS
COMPONENT char_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: char_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | e2cf40ac24d392a506d3669fd0004e51 | 0.579965 | 3.797553 | false | false | false | false |
1995parham/FPGA-Homework | Project-Phase1/src/sequential/controller.vhd | 1 | 1,931 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-04-2016
-- Module Name: controller.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (clk, reset : in std_logic;
fitness_reset, fitness_clk : out std_logic;
fitness_done : in std_logic;
memory_rwbar, memory_en, memory_reset : out std_logic);
end entity controller;
architecture rtl of controller is
type state is (rst, fitness_process, memory_read, increase, memory_write);
signal next_state, current_state : state;
begin
-- next
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
current_state <= rst;
else
current_state <= next_state;
end if;
end if;
end process;
-- outputs
process (current_state)
begin
if current_state = rst then
fitness_reset <= '1';
fitness_clk <= '0';
memory_reset <= '1';
memory_en <= '0';
elsif current_state = fitness_process then
if fitness_done = '0' then
fitness_clk <= '1';
end if;
memory_reset <= '0';
memory_en <= '0';
elsif current_state = memory_read then
memory_rwbar <= '1';
memory_en <= '1';
fitness_clk <= '0';
elsif current_state = memory_write then
memory_rwbar <= '0';
end if;
end process;
-- next_state
process (current_state)
begin
if current_state = rst then
next_state <= fitness_process;
elsif current_state = fitness_process then
if fitness_done = '0' then
next_state <= memory_read;
else
next_state <= rst;
end if;
elsif current_state = memory_read then
next_state <= increase;
elsif current_state = increase then
next_state <= memory_write;
elsif current_state = memory_write then
next_state <= fitness_process;
end if;
end process;
end architecture rtl;
| gpl-3.0 | c85ce4947bae28c79a46a715df19b2c5 | 0.603314 | 3.32358 | false | false | false | false |
quicky2000/top_mandelbrot_1b | mult_16_8.vhd | 1 | 2,687 | --
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mult_16_8 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
p : out STD_LOGIC_VECTOR (15 downto 0));
end mult_16_8;
architecture Behavioral of mult_16_8 is
signal internal : std_logic_vector(31 downto 0);
signal internal_reduced : std_logic_vector(15 downto 0);
signal abs_a : std_logic_vector(15 downto 0);
signal abs_b : std_logic_vector(15 downto 0);
signal l_neg : std_logic := '0'; -- sign of product
begin
-- Compute absolute values of operands
abs_a <= std_logic_vector(abs(signed(a)));
abs_b <= std_logic_vector(abs(signed(b)));
-- Compute sign of product
l_neg <= a(15) xor b(15);
-- Compute unsigned extendend product
simple_mult : entity work.simple_mult port map(
a => abs_a,
b => abs_b,
p => internal);
-- internal <= std_logic_vector(unsigned(abs_a) * unsigned(abs_b));
-- Trunk product
trunc : entity work.truncator port map(
i => internal,
o => internal_reduced);
--internal_reduced(15 downto 0) <= internal(23 downto 8);
-- restablish sign if needed
p <= internal_reduced when l_neg = '0' else std_logic_vector(-signed(internal_reduced));
-- internal_a(15 downto 0) <= a;
-- internal_a(17) <= a(15);
-- internal_a(16) <= a(15);
-- internal_b(15 downto 0) <= b;
-- internal_b(17) <= b(15);
-- internal_b(16) <= b(15);
-- internal <= std_logic_vector(unsigned(internal_a) * unsigned(internal_b));
-- p(15 downto 0) <= internal(23 downto 8);
end Behavioral;
| gpl-3.0 | 177a40617ef5f53a0aa42f160766de64 | 0.667659 | 3.471576 | false | false | false | false |
1995parham/FPGA-Homework | HW-3/src/p5/shitf-register.vhd | 1 | 913 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: shitf-register.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity shift_register is
generic (N : integer := 8);
port (data_in : in std_logic_vector (N - 1 downto 0);
load, clk : in std_logic;
data_out : out std_logic);
end entity shift_register;
architecture rtl of shift_register is
signal reg : std_logic_vector (N - 1 downto 0);
begin
process (clk)
variable I : integer;
begin
if clk'event and clk = '1' then
if load = '1' then
reg <= data_in;
I := 0;
else
if I < N then
data_out <= reg(I);
I := I + 1;
else
I := 0;
end if;
end if;
end if;
end process;
end architecture rtl;
| gpl-3.0 | dcca63adb5e6f8500f2d07898377d5bd | 0.506024 | 3.381481 | false | false | false | false |
gregani/la16fw | syncsignal.vhd | 1 | 2,658 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity syncsignal is
generic(
n : integer := 3;
negedge : boolean := false
);
port(
clk_output : in std_logic;
input : in std_logic;
output : out std_logic
);
end syncsignal;
-- http://forums.xilinx.com/t5/Implementation/Attributes-in-Asynchronous-Input-Synchronization-issue-warnings/td-p/122912
--
-- TIG="TRUE" - Specifies a timing ignore for the asynchronous input
-- IOB="FALSE" = Specifies to not place the register into the IOB allowing
-- both synchronization registers to exist in the same slice
-- allowing for the shortest propagation time between them
-- ASYNC_REG="TRUE" - Specifies registers will be receiving asynchronous data
-- input to allow for better timing simulation
-- characteristics
-- SHIFT_EXTRACT="NO" - Specifies to the synthesis tool to not infer an SRL
-- HBLKNM="sync_reg" - Specifies to pack both registers into the same slice
architecture behavioral of syncsignal is
signal sync : unsigned(n-1 downto 0) := (others=>'0');
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of input : signal is "TRUE";
--attribute IOB of input : signal is "FALSE";
--attribute SHIFT_EXTRACT of sync: signal is "NO";
--attribute HBLKNM of sync : signal is "sync_reg";
begin
process (clk_output)
begin
if ((not negedge) and rising_edge(clk_output)) or
(negedge and falling_edge(clk_output)) then
sync <= sync(sync'high-1 downto 0) & input;
end if;
end process;
output <= sync(sync'high);
end behavioral;
| gpl-2.0 | 2a644e28eec277122348886502286064 | 0.673439 | 4.133748 | false | false | false | false |
1995parham/FPGA-Homework | Project-Phase1/src/sequential/main_t.vhd | 2 | 750 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 24-04-2016
-- Module Name: main_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main_t is
end entity main_t;
architecture rtl of main_t is
component main
port (str : in string (1 to 120);
clk, reset : in std_logic);
end component;
for all:main use entity work.main;
signal clk, reset : std_logic := '0';
signal str : string (1 to 120);
begin
m : main port map (str, clk, reset);
str <= (others => 'a');
reset <= '1', '0' after 10 ns;
clk <= not clk after 50 ns;
end architecture;
| gpl-3.0 | 3148697a8d8f2e4341f78c06f2dbd6dd | 0.506667 | 3.623188 | false | false | false | false |
Project-Bonfire/EHA | FPGA-integration/RTL/NI_AXI_wrapper.vhd | 3 | 15,288 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_wrapper is
generic (
-- Users to add parameters here
NI_DEPTH : integer := 16;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
AXI_RX_IRQ : out std_logic;
--Router connection
R_RX : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXI_wrapper;
architecture arch_imp of AXI_wrapper is
-- NI component declaration
component AXI_handshake_wrapper is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 16
);
port (
reset : in std_logic;
clk : in std_logic;
--Router connection
R_RX : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- Abstraction signals for AXI
AXI_RX_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_RX_IRQ_out : out std_logic;
AXI_data_read_in : in std_logic;
AXI_TX_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_send_en : in std_logic
);
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
-- Abstraction signals for AXI
signal AXI_RX : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_data_read : std_logic;
signal AXI_TX : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_send_en : std_logic;
-- Number of Slave Registers 4
signal RX_reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal TX_reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
-- Instantiation of Axi Bus Interface S00_AXI
AXI_Network_interface: AXI_handshake_wrapper
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH,
NI_DEPTH => NI_DEPTH)
port map (
reset => S_AXI_ARESETN,
clk => S_AXI_ACLK,
--Router connection
R_RX => R_RX,
R_TX => R_TX,
R_DRTS => R_DRTS,
R_DCTS => R_DCTS,
R_RTS => R_RTS,
R_CTS => R_CTS,
-- Abstraction signals for AXI
AXI_RX_out => AXI_RX,
AXI_RX_IRQ_out => AXI_RX_IRQ,
AXI_data_read_in => AXI_data_read,
AXI_TX_in => AXI_TX,
AXI_send_en => AXI_send_en
);
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
AXI_send_en <= '0';
AXI_data_read <= '0';
if S_AXI_ARESETN = '0' then
RX_reg <= (others => '0');
TX_reg <= (others => '0');
else
--input
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
-- Read data from AXI
when b"00" =>
TX_reg <= S_AXI_WDATA;
when b"01" =>
AXI_send_en <= '1';
when b"11" =>
AXI_data_read <= '1';
when others =>
TX_reg <= TX_reg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (axi_araddr, S_AXI_ARESETN, slv_reg_rden, AXI_RX)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"10" =>
reg_data_out <= AXI_RX;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
AXI_TX <= TX_reg;
-- User logic ends
end arch_imp;
| gpl-3.0 | b27e76e496576c56d6360b4d49d1d6e7 | 0.611068 | 3.417076 | false | false | false | false |
zzhou007/161lab | lab02/teebee.vhd | 1 | 4,198 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:14:24 01/27/2016
-- Design Name:
-- Module Name: /home/csmajs/masfo001/lab2/tbbbbbe.vhd
-- Project Name: lab2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: my_alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbbbbbe IS
END tbbbbbe;
ARCHITECTURE behavior OF tbbbbbe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT my_alu
PORT(
A : IN std_logic_vector(31 downto 0);
B : IN std_logic_vector(31 downto 0);
opcode : IN std_logic_vector(3 downto 0);
result : OUT std_logic_vector(35 downto 0);
carryout : OUT std_logic;
overflow : OUT std_logic;
zero : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(31 downto 0) := (others => '0');
signal B : std_logic_vector(31 downto 0) := (others => '0');
signal opcode : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal result : std_logic_vector(35 downto 0);
signal carryout : std_logic;
signal overflow : std_logic;
signal zero : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: my_alu PORT MAP (
A => A,
B => B,
opcode => opcode,
result => result,
carryout => carryout,
overflow => overflow,
zero => zero
);
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
--add value will go to new n+3 digit
opcode <= "1000";
A <= "10010000000000000000000000000000";
B <= "00011000000000000000000000000101";
wait for 10 ns;
--add value will not go to new n+3 digit
opcode <= "1000";
A <= "00010000000000000000000000000000";
B <= "00011000000000000000000000000101";
wait for 10 ns;
--signed add value will be 0
opcode <= "1100";
A <= "00000000000000001000000000000101";
B <= "00010000000000001000000000000101";
wait for 10 ns;
--signed add value will be +
opcode <= "1100";
A <= "10010000000000000000000000000000";
B <= "00001000000000000000000000000101";
wait for 10 ns;
--signed add value will be -
opcode <= "1100";
A <= "10010000000000000000000000000000";
B <= "00011000000000000000000000000101";
wait for 10 ns;
--unsigned sub value will be 0
opcode <= "1001";
A <= "10011000000000000000000000000101";
B <= "10011000000000000000000000000101";
wait for 10 ns;
--unsigned sub value will be +
opcode <= "1001";
A <= "10011000000000000000000000000101";
B <= "00011000000000000000000000000101";
wait for 10 ns;
--unsigned sub value will be -
opcode <= "1001";
A <= "00011000000000000000000000000101";
B <= "10011000000000000000000000000101";
wait for 10 ns;
--signed sub value will be 0
opcode <= "1101";
A <= "00001000000000000000000000000101";
B <= "00001000000000000000000000000101";
wait for 10 ns;
--signed sub value will be 0
opcode <= "1101";
A <= "00011000000000000000000000000101";
B <= "00011000000000000000000000000101";
wait for 10 ns;
--signed sub value will be 5
opcode <= "1101";
A <= "00001000000000000000000000000101";
B <= "00001000000000000000000000000000";
wait for 10 ns;
wait;
end process;
END;
| gpl-2.0 | 6f9421721e74bba75368b077d395b830 | 0.624345 | 4.021073 | false | false | false | false |
zzhou007/161lab | lab6/StoredTernaryCAM_Cell.vhd | 1 | 1,436 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STCAM_Cell is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
cell_search_bit : in STD_LOGIC;
cell_dont_care_bit : in STD_LOGIC;
cell_match_bit_in : in STD_LOGIC ;
cell_match_bit_out : out STD_LOGIC);
end STCAM_Cell;
architecture Behavioral of STCAM_Cell is
signal FF: STD_LOGIC;
signal DFF: STD_LOGIC;
begin
process(clk, rst, we, cell_search_bit, cell_dont_care_bit, cell_match_bit_in)
begin
--reset data most important
if rst = '1' then
FF <= '0';
DFF <= '0';
cell_match_bit_out <= '0';
-- write data from search
elsif we = '1' then
FF <= cell_search_bit;
DFF <= cell_dont_care_bit;
cell_match_bit_out <= '0';
--search
--previous result is wrong therefore nothing matches
elsif cell_match_bit_in = '0' then
cell_match_bit_out <= '0';
--previous result matches
elsif cell_match_bit_in = '1' then
--check if current cell is a dont care
if DFF = '1' then
cell_match_bit_out <= '1';
--if cell is not a dont care
else
--check current cell if match
if FF = cell_search_bit then
cell_match_bit_out <= '1';
else
--current cell doesnt match
cell_match_bit_out <= '0';
end if;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | 0ac3616dc8e7a2b19f95d09b78b2310a | 0.609331 | 2.973085 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_read_fsm.vhd | 9 | 83,511 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 385065a1693c2713ea3806631222f6df | 0.95312 | 1.842371 | false | false | false | false |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/uart.vhd | 6 | 7,018 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(6 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
read_value_reg <= ONES(read_value_reg'length-1 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
end; --architecture logic
| gpl-3.0 | d2630bab8f94c3430ed6d7d896c856c4 | 0.550727 | 3.542655 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/tool/test.vhd | 1 | 277 | process(ALUop, a, b)
begin
case ALUop is
when "000" =>
res <= a + b;
when "001" =>
res <= a - b;
when "010" =>
res <= a and b;
when "011" =>
res <= a or b;
when "100" =>
res <= not a;
when others =>
res <= (others => '0');
end case;
end process; | mit | f40effb4f2f880fa7e4ff8ffc6bc1fa1 | 0.483755 | 2.79798 | false | false | false | false |
meaepeppe/FIR_ISA | VHDL/FIR_constants.vhd | 1 | 609 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE FIR_constants IS
CONSTANT Nb : INTEGER := 9;
CONSTANT Ord: INTEGER := 8;
CONSTANT UO: INTEGER := 1;
CONSTANT Nbmult: INTEGER := 10;
CONSTANT Nbadder: INTEGER:= Nb; --NUM_BITS_MULT + integer(floor(log2(real(FIR_ORDER+1))));
CONSTANT pipe_d: INTEGER := 0;
CONSTANT IO_buffers: BOOLEAN := TRUE;
CONSTANT CELLS_PIPE_STAGES: INTEGER := Ord +UO -1;
TYPE IO_array IS ARRAY(UO-1 DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
END FIR_constants;
PACKAGE BODY FIR_constants IS
END PACKAGE BODY FIR_constants; | gpl-3.0 | 92160d3fed4500d5a399904358a26ec6 | 0.688013 | 3.107143 | false | false | false | false |
zzhou007/161lab | newlab5/cs161_processor.vhd | 1 | 4,713 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.cpu_component_library.all;
entity cs161_processor is
port (
clk : in std_logic;
rst : in std_logic;
prog_count : out std_logic_vector(31 downto 0);
instr_opcode : out std_logic_vector(5 downto 0);
reg1_addr : out std_logic_vector(4 downto 0);
reg1_data : out std_logic_vector(31 downto 0);
reg2_addr : out std_logic_vector(4 downto 0);
reg2_data : out std_logic_vector(31 downto 0);
write_reg_addr : out std_logic_vector(4 downto 0);
write_reg_data : out std_logic_vector(31 downto 0)
);
end cs161_processor;
architecture Behavioral of cs161_processor is
signal ctrlbr :std_logic := '0';
signal aluop :std_logic_vector(1 downto 0) := (others => '0');
signal aluout :std_logic_vector(3 downto 0) := (others => '0');
signal aluResult :std_logic_vector(31 downto 0) := (others => '0');
signal aluzero :std_logic := '0';
signal earth :std_logic := '0';
signal talumux :std_logic_vector(31 downto 0) := (others => '0');
signal tpcmux :std_logic := '0';
signal tpcmux0 :std_logic_vector(7 downto 0) := (others => '0');
signal tpcmux1 :std_logic_vector(7 downto 0) := (others => '0');
signal tdataadr :std_logic_vector(7 downto 0) := (others => '0');
signal pcout :std_logic_vector(7 downto 0) :=(others => '0');
signal memory_out :std_logic_vector(31 downto 0) :=(others => '0');
signal memRead :std_logic_vector(31 downto 0) := (others => '0');
signal memWrite :std_logic_vector(31 downto 0) := (others => '0');
signal pcnew :std_logic_vector(7 downto 0) :=(others => '0');
signal muxreg :std_logic_vector(4 downto 0) := (others => '0');
signal muxdat :std_logic_vector (31 downto 0) := (others => '0');
signal aluReadB :std_logic_vector (31 downto 0) := (others => '0');
signal aluReadA :std_logic_vector (31 downto 0) := (others => '0');
signal regread2 :std_logic_vector (31 downto 0) := (others => '0');
signal ctrlw :std_logic := '0';
signal ctrlrw :std_logic := '0';
signal ctrlrd :std_logic := '0';
signal m2r :std_logic := '0';
signal alusrc :std_logic := '0';
begin
reg2_addr <= memory_out(20 downto 16);
reg2_data <= regread2;
write_reg_addr <= muxreg;
write_reg_data <= muxdat;
prog_count <= std_logic_vector( resize(unsigned(pcout) sll 2, prog_count'length));
instr_opcode <= memory_out(31 downto 26);
reg1_addr <= memory_out(25 downto 21);
reg1_data <= aluReadA;
--IR
InstructionRegister : generic_register
generic map (SIZE => 8)
port map (
clk => clk,
rst => rst,
write_en => '1',
data_in => pcnew,
data_out => pcout
);
--Fetch
SplitMemory : memory
generic map ( COE_FILE_NAME => "init.coe")
port map(
clk => clk,
rst => rst,
instr_read_address => pcout,
instr_instruction => memory_out,
data_mem_write => ctrlw,
data_address => aluResult(7 downto 0),
data_write_data => regread2,
data_read_data => memRead
);
-- Control Unit
CONTROLLER: control_unit
port map(
instr_op => memory_out(31 downto 26),
reg_dst => ctrlrd,
branch => ctrlbr,
MEM_read => earth,
mem_to_reg => m2r,
alu_op => aluop,
MEM_write => ctrlw,
alu_src => alusrc,
reg_write => ctrlrw
);
Registers : cpu_registers
port map(
clk => clk,
rst => rst,
reg_write => ctrlrw,
read_register_1 => memory_out(25 downto 21),
read_register_2 => memory_out(20 downto 16),
write_register => muxreg,
write_data => muxdat,
read_data_1 => aluReadA,
read_data_2 => regread2
);
REG_MUX_1 : mux_2_1
generic map (SIZE => 5)
port map(ctrlrd, memory_out(20 downto 16), memory_out(15 downto 11), muxreg);
REG_MUX_2 : mux_2_1
generic map (SIZE => 32)
port map(m2r, aluResult, memRead, muxdat);
ALU_MUX : mux_2_1
generic map (SIZE => 32)
port map(alusrc, regread2, talumux, aluReadB);
ALUControlUnit : alu_control
port map(aluop, memory_out(5 downto 0), aluout);
ALUnit: alu
port map(aluout, aluReadA, aluReadB, aluzero, aluResult);
PCMUX : mux_2_1
generic map (SIZE => 8)
port map(tpcmux, tpcmux0, tpcmux1, pcnew);
talumux <= std_logic_vector(resize(signed(memory_out(15 downto 0)), aluReadB'length));
tpcmux <= (ctrlbr and aluzero);
tpcmux0 <= std_logic_vector(unsigned(pcout) + 1);
tpcmux1 <= std_logic_vector(unsigned( resize(signed(memory_out(15 downto 0)), pcnew'length)) + unsigned(pcout) + 1);
end Behavioral;
| gpl-2.0 | 81daefa9a95752f6e3d8e83ff3f97d61 | 0.608317 | 2.82554 | false | false | false | false |
6769/VHDL | Lab_2_part1/T_flip_flop.vhd | 1 | 335 | entity T_flip_flop is
port(T,clk,clear:in bit;
Q,QN:buffer bit
);
end T_flip_flop;
architecture internal of T_flip_flop is
begin
QN<=not Q;
process(clk,clear)
begin
if(clear='0') then Q<='0';
elsif(clk'event and clk='1') then
if T='1' then Q<= QN;
end if;
end if ;
end process;
end architecture internal; | gpl-2.0 | f2e40de42c12c99372fb5b1e9602750b | 0.641791 | 2.596899 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/user_vlog/COREAHBLITE_LIB/@b@f@m_@a@h@b@s@l@a@v@e/_primary.vhd | 2 | 1,654 | library verilog;
use verilog.vl_types.all;
entity BFM_AHBSLAVE is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
TPD : integer := 1;
DEBUG : integer := -1
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AWIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of INITFILE : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of ENFUNC : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUG : constant is 1;
end BFM_AHBSLAVE;
| gpl-3.0 | 91bcbea0a00b43a69e873ec0e1806859 | 0.50786 | 4.024331 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/char_mem/simulation/char_mem_tb.vhd | 2 | 4,355 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: char_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY char_mem_tb IS
END ENTITY;
ARCHITECTURE char_mem_tb_ARCH OF char_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
char_mem_synth_inst:ENTITY work.char_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 587546308a30f88c4b1d01ddca2ce976 | 0.619059 | 4.623142 | false | false | false | false |
1995parham/FPGA-Homework | HW-6/src/p8/counter.vhd | 1 | 869 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-05-2016
-- Module Name: counter.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (inc, dec : in std_logic;
output : out std_logic_vector (N - 1 downto 0);
clk : in std_logic);
end entity;
architecture rtl of counter is
signal count : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
output <= count;
process (clk)
begin
if clk'event and clk = '1' then
if inc = '1' then
count <= count + (0 => '1');
elsif dec = '1' then
count <= count - (0 => '1');
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 491e6708b6b5023955ead4af1954099d | 0.50748 | 3.476 | false | false | false | false |
1995parham/FPGA-Homework | HW-2/src/p11/p11.vhd | 1 | 1,170 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 28-03-2016
-- Module Name: p11.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity n_shift_register is
generic (N : integer := 32);
port (serial_in : in std_logic;
w_s : in std_logic := '1';
clk : in std_logic;
serial_out : out std_logic;
parallel_in : in std_logic_vector (N - 1 downto 0);
parallel_out : out std_logic_vector (N - 1 downto 0));
end entity n_shift_register;
architecture rtl of n_shift_register is
component d_register is
port (d, clk : in std_logic;
q : out std_logic);
end component;
for all:d_register use entity work.d_register;
signal Q : std_logic_vector (N downto 0);
signal D : std_logic_vector (N downto 1);
begin
Q(0) <= serial_in;
serial_out <= Q(N);
registers: for I in 1 to N generate
D(I) <= Q(I - 1) when w_s = '1' else parallel_in(I - 1);
ds : d_register port map (D(I), clk, Q(I));
parallel_out(I - 1) <= Q(I);
end generate registers;
end architecture rtl;
| gpl-3.0 | 1e5aff846ec3fac3fb480cdc5392923a | 0.560684 | 3.136729 | false | false | false | false |
zzhou007/161lab | lab04/cpu_constant_library.vhd | 1 | 894 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_constant_library is
-- opcodes
constant OPCODE_R_TYPE : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_LOAD_WORD : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_STORE_WORD : std_logic_vector(5 downto 0) := (others => '0');
constant OPCODE_BRANCH_EQ : std_logic_vector(5 downto 0) := (others => '0');
-- funct
constant FUNCT_AND : std_logic_vector(5 downto 0) := (others => '0');
constant FUNCT_OR : std_logic_vector(5 downto 0) := (others => '0');
-- ALU signals
constant ALU_AND : std_logic_vector(3 downto 0) := (others => '0');
constant ALU_OR : std_logic_vector(3 downto 0) := (others => '0');
end cpu_constant_library;
package body cpu_constant_library is
end cpu_constant_library;
| gpl-2.0 | be324dee6eec20139bb20b4760d734e6 | 0.59396 | 3.298893 | false | false | false | false |
meaepeppe/FIR_ISA | VHDL/Cell.vhd | 1 | 2,220 | LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.math_real.all;
USE work.FIR_constants.all;
ENTITY Cell IS
PORT(
CLK, RST_n, EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SUM_IN: IN STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
Bi: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
REG_OUT : OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
ADD_OUT: OUT STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0) -- aggiunti 9 bit di guardia
);
END ENTITY;
ARCHITECTURE beh_cell OF Cell IS
SIGNAL mult: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0);
SIGNAL mult_ext: STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
SIGNAL REG_OUT_sig: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
COMPONENT adder_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
sum_out: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT mult_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
mult_out: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
Reg: Reg_n GENERIC MAP(Nb => Nb)
PORT MAP(DIN => DIN, CLK => CLK, RST_n => RST_n, EN => EN, DOUT => REG_OUT_sig);
REG_OUT <= REG_OUT_sig;
Product: mult_n GENERIC MAP(Nb => Nb)
PORT MAP(in_a => REG_OUT_sig, in_b => Bi, mult_out => mult);
mult_extension_0: IF (Nbadder <= Nbmult) GENERATE
mult_ext <= mult ((mult'LENGTH - (Nbmult - Nbadder) -1) DOWNTO (mult'LENGTH)-1-(Nbmult-1));
END GENERATE;
mult_extension_1: IF (Nbadder > Nbmult) GENERATE
mult_ext(Nbmult-1 DOWNTO 0) <= mult ((mult'LENGTH -1) DOWNTO ((mult'LENGTH)-1-(Nbmult-1)) );
mult_ext(Nbadder-1 DOWNTO Nbmult) <= (others => mult_ext(Nbmult-1));
END GENERATE;
Sum: adder_n GENERIC MAP(Nb => mult_ext'LENGTH) -- aggiunti 9 bit di guardia
PORT MAP(in_a => SUM_IN, in_b => mult_ext, sum_out => ADD_OUT);
END beh_cell;
| gpl-3.0 | 9f7a0b540eb96820461bcdff1853d204 | 0.628829 | 2.723926 | false | false | false | false |
6769/VHDL | Lab_2_part1/Counter16anDisplay.vhd | 1 | 1,184 | entity Counter16anDisplay is
port(clk,enable,clear:in bit;
hex0,hex1,hex2,hex3:out bit_vector(7 downto 0)
);
end entity Counter16anDisplay;
architecture combination of Counter16anDisplay is
component NbitCounter
port(
clear:in bit:='1';
clk,enable:in bit ;
Q:buffer bit_vector(15 downto 0):=( others=>'0') );
--Q:buffer bit_vector(15 downto 0):="1111111111111100");
end component;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
signal midQ:bit_vector(15 downto 0);
begin
hex0(0)<='1';
hex1(0)<='1';
hex2(0)<='1';
hex3(0)<='1';
counter_part:NbitCounter port map(clear,clk,enable,midQ);
displayLED0:segment7Decoder port map(midQ(3 downto 0),hex0 (7 downto 1));
displayLED1:segment7Decoder port map(midQ(7 downto 4),hex1 (7 downto 1));
displayLED2:segment7Decoder port map(midQ(11 downto 8),hex2 (7 downto 1));
displayLED3:segment7Decoder port map(midQ(15 downto 12),hex3(7 downto 1));
end architecture combination; | gpl-2.0 | 6bc2905370030f406f5994c8322b44ea | 0.649493 | 3.472141 | false | false | false | false |
6769/VHDL | Lab_5/Modelsim/Segment7Decoder.vhd | 2 | 1,327 | library IEEE;
use ieee.numeric_bit.all;
entity Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; | gpl-2.0 | 1521e5d30689a3d08241b9442745db1b | 0.577995 | 3.446753 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/output_block_fifo16_patch.vhd | 9 | 15,340 | `protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9616)
`protect data_block
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`protect end_protected
| gpl-3.0 | 7b76777651d27b05e5629472cbf538c3 | 0.93605 | 1.89828 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/KeyTop.vhd | 1 | 2,234 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:42:32 12/5/2013
-- Design Name:
-- Module Name: TContrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity KeyTop is
port(
datain,clkin,clk50,rst_in: in std_logic;
dataready_out: out std_logic;
datareceived: in std_logic;
out_char: out std_logic_vector(7 downto 0)
);
end KeyTop;
architecture behave of KeyTop is
component Keyboard is
port (
-- PS2 clk and data
datain, clkin: in std_logic ;
-- filter clock :5M
fclk: in std_logic ;
rst: in std_logic;
-- fok : out std_logic ; -- data output enable signal
-- scan code signal output
scancode : out std_logic_vector(7 downto 0)
) ;
end component;
component divEven is
port(clk: in std_logic;
div: out std_logic);
end component;
component KeySignaltoChar is
PORT
(
key: in std_logic_vector(7 downto 0);
char: out std_logic_vector(7 downto 0)
);
end component;
signal scancode : std_logic_vector(7 downto 0);
signal rst : std_logic;
signal fclk: std_logic;
signal st: std_logic_vector(3 downto 0):="0000";
signal dataready : std_logic := '0';
signal char: std_logic_vector(7 downto 0);
signal chartmp: std_logic_vector(7 downto 0):="00000000";
begin
rst <= not rst_in;
u0: Keyboard port map(datain,clkin,fclk,rst,scancode);
u2: KeySignaltoChar port map(scancode,char);
u3: divEven port map(clk50,fclk);
out_char<=chartmp;
dataready_out <= dataready;
process(char,datareceived,clk50)
begin
if clk50'event and clk50 = '1' then
if char = "11110000" then -- scancode = F0
st <= "0001";
else
case st is
when "0001" =>
dataready <= '1';
chartmp <= char;
st <= "0000";
when others =>
st<="0000";
end case;
end if;
if datareceived = '1' then
dataready <= '0';
end if;
end if;
end process;
end behave;
| mit | 7d60051b76f6c3127f5dab4fe46e59ac | 0.612355 | 3.094183 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_bram_ctrl_top.vhd | 1 | 43,430 | -------------------------------------------------------------------------------
-- axi_bram_ctrl_top.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_top.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl_top.vhd (v3_0)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/9/2011 v1.03a
-- ~~~~~~
-- Update Create_Size_Default function to support 512 & 1024-bit BRAM.
-- Replace usage of Create_Size_Default function.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter on full_axi module.
-- Update ECC signal sizes for 128-bit support.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update WE size based on 128-bit ECC configuration.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Add C_ECC_TYPE top level parameter on axi_lite module.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Set C_ECC_TYPE = 1 for Hsiao DV regressions.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move Find_ECC_Size function to package.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove C_FAMILY from top level.
-- Remove C_FAMILY in axi_lite sub module.
-- ^^^^^^
-- JLJ 6/23/2011 v1.03a
-- ~~~~~~
-- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite;
use work.full_axi;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_bram_ctrl_top is
generic (
-- AXI Parameters
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 1;
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
-- Reserved parameters for future implementations.
-- C_ENABLE_AXI_CTRL_REG_IF : integer := 1;
-- By default the ECC AXI-Lite register interface is enabled
-- C_CE_FAILING_REGISTERS : integer := 1;
-- Enable CE (correctable error) failing registers
-- C_UE_FAILING_REGISTERS : integer := 1;
-- Enable UE (uncorrectable error) failing registers
-- C_ECC_STATUS_REGISTERS : integer := 1;
-- Enable ECC status registers
-- C_ECC_ONOFF_REGISTER : integer := 1;
-- Enable ECC on/off control register
-- C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_Rst_B : out std_logic;
BRAM_Clk_B : out std_logic;
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl_top;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl_top is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Model behavior of AXI Interconnect in simulation for wrapping of ID values.
constant C_SIM_ONLY : std_logic := '1';
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- Create top level constant to assign fixed value to ARSIZE and AWSIZE
-- when narrow bursting is parameterized out of the IP core instantiation.
-- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default;
-- v1.03a
constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH);
constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH);
-- Set internal parameters for ECC register enabling when C_ECC = 1
constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC;
constant C_CE_FAILING_REGISTERS_I : integer := C_ECC;
constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC;
constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC;
constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC;
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
--constant C_ECC_TYPE : integer := 1; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-- Port A
signal bram_en_a_int : std_logic := '0';
signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
-- Port B
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_en_b_int : std_logic := '0';
signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal S_AXI_ARREADY_int : std_logic := '0';
signal S_AXI_AWREADY_int : std_logic := '0';
signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- *** BRAM Port A Output Signals ***
BRAM_Rst_A <= not (S_AXI_ARESETN);
BRAM_Clk_A <= S_AXI_ACLK;
BRAM_En_A <= bram_en_a_int;
BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_A <= bram_addr_a_int;
bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
-- *** BRAM Port B Output Signals ***
GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Rst_B <= not (S_AXI_ARESETN);
BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_B <= bram_addr_b_int;
BRAM_En_B <= bram_en_b_int;
bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- 13.3
-- BRAM_WrData_B <= bram_wrdata_b_int;
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
end generate GEN_PORT_B;
GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Rst_B <= '0';
BRAM_WE_B <= (others => '0');
BRAM_WrData_B <= (others => '0');
BRAM_Addr_B <= (others => '0');
BRAM_En_B <= '0';
end generate GEN_NO_PORT_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_CLK_B
-- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled.
--
---------------------------------------------------------------------------
GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Clk_B <= S_AXI_ACLK;
end generate GEN_BRAM_CLK_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_NO_BRAM_CLK_B
-- Purpose: Drive default value for BRAM_Clk_B when single port
-- BRAM is enabled and no clock is necessary on the inactive
-- BRAM port.
--
---------------------------------------------------------------------------
GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Clk_B <= '0';
end generate GEN_NO_BRAM_CLK_B;
---------------------------------------------------------------------------
-- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl
-- respectively, based on design parameter setting of generic,
-- C_S_AXI_SUPPORTS_NARROW_BURST.
---------------------------------------------------------------------------
--
-- Generate: GEN_W_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on top level AXI signal inputs.
--
---------------------------------------------------------------------------
GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate
begin
axi_awsize_int <= S_AXI_AWSIZE;
axi_arsize_int <= S_AXI_ARSIZE;
end generate GEN_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_WO_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on hard coded
-- value that indicates all AXI transfers will be equal in
-- size to the AXI data bus.
--
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate
begin
-- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported)
-- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW;
-- v1.03a
axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
end generate GEN_WO_NARROW;
S_AXI_ARREADY <= S_AXI_ARREADY_int;
S_AXI_AWREADY <= S_AXI_AWREADY_int;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI_LITE
-- Purpose: Create internal signals for lower level write and read
-- channel modules to discard unused AXI signals when the
-- AXI protocol is set up for AXI-LITE.
--
---------------------------------------------------------------------------
GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate
begin
-- For simulation purposes ONLY
-- AXI Interconnect handles this in real system topologies.
S_AXI_BID <= S_AXI_BID_int;
S_AXI_RID <= S_AXI_RID_int;
-----------------------------------------------------------------------
--
-- Generate: GEN_SIM_ONLY
-- Purpose: Mimic behavior of AXI Interconnect in simulation.
-- In real hardware system, AXI Interconnect stores and
-- wraps value of ARID to RID and AWID to BID.
--
-----------------------------------------------------------------------
GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate
begin
-------------------------------------------------------------------
-- Must register and wrap the AWID signal
REG_BID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_BID_int <= (others => '0');
elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then
S_AXI_BID_int <= S_AXI_AWID;
else
S_AXI_BID_int <= S_AXI_BID_int;
end if;
end if;
end process REG_BID;
-------------------------------------------------------------------
-- Must register and wrap the ARID signal
REG_RID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_RID_int <= (others => '0');
elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then
S_AXI_RID_int <= S_AXI_ARID;
else
S_AXI_RID_int <= S_AXI_RID_int;
end if;
end if;
end process REG_RID;
-------------------------------------------------------------------
end generate GEN_SIM_ONLY;
---------------------------------------------------------------------------
--
-- Generate: GEN_HW
-- Purpose: Drive default values of RID and BID. In real system
-- these are left unconnected and AXI Interconnect is
-- responsible for values.
--
---------------------------------------------------------------------------
GEN_HW: if (C_SIM_ONLY = '0') generate
begin
S_AXI_BID_int <= (others => '0');
S_AXI_RID_int <= (others => '0');
end generate GEN_HW;
---------------------------------------------------------------------------
-- Instance: I_AXI_LITE
--
-- Description:
-- This module is for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
-- Instantiates ECC register block if enabled and
-- generates ECC logic, when enabled.
--
--
---------------------------------------------------------------------------
I_AXI_LITE : entity work.axi_lite
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- C_FAMILY => C_FAMILY ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_AWADDR => S_AXI_AWADDR ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_int ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
AXI_ARADDR => S_AXI_ARADDR ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_int ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_RdData_A => bram_rddata_a_int ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int
);
end generate GEN_AXI4LITE;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI
-- Purpose: Only create internal signals for lower level write and read
-- channel modules to assign AXI signals when the
-- AXI protocol is set up for non AXI-LITE IF connections.
-- For AXI4, all AXI signals are assigned to lower level modules.
--
-- For AXI-Lite connections, generate statement above will
-- create default values on these signals (assigned here).
--
---------------------------------------------------------------------------
GEN_AXI4: if (IF_IS_AXI4) generate
begin
---------------------------------------------------------------------------
-- Instance: I_FULL_AXI
--
-- Description:
-- Full AXI BRAM controller logic.
-- Instantiates wr_chnl and rd_chnl modules.
-- If enabled, ECC register interface is included.
--
---------------------------------------------------------------------------
I_FULL_AXI : entity work.full_axi
generic map (
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_FAULT_INJECT => C_FAULT_INJECT ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => axi_awsize_int ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY_int ,
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => axi_arsize_int ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY_int ,
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
-- v1.02a
-- Seperate instantiations for wr_chnl and rd_chnl moved to
-- full_axi module.
end generate GEN_AXI4;
end architecture implementation;
| mit | 50f9b22fe2c010f1e61b30b5a2c77b92 | 0.46385 | 3.790034 | false | false | false | false |
sbates130272/capi-textswap | rtl/proc_text.vhd | 1 | 8,514 | --------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description:
-- Text Processor. Find the locations of a substring in a
-- string of data.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
use capi.misc.all;
use capi.std_logic_1164_additions.all;
entity proc_text is
port (
clk : in std_logic;
en : in std_logic;
idata : in std_logic_vector(0 to 511);
ivalid : in std_logic;
idone : in std_logic;
iready : out std_logic;
odata : out std_logic_vector(0 to 511);
ovalid : out std_logic;
odirty : out std_logic;
oready : in std_logic;
odone : out std_logic;
len : in unsigned(0 to 31);
reg_text_search : in std_logic_vector(0 to 127);
reg_text_clear : in std_logic
);
end entity proc_text;
architecture main of proc_text is
signal wrap_buf : std_logic_vector(0 to reg_text_search'high - 8);
signal buf : std_logic_vector(0 to wrap_buf'length + idata'length - 1);
signal iready_i : std_logic := '1';
alias needle : std_logic_vector(reg_text_search'range) is reg_text_search;
signal mask : std_logic_vector(0 to needle'length / 8 - 1);
type cmpres_t is array (natural range <>) of
std_logic_vector(0 to needle'length / 8 - 1);
signal stage1 : cmpres_t(0 to buf'length / 8 - 1);
signal stage2 : std_logic_vector(stage1'reverse_range);
signal stage3 : std_logic_vector(stage2'high+1 downto stage2'low);
signal stage1_valid : std_logic;
signal stage2_valid : std_logic;
signal stage3_valid : std_logic;
function strcmp (haystack, needle : std_logic_vector)
return std_logic_vector is
variable ret : std_logic_vector(0 to needle'length / 8 - 1);
begin
for i in ret'range loop
if haystack'low + (i+1)*8-1 > haystack'high then
ret(i) := '0';
elsif haystack(haystack'low + i*8 to haystack'low + (i+1)*8-1) =
needle(i*8 to (i+1)*8-1) then
ret(i) := '1';
else
ret(i) := '0';
end if;
end loop;
return ret;
end function;
signal lbs_empty : std_logic;
signal lbs_full : std_logic;
signal lbs_word : unsigned(31 downto 0);
signal lbs_bit : unsigned(log2_ceil(stage2'length)-1 downto 0);
signal lbs_valid : std_logic;
signal lbs_done : std_logic;
signal lbs_clear : std_logic;
signal done_next : std_logic;
signal idx : signed(0 to 31);
signal idx_valid : std_logic;
signal idx_done : std_logic;
subtype outp_count_t is integer range 0 to odata'length / idx'length - 1;
signal outp_count : outp_count_t := 0;
signal high_word : std_logic;
signal odata_next : std_logic_vector(odata'range);
impure function odata_pad
return std_logic_vector is
variable ret : std_logic_vector(odata'range);
begin
for i in 0 to odata'length/32 -1 loop
ret(i*32 to (i+1)*32-1) := endian_swap((0 => '0', 1 to 31 => '1'));
end loop;
return ret;
end function;
begin
iready <= iready_i;
buf <= wrap_buf & idata;
WRAP_BUF_P: process (clk) is
begin
if rising_edge(clk) then
if reg_text_clear = '1' then
wrap_buf <= (others=>'0');
elsif ivalid = '1' and iready_i = '1' then
wrap_buf <= buf(buf'high-wrap_buf'length+1 to buf'high);
end if;
end if;
end process WRAP_BUF_P;
COMPARE_P: process (clk) is
begin
if rising_edge(clk) then
mask <= strcmp(needle, (needle'range=>'0'));
stage1_valid <= ivalid and iready_i;
stage2_valid <= stage1_valid and or_reduce(mask);
stage3_valid <= stage2_valid;
for i in stage1'range loop
stage1(i) <= strcmp(buf(i*8 to buf'high), needle);
stage2(i) <= and_reduce(stage1(i) or mask);
end loop;
stage3 <= "0" & (stage2 and not resize(mask, stage2'length));
end if;
end process COMPARE_P;
list_bits_set_i: entity work.list_bits_set
generic map (
DATA_WIDTH => stage3'length,
INPUT_FIFO_ADDR_BITS => 6)
port map (
clk => clk,
en => oready,
clear => lbs_clear,
empty => lbs_empty,
din => stage3,
din_vld => stage3_valid,
full => lbs_full,
word => lbs_word,
bit_idx => lbs_bit,
vld => lbs_valid);
DEDUP_P: process (clk) is
begin
if rising_edge(clk) and oready = '1' then
idx <= signed(resize(lbs_word * (idata'length / 8), idx'length)
+ resize(lbs_bit, idx'length)) - wrap_buf'length / 8;
idx_valid <= lbs_valid;
end if;
end process DEDUP_P;
DONE_P: process (clk) is
begin
if rising_edge(clk) and oready = '1' then
lbs_done <= idone and lbs_empty and not stage1_valid and
not stage2_valid and not stage3_valid and not ivalid;
idx_done <= lbs_done and not idx_valid;
odone <= done_next;
end if;
end process;
OUT_P: process (clk) is
begin
if rising_edge(clk) then
ovalid <= '0';
if oready = '1' then
if idx_valid = '1' then
if outp_count = outp_count_t'high then
outp_count <= 0;
odata <= odata_next(0 to odata_next'high - idx'length) &
endian_swap(std_logic_vector(idx));
odata_next <= odata_pad;
ovalid <= '1';
high_word <= not high_word;
else
odata_next(outp_count*idx'length to (outp_count+1)*idx'length-1) <=
endian_swap(std_logic_vector(idx));
outp_count <= outp_count + 1;
end if;
elsif idx_done = '1' and done_next = '0' then
odata <= odata_next;
odata_next <= odata_pad;
if outp_count > 0 or high_word = '1' then
ovalid <= not done_next;
high_word <= not high_word;
end if;
if outp_count > 0 then
done_next <= high_word;
else
done_next <= not high_word;
end if;
end if;
end if;
if en = '0' then
odata <= (others=>'0');
odata_next <= odata_pad;
ovalid <= '0';
high_word <= '0';
outp_count <= 0;
done_next <= '0';
end if;
end if;
end process OUT_P;
FLAGS: process (clk) is
begin
if rising_edge(clk) then
if en = '0' then
iready_i <= '0';
odirty <= '0';
lbs_clear <= '1';
else
iready_i <= not lbs_full;
odirty <= '1';
lbs_clear <= '0';
end if;
end if;
end process FLAGS;
end architecture main;
| apache-2.0 | 736aa989e2b159ddbeee3af7f825fa51 | 0.492013 | 3.889447 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@b@f@m_@a@h@b@s@l@a@v@e/_primary.vhd | 3 | 1,221 | library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHBSLAVE is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
TPD : integer := 0;
DEBUG : integer := 1;
NAME : string := ""
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic
);
end MSS_BFM_AHBSLAVE;
| gpl-3.0 | a0f587be535b237a90630c3910123666 | 0.415233 | 4.111111 | false | false | false | false |
meaepeppe/FIR_ISA | VHDL/FIR_filter.vhd | 1 | 4,881 | LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.math_real.all;
USE work.FIR_constants.all;
ENTITY FIR_filter IS
PORT(
CLK, RST_n: IN STD_LOGIC;
VIN: IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1
VOUT: OUT STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_fir OF FIR_filter IS
TYPE sum_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL Bi: sig_array; -- there IS Ord instead of Ord-1 becaUSE the coeffs are Ord+1
SIGNAL REG_OUT_array: sig_array;
SIGNAL SUM_OUT_array: sum_array;
SIGNAL VIN_delay_line: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Coeffs_delayed: STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0);
SIGNAL DIN_mult: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0);
SIGNAL mult_ext: STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
COMPONENT Cell IS
PORT(
CLK, RST_n, EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SUM_IN: IN STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
Bi: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
REG_OUT : OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
ADD_OUT: OUT STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0) -- aggiunti 9 bit di guardia
);
END COMPONENT;
COMPONENT Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT mult_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
mult_out: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
-----------------------------------------------------------
------------------------ Input Buffers --------------------
In_buffers_1: IF IO_buffers GENERATE
VIN_delay_line(0) <= VIN;
data_in_reg: Reg_n GENERIC MAP (Nb => Nb)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN,
DIN => DIN,
DOUT => REG_OUT_array(0)
);
Coeffs_in_reg: Reg_n GENERIC MAP (Nb => ((Ord+1)*Nb))
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN,
DIN => Coeffs,
DOUT => Coeffs_delayed
);
VIN_in_reg: Reg_n GENERIC MAP (Nb => 1)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => '1',
DIN => VIN_delay_line(0 DOWNTO 0),
DOUT => VIN_delay_line(1 DOWNTO 1)
);
END GENERATE;
In_buffers_0: IF NOT(IO_buffers) GENERATE
Coeffs_delayed <= Coeffs;
REG_OUT_array(0) <= DIN;
VIN_delay_line(1) <= VIN;
END GENERATE;
--------------------------------------------------------------
------------------------ First Multiplier --------------------
Coeff_gen: FOR i IN 0 to Ord GENERATE
Bi(i) <= Coeffs_delayed(((i+1)*Nb)-1 DOWNTO (i*Nb));
END GENERATE;
DIN_mult_gen: mult_n GENERIC MAP(Nb => Nb)
PORT MAP
(
in_a => REG_OUT_array(0),
in_b => Bi(0),
mult_out => DIN_mult
);
DIN_mult_extension_0: IF (Nbadder <= Nbmult) GENERATE
mult_ext <= DIN_mult((DIN_mult'LENGTH - (Nbmult - Nbadder) -1) DOWNTO (DIN_mult'LENGTH)-1-(Nbmult-1));
END GENERATE;
DIN_mult_extension_1: IF (Nbadder > Nbmult) GENERATE
mult_ext(Nbmult-1 DOWNTO 0)<= DIN_mult((DIN_mult'LENGTH -1) DOWNTO ((DIN_mult'LENGTH)-1-(Nbmult-1)) );
mult_ext(Nbadder-1 DOWNTO Nbmult) <= (OTHERS => mult_ext(Nbmult-1));
END GENERATE;
SUM_OUT_array(0) <= mult_ext;
-------------------------------------------------------------
------------------------ Matrix of Cells --------------------
Cells_gen: FOR j IN 0 to Ord-1 GENERATE
Single_cell: Cell PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN_delay_line(1),
DIN => REG_OUT_array(j),
SUM_IN => SUM_OUT_array(j),
Bi => Bi(j+1),
REG_OUT => REG_OUT_array(j+1),
ADD_OUT => SUM_OUT_array(j+1)
);
END GENERATE;
-----------------------------------------------------------
----------------------- Output Buffers --------------------
Out_buffers_1: IF IO_buffers GENERATE
data_out_reg: Reg_n GENERIC MAP (Nb => Nb)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN_delay_line(1),
DIN => SUM_OUT_array(Ord)(Nb-1 DOWNTO 0),
DOUT => DOUT
);
VIN_out_reg: Reg_n GENERIC MAP (Nb => 1)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => '1',
DIN => VIN_delay_line(1 DOWNTO 1),
DOUT => VIN_delay_line(2 DOWNTO 2)
);
VOUT <= VIN_delay_line(2);
END GENERATE;
Out_buffers_0: IF NOT(IO_buffers) GENERATE
DOUT <= SUM_OUT_array(Ord)(Nb-1 DOWNTO 0);
VOUT <= VIN;
END GENERATE;
END beh_fir;
| gpl-3.0 | fede32592ac6b39c4642041b773af70d | 0.539644 | 2.940361 | false | false | false | false |
gregani/la16fw | test_mainmodule.vhd | 1 | 4,742 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_main is
end test_main;
architecture behavior of test_main is
-- Component Declaration for the Unit Under Test (UUT)
component mainmodule
-- generic(
-- tick_1M_div : integer
-- );
port(
clk_in : in std_logic;
spi_ss_n : in std_logic;
spi_sclk : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic;
led_out : out std_logic;
fifo_clk : in std_logic;
fifo_empty : out std_logic;
fifo_read_n : in std_logic;
fifo_data : out std_logic_vector(15 downto 0);
logic_data : in std_logic_vector(15 downto 0)
-- logic_data : in std_logic_vector(15 downto 2);
-- debug, debug2 : out std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal spi_ss_n : std_logic := '1';
signal spi_sclk : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal fifo_read_n : std_logic := '1';
signal logic_data : std_logic_vector(15 downto 0) := (others=>'0');
--Outputs
signal spi_miso : std_logic;
signal led_out : std_logic;
signal fifo_empty : std_logic;
signal fifo_data : std_logic_vector(15 downto 0);
-- internal signals
-- Clock period definitions
constant clk_period : time := 20.83 ns;
constant sclk_period : time := 100 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: mainmodule
-- generic map(
-- tick_1M_div => 48
-- )
port map(
clk_in => clk,
spi_ss_n => spi_ss_n,
spi_sclk => spi_sclk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
led_out => led_out,
fifo_clk => clk,
fifo_empty => fifo_empty,
fifo_read_n => fifo_read_n,
fifo_data => fifo_data,
logic_data => logic_data(15 downto 2)
);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- send spi data
procedure spi_start is
begin
wait for 2*sclk_period;
spi_ss_n <= '0';
wait for 2*sclk_period;
end spi_start;
procedure spi_stop is
begin
wait for 2*sclk_period;
spi_ss_n <= '1';
wait for 2*sclk_period;
end spi_stop;
procedure spi_send(data: in unsigned(7 downto 0)) is
begin
for i in 0 to 7 loop
spi_mosi <= data(7-i);
wait for sclk_period/2;
spi_sclk <= '1';
wait for sclk_period/2;
spi_sclk <= '0';
end loop;
end spi_send;
begin
-- wait for internal reset
wait for clk_period*50;
-- insert stimulus here
-- -- read adress 0x00 (fpga bitstream version)
-- spi_start;
-- spi_send('1' & to_unsigned(0, 7));
-- spi_send(to_unsigned(0, 8));
-- spi_stop;
--
-- -- write adress 0x05, data 0x80 (set led pwm to 50%)
-- spi_start;
-- spi_send('0' & to_unsigned(5, 7));
-- spi_send(to_unsigned(128, 8));
-- spi_stop;
--
-- -- select channels
-- spi_start;
-- spi_send('0' & to_unsigned(2, 7));
-- spi_send(to_unsigned(255, 8));
-- spi_stop;
-- spi_start;
-- spi_send('0' & to_unsigned(3, 7));
-- spi_send(to_unsigned(255, 8));
-- spi_stop;
--
-- -- set base clock to 100MHz
-- spi_start;
-- spi_send('0' & to_unsigned(10, 7));
-- spi_send(to_unsigned(0, 8));
-- spi_stop;
--
-- -- set sample rate to 5Mhz => n = 20-1
-- spi_start;
-- spi_send('0' & to_unsigned(4, 7));
-- spi_send(to_unsigned(20 - 1, 8));
-- spi_stop;
--
-- -- start sampling
-- spi_start;
-- spi_send('0' & to_unsigned(1, 7));
-- spi_send(to_unsigned(1, 8));
-- spi_stop;
--
-- -- read some values from fifo
wait until fifo_empty = '0';
-- wait for 100 us;
-- wait for 50*clk_period;
-- wait until falling_edge(clk);
-- wait until rising_edge(clk);
-- for i in 1 to 1000 loop
-- fifo_read_n <= '0';
-- wait for clk_period;
-- fifo_read_n <= '1';
-- wait for clk_period;
-- end loop;
wait;
end process;
end;
| gpl-2.0 | 139eff7a2e3f8b2c7c130ded44e625af | 0.488823 | 3.448727 | false | false | false | false |
zzhou007/161lab | newlab5/cpu_constant_library.vhd | 1 | 1,511 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_constant_library is
-- opcodes
constant OPCODE_R_TYPE : std_logic_vector(5 downto 0) := "000000";
constant OPCODE_LOAD_WORD : std_logic_vector(5 downto 0) := "100011";
constant OPCODE_STORE_WORD : std_logic_vector(5 downto 0) := "101011";
constant OPCODE_BRANCH_EQ : std_logic_vector(5 downto 0) := "000100";
constant OPCODE_ADDI : std_logic_vector(5 downto 0) := "001000";
-- funct
constant FUNCT_AND : std_logic_vector(5 downto 0) := "100100";
constant FUNCT_OR : std_logic_vector(5 downto 0) := "100101";
constant FUNCT_ADD : std_logic_vector(5 downto 0) := "100000";
constant FUNCT_SUBTRACT : std_logic_vector(5 downto 0) := "100010";
constant FUNCT_LESS_THAN : std_logic_vector(5 downto 0) := "101010";
constant FUNCT_NOR : std_logic_vector(5 downto 0) := "100111";
-- ALU signals
constant ALU_AND : std_logic_vector(3 downto 0) := "0000";
constant ALU_OR : std_logic_vector(3 downto 0) := "0001";
constant ALU_ADD : std_logic_vector(3 downto 0) := "0010";
constant ALU_SUBTRACT : std_logic_vector(3 downto 0) := "0110";
constant ALU_LESS_THAN : std_logic_vector(3 downto 0) := "0111";
constant ALU_NOR : std_logic_vector(3 downto 0) := "1100";
end cpu_constant_library;
package body cpu_constant_library is
end cpu_constant_library;
| gpl-2.0 | 020288323144b23023d964550aebe483 | 0.60953 | 3.365256 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/Keyboard.vhd | 1 | 3,036 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Keyboard is
port (
datain, clkin : in std_logic ; -- PS2 clk and data
fclk, rst : in std_logic ; -- filter clock
-- fok : out std_logic ; -- data output enable signal
scancode : out std_logic_vector(7 downto 0) -- scan code signal output
) ;
end Keyboard ;
architecture rtl of Keyboard is
type state_type is (delay, start, d0, d1, d2, d3, d4, d5, d6, d7, parity, stop, finish) ;
signal data, clk, clk1, clk2, odd, fok : std_logic ; -- ë´Ì´¦ÀíÄÚ²¿ÐźÅ, oddΪÆæżУÑé
signal code : std_logic_vector(7 downto 0) ;
signal state : state_type ;
begin
clk1 <= clkin when rising_edge(fclk) ;
clk2 <= clk1 when rising_edge(fclk) ;
clk <= (not clk1) and clk2 ;
data <= datain when rising_edge(fclk) ;
odd <= code(0) xor code(1) xor code(2) xor code(3)
xor code(4) xor code(5) xor code(6) xor code(7) ;
scancode <= code when fok = '1' ;
process(rst, fclk)
begin
if rst = '1' then
state <= delay ;
code <= (others => '0') ;
fok <= '0' ;
elsif rising_edge(fclk) then
fok <= '0' ;
case state is
when delay =>
state <= start ;
when start =>
if clk = '1' then
if data = '0' then
state <= d0 ;
else
state <= delay ;
end if ;
end if ;
when d0 =>
if clk = '1' then
code(0) <= data ;
state <= d1 ;
end if ;
when d1 =>
if clk = '1' then
code(1) <= data ;
state <= d2 ;
end if ;
when d2 =>
if clk = '1' then
code(2) <= data ;
state <= d3 ;
end if ;
when d3 =>
if clk = '1' then
code(3) <= data ;
state <= d4 ;
end if ;
when d4 =>
if clk = '1' then
code(4) <= data ;
state <= d5 ;
end if ;
when d5 =>
if clk = '1' then
code(5) <= data ;
state <= d6 ;
end if ;
when d6 =>
if clk = '1' then
code(6) <= data ;
state <= d7 ;
end if ;
when d7 =>
if clk = '1' then
code(7) <= data ;
state <= parity ;
end if ;
WHEN parity =>
IF clk = '1' then
if (data xor odd) = '1' then
state <= stop ;
else
state <= delay ;
end if;
END IF;
WHEN stop =>
IF clk = '1' then
if data = '1' then
state <= finish;
else
state <= delay;
end if;
END IF;
WHEN finish =>
state <= delay ;
fok <= '1' ;
when others =>
state <= delay ;
end case ;
end if ;
end process ;
end rtl ;
| mit | ffa9fb297e1b471276def86ccf2c5946 | 0.495718 | 2.988189 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/cross_clk_sync_fifo_1.vhd | 1 | 94,731 | -------------------------------------------------------------------------------
-- $Id: axi_quad_spi.vhd
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_1 is
generic (
C_FAMILY : string;
C_FIFO_DEPTH : integer;
C_DATA_WIDTH : integer;
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_S_AXI_DATA_WIDTH : integer;
C_NUM_TRANSFER_BITS : integer;
--C_AXI_SPI_CLK_EQ_DIFF : integer;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_cdc_to_spi : in std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi : in std_logic;
SPISR_0_CMD_Error_cdc_to_axi : out std_logic;
----------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic;
spisel_d1_reg_cdc_to_axi : out std_logic;
----------------------------------------
spisel_pulse_cdc_from_spi : in std_logic;
spisel_pulse_cdc_to_axi : out std_logic;
----------------------------
Mst_N_Slv_mode_cdc_from_spi : in std_logic;
Mst_N_Slv_mode_cdc_to_axi : out std_logic;
----------------------------
slave_MODF_strobe_cdc_from_spi : in std_logic;
slave_MODF_strobe_cdc_to_axi : out std_logic;
----------------------------
modf_strobe_cdc_from_spi : in std_logic;
modf_strobe_cdc_to_axi : out std_logic;
----------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
----------------------------
reset_RcFIFO_ptr_cdc_from_axi : in std_logic;
reset_RcFIFO_ptr_cdc_to_spi : out std_logic;
----------------------------
Rx_FIFO_Empty_cdc_from_axi : in std_logic;
Rx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Full_cdc_from_axi : in std_logic;
Tx_FIFO_Full_cdc_to_spi : out std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi : out std_logic;
----------------------------
dtr_underrun_cdc_from_spi : in std_logic;
dtr_underrun_cdc_to_axi : out std_logic;
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1));
----------------------------
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic
);
end entity cross_clk_sync_fifo_1;
-------------------------------------------------------------------------------
architecture imp of cross_clk_sync_fifo_1 is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
signal spisel_pulse_cdc_from_spi_d4 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Full_cdc_from_spi_d1 : std_logic;
signal Rx_FIFO_Full_cdc_from_spi_d2 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
signal modf_strobe_cdc_to_axi_d1 : std_logic;
signal modf_strobe_cdc_to_axi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal rx_fifo_full_int, RST_RX_FF : std_logic;
signal rx_fifo_full_int_2 : std_logic;
signal RST_spiXfer_done_FF : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_int : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal reset_RX_FIFO_Rst_pulse : std_logic;
signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
signal SPICR_RX_FIFO_Rst_en : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal SPICR_RX_FIFO_Rst_en_d2 : std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
-- signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
-- signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_spi_d1 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_spi_d2 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- -- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
-- signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
-- signal modf_strobe_cdc_to_axi_d1 : std_logic;
-- signal modf_strobe_cdc_to_axi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal rx_fifo_full_int, RST_RX_FF : std_logic;
-- signal rx_fifo_full_int_2 : std_logic;
-- signal RST_spiXfer_done_FF : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal reset_RX_FIFO_Rst_pulse : std_logic;
-- signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
-- signal SPICR_RX_FIFO_Rst_en : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
--------------------------
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of CMD_ERR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_D1_REG_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_PULSE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MST_N_SLV_MODE_S2AX_1_CDC : label is "TRUE";
-- -- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_EMPTY_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_FULL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPIXFER_DONE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_RST_AX2S_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of RX_FIFO_FULL_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_S2AX_1_CDC: label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of DTR_UNDERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SLV_MODF_STRB_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_EMPT_4_SPISR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
attribute KEEP : string;
attribute KEEP of SPISR_0_CMD_Error_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_d1_reg_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of Mst_N_Slv_mode_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d1 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
SPISSR_cdc_from_axi_d1_and_reduce <= and_reduce(SPISSR_cdc_from_axi_d2);
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE =0) generate
--==============================================================================
CMD_ERR_S2AX_1_CDC: component FDR
generic map(INIT => '0' -- added on 16th Feb
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi,
R => Soft_Reset_op
);
CMD_ERR_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISR_0_CMD_Error_cdc_to_axi <= SPISR_0_CMD_Error_cdc_from_spi_d2;
-----------------------------------------------------------
--==============================================================================
SPISEL_D1_REG_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
MST_N_SLV_MODE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi,
R => Soft_Reset_op
);
MST_N_SLV_MODE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi_d1,
R => Soft_Reset_op
);
Mst_N_Slv_mode_cdc_to_axi <= Mst_N_Slv_mode_cdc_from_spi_d2;
---------------------------------------------------
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLV_MODF_STRB_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor Slave_MODF_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;-- 2/21/2012
--==============================================================================
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
RX_FIFO_EMPTY_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
RX_FIFO_EMPTY_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Rx_FIFO_Empty_cdc_to_spi <= Rx_FIFO_Empty_cdc_from_axi_d2;
-------------------------------------------------
--==============================================================================
TX_FIFO_EMPTY_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi,
R => Soft_Reset_op
);
TX_FIFO_EMPTY_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_cdc_to_axi <= Tx_FIFO_Empty_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi,
R => Soft_Reset_op
);
TX_EMPT_4_SPISR_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
--==============================================================================
TX_FIFO_FULL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
TX_FIFO_FULL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Tx_FIFO_Full_cdc_to_spi <= Tx_FIFO_Full_cdc_from_axi_d2;
-----------------------------------------------
--==============================================================================
SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi,
R => Soft_Reset_op
);
SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_d1,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P;
-------------------------------------------------
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d1,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RX_FIFO_Rst_pulse <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
-----------------------------------------------------------
------------------------------------------
RX_FIFO_FULL_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Rx_FIFO_Full_cdc_from_spi,
R => Soft_Reset_op
);
RX_FIFO_FULL_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Rx_FIFO_Full_cdc_from_spi_d1,
R => Soft_Reset_op
);
Rx_FIFO_Full_cdc_to_axi <= Rx_FIFO_Full_cdc_from_spi_d2;
------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------
DTR_UNDERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
--drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2; -- 2/21/2012
end generate LOGIC_GENERATION_FDR ;
LOGIC_GENERATION_CDC : if LOGIC_CHANGE = 1 generate
--==============================================================================
CMD_ERR_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPISR_0_CMD_Error_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => SPISR_0_CMD_Error_cdc_to_axi
);
--==============================================================================
SPISEL_D1_REG_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_4: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d3,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d4;
--==============================================================================
MST_N_SLV_MODE_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Mst_N_Slv_mode_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Mst_N_Slv_mode_cdc_to_axi
);
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
--Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
--Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLV_MODF_STRB_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2,--Slave_MODF_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;
--==============================================================================
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
-- modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2;
--==============================================================================
RX_FIFO_EMPTY_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Rx_FIFO_Empty_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => Rx_FIFO_Empty_cdc_to_spi
);
--==============================================================================
TX_FIFO_EMPTY_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_cdc_to_axi
);
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
--==============================================================================
TX_FIFO_FULL_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Full_cdc_from_axi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Full_cdc_to_spi
);
--==============================================================================
SPIXFER_DONE_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spiXfer_done_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_cdc_to_axi
);
--==============================================================================
RX_FIFO_FULL_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
--==============================================================================
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
--==============================================================================
DTR_UNDERRUN_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
--==============================================================================
SPICR_0_LOOP_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
--==============================================================================
SPICR_1_SPE_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
--==============================================================================
SPICR_2_MST_N_SLV_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--==============================================================================
SPICR_3_CPOL_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--==============================================================================
SPICR_4_CPHA_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--==============================================================================
SPICR_5_TXFIFO_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--==============================================================================
SPICR_6_RXFIFO_RST_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--==============================================================================
SPICR_7_SS_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--==============================================================================
SPICR_8_TR_INHIBIT_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--==============================================================================
SPICR_9_LSB_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
--==============================================================================
SR_3_MODF_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
--==============================================================================
SPISSR_SYNC_GEN_CDC: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
SPISSR_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPISSR_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi,
scndry_out => SPISSR_cdc_from_axi_d2(i)
);
end generate SPISSR_SYNC_GEN_CDC;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
-- drr_Overrun_int_cdc_from_spi_d1 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
--drr_Overrun_int_cdc_from_spi_d1 <= drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1_CDC;
DRR_OVERRUN_S2AX_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => drr_Overrun_int_cdc_from_spi_int_2,--drr_Overrun_int_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => drr_Overrun_int_cdc_from_spi_d2
);
DRR_OVERRUN_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
drr_Overrun_int_cdc_from_spi_d3 <= drr_Overrun_int_cdc_from_spi_d2;
end if;
end process DRR_OVERRUN_STRETCH_1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2;
-------------------------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC;
-------------------------------------------------
RX_FIFO_RST_AX2S_1: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => 1 --AXI to SPI as already 2 stages included
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_RX_FIFO_Rst_en_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_RX_FIFO_Rst_en_d2
);
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC_1: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d2,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RX_FIFO_Rst_pulse <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
----------------------------------------------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i) ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
SPISR_0_CMD_Error_cdc_from_spi_d2 <= '0';
spisel_d1_reg_cdc_from_spi_d2 <= '0';
Mst_N_Slv_mode_cdc_from_spi_d2 <= '0';
slave_MODF_strobe_cdc_from_spi_d1 <= '0';
modf_strobe_cdc_from_spi_d1 <= '0';
end generate LOGIC_GENERATION_CDC ;
end architecture imp;
---------------------
| mit | 3c5f44f2761af27f13451d2d0c49a4b9 | 0.418796 | 3.798661 | false | false | false | false |
gregani/la16fw | test_main.vhd | 1 | 5,779 | --
-- This file is part of the lafw16 project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_main is
end test_main;
architecture behavior of test_main is
-- Component Declaration for the Unit Under Test (UUT)
component mainmodule
-- generic(
-- tick_1M_div : integer
-- );
port(
clk_in : in std_logic;
spi_ss_n : in std_logic;
spi_sclk : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic;
led : out std_logic;
fifo_clk : in std_logic;
fifo_empty : out std_logic;
fifo_read_n : in std_logic;
fifo_data : out std_logic_vector(15 downto 0);
logic_data : in std_logic_vector(15 downto 0)
--logic_data : in std_logic_vector(15 downto 2);
--debug, debug2 : out std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal spi_ss_n : std_logic := '1';
signal spi_sclk : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal fifo_read_n : std_logic := '1';
signal logic_data : std_logic_vector(15 downto 0) := (others=>'0');
--Outputs
signal spi_miso : std_logic;
signal led : std_logic;
signal fifo_empty : std_logic;
signal fifo_data : std_logic_vector(15 downto 0);
-- internal signals
-- Clock period definitions
constant clk_period : time := 20.83 ns;
constant sclk_period : time := 100 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: mainmodule
-- generic map(
-- tick_1M_div => 48
-- )
port map(
clk_in => clk,
spi_ss_n => spi_ss_n,
spi_sclk => spi_sclk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
led => led,
fifo_clk => clk,
fifo_empty => fifo_empty,
fifo_read_n => fifo_read_n,
fifo_data => fifo_data,
logic_data => logic_data(15 downto 0)
);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- send spi data
procedure spi_start is
begin
wait for 2*sclk_period;
spi_ss_n <= '0';
wait for 2*sclk_period;
end spi_start;
procedure spi_stop is
begin
wait for 2*sclk_period;
spi_ss_n <= '1';
wait for 2*sclk_period;
end spi_stop;
procedure spi_send(data: in unsigned(7 downto 0)) is
begin
for i in 0 to 7 loop
spi_mosi <= data(7-i);
wait for sclk_period/2;
spi_sclk <= '1';
wait for sclk_period/2;
spi_sclk <= '0';
end loop;
end spi_send;
procedure read_fifo is
begin
wait until falling_edge(clk);
wait until rising_edge(clk);
wait for clk_period/10;
while (fifo_empty = '0') loop
fifo_read_n <= '0';
wait for clk_period;
fifo_read_n <= '1';
wait for clk_period;
end loop;
fifo_read_n <= '0';
wait for clk_period;
fifo_read_n <= '1';
wait for clk_period;
end read_fifo;
begin
-- wait for internal reset
wait for clk_period*50;
-- insert stimulus here
-- read adress 0x00 (fpga bitstream version)
spi_start;
spi_send('1' & to_unsigned(0, 7));
spi_send(to_unsigned(0, 8));
spi_stop;
-- write adress 0x05, data 0x80 (set led pwm to 50%)
spi_start;
spi_send('0' & to_unsigned(5, 7));
spi_send(to_unsigned(128, 8));
spi_stop;
-- select channels
spi_start;
spi_send('0' & to_unsigned(2, 7));
spi_send(to_unsigned(255, 8));
spi_stop;
spi_start;
spi_send('0' & to_unsigned(3, 7));
spi_send(to_unsigned(255, 8));
spi_stop;
-- set base clock to 100MHz
spi_start;
spi_send('0' & to_unsigned(10, 7));
spi_send(to_unsigned(0, 8));
spi_stop;
-- set sample rate to 5Mhz => n = 20-1
spi_start;
spi_send('0' & to_unsigned(4, 7));
spi_send(to_unsigned(20 - 1, 8));
spi_stop;
logic_data <= (0=>'1',others=>'0');
-- start sampling
spi_start;
spi_send('0' & to_unsigned(1, 7));
spi_send(to_unsigned(1, 8));
spi_stop;
-- read some values from fifo
for i in 1 to 10 loop
wait until fifo_empty = '0';
read_fifo;
end loop;
wait;
end process;
end;
| gpl-2.0 | 1a891a2b06dbdb095604ced55c7b3e85 | 0.524485 | 3.772193 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/divEven.vhd | 1 | 1,050 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: xx
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity divEven is --
generic(N: integer:=20; half: integer:=10; size: integer:=4);
port(clk: in std_logic;
div: out std_logic);
end divEven;
architecture behav of divEven is
signal result: std_logic:='0';
signal cnt: std_logic_vector(size downto 0):=(others=>'0');
begin
process(clk)
begin
if (clk'event and clk='1') then
if (cnt<half-1) then
cnt<=cnt+1;
else
cnt<=(others=>'0');
result<=not(result);
end if;
end if;
div<=result;
end process;
end behav;
| mit | ac9b00d8fa9ce19ac91967e8c55bdfe4 | 0.551429 | 3.409091 | false | false | false | false |
zzhou007/161lab | lab02/bin_bcd.vhd | 1 | 4,494 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity bin_bcd is
generic(NUMBITS : natural := 32);
Port ( I : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
opcode : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR(NUMBITS + 3 downto 0));
end bin_bcd;
architecture Behavioral of bin_bcd is
signal test : std_logic_vector(67 downto 0);
begin
process(I, test)
variable bcd : std_logic_vector(67 downto 0);
begin
if (opcode = "1100" or opcode = "1101") then
if (I(NUMBITS - 1) /= '0') then
bcd := "111111111111111111111111111111111111"&std_logic_vector(I);
bcd := (not bcd) + 1;
else
bcd := "000000000000000000000000000000000000"&std_logic_vector(I);
end if;
end if;
--if unsigned
if (opcode = "1000" or opcode = "1001") then
bcd := "000000000000000000000000000000000000"&std_logic_vector(I);
for i1 in 0 to 31 loop -- repeating 32 times.
bcd(67 downto 1) := bcd(66 downto 0); --shifting the bits.
if(i1 < 31 and bcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(35 downto 32) := bcd(35 downto 32) + "0011";
end if;
if(i1 < 31 and bcd(39 downto 36) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(39 downto 36) := bcd(39 downto 36) + "0011";
end if;
if(i1 < 31 and bcd(43 downto 40) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(43 downto 40) := bcd(43 downto 40) + "0011";
end if;
if(i1 < 31 and bcd(47 downto 44) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(47 downto 44) := bcd(47 downto 44) + "0011";
end if;
if(i1 < 31 and bcd(51 downto 48) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(51 downto 48) := bcd(51 downto 48) + "0011";
end if;
if(i1 < 31 and bcd(55 downto 52) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(55 downto 52) := bcd(55 downto 52) + "0011";
end if;
if(i1 < 31 and bcd(59 downto 56) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(59 downto 56) := bcd(59 downto 56) + "0011";
end if;
if(i1 < 31 and bcd(63 downto 60) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(63 downto 60) := bcd(63 downto 60) + "0011";
end if;
if(i1 < 31 and bcd(67 downto 64) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(67 downto 64) := bcd(67 downto 64) + "0011";
end if;
end loop;
O <= bcd(67 downto 32);
--if signed
else
for i1 in 0 to 31 loop -- repeating 32 times.
bcd(67 downto 1) := bcd(66 downto 0); --shifting the bits.
if(i1 < 31 and bcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(35 downto 32) := bcd(35 downto 32) + "0011";
end if;
if(i1 < 31 and bcd(39 downto 36) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(39 downto 36) := bcd(39 downto 36) + "0011";
end if;
if(i1 < 31 and bcd(43 downto 40) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(43 downto 40) := bcd(43 downto 40) + "0011";
end if;
if(i1 < 31 and bcd(47 downto 44) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(47 downto 44) := bcd(47 downto 44) + "0011";
end if;
if(i1 < 31 and bcd(51 downto 48) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(51 downto 48) := bcd(51 downto 48) + "0011";
end if;
if(i1 < 31 and bcd(55 downto 52) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(55 downto 52) := bcd(55 downto 52) + "0011";
end if;
if(i1 < 31 and bcd(59 downto 56) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(59 downto 56) := bcd(59 downto 56) + "0011";
end if;
if(i1 < 31 and bcd(63 downto 60) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(63 downto 60) := bcd(63 downto 60) + "0011";
end if;
if(i1 < 31 and bcd(67 downto 64) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(67 downto 64) := bcd(67 downto 64) + "0011";
end if;
end loop;
if (I(NUMBITS - 1) /= '0') then
if bcd(63 downto 32) = 0 then
o <= "0000"&bcd(63 downto 32);
else
O <= "0001"&bcd(63 downto 32);
end if;
else
o <= "0000"&bcd(63 downto 32);
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | ba75d300af96c1c5e8d93a3840fd4958 | 0.582109 | 3.010047 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/sha256/tb/sha256_tb.vhd | 4 | 3,681 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_tb is
end entity sha256_tb;
architecture sha256_tb_behav of sha256_tb is
alias slv is std_logic_vector;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_125 : time := 8 ns;
signal clk : std_logic := '0';
signal reset : std_logic;
signal msg_in : slv(511 downto 0) := (others => '0');
signal digest : slv(255 downto 0);
begin
reset <= '1','0' after 12.5 * tclk_125;
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => msg_in,
digest => digest
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => msg_in,
digest => digest
);
end generate sha256_qp_gen;
msg_gen: process is
begin
wait until reset = '0';
-- input message 'abc' after padding
msg_in <= X"00000018" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"61626380";
wait for tclk_125;
-- input message 'hello' after padding
msg_in <= X"00000028" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"6F800000" & X"68656C6C";
wait for tclk_125;
-- input message 'bitcoin' after padding
msg_in <= X"00000038" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"6F696E80" & X"62697463";
end process msg_gen;
clk_gen: process is
begin
clk <= not clk;
wait for tclk_125/2;
end process clk_gen;
end architecture sha256_tb_behav;
| gpl-3.0 | 7956b76c63adf0a717f983baed215e52 | 0.480848 | 3.806618 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/lite_ecc_reg.vhd | 7 | 68,156 | -------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: lite_ecc_reg.vhd
--
-- Description: This module contains the register components for the
-- ECC status & control data when enabled.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/17/2011 v1.03a
-- ~~~~~~
-- Add ECC support for 128-bit BRAM data width.
-- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and
-- modify BRAM address registers.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite_if;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity lite_ecc_reg is
generic (
C_S_AXI_PROTOCOL : string := "AXI4";
-- Used in this module to differentiate timing for error capture
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : INTEGER := 1;
-- Enable single port usage of BRAM
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Clock and Reset
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI-Lite ECC Register Interface Signals ***
-- All synchronized to S_AXI_CTRL_AClk
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** Memory Controller Interface Signals ***
-- All synchronized to S_AXI_AClk
Enable_ECC : out std_logic;
-- Indicates if and when ECC is enabled
FaultInjectClr : in std_logic;
-- Clear for Fault Inject Registers
CE_Failing_We : in std_logic;
-- WE for CE Failing Registers
-- UE_Failing_We : in std_logic;
-- WE for CE Failing Registers
CE_CounterReg_Inc : in std_logic;
-- Increment CE Counter Register
Sl_CE : in std_logic;
-- Correctable Error Flag
Sl_UE : in std_logic;
-- Uncorrectable Error Flag
BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_En : in std_logic;
Active_Wr : in std_logic;
-- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- Outputs
FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1)
);
end entity lite_ecc_reg;
-------------------------------------------------------------------------------
architecture implementation of lite_ecc_reg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Start LMB BRAM v3.00a HDL
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirrorring of registers in address space of module
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11
constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00
constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01
constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10
constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00
constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00
constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01
constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00
constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01
constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10
constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00
constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00
constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00
constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00
constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01
constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10
constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
constant C_ECC_ON_OFF_WIDTH : natural := 1;
-- End LMB BRAM v3.00a HDL
constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0');
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal S_AXI_AReset : std_logic;
-- Start LMB BRAM v3.00a HDL
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegWr : std_logic;
signal RegWr_i : std_logic;
--signal RegWr_d1 : std_logic;
--signal RegWr_d2 : std_logic;
-- Fault Inject Register
signal FaultInjectData_WE_0 : std_logic := '0';
signal FaultInjectData_WE_1 : std_logic := '0';
signal FaultInjectData_WE_2 : std_logic := '0';
signal FaultInjectData_WE_3 : std_logic := '0';
signal FaultInjectECC_WE : std_logic := '0';
--signal FaultInjectClr : std_logic := '0';
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0');
signal CE_Failing_We_i : std_logic := '0';
-- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
-- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0');
-- signal UE_Failing_We_i : std_logic := '0';
-- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0');
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg_WE : std_logic := '0';
-- ECC On/Off Control register
signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0');
signal ECC_OnOffReg_WE : std_logic := '0';
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0');
signal CE_CounterReg_WE : std_logic := '0';
signal CE_CounterReg_Inc_i : std_logic := '0';
-- End LMB BRAM v3.00a HDL
signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0');
signal Enable_ECC_i : std_logic := '0';
signal ECC_UE_i : std_logic := '0';
signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
FaultInjectData <= FaultInjectData_i;
FaultInjectECC <= FaultInjectECC_i;
-- Reserve for future support.
-- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn);
S_AXI_AReset <= not (S_AXI_AResetn);
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
--
-- Description:
-- This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
--
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
--
-- Synchronized to AXI-Lite clock and reset.
-- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to
-- the AXI clock.
--
---------------------------------------------------------------------------
I_AXI_LITE_IF : entity work.axi_lite_if
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH
)
port map (
-- Reserve for future support.
-- LMB_Clk => S_AXI_CTRL_AClk,
-- LMB_Rst => S_AXI_CTRL_AReset,
LMB_Clk => S_AXI_AClk,
LMB_Rst => S_AXI_AReset,
S_AXI_AWADDR => AXI_CTRL_AWADDR,
S_AXI_AWVALID => AXI_CTRL_AWVALID,
S_AXI_AWREADY => AXI_CTRL_AWREADY,
S_AXI_WDATA => AXI_CTRL_WDATA,
S_AXI_WSTRB => axi_lite_wstrb_int,
S_AXI_WVALID => AXI_CTRL_WVALID,
S_AXI_WREADY => AXI_CTRL_WREADY,
S_AXI_BRESP => AXI_CTRL_BRESP,
S_AXI_BVALID => AXI_CTRL_BVALID,
S_AXI_BREADY => AXI_CTRL_BREADY,
S_AXI_ARADDR => AXI_CTRL_ARADDR,
S_AXI_ARVALID => AXI_CTRL_ARVALID,
S_AXI_ARREADY => AXI_CTRL_ARREADY,
S_AXI_RDATA => AXI_CTRL_RDATA,
S_AXI_RRESP => AXI_CTRL_RRESP,
S_AXI_RVALID => AXI_CTRL_RVALID,
S_AXI_RREADY => AXI_CTRL_RREADY,
RegWr => RegWr_i,
RegWrData => RegWrData_i,
RegAddr => RegAddr_i,
RegRdData => RegRdData_i
);
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
--
-- Save HDL
-- If it is decided to go back and use seperate clock inputs
-- One for AXI4 and one for AXI4-Lite on this core.
-- For now, temporarily comment out and replace the *_i signal
-- assignments.
RegWr <= RegWr_i;
RegWrData <= RegWrData_i;
RegAddr <= RegAddr_i;
RegRdData_i <= RegRdData;
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- --
-- -- All registers must be synchronized to the correct clock.
-- -- RegWr must be synchronized to the S_AXI_Clk
-- -- RegWrData must be synchronized to the S_AXI_Clk
-- -- RegAddr must be synchronized to the S_AXI_Clk
-- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk
-- --
-- ---------------------------------------------------------------------------
--
-- SYNC_AXI_CLK: process (S_AXI_AClk)
-- begin
-- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- RegWr_d1 <= RegWr_i;
-- RegWr_d2 <= RegWr_d1;
-- RegWrData_d1 <= RegWrData_i;
-- RegWrData_d2 <= RegWrData_d1;
-- RegAddr_d1 <= RegAddr_i;
-- RegAddr_d2 <= RegAddr_d1;
-- end if;
-- end process SYNC_AXI_CLK;
--
-- RegWr <= RegWr_d2;
-- RegWrData <= RegWrData_d2;
-- RegAddr <= RegAddr_d2;
--
--
-- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk)
-- begin
-- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then
-- RegRdData_d1 <= RegRdData;
-- RegRdData_d2 <= RegRdData_d1;
-- end if;
-- end process SYNC_AXI_LITE_CLK;
--
-- RegRdData_i <= RegRdData_d2;
--
---------------------------------------------------------------------------
axi_lite_wstrb_int <= (others => '1');
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_SNG
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If single port, only register Port A address.
--
-- With CE flag being registered, must account for one more
-- pipeline stage in stored BRAM addresss that correlates to
-- failing ECC.
---------------------------------------------------------------------------
GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
-- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY
signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d2;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time.
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline).
-- During read operaitons, use 3-deep address pipeline to store address values.
FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_DUAL
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If dual port BRAM, register Port A & Port B address.
--
-- Account for CE flag register delay, add 3rd BRAM address
-- pipeline stage.
--
---------------------------------------------------------------------------
GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
-- Port B pipeline stages only used in a dual port mode configuration.
signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_B_d1 <= BRAM_Addr_B;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_B_d1 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d2;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
-- Only one active operation at a time.
-- Use one deep address pipeline. Determine if Port A or B based on active read or write.
FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A).
-- During read operations, use 3-deep address pipeline to store address values (and from Port B).
FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_DUAL;
---------------------------------------------------------------------------
-- Generate: FAULT_INJECT
-- Purpose: Implement fault injection registers
-- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB)
---------------------------------------------------------------------------
FAULT_INJECT : if C_HAS_FAULT_INJECT generate
begin
-- FaultInjectClr added to top level port list.
-- Original LMB BRAM HDL
-- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0';
---------------------------------------------------------------------------
-- Generate: GEN_32_FAULT
-- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 32-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (25:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_32_FAULT;
---------------------------------------------------------------------------
-- Generate: GEN_64_FAULT
-- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 64-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (24:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_64_FAULT;
-- v1.03a
---------------------------------------------------------------------------
-- Generate: GEN_128_FAULT
-- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0';
FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 128-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (96 to 127) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (64 to 95) <= RegWrData;
elsif FaultInjectData_WE_2 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_3 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_128_FAULT;
end generate FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: NO_FAULT_INJECT
-- Purpose: Set default outputs when no fault inject capabilities.
-- Remove check from C_WRITE_ACCESS (from LMB)
---------------------------------------------------------------------------
NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate
begin
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end generate NO_FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: CE_FAILING_REGISTERS
-- Purpose: Implement Correctable Error First Failing Register
---------------------------------------------------------------------------
CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate
begin
-- TBD (could come from axi_lite)
-- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
-- else '0';
CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
else '0';
CE_FailingReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
CE_FailingAddress <= (others => '0');
-- Reserve for future support.
-- CE_FailingData <= (others => '0');
elsif CE_Failing_We_i = '1' then
--As the AXI Addr Width can now be lesser than 32, the address is getting shifted
--Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000
CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0);
--CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ;
-- Reserve for future support.
-- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1);
end if;
end if;
end process CE_FailingReg;
-- Note: Remove storage of CE_FFE & CE_FFD registers.
-- Here for future support.
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_64;
end generate CE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_CE_FAILING_REGISTERS
-- Purpose: No Correctable Error Failing registers.
---------------------------------------------------------------------------
NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
-- CE_FailingData <= (others => '0');
-- CE_FailingECC <= (others => '0');
end generate NO_CE_FAILING_REGISTERS;
-- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0
-- This generate clause will never be evaluated.
-- Here for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: UE_FAILING_REGISTERS
-- -- Purpose: Implement Unorrectable Error First Failing Register
-- ---------------------------------------------------------------------------
--
-- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate
-- begin
--
-- -- TBD (could come from axi_lite)
-- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- -- else '0';
--
-- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- else '0';
--
--
-- UE_FailingReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingAddress <= FailingAddr_Ld;
-- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingReg;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_64;
--
-- end generate UE_FAILING_REGISTERS;
--
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_UE_FAILING_REGISTERS
-- -- Purpose: No Uncorrectable Error Failing registers.
-- ---------------------------------------------------------------------------
--
-- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate
-- begin
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- UE_FailingECC <= (others => '0');
-- end generate NO_UE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: ECC_STATUS_REGISTERS
-- Purpose: Enable ECC status and interrupt enable registers.
---------------------------------------------------------------------------
ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE;
ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE;
StatusReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_EnableIRQReg <= (others => '0');
elsif ECC_EnableIRQReg_WE = '1' then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
---------------------------------------------------------------------------
-- Generate output flag for UE sticky bit
-- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted.
REG_UE : process (S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE or
(Enable_ECC_i = '0') then
ECC_UE_i <= '0';
elsif Sl_UE = '1' then
ECC_UE_i <= '1';
elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then
ECC_UE_i <= '0';
else
ECC_UE_i <= ECC_UE_i;
end if;
end if;
end process REG_UE;
ECC_UE <= ECC_UE_i;
---------------------------------------------------------------------------
end generate ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_ECC_STATUS_REGISTERS
-- Purpose: No ECC status or interrupt registers enabled.
---------------------------------------------------------------------------
NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
ECC_UE <= '0';
end generate NO_ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: GEN_ECC_ONOFF
-- Purpose: Implement ECC on/off control register.
---------------------------------------------------------------------------
GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate
begin
ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
if (C_ECC_ONOFF_RESET_VALUE = 0) then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
else
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1';
end if;
-- ECC on by default at reset (but can be disabled)
elsif ECC_OnOffReg_WE = '1' then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH);
end if;
end if;
end process EnableIRQReg;
Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH);
Enable_ECC <= Enable_ECC_i;
end generate GEN_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC_ONOFF
-- Purpose: No ECC on/off control register.
---------------------------------------------------------------------------
GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate
begin
Enable_ECC <= '0';
-- ECC ON/OFF register is only enabled when C_ECC = 1.
-- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then
-- ECC should be disabled.
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
end generate GEN_NO_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: CE_COUNTER
-- Purpose: Enable Correctable Error Counter
-- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits.
-- Parameterized here for future enhancements.
---------------------------------------------------------------------------
CE_COUNTER : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0';
-- TBD (could come from axi_lite)
-- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and
-- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
-- else '0';
CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
else '0';
CountReg : process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
CE_CounterReg <= (others => '0');
elsif CE_CounterReg_WE = '1' then
-- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1);
CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31);
elsif CE_CounterReg_Inc_i = '1' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_COUNTER;
-- Note: Hit this generate when C_ECC = 0.
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_CE_COUNTER
-- -- Purpose: Default for no CE counter register.
-- ---------------------------------------------------------------------------
--
-- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate
-- begin
-- CE_CounterReg <= (others => '0');
-- end generate NO_CE_COUNTER;
---------------------------------------------------------------------------
-- Generate: GEN_REG_32_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 32-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_32_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_64_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 64-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_64_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_128_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 128-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95);
when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_128_DATA;
---------------------------------------------------------------------------
end architecture implementation;
| mit | 70f696464f2f8739ed622b25fa1190a7 | 0.468528 | 4.231978 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_cntrl_reg.vhd | 1 | 21,279 | -------------------------------------------------------------------------------
-- $Id: qspi_cntrl_reg.vhd
-------------------------------------------------------------------------------
-- qspi_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
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-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi. This module decides the
-- behavior of the core in master/slave, CPOL/CPHA etc modes.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_quad_spi.
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_SPICR_data -- Data written from the PLB bus
-- Bus2IP_SPICR_WrCE -- Write CE for control register
-- Bus2IP_SPICR_RdCE -- Read CE for control register
-- IP2Bus_SPICR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register, 10 for control reg - to match old version
C_SPI_NUM_BITS_REG : integer;
----------------------------
C_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPICR_WrCE : in std_logic;
Bus2IP_SPICR_RdCE : in std_logic;
Bus2IP_SPICR_data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- SPI module ports
SPICR_0_LOOP : out std_logic;
SPICR_1_SPE : out std_logic;
SPICR_2_MASTER_N_SLV : out std_logic;
SPICR_3_CPOL : out std_logic;
SPICR_4_CPHA : out std_logic;
SPICR_5_TXFIFO_RST : out std_logic;
SPICR_6_RXFIFO_RST : out std_logic;
SPICR_7_SS : out std_logic;
SPICR_8_TR_INHIBIT : out std_logic;
SPICR_9_LSB : out std_logic;
--------------------------
-- to Status Register
SPISR_1_LOOP_Back_Error : out std_logic;
SPISR_2_MSB_Error : out std_logic;
SPISR_3_Slave_Mode_Error : out std_logic;
-- SPISR_4_XIP_Mode_On : out std_logic;
SPISR_4_CPOL_CPHA_Error : out std_logic;
IP2Bus_SPICR_Data : out std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
Control_bit_7_8 : out std_logic_vector(0 to 1) --(7 to 8)
);
end qspi_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of qspi_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPICR_data_int : std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal SPICR_3_4_Reset : std_logic;
signal Control_bit_7_8_int : std_logic_vector(7 to 8);
signal temp_wr_ce : std_logic;
-----
begin
-----
----------------------------
-- Combinatorial operations
----------------------------
-- Control_Register_Data <= SPICR_data_int;
-------------------------------------------------------
SPICR_0_LOOP <= SPICR_data_int(C_SPICR_REG_WIDTH-1); -- as per the SPICR Fig 3 in DS this bit is @ 0th position
SPICR_1_SPE <= SPICR_data_int(C_SPICR_REG_WIDTH-2); -- as per the SPICR Fig 3 in DS this bit is @ 1st position
SPICR_2_MASTER_N_SLV <= SPICR_data_int(C_SPICR_REG_WIDTH-3); -- as per the SPICR Fig 3 in DS this bit is @ 2nd position
SPICR_3_CPOL <= SPICR_data_int(C_SPICR_REG_WIDTH-4); -- as per the SPICR Fig 3 in DS this bit is @ 3rd position
SPICR_4_CPHA <= SPICR_data_int(C_SPICR_REG_WIDTH-5); -- as per the SPICR Fig 3 in DS this bit is @ 4th position
SPICR_5_TXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-6); -- as per the SPICR Fig 3 in DS this bit is @ 5th position
SPICR_6_RXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-7); -- as per the SPICR Fig 3 in DS this bit is @ 6th position
SPICR_7_SS <= SPICR_data_int(C_SPICR_REG_WIDTH-8); -- as per the SPICR Fig 3 in DS this bit is @ 7th position
SPICR_8_TR_INHIBIT <= SPICR_data_int(C_SPICR_REG_WIDTH-9); -- as per the SPICR Fig 3 in DS this bit is @ 8th position
SPICR_9_LSB <= SPICR_data_int(C_SPICR_REG_WIDTH-10);-- as per the SPICR Fig 3 in DS this bit is @ 9th position
-------------------------------------------------------
SPISR_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
----------------------------
--signal ored_SPICR_7_12 : std_logic;
begin
-----
--ored_SPICR_7_12 <= or_reduce(SPICR_data_int(7 to 12));
-- C_SPICR_REG_WIDTH is of 10 bit wide
SPISR_1_LOOP_Back_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-1);-- 9th bit in present SPICR
SPISR_2_MSB_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-C_SPICR_REG_WIDTH); -- 0th LSB bit in present SPICR
SPISR_3_Slave_Mode_Error <= not SPICR_data_int(C_SPICR_REG_WIDTH-3); -- Mst_n_Slv 7th bit in control register - default is slave mode of operation
SPISR_4_CPOL_CPHA_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-5) xor -- bit 5-CPHA and 6-CPOL in present SPICR
SPICR_data_int(C_SPICR_REG_WIDTH-4);-- CPOL-CPHA = 01 or 10 in control register
end generate SPISR_DUAL_MODE_STATUS_GEN;
----------------------------------------
SPISR_NO_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 0 generate
-------------------------------
begin
-----
SPISR_1_LOOP_Back_Error <= '0';
SPISR_2_MSB_Error <= '0';
SPISR_3_Slave_Mode_Error <= '0';
SPISR_4_CPOL_CPHA_Error <= '0';
end generate SPISR_NO_DUAL_MODE_STATUS_GEN;
-------------------------------------------
SPICR_REG_RD_GENERATE: for i in 0 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPICR_Data(i) <= SPICR_data_int(i) and Bus2IP_SPICR_RdCE;
end generate SPICR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------
-- Bus2IP Data bit mapping - 0 to 21 - NA
-- 22 23 24 25 26 27 28 29 30 31
--
-- Control Register - 0 to 22 bit mapping
-- 0 1 2 3 4 5 6 7 8 9
-- LSB TRAN MANUAL RX FIFO TX FIFO CPHA CPOL MASTER SPE LOOP
-- INHI SLAVE RST RST
-- '0' '1' '1' '0' '0' '0' '0' '0' '0' '0'
-----------------------------------------------------
-- AXI Data 31 downto 0 |
-- valid bits in AXI start from LSB i.e. 0 |
-- Bus2IP_Data 0 to 31 |
-- **** IMP Starts **** |
-- This is 1 is to 1 mapping with reverse bit order.|
-- **** IMP Ends **** |
-- Bus2IP_Data 0 1 2 3 4 5 6 7 21 22--->31 |
-- Control Bits<-------NA--------> 0---->9 |
-----------------------------------------------------
--SPICR_NO_DUAL_MODE_WR_GEN: if C_SPI_MODE = 0 generate
---------------------------------
--begin
-----
-- SPICR_data_int(0 to 12) <= (others => '0');
--end generate SPICR_NO_DUAL_MODE_WR_GEN;
----------------------------------------------
temp_wr_ce <= wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE;
-- -- SPICR_REG_0_PROCESS : Control Register Write Operation for bit 0 - LSB
-- -----------------------------
-- Behavioral Code **
SPICR_REG_0_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(0) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(0) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH);-- after 100 ps;
end if;
end if;
end process SPICR_REG_0_PROCESS;
--------------------------------
CONTROL_REG_1_2_GENERATE: for i in 1 to 2 generate
------------------------
begin
-----
-- SPICR_REG_1_2_PROCESS : Control Register Write Operation for bit 1_2 - TRAN_INHI and MANUAL_SLAVE
-----------------------------
SPICR_REG_1_2_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '1';
elsif((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_1_2_PROCESS;
----------------------------------
end generate CONTROL_REG_1_2_GENERATE;
--------------------------------------
-- the below reset signal is needed to de-assert the Tx/Rx FIFO reset signals.
SPICR_3_4_Reset <= (not Bus2IP_SPICR_WrCE) or Soft_Reset_op;
-- CONTROL_REG_3_4_GENERATE : Control Register Write Operation for bit 3_4 - Receive FIFO Reset and Transmit FIFO Reset
-----------------------------
CONTROL_REG_3_4_GENERATE: for i in 3 to 4 generate
-----
begin
-----
SPICR_REG_3_4_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (SPICR_3_4_Reset = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_3_4_PROCESS;
----------------------------------
end generate CONTROL_REG_3_4_GENERATE;
--------------------------------------
-- CONTROL_REG_5_9_GENERATE : Control Register Write Operation for bit 5:9 - CPHA, CPOL, MASTER, SPE, LOOP
-----------------------------
CONTROL_REG_5_9_GENERATE: for i in 5 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
SPICR_REG_5_9_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_5_9_PROCESS;
----------------------------------
end generate CONTROL_REG_5_9_GENERATE;
--------------------------------------
--
-- SPICR_REG_78_GENERATE: This logic is newly added to register _T signals
-- ------------------------ in IOB. This logic simplifies the register method
-- for _T in IOB, without affecting functionality.
SPICR_REG_78_GENERATE: for i in 7 to 8 generate
-----
begin
-----
SPI_TRISTATE_CONTROL_I: component FDRE
port map
(
Q => Control_bit_7_8_int(i) ,-- out:
C => Bus2IP_Clk ,--: in
CE => Bus2IP_SPICR_WrCE ,--: in
R => Soft_Reset_op ,-- : in
D => Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i) --: in
);
end generate SPICR_REG_78_GENERATE;
-----------------------------------
Control_bit_7_8 <= Control_bit_7_8_int;
---------------------------------------
end imp;
-------------------------------------------------------------------------------- | mit | 32b44ae13e407253298d8c84d745dbc5 | 0.441374 | 4.297052 | false | false | false | false |
meaepeppe/FIR_ISA | VHDL/tb_FIR_filter_direct.vhd | 1 | 4,772 | LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.math_real.all;
USE work.FIR_constants.all;
USE STD.textio.all;
ENTITY tb_FIR_filter_direct IS
GENERIC(
N_sample: integer := 202
);
END ENTITY;
ARCHITECTURE test OF tb_FIR_filter_direct IS
TYPE vector_test IS ARRAY (N_sample-1 DOWNTO 0) OF INTEGER;
TYPE coeffs_array IS ARRAY (Ord DOWNTO 0) OF INTEGER;
TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF SIGNED(Nb-1 DOWNTO 0);
FILE inputs: text;
FILE coeff_file: text;
FILE c_outs_file: text;
SHARED VARIABLE input_samples, c_outputs: vector_test;
SIGNAL tot_pipe_stages: INTEGER;
SIGNAL CLK, RST_n: STD_LOGIC;
SIGNAL VIN, VOUT: STD_LOGIC;
SIGNAL VIN_array: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL sample: SIGNED(Nb-1 DOWNTO 0);
SIGNAL DINconverted: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL filter_out: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL coeffs_std: std_logic_vector ((Ord+1)*Nb - 1 DOWNTO 0);
SIGNAL visual_coeffs_integer: coeffs_array;
SIGNAL regToDIN: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL DOUTtoReg: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
COMPONENT FIR_filter IS
PORT(
CLK, RST_n: IN STD_LOGIC;
VIN: IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1
VOUT: OUT STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
Tot_latency: PROCESS
BEGIN
IF IO_buffers = TRUE THEN
tot_pipe_stages <= 2;
ELSE
tot_pipe_stages <= 0;
END IF;
WAIT;
END PROCESS;
DINconverted <= std_logic_vector(sample);
DUT: FIR_filter
PORT MAP (CLK => CLK, RST_n => RST_n, VIN => VIN_array(2), DIN => regToDIN,
Coeffs => coeffs_std, VOUT => VOUT, DOUT => DOUTtoReg);
VIN_array(0) <= VIN;
VIN_REGS: FOR i IN 0 TO 1 GENERATE
REGS_VIN: Reg_n
GENERIC MAP (Nb => 1)
PORT MAP(CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_array(i DOWNTO i), DOUT => VIN_array(i+1 DOWNTO i+1));
END GENERATE;
REG_IN: Reg_n
GENERIC MAP (Nb => Nb)
PORT MAP (CLK => CLK, RST_n => RST_n, EN => VIN_array(1), DIN => DINconverted, DOUT => regToDIN );
REG_OUT: Reg_n
GENERIC MAP (Nb => Nb)
PORT MAP (CLK => CLK, RST_n => RST_n, EN => VOUT, DIN => DOUTtoReg, DOUT => filter_out );
CLK_gen: PROCESS
BEGIN
CLK <= '0';
WAIT FOR 10 ns;
CLK <= '1';
WAIT FOR 10 ns;
END PROCESS;
VIN_RST_gen: PROCESS
BEGIN
VIN <= '0';
RST_n <= '0';
WAIT FOR 10 ns;
RST_n <= '1';
WAIT FOR 5 ns;
VIN <= '1';
WAIT FOR 745 ns;
VIN <= '0';
WAIT FOR 60 ns;
VIN <= '1';
WAIT FOR 3280 ns;
VIN <= '0';
WAIT;
END PROCESS;
test_input_read: PROCESS
VARIABLE iLine,cLine, coutLine: LINE;
VARIABLE i,j,k: INTEGER := 0;
VARIABLE coeffs_integer: coeffs_array;
BEGIN
file_open(inputs, "samples.txt", READ_MODE);
WHILE (NOT ENDFILE(inputs)) LOOP
READLINE(inputs, iLine);
READ(iLine, input_samples(i));
i := i+1;
END LOOP;
file_close(inputs);
file_open(coeff_file, "coeffs.txt", READ_MODE);
WHILE (NOT ENDFILE(coeff_file)) LOOP
READLINE(coeff_file, cLine);
READ(cLine, coeffs_integer(j));
j := j+1;
END LOOP;
file_close(coeff_file);
visual_coeffs_integer <= coeffs_integer;
file_open(c_outs_file, "c_outputvectors.txt", READ_MODE);
WHILE (NOT ENDFILE(c_outs_file)) LOOP
READLINE(c_outs_file, coutLine);
READ(coutLine, c_outputs(k));
k := k+1;
END LOOP;
file_close(c_outs_file);
FOR i IN 0 TO Ord LOOP
coeffs_std((i+1)*Nb-1 DOWNTO i*Nb)<= std_logic_vector(to_signed(coeffs_integer(i),Nb));
END LOOP;
WAIT;
END PROCESS;
test_results_write: PROCESS(CLK)
VARIABLE oLine: LINE;
VARIABLE i, j: INTEGER := 0;
VARIABLE diff: INTEGER := 0;
FILE results: text is out "output_vectors_direct.txt";
FILE output_diffs: text is out "output_diffs.txt";
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF VIN = '1' THEN
sample <= to_signed(input_samples(i),sample'LENGTH);
i:= i+1;
END IF;
END IF;
IF CLK'EVENT AND CLK = '1' THEN
IF VOUT = '1' THEN
WRITE(oLine, to_integer(signed(DOUTtoReg)));
WRITELINE(results, oLine);
diff := (to_integer(signed(DOUTtoReg)) - c_outputs(j));
IF(diff /= 0) THEN
WRITE(oLine, diff);
WRITE(oLine, string'(" Sample: "));
WRITE(oLine, (j+1));
WRITELINE(output_diffs, oLine);
END IF;
j := j+1;
END IF;
END IF;
END PROCESS;
END test;
| gpl-3.0 | 8bc95bfee32b25681ad3b42a1461fff3 | 0.618609 | 2.787383 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/char_mem/simulation/bmg_stim_gen.vhd | 2 | 12,579 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (0 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0):= hex_to_std_logic_vector("0",1);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (24319 downto 0) of std_logic_vector(0 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(0 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"char_mem.mif",
DEFAULT_DATA,
1,
24320);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(14 DOWNTO 0) <= READ_ADDR(14 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 24320 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | e602ef1ce6d7a7b577900f4d6a0a6f55 | 0.547659 | 3.683455 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/IF_ID.vhd | 1 | 1,406 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:16:59 11/21/2013
-- Design Name:
-- Module Name: IF_ID - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IF_ID is
Port(
Instruction_in : in Int16;
Instruction_out : out Int16;
PC_in : in Int16;
PC_out : out Int16;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC
);
end IF_ID;
architecture Behavioral of IF_ID is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
Instruction_out <= Int16_Zero;
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
Instruction_out <= Instruction_in;
PC_out <= PC_in;
end if;
end if;
end process;
end Behavioral;
| mit | a4e4ce05c112adc6ff86a24ae4ee1fa8 | 0.559744 | 3.446078 | false | false | false | false |
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