repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
1995parham/FPGA-Homework | HW-2/src/p9/p9.vhd | 1 | 885 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 28-03-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (clk, reset : in std_logic;
count : out std_logic_vector (N - 1 downto 0));
end entity;
architecture behavioral of counter is
begin
process (clk, reset)
variable count_buff : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
if clk'event and clk = '1' then
count_buff := count_buff + '1';
count <= count_buff;
end if;
if reset = '1' then
count_buff := (others => '0');
count <= count_buff;
end if;
end process;
end architecture behavioral;
| gpl-3.0 | 4ee0a329e02d4180540380fb93ae727f | 0.529944 | 3.554217 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/async_fifo_fg.vhd | 12 | 121,997 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v11_0;
use fifo_generator_v11_0.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
--use proc_common_v4_0.coregen_comp_defs.all;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising wr clock edge to issue assertion
Wait until Wr_clk = '1';
wait until Wr_clk = '0';
Wait until Wr_clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Almost_full <= '0' ; -- : out std_logic;
Almost_empty <= '0' ; -- : out std_logic;
Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| mit | 696048951485d3ef4aa9d8922d203a62 | 0.399305 | 3.945824 | false | false | false | false |
gregani/la16fw | led.vhd | 1 | 2,251 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
----------------------------------------------------------------------------------
--
-- makes the led blink according to the led_brightness value
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led is
port(
clk : in std_logic; -- system clock (48MHz)
tick_1M : in std_logic; -- 1MHz tick
reset : in std_logic; -- reset (sync)
brightness : in std_logic_vector(7 downto 0); -- led pwm value
invert : in std_logic; -- invert output
led : out std_logic -- led output
);
end led;
architecture behavioral of led is
signal count : unsigned(7 downto 0); --pwm counter
signal led_int : std_logic;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
count <= (others=>'0'); --clear counter
led_int <= '0'; --turn off led
elsif (tick_1M = '1') then
--increment counter
count <= count + 1;
--update led
if (count = unsigned(brightness)) then
led_int <= '1';
elsif (count = 0) then
led_int <= '0';
end if;
end if;
end if;
end process;
led <= led_int xor invert;
end behavioral;
| gpl-2.0 | 4d8940d6aa79a16054cab3be2ddf1c60 | 0.550422 | 4.328846 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/Passer.vhd | 1 | 2,120 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:11 11/21/2013
-- Design Name:
-- Module Name: Passer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Passer is
Port(
IDEX_alusrc: in std_logic;
EXMEM_RegWrite : in STD_LOGIC;
MEMWB_RegWrite : in STD_LOGIC;
EXMEM_W : in STD_LOGIC_VECTOR (3 downto 0);
MEMWB_W : in STD_LOGIC_VECTOR (3 downto 0);
IDEX_R1 : in STD_LOGIC_VECTOR (3 downto 0);
IDEX_R2 : in STD_LOGIC_VECTOR (3 downto 0);
ForwardA : out STD_LOGIC_VECTOR (1 downto 0);
ForwardB : out STD_LOGIC_VECTOR (1 downto 0);
ForwardC : out STD_LOGIC_VECTOR (1 downto 0)
);
end Passer;
architecture Behavioral of Passer is
begin
process(EXMEM_RegWrite, MEMWB_RegWrite, EXMEM_W, MEMWB_W, IDEX_R1, IDEX_R2)
begin
ForwardB <= "00";
ForwardA <= "00";
ForwardC <= "00";
if (EXMEM_RegWrite = '1' and EXMEM_W /= Zero_Reg and EXMEM_W = IDEX_R1) then
ForwardA <= "10";
end if;
if (EXMEM_RegWrite = '1' and EXMEM_W /= Zero_Reg and EXMEM_W = IDEX_R2) then
if IDEX_alusrc = '0' then
ForwardB <= "10";
else
ForwardC <= "10";
end if;
end if;
if (MEMWB_RegWrite = '1' and MEMWB_W /= Zero_Reg and EXMEM_W /= IDEX_R1 and MEMWB_W = IDEX_R1) then
ForwardA <= "01";
end if;
if (MEMWB_RegWrite = '1' and MEMWB_W /= Zero_Reg and EXMEM_W /= IDEX_R2 and MEMWB_W = IDEX_R2) then
if IDEX_alusrc = '0' then
ForwardB <= "01";
else
ForwardC <= "01";
end if;
end if;
end process;
end Behavioral;
| mit | 01fe07bf9148afed3351dd8e5d1338c6 | 0.608962 | 3.076923 | false | false | false | false |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/new/pr_axis.vhd | 1 | 5,119 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pr_axis is
generic (
DATAWIDTH : integer := 64
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end pr_axis;
architecture rtl of pr_axis is
component axis_lut_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH - 1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH - 1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
component pr_axis_loopback is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
signal pr_m_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_tlast : STD_LOGIC;
signal pr_m_axis_data_tready : STD_LOGIC;
signal pr_m_axis_data_tvalid : STD_LOGIC;
signal pr_s_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_tlast : STD_LOGIC;
signal pr_s_axis_data_tready : STD_LOGIC;
signal pr_s_axis_data_tvalid : STD_LOGIC;
begin
input_lut_buffer: component axis_lut_buffer
port map (
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tkeep => s_axis_data_tkeep,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
s_axis_data_tvalid => s_axis_data_tvalid,
m_axis_data_tdata => pr_s_axis_data_tdata,
m_axis_data_tkeep => pr_s_axis_data_tkeep,
m_axis_data_tready => pr_s_axis_data_tready,
m_axis_data_tlast => pr_s_axis_data_tlast,
m_axis_data_tvalid => pr_s_axis_data_tvalid,
clk => clk
);
output_lut_buffer: component axis_lut_buffer
port map (
s_axis_data_tdata => pr_m_axis_data_tdata,
s_axis_data_tkeep => pr_m_axis_data_tkeep,
s_axis_data_tready => pr_m_axis_data_tready,
s_axis_data_tlast => pr_m_axis_data_tlast,
s_axis_data_tvalid => pr_m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tkeep => m_axis_data_tkeep,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tvalid => m_axis_data_tvalid,
clk => clk
);
pr: component pr_axis_loopback
port map (
s_axis_data_tdata => pr_s_axis_data_tdata,
s_axis_data_tkeep => pr_s_axis_data_tkeep,
s_axis_data_tready => pr_s_axis_data_tready,
s_axis_data_tlast => pr_s_axis_data_tlast,
s_axis_data_tvalid => pr_s_axis_data_tvalid,
m_axis_data_tdata => pr_m_axis_data_tdata,
m_axis_data_tkeep => pr_m_axis_data_tkeep,
m_axis_data_tready => pr_m_axis_data_tready,
m_axis_data_tlast => pr_m_axis_data_tlast,
m_axis_data_tvalid => pr_m_axis_data_tvalid,
clk => clk
);
end architecture; | mit | 4dd94c3dd2ee3bf8fa567f4761e726a5 | 0.566908 | 3.315415 | false | false | false | false |
zzhou007/161lab | lab6/TernaryCAM_Cell.vhd | 1 | 1,379 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TCAM_Cell is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
cell_search_bit : in STD_LOGIC;
cell_dont_care_bit : in STD_LOGIC;
cell_match_bit_in : in STD_LOGIC ;
cell_match_bit_out : out STD_LOGIC);
end TCAM_Cell;
architecture Behavioral of TCAM_Cell is
signal FF: STD_LOGIC;
begin
process(clk, rst, we, cell_search_bit, cell_dont_care_bit, cell_match_bit_in)
begin
--reset data most important
if rst = '1' then
FF <= '0';
cell_match_bit_out <= '0';
-- write data from search
elsif we = '1' then
FF <= cell_search_bit;
cell_match_bit_out <= '0';
--search
--previous result is wrong therefore nothing matches
elsif cell_match_bit_in = '0' then
cell_match_bit_out <= '0';
--previous result matches
elsif cell_match_bit_in = '1' then
--check if search input is dont care
if cell_dont_care_bit = '1' then
cell_match_bit_out <= '1';
--if search is not a dont care
else
--check current cell if match
if FF = cell_search_bit then
cell_match_bit_out <= '1';
else
--current cell doesnt match
cell_match_bit_out <= '0';
end if;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | 421ae88c4733cfe50984bce9bb9e6bab | 0.613488 | 2.984848 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/reset_blk_ramfifo.vhd | 9 | 34,296 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Rj+AdZYW+VUNXAOz3XP0Xp6iw2LXzjpEDFsEuGU5GAH+XonxCbUrPhYORH4FVIuHxzCprQRbJGzO
eMJpaEHzbA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cTcVm6s0DGxAAMCtdFyx41slUgDDOkCBFnG9hTEM5KWONsrIyDhEFPtt1A09mtlRb3+AKjeg0LZE
QLUjEwDoH6AjwVNz/0cpFuaQ4WKQK3jyXFw2yWh6HM7gj0bp1x/fEO11BmQpBY29AK4pvkfvhs/n
Br2mIb709NZHQxXWARg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DLaCV849AbxcVKmbzKR6hG0c8ks3pP5bUlTlbiQNm2ZnSuIbRwxGzlnl9kCTJ4RrZqHgUhcwnQkK
KPLteF6xlV87r9WKv9kPEUdWHZEt4WXeWqyyuHySlO7nWt85AjoHSlW4Y3iZ4zdSLyXGn6V7u56T
UM7/fBQWLiPCAWez0B/71bfUq+2ltHtFY+/OzGTdm+5qb7DPAHA8QUq/YTag6iRctvrFEilJRATe
qRtQI+pD/MMwp4Cr15iJydmtw4/tg9W6kuNsa4r7QZxMnV6B8R84uXsaDh7leGH7IdoT8gI5a322
civH5jMoNpLeeFPJ9j+adkRWtlbNl8nhMU/l5A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WGiRuSTb99wWbTUkGbaflGglYU0XLEiDl1o/pQVWtssiIWXPJdE8vXDZJrMxtWcriMSUKKeHz5Tg
w8XNGXV51p/kQp5tV8JZOAzCWyXzHP5ZVlQBXfnXp1v2vNeCAqKagA8U++IR8fMk0JvhSgIvGqNP
xgSTySyAuaLR3SrZNuM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qj/xydO74HwkhcEvzqBQ1eiF/Hw+vsggtXGUFOwhzVihvSNhKxTjIvdvB1VJXYwlUCqyYnRqqDj2
41vijtHm+4XO7qI8pMw7CGKmv7IyZ7YQtXkUgHnArYeRfI9Ps0WvOMvJRvu1UXtaHhCB4ae/OqxZ
SnHivzrrb4wqIls3OdRMP/o48zY9lnqVAsoeiL5Zu6VN/rRlqdcVlOCrGGkw7VzAN96bMfFgCwY2
iucbdGEdAR8fcL01x+/yiduys+NiSdMCvMsPb15qGzNj/P8JKFqKmNqRzLHudKtVsOTqgpQ4WgPz
MNEoCx3kWPDmsjHvxm2399dnFhqLtV3t0G7Ndw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23648)
`protect data_block
2/aRFvIsllp3fSjtVHRlyV3UBtXey3LE27c6z0X06dub5JaTOFBpF9WFOkIJoDQ1V/qfKQ8dZx0g
NJzFhBthApE2T8DfVgWgd4VhjYeZzzkCAgNiPDeXR7gRyVpxCTYJFQZWB9FdRtcRWZs5DGHvRIvf
c7rOFbz0QbHh2WltON3eViW1Dglrl69m0Q0QhSoBeJohd0qBOsjsmUzEgpCyQLLBZAKSVL73535r
bZvXt4fEUkAAoDY7/XcU92+pZwLNC9EPHVZ2r8t1AoKF6w0xb3KB0K5tEDug2eeQknG4ah8GYTv1
FsVZWUryDymoSohQwny+k+tIh/LiksbDPfGY/rbKkgrQxS4RWBXST+kCdkMaIt7wEh2ZSXFcs3Dz
m+APUA4SR6uhYvHLfOkYCBcLDaZ+QKLqOL3Y6HI1jdU/1sOEbBHo315cLagG7IzoRF9U3wOBhOkS
U0vL385x8JHPAgrmaytmoBu99MXQt4oTNDvfLShIrANXx0Nejl8mBWVy0OX87p1h5Qa6by1uP7mb
Xjlts9g3vBQdt8Le00/pKbB2rBaOMRfPJWIXNXhUOSqCrSx3uiL7R5BZf8CFRawySq9wOTP41MjS
nDFAGSKM6OcjQDnMXgX9bi1XrWu+82Ed2zlVK19QHmO73cYdCzLVDkDrwer6QJw0rn+n1Ml1oH+m
0aunGrQXVx4SKhQUQc+1x/P860jULJWvq5J3FlBS8U0QGZ8u0IZWc2FupGHJ08V6nnzmbue3uls+
2W6dxhWlwJwzXHGvSffgjIJbcF1uxKrlL7VoSdGTLFWRm03TznmxQZJ3xyAhbAF7rtZrVTqD9kio
UpdgmbSnhfUeQRZ188iO4WfkCCEF1rj19cOwQHAxuiIJw7k1ngcYDE6V7uxaphl+66tWHFD5238C
VbZlG4EoN9TT+twQmdk4RFdeQYq9mERMf5HQA/c2n7s658xWFmPpefcuPsK5wiZTqKmwZaqnP951
THgT288ry8fXAeiTq05sZTY4MAjj4cTCpZnEEnC1w4D7SEQcmZOJPd/8xDJ69NywR78OmiWIlaBr
Eo8M29VSJcHdCfLcgjE+ZpIUaz7MbNYZwG1iUMbj8CuSVPEaXYBWPdNln7RDkDiqBzNaQbpvc6bl
GM5CFx2955Xtn4ghjcN0Kbke16c9dbxwQdxPUIun2sbuygwYhnEac9pqDgcti6XL98SpdPcrM/Mw
Mp9Niw5uJtgcGeDL68PsJzSpwlggmWgnO3Ma8skMnLwe+6x3YSV5qEPbesy3fO4LLaSn0o4D91mz
rCqFWeJk/806FJqB5DI/IudIjUVkMP+ueBxmOmrIN7qDZTKPYahhX6R11mOtyDph7jrqiazAUfF3
M+BuIMUUT1pAPAkjEQhVvX5JHsKXDZdFQNIavCA09euw8SnBvFW59k+l84VtizHbLMlXMNU+Nxlt
4XG6+g5s5ccBsn4jf1J1tmDmFAC5S5LHMppQeeNWJtYsR1eI0iFTq5HQF1yvM0GonkgsXFSN1AxL
PmSj8p0hx9DzlEOfJPjxHPLr/iSTB5ACJrPajQcRsGlnahqLsMFZz6v+/JeCNAPd8TRh2BeTxlhc
4MEFTTczoYHDoP3rb76DLyGnlHgRtRYgQlFQvYbK9s9qCHXuiu0iwz8vPeuNLVwV6bH/PbA3eUHN
i3hCVZzl0PBpVRDcN4r0rmv+JeVstKZJii6Qp7N7OPzrlC6cU4aDlvNtQ/aEIqeXBP6ofVvQ1IJl
JCz6g/KQ7pUdlubQLhnR/uPuIekHgygYadXfe/IuKqW43iA26RWYBMbelVXxdXF+uqy4njGknWZD
YDLQlWfoC01JcYQCrJBYHnpgn4i2+zmO1pNNCv1tA7H7GBAUkb4g+3xZHmcJi3cZmXe5imOaKyoo
cujbYnQcmybhjrkPh514tRdX6hLvnK4QkgrUW1DDJ83ykXG7Qq/Y4kgNLJVfzrJ6fn0IS5VdZbYt
h0ta9b31YHhbPmKb3pE5Tm29dVfhmPA8lVPtJaFi0jJ6wZnErcmtHWUaUgPms5ja661FuzgPwaBT
spBystI7uQbg/5qFv3Su+Ed0Ncguj3V1j1/PxCdisXVZ6YC43qGkOF8DDqFwwQgqi3b+c1SXCl3r
Bi8Axc4Zr5KaukR0uUCqZ9MzI72ZFFj8jYE4rqqj/MjYX+uMpaLRJXm8k8Fo2WrKAhM0HinoHTP1
YMapzCdslN3aF2hIvXXrJi+v7djhuBiT95nx+xmKhHfxOEWxZpVFLVw1/nBzeyp6SbUlGeOZAXYT
MmtaHLy6RgnmYzjNaXFFSjXlub7hr35Ix4Ec5jtEki9AXb3JmcE9YkMD+dX8M5QfZRhw9BCQvP4o
8W0rlIMUZYm9UsIeqdBtTc8ha4EG2HViLFPW+a8fzm63lMhJQ37cGAkvEYSZsvfF4g/Eo0kPUGPU
nQV9WdG0EaLB0A5JBAS//utx5ceUIb8OluTaIsVGp/j5pslTtyaYj8XPxKS7o1RQwmkgrVAxQhKa
I6m5x1RPUUjSZV56cbEVntJyXap84Rtyh7dqvb+Ix60o801OeOIDJNdoo/y84P3J5PlOwf1LEW7N
EzFSXvI0+NHYO2VaTluMtUd2s2fxULqcDrx3t4v+VyUqKuEGE1MUeGyCwclQJu9jwmqiyHGVK5Aq
j0v6JyySSqXZSCTJqEOa37irq30J5aWUwL8AqYUY6bai5Nb57GGRvpAblvC6SfMcHZiTGa1cPH3i
cVj/oJIFknowlgcdDt1Uzg8kSX8RTVcqSJwvujqALSlEU03CdYwCd2sYhT4hR1H+gXiR4r2V/OLL
RLKRSCEVXjI+E6d2S+CVzf4ZNeovUBL1vunj9iQ0sl3A7W/vV7rzmFVDhnNC0UlDUPD2mvFEsZrK
SlMVbzfaRg+PiuAzCvXlbH7hc0UnEGT622TWdXjus71Mi5D6eSWhHlAnMp0fzFvN9YAvbRjSLRhU
MupF0OK6tpXdw5warDRiyg28Eo3D+3kQhaKWUg08nHEX35oW2apNmpCcB5qGm0xON2UZodjTYciz
/xsQG2amfvvRICaWEZa1b0pfQdpAcWKTZKBvkjVqFQYlFCaStl+Z3LKk6IvHhJmNu/tMSuQUfYJr
A77uFHdnNf8A4QpCvwQpll+7Nf2QiLpnYs61laa0eGqkz17x6iUElqYrgfrnZ0ahF2bYuWx3pNsC
xQTYzwSs/iWvjmDZ235UFR7fZ+Kr7fyRSpSqLATdCEwlwvzr12EFJVQlYzh3oIEj9ZfAnibDHX+W
0RvmifGf8FNgxIWh0oQQ/KGlAskJVQI65U9XzNni4/qo1CHLgvQfFX02imu3Em93NICkoKZe0NwZ
/CO+lXE4RCKod+NW0AlnDSNEPNKp/hkFhg2XD/hkvPxwMEhOH+KlwgoKkaoMp81GmhuydSGZZhls
fYCngtF1+B8zW4IvRnXAgCjFsYqGdPp90yAcfZ+hwG1CDKi8+LqATcG1WzX3B08KTeqzRjLJkZPj
NMZFeN5XtbnLAzDlxNVulJeEydJ60c4VgcPF+UM9DxBfHXW5p6nFOAb2JhBBew1w5a+TocGwzILQ
5O+/Yz5qpRlHOEN9/WkRlNUzVhODl9f2y9JnhvspHCW3z9myuIRt3mHKbkV+xsJByJAGqrRaGekL
n8znoxYCgvQPFRG8QYhRMIrQ77uDjT8yPXyBrqUAzQhLkrlLla295KSccW0kc/VIxlDnQYpP9rKJ
/phsTy7N0AQqpNfiaWojqhvsfOrNjrHB5ydsGJGt2JAZCAuZ/eXjB3czEUc9fo+9PH6bju28Ivid
ZZL6zNp8klGsSZtFnCI6IOCKo+iYGbBrZK+F9QpbelliqwCBL7UQBhnYdoyN9b4EkbqPc5DcN8/k
nafCvjRz62gslECbDphstPdrolbpPTdAtHtWiFqWURoVMSAkBbgWZr/zsM8DOlbhwQxdFb7Wzp4q
k5HROYDDeR+GExPqIGMXXiJKoM/HX6wGsXHJhP5x7ucao7XKhLvuEb5063GNUlbSbrzwdgA3SlmY
EnTMDN+Nb3hqROzl+pmF7DaFHPXEeb0UmrNdHjXQr9Zk6q71wKkzqF4rkWUxKEMkdB5s+dUeucnl
JHe/h8aA3hUv8MlOR2Ntk7cHJfc8ndYC5U1cjtk0+OgWf1W9ejpsuQ5L9ZvHbXo6JysTsZLolnVC
EtxaDgl/CxnQiTuKvqMECJZbojVrp6J/T7GegpIBVQJklbcMejaAeQ8My8UVbfZ1JDqbshVt3Iqo
sO3u10kMSjTqnehlFzat9oywPkhXLnyhM6/pep63qaz6ciSnd2yNfHws2G/KMHATP+FFXlmba5zP
An8pYnmQcBS+hR9DsCsQ900gLmQLbTN5DvkJR/q4SE6RrFBYk0Odx7I/ukv8lbNK7bV+mQIqD9Wh
J3OX+A2mgsAaZWHviLa4N8yyL9GW4WfZuWDhbhUEgQaVGDxUDo3lkOpHw9uh54nYGmlgs1U615LL
PQnKCDZ9CXi5tpbG+cUUyGWfZArgbFNs2RhPOnf8P8K/Z2Cey3B1St1otFlTkjvrjfROipuHaxNV
7sRVN0v6vfz7X4PhA7Ujq6l9B4NzKl0irvRGHjpRlJL2oMWJQNbnGZbTwUFFqAtEtjCBskhn2H2F
eYVoId0RS/dPuH2wFY1wAiR7sRYPKYIiSGAv+i15bFduNxgFKYUx4nBwUu1H5sDTrj5JbpvMIYcI
IUXrqS9DqqSyssf4XNRirtvwBEb5JovuvgNGLJBRWIASrg330DwEy99f5ZD/Bf7HoHdag835IJgz
EHvCxAU/45RyDCfu6NMuvEV+v9hUP94GOXBu4aw+BNCcQIisxHEzbBKdVeMxPvc4Stn+pxsyV9jd
Qa3x4KUDZQ0Iul1/lk6lD9drFJut4IO7VMAUpblxKUa1WPomxxZTTOCsGZesu8xJyCY+knuUTgpU
iZo1zlZ9tAUPdPUYrGGXuoFFhXbhMS3Vqo/NDN710ArW2XaMSxbr8gJZX0gURdTwxyRsUFS9v0VY
uAxbtagIso55VnIo8h6O84bTSrzGeg4NUVFP7D4oWMcHZRQCsfWWYH8GEWxtlr+5Yr/4CnWp07X5
VxLpaL9BDhUAExmOj1MJBIN6JY3eIGp35FKkoF11uzaAwXhHb7OHFdYp8cTTCh4zXbTM6jBOtvrX
S0+Uc4+RmrS1Io43Ii6cDSeq1dTWcTX4VWRdKQT9GkLKLGqkdq7C+pwj1IP39OidFfYaN3UsVoWb
FvVYAsrwbp2SmOoe2bmiEuzuH4eVYhPaYYdTaENMyTM7mOatKlFyC+WNmQZehBbVWMPudnC8evZo
MDzDS+H8FkqfSt+Q3mUx6C2sR1lN+z7yLmdH+L89H4IIZW1I7DRs5ZZ9Nr/DYIIdx7bfd/aj0G/8
fDj3/9FRP/wQ227ansD3EPszyWvx6NCw0WZck3L5vXN+UQqlh9+0CvZw/50LxGV1L2IhawVuSMte
imYsE0iMM6unW5+QIalNtoNP+vuPi0TQgRAQvaj9tKfS6r1mEHVNeoD9t37r1tonfWg6IL/SdhAO
MKjujdNAEnF1JsfmlKsb6pYk/B1NH4+CUvGQAgA1EmKhK2DaaSUKm+X/3Iylv0lgExUIatsLCzP7
92RqAZzsqJyuE0kth2frG6CwXjg0y4G/bSrgI4C1jGu4ZNbwyD+3Ld23hA/1jl+xUUAQnBcruYui
LXvy2jK6yvyVhrmtLcX6PmtkjOw72IkNSBoAOUKg0f1NrKMCx6y9tHM6kBd2gQDhSjqEB4bGZr4w
BXW/vJtAgAWwCHfvHdiN3UxhAyLYfVVal7kwCCI2mJlSB9JpvIpCSPYvHWmBfQ5xzd0JtiEvinOp
5FGuMXvmtDq/2HqTt8vtK5j7EDSQH4ChIyHH/eG5P4Gcohv92aYvcxT+syJAHJRCLAx6MGwFjrLy
kl+U1cvgN2MnDtbQ4DBOBm6tQ7MTgPGhK3d+apj5Qm49qgyGjuxFIyAj3MY8MMlHJedCmphLBxGo
IG+AsLaRSYgmLATwLUVMdWNiTcUjYHvZAkHdEE/Fc5KOWwCGNffeOaydyuxzd90fRqG5VMeMh28W
5PsZNDUBteqJDi1sq2Aq2FZ4AjlT7ZwhMQAMDmSXDQ2eUT8+/YDLEzB72ivlg+/d63CuzzmAC+KV
4oe23ebTA8z48e8PpwKoetLVQId71qgxlmsrDZ7Wts9VgE66+8PCPNvwV6X6+FPzlEHp2RDjOP29
I2dqdyUw6yQdK0zebMGEFHqRxw0BjBGWxpPYa7IyE7WQ5LkpDvjMzoUZpe2Ob18eJZbf+ln0iDfF
sruSmVlEi1TTAVzHkmJLJ9dupV7yA82rz3Y55WXdmF5km+f8nPyt2qQXGr3ERoA2MfufBqa9bgxY
b7Pnaa30gYr7WCY8iO4ohw0GBBfqGnt9nLgDcPkd5B9OeZWpBZuY4HamesBBKlB9hzPIylAO7Dui
IWtxYBJKCfvTmIkQGmCQki0a7dx3dzHAgWDb5Y4sn5LjxTLR7uz3QihWF6sK9lpgm6qxmaRrFGdv
Cc4YS53e8QM8tHkQSu0+W0lsW9cWOFIimLwaT6YgFD6ivr9xSWdR8zBOI2dFQ+y3/pC+p2tIV3nh
URL7sPnWimylDzWuk5ATYmDg1aDH54U6oaBewEyQ+/qm6chUNO7JsY/v1Bm8eXM460UUADbTzyOn
lE3hTvqUXwgKCk8kjkUliYvIrJ0ncCgGhq5QbPJcaEXeWxs8324fb2BVzxYFqqk61y715T9cNO/O
p0I1WmXPBxSNFnSu38fY6ToWPYbL7rY4sERUt6yxkop1ekFtoSWhu5R/H3hUSLpCHCSUO/pxiVSi
UBbeP0gEZKJP2lvXWRR5YF7HWPQkYsqrVMxP8Iye+2RTTNdQDE/0q8SgFQCq5+RfOk55UvIWRZqq
03RrUwufTBHUwfMgSGP/m08Eq9lcBAie+VqbZkqllTGbr41nPBFr9Q1MF/zL4F348HFB9Vr//yji
ZoH8XPu6dz1n7/p41c5FVXo9CjM07pichU/wlfbA9YGdRTBnWWxFXXWJOmJEfQgGrFBdl3mnhqEY
x0jJ9MiCDjEfWFmM+jfyj07pc6L+RsjakQUTj/Bdr7xhCF1aYRS4hYEjBVxjbplimEigtIGxRg7m
ZCHkR4MAU1tXUuVxgjtT9P7nt7S7HfFUDKKakE7X1uFmvzvcLEMg6A0nHQhsmyvkPRvSsCqZ3pkl
gQSUEbfUkb6em4ZnBIt3eoGkwJZb3QaRsDQvpswIRCOMzBraCtLWJF7FnPyPUoIfDu3XECGcewHA
/noLfNA5LpodXZRsWmgAOLpKfR1UDuv+n2QqT/sMrPa0NbA4ZsASqfWEo+Kab7sY2BWcMI0ojca1
jbSeMYBr/Sz11Hi4fUfUreuJ0UPzaXOdg3MC/TqNSd8ZN/V2R5QeKBCrE33fwDJEXJlUwWjW0Ql+
nF4rKy/QtJ/qKoGY690YSNvZRm4Zu0hnrEnRzamlZrTL5lcfxi6p7o3d5mkWRMcU5yp221PY4il1
ZcrEeueruVEhr+4tqfTkCNjBkiNdLAb33YxBqqEiqCKW9WjMcUpm3RY5mcAxkUoQqxsy/LHGJLqn
b5LcSXyAmQNrCQZuR7h/USXb+Ag1Ker2mqkdZbWD6bXFKnpk9jZAIVnGryAvCD1MmuczSbnZB8j3
WwX+jGoPF1LT1ab4SCZ66pdOKNWTAfXZBHS3EBV4G3CBCbvtEu0GI9Ht2nWl6VhWOW9SdZDCNpM1
dpk6JOmvl2MEhnKDvXKgnCNIy9r8m7TtAWutc5bNFweAc9OI4bYUeJ/LEAr0xAmYfQkYI+NDTVvg
ydTF1Cu8h6lxUmo+quCyp6T7kI9A50m6naljWcrMYNaKEuKK1XZO1e6HLHQBUQYO07RoJBR4zWE5
wYkFVpKSua+bIJx/PsHGhS+ImSsybFC4/KEj93FH+bciCrTSW3FS5OSFpVtXlFZ9lpgHi7Fxdkqf
SMhwcuWiPNNkbXkhn6Lq+VQoN4Ror9nQN+nvrbK37EAhj3i4qOwgm2wJ8MfY2y2Ixtr4V3yEVGly
uoNtUWUbla8ec0nv+Ra4Pa6GB7YBXS7FFL1WNMXllEt7zQv6/HQpOuPzXMgZ2G1BtNOqjdggEQ6t
e1TAFQEjGhTfvacdesPSTxpMarDl+r7cpnV/92mkxe0pFP2QeGYzcWuq//Gvxq+JpjSiEEYhAmx2
VURhGmPePhDlnfm8hQA9w0dcemhORQ+OrSIjNoJJU4ZSvPIq8GMtGT+0K/Xl9K6EbKAS76qjDrws
4g6CnkZxZ2xBT1Wf/1hiDr4/cQFlNs2TxXUxmyOKRnIuBqtmlh59hQDgh/n6hxa3BRfPkoCQC0pl
0emn0W6xh0oIobGXWfx3HZxsEQWF5BGLFY1r8ufpofwZB5/yz+pHYKfSWDw0WPvY96OEprSMRALa
Rel3C/0deFSrVlKXuCC9zMaY3PCOv8WgeOBbuBLmLXUUxXeI9aJ4Y5dE43Q4PBVEp21SecDxiGHE
ak2FUmLUKICJVaGJj5pp0ran4J7Fmn3zoq/F6t2ivJx8Y95inbGtmuwQBieU2YzPDPCSST4Ypogg
3KBWkqUaiiuCEdencl7fH8T++ns0T1pKqs/rt1y8LDQxuHvMuc3tFDB4ZS+a7lxfvmklF//+Dmhx
fsBiNE2dH+AORiplZ0B/yb2rXZ8o+S1vOXZTSG+A9g5Sl5oV4+i6IbRlEbLMLOZX+9cIONxAFjHq
VD1p8nyiUfg7obrNg9X3OsCZe95fQktyyk21zWJ89jU6kf2j56ie618tErKYxUoxdyBYnLwmY9Xu
S/o9mZVu8PTpBVTpe2zxHMgahxzXBITJlcwWLGTQCi7j3Nml3KtXpfpyT2dYFyzEfsnpRmFYnDtL
FUCQPLQVF9od+N22WAdKQTpPmQrxETksyiQEhLVrPT3EUrO6/z3dLxZrRIHTnrei0fzzJottMIEJ
OWA3JSxisNEeRrj1l/th9ta47/0BIjHR1VN+EPqKbL809hAGrnxVcY5rwQE0ed0KqwdSui5I/eVK
K+5mg+4QwVpBFow0J5fuyyl2rWX4Zkt1nY9NoCv94o+mVI4tGKP9BQCdUPCBPGja55M6ULZQstD8
TkjK7GIF3jgk4XWR0MVBCdJkleSTwv1BAKz4FOdUK61LvYnBP0MNas9iiPSMEIjpE6cjAkmSvAYI
IGG9KZWIReHlmEkJT3A8TNr7v7I1lj6+EK+qk/WB2hnZz9SrGX0EOCQ3ZnH5oZg0ft7/9Ofu1c8l
uvxZdMQkrbxOnR8Zf1i/WJObVzSW+jA9X8Ajn+0Qar3mlf7fzFq69bZsDQbUKHEMyTi5+9ryBHG9
NkYlACLiIwnfwu6qFcI5El1KovB+iMaQOtoSKiKNMthXXsv6vbsq+cUYRT/Bx1Dcz5BnpW+CN6AO
7ij48a4ZlQSGmpHxkGFMT6p4R2D0/eFVcpov3LaNfzigR9cI/0s8ThNuGh4YT7nZXoKZdxstiWWu
UFPobFy8JmfpE13Buo1JhJyBGlXDKxRFsM46x6KOwtE38zFXakOJReykRnR/gSrhrbNgM4lah0aF
MWYdhXlBVCojhf1aLNw7KOFRvGI9GV+y/oKswCj3i79tcPzPhe3QBFNNzWiveQt2Hku5NAFPnpBz
1G4E482eLiUNp9jpfBPh5rOFImvc1IJk75QVsGF1kXzNFN0W2zVBD6taJm03zJ2ed0QErndVS10H
oDVORdC7kM2dLOYPiN2EHa0VQjCoKWuf2gT16TIrECkoU/xfRRsB+fPyXcyJcKG/q+OpUTcT/eJi
wxbnzwch3K+WE089SU1XmMzV3GGqTOlSc0n9olyEq/kjRP/Hbhd1P8cMdRYQYYCCN08KpOZCO++5
/EWRpyWKWfvQUGQo1B9GJFA4sQMnyJzAZfpjda5N74SFkCJyMSDJNNIrBuviXbKKkL6G29jNBOHo
VUwB2nxJX4RlkEh8pbsi2guqafFKN9TAtdfCWA3pkCF0fmYc8DQb72hqfCWDZF3d/TQq4B996sEo
g6ZXy/W5l48cbULQIYrnicJpa+GMwpf7qZdrMl0fiEgOEBXTM2N5HCetb3OB1GkoE2p82YHofimR
UtM3ZMCNV4Uj6s7JImHttk+7MUrNoy5o/hklVgDPpUcDXqrpk1EZGtqkLQjhTde4uw/gtzgzkBJd
lhPtQYwUH5t29Tlob3KHkxprCFSEU0FNl8L7NO1riXRPrdQo8NSWVcR/bh6mclgjwh9Yb0aAyHA6
V4ZNSyp/kCX6yip1cFrkNzbKZBNUND1RlJSt11afcfFNPHkL8ZDJlxHWvCKV9yFhd+CwfP6b3TQD
U3mkHrYySqC8vPGbHQZN63s8rgm/fSQm6gCYeFy0POug7V/leXujQH1ACOooaNq7vPCnSqVOKiIf
h84PD5iaxqmwmWxPVbYhh+mZ0hfa9Gft+/FzF5hPPH9wvPth2I4z1joiSfQy2NkDjU7kbUWL9Y3H
xsSotyYZzmgT6IkIPxRKSpC1k0TFReaY8Fz5RgxNSMgi5EFqSc1MCnRRO61/WpFsUwGErjoC4baS
9PR1Dnk+ovs24tzgsc8QnBSgG3K/bcQJwG6htj/4oXaRWcQyh+cEH22368aFuj0Ev06H9DojxuJN
kU+EnGaFi97fN5wrqPLo1HrDVLIGKykzpaJeJqBiqLt3sJxoSSSAVCbZ5L7c1LnD586UBmo2OV15
OY1sM/Qx2pkm2CPr7R0OOzjltaMLydAdt/feQHqtVsUUwSsuaqFWfB93+iMvp0Swqx5BcjYH3z/h
7jJOaDyGcoYnQd1AfzpmqPW8eYhV8xs/AutquL/xv+wx9L3qR3gRXl7q6KA0FA1cmrASnwjOvmL6
FG6QoDkBAW2LRfJuaFJve+MXltWPmFBsWVt7Hfnr3CF9vFiMtpcHpUjOYMEZtCh+Vbz7o+JH6Mha
Dg0gW265NEYCu8RLqeBPdEuovPWToJZuL2gQpLKMuZwZCC2ivIfoL194rk/qp3eUiz9jOtcpfd3L
yojofEXg51iSVAhFkJ3z+ab15fNtNTZoWd1FF/C4gUlCjtg3r2DFIbJSf7qHFM+Liy6o0Yw2AsDu
hbkoJy9esAMtmfgw+ToPDu/VQ1hrBJ7RNkRia9d5WjS8llWpo1al+KvCgibYXODlP3VBWMfEweTZ
GDmrzJ/kPBielQ5RtrkLNr+5lXWxuMrZ52O7hYBTDSnOQpRhiMcnbMm8eZmuIoS8WG7/1+OiBElc
QWcH+ly+nf4gpUiqBHyy0t40GvCofAY5gd02578UbZxVJGrzx3hvP6PV6zN7RihGe8Y7QZ0uUX1n
n6YvlHK8k9Y4fvqlJgvC+P2p3iX5s2jmODLj355DVs5xEA6iBjLVg+8ZCzw/IalYl52cNJDr2Kg5
m0a7PSYlzeHFqKCaUFb3NibKklnhrftC6z0W13x0fvLLxhQPB7nnTc1k2AG2oA7deamTCl0cKPtE
9zNxMC/uOHIFx2CKGqMhKws6eA61/A4qsh56MFTizC6FB0Yporqfnxjj93FIdkf6rb9rh/EoNdda
5mXQ4/UbMCzkPi5VFfcxqm18ErsUHCihH7ZvYkWWTDFk0Zj2OyUVLygxFB/pJ3OXqVVRCVxdSZTv
YkU8rehOjBA4/J/ic6e6gF96dyGxEUnfaF1F/Mx6w1IA8XDOIF8ix6keCgfVJAkyVE8ziq1kTpCa
b3n1gRIEUsdpDbUcH/01KgJChCOYyNi35gvek6AJt2jTqF8W66Lp3p5uvagsn7emaovASLdbrO86
gqLbFNkIj9KMCuenBtE5onmxg7j+5g23jEUy8euTe4eU6RfSXEI6JB26uOfDOsIC9OT1gKMDyJd7
NHQ5ImjnLmVy5KTWXUyo4IQO1aKhC6LsJ9kQFIjNnjut0dsZc27zzCCUTXqIaG0oLfaFbV8scsGe
KK5Mo0Sg4XljJrPyoVqDXfVqD+i8UahnzPGE0WQsaVuMXAPwR0uAReUQuqm6zvz2kuozBxCr3Nhv
Rbo13Ju+3m029YnDWXqBh4bTZBaN+BGQM67JAk3UWk4b/Kid//oD+lPAIW95py0OTB+xxHUPHr/1
P/b5dG7nL4gIziJ6IF+dGvXUdzH0zJ38FQSPRSk8/DxcfWFzoAFnUcOSzH2WVQduHLXncuQBJf/r
ipISLaIFFBUYeWs3ota/UQqVHV3QjULUn7PTTDl3vpmC/59OvubBENK5P4Oehkrgp5qL5v3O4rUU
/9MUOZkrZla3HwKU5rOc1jnMPNO52Ne3EYGmcSw1o1fWchVfxz7xdTgBiNDh/n4+4/Eg2jxWA1O1
7DR8zrrFIS3LyUsFDt9aUQXFRc/WxesjUz7c1EKNt6DiyU1njvBT+GbhkXNygjAN2wic41U8GBmG
A+Ehd6DMzK0mzF6mDMSgO4abzMIsJyYUFuYiRNUGEPHwUCoZeY3zJiJykgLI0h8397kWA5pmVz8m
Hde/4z+5Utq4kIMOAax8Dec2x/G9HWmkaN8InnhYtNBhRCDq7wm+NMclmnLiciXRcVdw87UWu7iw
zVcYu/OxePZnPzODDCyjYBEhbmE6kPZF3cXVYQeY1PK8xr9u9kYhZpRgj+FBj6juiFO2a15k9BtD
ueIxv5Ue24U8k6fZo4n8WEdjGKctjvklhDP1uE8Txshx+i8D4tSrOEiwEvlTIRlvko2ldBYidT2g
tI400T7lDpo++AN6WYk0VCO8EElncKO1rP4Okyl4pTe+n46uc97F61iGmlTk8w4V83vv3hrA6m3X
1+DPWPr/K5vC6cBVVbymtQM7YNsAjC3zFv4KJh8TkFmJc60WWeN4Ks0/jQyXn1pl4yTZ3liZ3aRQ
z+zzZ6pbomVZAUDfykhBRv+yzbPmnJbNIrM3ptcoMWnDkOSO7gqNrafZYocuNuQ3z0RoatF0jh8U
iKIZzw+jrZ+iBQkIPv5dwdxxKJlw0oK8hko+cSGAKoR5wBbBDYb1//1uK2s2riZ5u1WdAyKSPYlW
Z3XWjf6Le/bHhf7Pmj+Rb3oGmbbJgF6kV4Rd91Xsco2ap4pPSIL/H+UbB/wPJty2KmHGa366ogoB
bqj8uZJBpsOZ5zLGY8K6JZJKQb77WxRwM9xWaIl9uuqmDSRtT3+40siR+8dByWVoX57bqnUIcVrS
YG2F9Ii3hI6du/1afipRMNlAC2QWre76CMUBF7Tj2x07SdBLyXKNfSDW6XfmLKtNR1oYEtyZ7lFQ
hsj/nYgOJrME06pu4RfaTyHhNkD/V+fxhl/aLAdLoCdOf+DvAQ6FA6OJbGSb8pFMKnaLMffLw922
fyTVsnDdkBCAncyr/yawOSB5r4jylondo6TgleViU5lVruZSUodMIJCAPxHcLZQotnA26Mk/igtj
sc/k8t0+xSLhMgUw7E7hC22/aNfaLxiBwRcdtM0B00F8sCveKnxBEQWrvdQrds0c8dFs8IcRFeWR
zPaQS1A5rTdKZ0hbMVKSYMDG/l8SUpcARWhVVqzX74MjVJxbEBZLo9V0JF7MctXAO1QhVwOU0pV/
crecmfO/RqDtcaPugy58ahOEEvEaze45XbfUh5Nw92A0W2jSeVM4zSHD77RcdoIaCwpTCxhXTOsV
oIliawRU00+C987eIbLntUT5884xBaq5q16EvdoVAWCllAz5o+JpQUiC3Ynux50SxJUmnHPwiPFx
XLvBRtescTBfWLuwEHuKZFITruAswnehTi/Ma+BwxxCLkKmLr1A5/gFyLCgjBWzleg7x5k6ANvXz
XttAgT62Xfw67eFu8YT8bHD6upkA3cCd8iulCgvZW5S3Bbpf5aooUYwcbWqn8rXJGOWKINWYyVWr
YTwxu5CJwZRkZfHrotIum9+bpWlRUUGwOSN4eXkkInhHBApfWaDAIXvVQPweb1GzNeLupPnAGaib
DZzqsd96X5XQvHqyDINjmBnAJHYtA2I5gx1stxDKZT0U6Xps+LrPrgNXXuSy95SFbjbSRyUccfvI
+8dyrvVyhFwxge85cjXSBPmPwHgxiG5bT4mjQdcc72RNSpwRZDG1aHMmdQJsN8uTOhKwhj3gBkzl
welNY0ZQPnmNrMn/glzF3xCEaTcdGnS91m+e/h3cywpGubYwuSMBTbTUU7vxiqtArtKiHr4sUUEr
s++2WDkdPWsjfYw7Pq8PWv47ztixm4ECYpUppkGeU5k0qcF5R6puURM9z+wVWOGV80Twr8TW9ear
CW29kprt9n51GWgLJKn5mce2bGY/Ebr3zpx9b8gmyFWV2UzNAqTgH2nWrF46Cl9WiEJfmVAlFT/B
Ootjvr0+jIBAQOX3b33zpqP4yQNOl8ilqnkDptZ/ri3Cr0rI3U1zMuSOS5sNqHe5bfZ5vgQliy0V
tFgrXfh3ClihOIyVaWgF5JWmZG4sZKSpzEopyn+GEZGexMbhmhO5orrF0hhRzO88QTb1NWG3MqrR
a9xViBAOjebkcDZR7njJj4Y3YegEF8sEpu6oIcSgqqL8+qAta99QNJfB50PDuGeurygMZChmZuv/
COydhNlATvR66Fb79iDue5ecum9XjEzqERwnxBDc6JIwNOW1HXJm+FWaAGAV51/pIKuNF+3lNrq1
0tEqrzW1+Nf1CVrRMHAHNd85GbYG9YwGkSLa3v60l9wToS36/wY++dnbjC8vfn/23TBM2wROyaqC
DWOZD6Xoo/d1gjWNJN3j2O68AKEnqwxM9sambNFRag9kbrDlb9mRPlcIXLSJHmlqGKTiHOfu6SeZ
DzTOpPVfC+MwrlA06sdTjD4fRJBBkFqunSAMjN6pexrfzyo1bRTbjQ2ptBJJWU+sPIHu3CK0qekr
kD9KkBXgHHlq6EWlB2bXp0+RKDqe7b1xgsLitVYrUBz0KImABYPhEwv+ePYNhys0bgVVfP1O/+4W
ZDvkb7KiivBJYhDaB3WfkmQ5CW91d86n4eZ2wIgbi9Vrf6FbRQU/BygB1yQdsXsY9m3kwtS2adxx
9wezm/i96VZd0I89owRcFcM13my5o0B9QkrNtTzbVI/NDE5Z+4H8G2I54+aFz0jmUWiheKAAtw7Q
7CjwjTcezFY9yfxtwaSivMzkr1VbjGFktag245EWQCIysIXF+elPneaEZjccyGOwpwe53J1LQWoO
jMXz97MgUGmSj6yvKE189rZpAbwOPjnK6y7ft3qUj5hyxTbwhEn1YZrL2ys8mfeMNrykJ1k9Ui4f
/jOpbJ5uIefBsLM+lHR5/16g2qiF25VO2BctSYLEyzTjREs4KxKv5lio0/iDh3pEI38PFjSvZQjw
RFBzeANjO4TpruPQ6E1GPBMAvo1N4GvRGXfwEhTM9bTkNYtEaWhHgShCDik0OHpfbQwUf0t3dgL/
7fwj4yLkE7/+JibodHSSzP5DGvhYmlt8VQe3izk0zF/YKYGmHFBAnwqagVTmFjJ5u1GVbx5sbcca
0OQ/U7Gt1Bg7wWb9xQfJG9XYEhXbCpMQ20GqFaVNICerw5c+WPtdHHXeMS6T4xVpoJpqe0/Tkhia
m1R2AC6mz99VDZqftUM0PAf3JDuwHebBrFKjeTbFNshDgG0ErwgPPQn2RS3ryDVDZjFeDqb7qjDf
dyhdb3lx5nvfk7ciVWo2KULEKOAO1C1mMb6Ds+J4eyfeeTCSIAenOGB+BJDKi4im1s9ncQAqpCs3
H87R8nhE93ZALg5ss5ZkBl3mMkuzdO8k8TKMt6bERrAXwIu+vkHoJXCM8RZKm6T5XDtu9ohgmso5
z6jIHKs2QC4CexyBjfOrsthNpwQr03x2OnaL5VvxI78OScjhh8lphXHZsiNKvIgHEJLpA8fZeCHW
HLvKkUkOk0XzBbXEseK0MVQTy+YJQxqUpYz1eXI9mkg8ZvCdgGMBA4ozr8NBLtcazCiXZFvXXhMq
j9BiGKZe+GzXWvhcapMlvVk1kNzUZFWuqIQ1TsRhWLquRfYUR8gwJkHrsrYngoOhgyR/hHb1/Eim
ZXaKBJUuWk6silG1VJ24iDvFrmt6Z1I1vXoAv7GftsTK62mcOw1s1ZDpAZZiPTsmfFrdzTLk677H
w5lZdyeY616qnTXDXUj4ANuZXkL+f6DgAZmGI/aHgwNVYhcfYW80Lrjit1QfWtrG+yEqLq6/z2+F
IGWpUl7AYSudtxWQUGw45ET4/W4EOlTgTBmPK1i5KeCB0byjmRDcQHzDX5KzmRTfd04EdkFK2MMJ
rjd5ApghXTB1gA5+F0a0Hek7XtNw+0LMTQ1dTZA8yLxH+qq1T+co34hKcJ7O2opaHaMp5Bn3AmqE
KK/1sxL3CZ5Cn0Q+khwwuFchklYItbYJyoT9uHWeCMmmDlTRhLEArplztLy+MDtdKbR3b/Lr81eB
hkorJ9/Zc/Bcl2kLkbNWokpZbohmbkJ/5thvlIGP6An+eYiy9ZIhx5E/37pg2VFW5Jw7xSWlu5gm
SNvMm8ehkMJF91s+G2gh7ei/TpKLuaOOP8koStqPi/5TmdkOkRYZYj/P7uVSMDXkg8DPOfOextGj
Ktzd01b0BfA5zvf4sPh1yjJR3E6oZkbMKMrBjAjwzOBwcPMkzgYCmvZUAp6M8yUEjQr5tyoWcSoQ
Yf2D8pUVv79QUULyK68XWdrONq3AuBh8nPNPj39rznn1CSwgSmm+uSahYrA7misdrzRBz7FkmnWg
eJz90eYmjdH5UAda/bF4zB8/RV36V8GWAfqeG8K8woOq1R/8DlnXa4lPtVPCh9uKVlo+bH3ZD13N
ohro22CiJbtZ0didO3O1NVLLc6J8vN80AzLb6pktSjB9Sh/mS00oX6WKlFw8H+/UELAwr+1OXMtU
gq5upN7u61ZC/bcf/HHmyH6OW2qg391aTIq+JCrwq4zHysZz8BBuykUooCQAVKQRt2Q+87QUbjnO
rA5L9s6M+wvrln7OVMyMn2K7FJtAqhyFhrp+6SQXHX/1LbElN/HdAm8gS1fAx2TIQO22Ac+GXy11
hp7rnRHUsJ/gXGBxSdr5A7j2KjU4Lc5IwrNFjzB0v/xt1RHfQPnU0xKvz5+r74J25RpFXDgd0P5m
vR4v1QKbamwKjuEalnf0eOsdWFCepOi8pUQjtBEp/CUZ2w/cGgJrBAZX6AqEAH7DgivDww+7yJ21
SFnsONJZarAU7bTcBwY/LhsuPLervRvrfCuU/1FfqMTU15EXSJV1pqrgWDZBtP75yuYmckq2o9k9
JmKmMv/A4wgCEg7medtitYF8vzjklIz0bCxU3/5VqFWEnP+UrNij/FaEgQ4IGgRrDhT6U6FX7khG
mkgbb8BSVujci13iZougiS5J93ujSJBEsE0nAwd5e3rmx7+tRM4qIskLSiT0Rvl9I4MX14xTIdtS
rg+fABmyesls4xnTMdL8Yv3Fx3t1hffwqOBjrUKxGHSC4BiXOVpngKy0Q+oH/wgUKa4R2seVtw80
maAFzQ20Lq/ZMZj6APgw6+gqMM5cl+p5bOAvY//VhRa777/8m8zVPv3wPTjCU5tLRgMmkfYOz40F
m3tUQvWtd/JFcxDCoHPJ9eREA1xC7s2TfMAlsa9t9ZjBUdBV8zoahcc1Y9w3QQNA9hGt3XIkB/2L
dtUAaEWvZepcCdSL/Dto6OqDC8gVEbmFm8d3Id+rlExRTdPBpgo8AvNuevLAceg+9i1EaVO6+U7P
MkXHp9S3LZsUtUKIrsWhWbE7q+87NNGd0/GshQRqqVl9vkASgmwiJelg3iVCy/159Y8fjOJbZB+y
7Ms5MYowz+MZNUazO+wxwlg8+rbco4xXrf7BW2k2N6isVN6yVdez+98aMxeQGSGkJHftH8jft1Oz
BKtOqZZCKFpULDx1EFw/ruXnYhMTdfZ8rC6aZ21fgw0xYe+RgFIbs0NjV8zP0/k3AZjSHjan89oA
iUUNvXWj8qGtJ7EewQ5SeL6qvyQJSZ+jl6SKL7VGnSkPysRvhp5eSsieCqfK99c1hbkEiYbmV9/l
Bj9u2LzsZapD1ci0/cZ+IFZg5g5M7q/VUJQvGcpr8GAxokiSs2oKo9q6f7tZGAqZbVyp1TuvZu0l
gYkWB8jvcOTnzi1EL9qBtJvyZ51GjOZmSvu1dKXdv3IyQr0itUDvJHbVYlAXNF8evRMq6p2lrDMU
tIVs2cevgBkSbUB84Ks+j0fnPtbkChKCnixRHm0P7kl8neAp21hvkFC4C40EUA3XevVjSHt/eD4y
v3LT3nntrCDlq+9gAM0VY2h7VRPs9xzmZzXxB3oe6orYpjykVXc+8l1Lu2Vy/mY/rrG8vq+ZUqeP
RPmcH2l5iuwifSxKhzyHVnnq56KlVHZ9er0Ktc4Gyzj3skFdQEDdwJJao+1UOOADr5CJW3vfeMmY
lZkRupHziemqnuSkNp1UTfpOirMSAXHMmBdNB7tr9llm29DUIwgRsU7VVao19AtLKwOGbigt4wnV
Tb84pOL1+YIslXT/86yQ9MVc1hjuSFb70QKEI7kiWNAZB7w1CGskd+bRpIS9HM4hEi3JvYs51sjD
4sSZ9GMSHeddv63GTqNxKY6C0KgkNBU52oJJbffC6ADxwqkTPr5IWBirvnIeNjBdauPu6yvtp7Vx
bXm7CJGAAW0BsXCqSyiv6+t5KgD9FPyUn27hnC8nmRkI+uPneAODVitimkQNZQed5uZrfo0leU0K
RxGUy1kP89y9q6lDmbCq5pfQ7wEgWDPvkZxinQkI9RbiSxpwXXFGXpY1xY91Y5LGLrWQZzmhpJ+y
Ndz78MyyhuC2PMui299kJr7hjPuZvT59IqTzAn8sDXEydGnN6NJXz8O3wBJ1oYlrvRX1XEJOl29+
83eUy0fsQezLLU/AjS32VitqH6PAfRO0CMjTWZKqtSBba1RWiULJ4RFOPlOFr1U5y4B5/VaMATCq
oa+nmmkuBI4xJmLxR3FgejWwras8QZmPppTtR1mYjuBq00d8FJ8cFW528Ji5f5XmC//o6qvvomMZ
iUqFxgIO90q6Riv+QAAFc7xEI8vBnQydR2mNh8rewP4lfxyuaDJrR/Oz8EWrSmGNpmbtaE4OYAc8
wjFmRuxYX0LWCLf+v+gV2Gro2y1TALW7xc0boHL2ckVRs+FuxCu3IPQ4rITPRAjOVpzikn32FEKI
OYcUE0O1zOayJxPpRQsdLiaTO6PSFIFs6kqbAZy3qzSSSaokp8bef2vM96DGf1387oDeCzdbTmo7
pyfrBThyDI4wb4poSzOXpfJJJJjJfIZDeYJf8MjJl6Gq2nHP0BxX8PnI1h6o5qqcJ8dUXvgn0lEH
0amPgDSA3axWeScEO1vkiA4Hm1kggJlcSLPvKS4VDUltKj/BMiRUyYUlBZ2TUnUVEtKlwPMd43yb
5Mc07mscTdI7QNzhwnuxpEOyuIolhEhzuiryQSZ8Qri0+w6N6IqM+A6KWbz68uUmDjQ2JRljpxBw
fdHVdzXlJM/gpRnZIYzcU5O2Z8I5AgxB1Ru+LUyF+XbE8Dg2u/ng9SwhN5QCuQ2+/2+DMgnS3mKm
fyAn91CGuIAaHIqDa8Kts3iAY3CJNj3GJ4CWbhkOBptw7kwHLI8Nb4AKTqzT+2GnzpnuaPoMTrpn
5Jb5CwUBi60Kmz2+aMTeNqG8LBtPiDiWjDmzeO75Y9qbwBMxHSimSP3M/C0g62xhuTPWFKou3LsB
i036Rc9KPzyAtcIE2fAFyhbi9cRELMewQW30JeHuMuxKCc4B8d2WIC/luXJt3eu26PR7hkv9LfZp
8qIiMAeMvI/PiwWEoG4qb/dYxLUugyvRRtKb/MvZM9bKhm/H5W2rmcSrqc1sXRpuZ17zHFnhbtoT
BrspSj+XN8VgYZhrRomkQmPs656xgkY5BsY/zRhlcXpt4eQHOATVuPk0eYsH+A2jb7gELqXAYX7L
u41fagg7GMY7+2gr4IETIBGU85ieUGiX5vPQm9DWJ7d46agSUrR3zkmhkLN5a603fxRzgw73ER1X
xh/tszSi6LH2SLalT70N4RIthJIehy7ek9rUNdLWTT3Quo/z+2snm5Q5Ne0D253N5WaPf0D3IvE+
KY0Cemqv7gdzsUBD0cF3SUW4LWf31Ux7O/Ov/KF1xSw3KVi00bldtAIlA0WeLpZKB5MVL06u7UaJ
ZZ6q/emEVq3lWuS4dHJ2oeu13zlxJrZFeajouuWY+nKN2LfxZ3hF18S26CeykzCHFl0ELwIhRi2a
Kg9PXVXRea6954itfOLjGxkfJ5tIDuaIVa3PQpbnRvQbqSweljiLraaUVNsXZVpagBpmXrsAgNkX
nPmjpPv9fsjgK5HmBG/IH2HoGtyyaMY0oSkm7DrqYjWdvN5dSSYK6BASR2npO+s+tFtthhe2wwJC
wQQdXe/bWTi9VxxSK5cakWgLBhe3G1VQ5iDPG2EzHD/aDABonG43GtfCU6XEfqqyTRnAericDeHX
r3cCsWJPimnlQGVEivbGN1Lvrfxn9WhkvnF4hwA09qWFmQ2mCbizElFG+eAdA6qC8rgRYmKQrFVM
5WUJUuzIOg6i+v++cANR9hMbn/EpmqptrpRo4UKjA4nG0h6YyfOERcNlqzAZ9v+V7UfSeLtG7WRV
EDRALt24U13fqvkSjXyhLVeSNlJCUj8Hn7usPg/ZAnnB2gv9CU4mEQ9voaElWzfqalMdmbkbzjOk
OIaF57pt4l3u64MRqV217MPRaVAdMupjnglIEgmtqJoXaJQDj5qeHcEN32CKZibfMISr/ccKDdn+
uWAD4Ba090Ek5ra0FuvWoEX5NgjyFcU5EAyTGCmFbmAAonBWFbD9z88B5bcWFFn8olQt+vO4uiPP
8KBaiUePGOVzbP1GG4B7Hqvhvs0QgBbC4NGCPwO1hz7d3Z+Bpf8YSk3szAjvIwyRsvAouI4ijvCA
rxbqbMEn7t2jkrR+YlGu9i8FnVdTjS6X46TDFOd+14N24ciPRamiYBW3qbrNPmE+ZAR2zjivAC8K
+08SotuMbfn6eaGk+BdRXuVZPER0G/HsWLF7gRfPCDHvxl2/Am+Jji3loWFLI4g9Z3Owir2gWeas
xhSXJw6mEWwWjN/A0zQhI/cTa846YdbcMfzK26ch6/YtEgD5qWY8TN6H8JJJfdNUOU1XKLgCXvyL
bhYkVcBnmN93ZlmfsfPVyNHzkLXmWr+3tCekQnzrv62xRPiUi5uXmmpzElbxqGmTPqoj57yJ1O+7
jYA9Iv83E993nPhjm/IEVUtAcAt2u7uvebvqP0MoKYzKMkGJYzzcqp/1u22dfJn1ViXAjdScCjMm
btVZBcHBjwZyG+DVVoVY8/f/XC8EZVYdttn8Un7zHEzu6+O0wkHpm/NggMol8RaMAbHzQ1rDr4fd
xJh+HCZQk4moc+Vv2Ct1ENEh3csMcAhCQrRDbG9pgnDhQdeCbUC8ttna9nzZConSOdj72TxMTcBS
KMJ+XCjUTb+sOPtxY7ARPkXqhlkAXuAgcVlUFh5YKfp5IMRBF2DTPtbC09DyBJwMyL2yRedQRyMM
y02HASVx8U8ZVQJzhRi6ap8SLyjCO4PlDW9CyxGbUlaNY/smnZgm8+axtT2uf7DEy/vkx7dJ12RL
hAmOl/otdg3Y6m+SJQWNvdiBnUBba1wbde7qRA4XHnOlxv1ufl3ap/+YSacNxmUWxBzf65t7zHme
hm819zm0ntuAQ6MN+iieMtEQabBb5n4xcruXfNJDyCGD5SEoFQLjb4+y6FsPvaGpp3B2etSF6uta
3wHZIP9B6Kx7SDgt+g5sf3Ap8Ga1AdY1W83+X3oZOB2MZPG85PeOeu6PVs/QCzVyUTytMRnL5UIN
e+HU4l8VXXQ+qvOnqgGnCr6usF48o87TyAU+PNZTvuT+jx6rYeCu+NmIWJ83UpKA369aI4WvJ0Qo
wy5R7cu/znINVSkDVHVwZ/3FMdT+LCJglKD30HUdnL1JSJXI70E6fWBiZ9WFkCPOBDtGZr5ygJpZ
XwrgSEdmRuSbWwdfubWFD9k80xSmMIwNvku5eGcIviKpdvIBkLCfgtbsJeffxwwbx+ftG6bjy508
YhbfakIaCjzM6m3YVSu3uzg7HMrkvUGaWMV6jxuaS5fZshete+9v/NIjfqvpeBpCDVXG4ibD8357
09Wduv6wXIswH3qLPFaLGA9u12kdhCXhYVwu2f38qu780LDLzMW7gdJFtPza+3SPV0YCasLpliHA
j1WKtvEdcN5LgOQr+NXBE/nRGC78mZxCq0MgVwJ9BW17BH/P/Q9wiTqySBdRRRc5qY0lcl1IKF6d
4JXmC0szI+pS/XHiEa039WQIwtnno39mHEEUq2xOZnn+mzQoCATrwWCxBX4aEaKUS+alii0nr0FE
f+Zvj5fxdn9E2PvGSyvqtXuFhoW6UOlylvnUZzk1D7pxykCm3Ez+3sMZbHiiWBvfPyCBmbUG4ycS
hE5AM4XJ/tz3sN+e7tehOCWE16+XFwV8e4ZvYdrQgI0usMFdKCNSUPAGIuFTVEAgTlGH0R8eLY4A
FLbd4NXBXVk12L1aCnYmnanbuAHKVlIt8AUcmhsfWTXZwh5Fwsya9GDpISROkGug0tyc1wmo08Mj
57KT1PxuQgxE/4miYSNbUQaBXXNeAyMYeK2h/HuBXb/oF+72wLMVhvJUjfN6YaYvor575qyeQjJq
CdIctjH7ej/2BLPjtgfl3Ho+bMMwudAcM1awgojKKQb/0rLAGkZLZzfKtonVeGUK7gtSLyBy6WGy
Kj7tnPczPWvgxrJygvCkquA1qaqHt1FwYt9bQS9jaRYo1C8dJcbGfUUF04nObGFAZfYLY+hmuuBd
cgm5Bz6upntHV4rJeKoL/GgepQw0zA/7s+wH1JZSebM4yYq74CnrPHB3ku1GE5cs1QjKxOELH4St
dz3I2Um6PfttdjZQm4YmcUHB2A9tltKYPGbwtwDI1kb26vBqffO5KqP/SEfK5GqF3xu18z6WKmQo
Kg7fUPJmmohK63jyU46I8fMWDro2BAQEqnEsImigw5v9Nqle8K/rJjkoqCSeT/Nn3YUe2YNfa+z+
V1M7KkZwYiS1U013T1ohf/1PoI2F2TP6M0ql/zNrrvyl8bviIMlHH6meliNAzc9jEsswVto7fx7t
Bt/97Toaw5hm9UpUlkH/kqeOolGsaUbSlsx72+/D0ErWtFzi/qraxYGhjUyfPk+SqctubrCHNvA0
j+CJsJYCFK5a33RuYkS7Ywj7Hpi17jxegT0DWDmS3xD5xuEYaUBxpVMkIA+xewbIw0yZudXw5Q8X
yBcpy5kE7gTb3e3gYURuY72QVyttBWkAaPh6bK5BCdgnfy8VmLJFob9w8RygbfNPvdtX2A/jVfMy
Fc7GmgKTj6OUe5I+criBH7G+wa1o9BqhpsscOPzD67L04165TQ2dOdiLIC6ka8c6M/ymrylmzOgP
rGNI8gp1yO+9IE0JXRkat5iQd6gU3s/7Uix8WgniiXn835dMFkMkYWsIbW3JcJ8Lr8TS4Ymi+isc
erW0tjpPfb011tOhDKF7g9Ik7gOY/Ak1K/06FaYLjhcdx5wQAMPlGgsLLSYKk4k2WcutJks38/Mn
scR/aFZhPmfdf3tzSCQ3nEwk0E/COEF0gu89zMv/Y2aND0y5qTmB3MbtdsSYj/ydImt1CsiPMrQa
7mCzwilxAiwpyyjVhm89Es4cFYyaJBjHYPVMypFPCo6SnJ9LOrY1N89Xv8sP1s/0Pg9M/BmYtB11
VbhAP9dWrB44EJiDjnUoRfTv4h3dAOuSlszJ96xrthuqo5dV6hyx9xxtouG9zcP+gNrmSmi5KcIC
fY5ipEfjZyCZGeH+Au2TAynnCnqG0cQYNB3FpRp/oada/uiYkOIpwWO/pV7IMNc4tMgGpI/mJ5Vl
c3kiRDXLDIe21SPtvXTUNJw3k3meTvcXGTTzG9bFADgIRoAY8pVEBb7oEtOwWXaXAK/+V6NEZLii
SvTWI2Z5fFq7Cl9JkvZKdJ87QsXT2wv4TGSHzIULQe98z+XqILeL+ZeVHaFX1k9Qx9cgQrodlAUL
3vY6L6Z77qYAbsJfBVUuQCRBqJohkn3vfxt+ZKe9Ffu3cEq2gRumTCFfNDBUuZCabtDv9qt/ADI+
5dvyZ+NLzqze749/aXKPNwueBbXfwF0yqzR9BbUPksBzvmACY9ut3597BcOlHgumQ1yxBvS8f1Q0
TH42i/bGgjxmp7g3Pvp2rSd1fSrz0EzabqV43k+YTshZol5XWiGnv5Hd7J0Q6rx1MmgNStk/RWAQ
yNbheh8k9rfuts7yW3HfUxqXymMyupJUgxuTkIhxhs9nJMJKWWe8F+GX4ZSHUEeGCga5pmGYYqkM
clXjBT0Kv4+7cnQWXOk8ewDskoiVMV9wvo0MR0yxaCk1HYXxC2TnugaD+cmtMqrMDWxYvORR4SwX
syD5Vk2C97UAJQ2kZeDhlc/tSybko0s1f1+07xzmOjQje6POB1IWZkjyoin7GhmyUCvuhq0bU+7W
iWovQUCmckoOXydFu8y7Cdarr/ZddgY4uFL47NEz7D28Ihedk5zAdTQrqCNzRn4oOFceuDRpfVnZ
xGoO8wiiZ5I8yRaiL0kIU0aB9wXl5i/EMCPefF4Y+SLHBQjD3gxzsZhW5vdqL6Q/Uw6b2J5pdLfe
pXy5BYiPMGBKWOrAvckhGGRRi7Is48S3ZtsNCAWR1RgPDDpV5i7csb0voSWhEm0XGpwThmqWPXQ8
C6RQiBxL2HKI+gJxWpUuQ68EYyxqiNskJEQYmaGquFaxuw4HGwiXgfOQrgnUtZLNtjnUC7Bk72oa
kembPtRZBm2ZpBsUdQ4fIHvRDiNoGGOKrPCMctWQeZs8yi2oRrJlNSRTa+dcWljGxpPuDO8eTMZ0
ER0sFqrCl7AZxpgOeFuzTaeHHeOVYrfINrdbeQutWigsW04WjALtEW7IB2vWoGVQ1eSwpraqGnO1
DuFjK+QmCCruqUAvL/rLArE3VdCxvW2fwsJYZANtouej4TpNQKlg3iINSVP1EvFagxGjWCXMWqZ+
xKeE08YdWLnBcsvBhRGYy0i8ei0KdfcEDiKUVp2AiIsGX0L31CWuCphDJnWHbH07m5sZav5kfJfv
sL2t8WO+2Uu2sS/mMdAqUBsY34bLhQFIJD77PC0QgNWxHE/SE/qap9fHc0EmqFoiXUnS1Ep28edC
bHxeyObINjvm0p2YltwlgAdE8QKJI56rvLNeMTJowduSyOxzf3dGiLCAMAs33d0OfxEs1/gY6kPQ
t+vUBLCvuPoudqXbBWunm4MBNPnK831NV79w7ZKyVYEdROgs+Vo1DPfk3Rt1Ok99iLMhYh3u7jGn
IGlSyTfmiXBYAiWqNC4rs/TCQpc3OiL4cX+ftoegFGjE1OT0oTNlvyNoekeDVEd26rZgv5xJKdP+
R8WJ1gBwy0JBpPSLX64kqKGpgt7SXN6UE8IUsVm9NYxtfUzX52pHkM/Jap7PwTgBBTQYLNoe0IBP
xCp4W/j/YRlMAUOnxRXQAicKEtOa/CfdrmrYOQpwoutVw0ffB4WU7IVAO3JGUcWGEczVIsCRCC8s
B/PuXFRbQY7aqYez7ei154sQ7TcRAXsSzO6QtP2QsWZUuc/PJjOXUIyPnIhmLaRrLJ3SUyGdXsjz
OCJrr39XCIGe8sxpQuhmksPHJxkUUuK7IWzrKQtPxIpuy8z/OhNldDaY6Bfq11YJNveNrrfqVrtR
ESgHEkweRIFa4Rt0gFo58mil2bQuF671Qpnss5izAO+VzHEZAEDnZ4463fT6pt7UrRgdkVntz5Ww
YtkVzfS5M0BzbqSUvDg4UaOApDN/XzoBK5hSltv6GPC349P2MMmFrysj3dPnFdAVV0P70OuTYWTw
cTwO64033SyrAMEPH1d859sXc3edtdIuexVybzRWCGBVE2RLCB/7SwmhoVOPfGnrur94cT2GQuUQ
iklIeG/+YRPIC7twzeFcrOw8Q9F7cn/eXtw0mNKOLb/hK22IVyir+iZ8RUxYNENP1Sr+XEEKMklV
P/tXOFuZ+5S2/GUSXuWg+wFnyPc6mI0pz118Jbm88OA/duitWungxPBV9CeGoA/slKL30c0qELml
jgy3f6wccDZgGwdR9EHOdZsADXF0T5FC2P1zdZEDjqqITtcoZ3JGl22k9OqE1wznH9/qJUH1Hv2Q
9Gq6ksDVeldCVDbSTXBxc4EbXdpLOqHJdLwTXxu3AgUOHKi4LKqLkJyofcXd9ilkv1tVxNMZhl6C
TCZWI9fVuYfD1DBDmCwkVQfRu2tOATnndO5NRoO9G0M4K0KLjQ43pj3sifyynvKYqZkKE7QFlnW1
LBfQqVHoSqnVE7Ah/Q2/LNkMZ4ebs1QwfgGxCpR3bENgfq/zDWEik0OFJI+4jnSzPKE1WD2g3M8y
Ao/Bsd0GiGL4RuVSTyY37EhCBfsB2+W/BHwx3FXhtwGKz0kUrU4ZAXnhuE+7oBfrnhE3vnu6ZZX9
0PjflbCBLYL0mIt8Pg+TZ1czgNW8Xnc6fIirrMAOaA09GfOEZ0mbJW6jmRh1mhuKqHGM8QIpOgFn
YBjCa5VRNUJIJXoPmPRtMuJ5SQyU5oL5zNU9beA0gleNyYfH4GnsKhpOa6wl/VoqjRnCBxQuDtSw
cjUQiXShnZp8L91Jbg2FQ56+IUnmRLCS+siOOkvgP2SZQmYUMtX7nv6AIvOeKAflA3k5IP5S3Gv4
hO6t6xxZCUfOx2M30UgFuCQUff2hwJxt4A5+ROCNyEbal0/ppfgBE3a7ws7c4ad2YQze+Nw8xhaa
zbT0PQKro6H35YcAHlEZNVaqmRD9foZvqa2mtRqBLVhRnzvS7oMTv/6Fuiu8dFV2jUMRu3uxQbv0
NlM4n58igJ2OwQyHUZ2R+1T+we9hsjrz96gwFteLXefn/UH2/LObvobzgmYy+gHg9pKI+4AhtxcI
Aexm85KbOPf761WWz4Q9GlIZLwRM84+mRWKBEbNGSdVlDtKKWZxCP95xJkIsGiwSmMAbTxnjz1+M
d/j7J1G/w+icThIjmTUfS8yBWQKnRh0MryGkS5t5/LDkr7kKumFCYUBTOLumeXHkJysgig4pVsJj
p8fHIrRr37r8PQh0BGCCIM3qZLTWtwjM/TEfMyuZtXVJc2PTZjU1wbR0rUNgd95tSx8AYXoR0wSr
3lnE7EnjmWvQA13yqR164UBx/G2RcRv/1g1oyn7YhBsoZKKeZ8ELfktsO++Fo/RVuCzQz5mn4nAk
NxbSwJsg7yzj+aQbmPnNvYAOCbEbUEGJ8+tbKsxhE0LD6k8xz7hTgZ5OzJw+THndahutkT7muqOd
QOnL/UDaf3Y4RfYcS1DfgK5GrMTGMIdJiDoV5wWe342IZ+5N98NNPIH0Xe54ynAyLk9vYY8fgaXv
h1FcNJj5AzJp1jQo0O8CqoJWRbk8FGorF19fCmKzKkrmQAs9gZ7o0NpPjm05M9P1ycI2V8LxQrh+
0FBZ9w+dTxuQKpUmUyU6criwJhwhA3nVTZ2v4a+TM5RDn+ma+qDPKK3tuk4+2qN3jj44XEUI2G3G
chMuP43Xh2GY1Pyk4Xt1suOBffmhCAfjSec5tEkHv0GZueRk4kwzvJNB5Bqwo2X4Nltyi+UicImH
zXXwMax65PKRs6nILKYjuI5XRM3qIxxF5E8zOKh4D8bZLwFSTNcjOHDn/EvHZzQqoIk95phrmA6q
egnVk/FjTmLvVU9BA4vIKW6EzpLz/s1/t5LyNDvKAQEC05/7CVk2BtCAAqaGcA1EDYrhWmPfkvsR
r1QpH1PZc7ar583JnjqiQ57VHg17hOjURJr9NdeZbOn6IiSOy1IPveQ4HWz4Ch0xXr6s3LDEQybK
Wyj0jWYgk15PADX2UL6T75H7kfI/HMXazgvw7kLxMOPtgPFcBTTXvWkuRGScT7SkcQ8hiNDnJ5wj
mtQ55wc7PGsNQtPnujqzNtS5ywCGt+x3a80KrToKzi58QpZJIwgZXdPKdIAIXYs4B5Mr1aSVpoVk
wDVLHIiv9iiJlJTZ2Krwb7Pi2FB5KMD2bY/wH9Ewy//fKefahyK8B5WjSJzo6EKCm6FCBTDIz/W6
Yuln9oDjm1M0k76yKNnKXv+pLzXx7mktwtxLCbcsRfbKGN0a9AKCXAxuEp6lvr+qat/MTMnuYNLm
v2wGUIlDowqTFnb2bT1R2/bN3fG/xO4bIaKAcJYK278HRlwTlUjnsl1nSr7ZCF10bb4E3vqnboEq
Cjrl0Bjaw552fy/Uq2VY8u5oNclVgh1JsLg+WmfFyMgInBchOq4F7YYQYKNNEMli4nN9cREevuTz
STHJswqJZQs8GiTvF8lobgnQvPU5ZIXbg7sqtN1niqxgeTvGJAPsexHZtl/m7Z0+gOs5uDmZ8zu+
4elRwg+KSKQmacwkDZ/9caNS13ZvaW0J+3aJlD3qNCRjnG4MdcHuL3Ovq6EvCpao0l68dyM+pAwH
NKDePmVs33i5pyS3RzXsXU3+/v3mYV8wWf/cJz8YAVHPphxxVN6MhLLNfnANuB3IibXiBzjen+wi
7LuiekKYMqLMDL7DBR0UnUCCKoDGdXokPATlAjUACFAc5W/YaHhkiih9YTgf7WRuN7WFARIS13l6
CYIuYteLXkTP5V4TgdnLNXnFQHFRYdF3eQnDWuev3qmuOYhgPVVU4XCpH2X/UizSc9tYct5KgwqI
ASb2dSsNHcMpEsVQdSA5dAWfZVSS9pt8ahzTreapkVk0uYl8sScwScIki7mDR0a02LED6zuE+LTa
bfY88LJL8wJwvvfc/1mD3nGKAYjkue22QIQHvdLWv+emXpVRVmGjgC+Ek9G8QluEV8Oq4ZqcA10g
YLKjh/KZOL6Tc7gXWoKOzayMIDBwFbmb9kx+dsJ6786Qn6rjpkB1WvjC6SPrPfE011BUO2UfZXoK
eh1zAdIlhVy3rbqxPt3ZwMlykl/nFwzaPX4lb9WJDrHMWEQWEnsq9ioJj/dSauQTkznBc+8XMW5b
sC1mbHBJqtoXOv9QDHbGq0LWek6BgpQajToWqikWkWrCelVpqsjiq56MNimF7+3h68zRSHaKy5zS
hKn3XjjUYHLgndPvjUDqf1nAf78kpkPbAzPPi3GHTwQg3bP5QFAFkLMI+50RmcjFmOP1rpxlZCnn
f+iiUMP97ZusohMelI9XTPqQPfFyKfihq9Xfql2UqLBve4UY4wGO5G9R5ng4E5F4B8EfKnqCcWwT
282cbNeUcG7mReZkB21j+3wQ8/mMtIo2f3v71f13ey6TUo+y2gNHPhHDRg/TJF4a9803DuhzBz6U
vo4FvFCyqVA9Q3RjPgAPnbkrs9nLwjPDJTclYOxUVoP07ciM9Htm5dm0F6rNRgPJtwymZo/IJ0fs
ywhd2IRjaWavAYLRV29KpvYzM6nCnn44UBmFWGZu88KX2bm7bibKpTErk5sYbsUGEtsDqJ/hgxuJ
Kd+QhHruC9SuGRjP++lUPrFcFKH2+eiESwc3qcYanAoXOs/Z8Y8E732GLp1JL27bH6sakYxZI8+Q
feANt8oHe3evpxn92Coaq9Sbbrh9grPBrzzAOFXoCI2JCYBYKZYyQeaVxXfaHJtyMeC0l26EmlOm
e8it65XwDd6e179CuZO8tdx3SYnc6287zk8aL+RGWQ+r4HxE49FeeVMeQEqlbK8OKBKIRb/M5k0d
eGw0gQhkPK7d7DcFHkKb13qxc4+2lIRdWjwklxXE+S70WmowgFEq54JZz20B4TqL0guSqTFw9qd6
eDpqKS/ZcZ23vvCKQ/xjBUbd/aoNaP3/Sz6Xx6FGA1gTHq5F09kQCA5izDR2yVeMvOPVSiS8jWDb
hOL/2m8xG5nfFIeyv2eEA2EXiai6g1EE7qTvvq5tVvaJkQAakOutaOFNbt691XtBHAsuSIN/wxVS
jDzh5L7pRigV5fWt6PCdugcIARYGPIe+upCRWGJrzvoIpupuEnxDcigvBNsO/kiBsZs9X4ulNC2W
9a79ady4MEBBXLIU9cBu+kgONvJ30jkx41PPHhyvP+raZUmAA2mAnvZvjtCzIDEQO0XzgPqCwdrn
+4VtQs0pRymvdvYbEIxaqkPjWMfy/h5QkH8xFZVl25fpCAptMVwxRnYvMzx+8S3hlitFBfLq2ZIK
dXUkk5H8eRHxaw+zyWINiX5qQcw/ZhuEl887xpMP70gBp5VusxlzT1A4hyf9coXqUKB5dlTEHKn/
kCT9dFdALc8ppAWnjT+e0EwsN0Hax0g0SJW1iaBY9M2mCP1Uy2MZR5nMnqRlFkxVO+OyRQZrZNpu
4VidRGM1aVpr2PpCSDfbRs6/P0IGpefHNjYmUvz0/ot9NtJUrX8vC/UuGK2BnKc5BfOlltaaxWUO
/X0sa38yMnLVMGFCgqt7xxZf/TkplSRXRKC7w4TQ2CSo81z6p1Lo9bj7RA9Me0bYJJSeLfDOfJPk
dgKqWElIdy5wzY3tkjhgun4ajfOiw6ERzsChUBJsf0I0HhqY3vczzqk2kCBk3kxJXhBrKNd93xly
YSd0Lr7TLXF3AfQB3mb1F1txw8XdJqsit1URpv3o18UD/iBGxa9DjEipD5diTxOEGVIhSlOAsB+D
Ot88E2NZgEau1+fQnDe1WMFyPbsXIl7Qk+bgbEDy32wYMYY3okMV2/Jj1/Xlj8VnctT+BflZZYsa
PiTbW0F7F2HYOLu3jt6jDhBcXWktmwz5p4uUZpVwmps48Y+ZxQwhSlQcOz+lBja+En9xxL5TJGqI
1v+hUAxtUHgdQuX7F+2TQeAj0zcW91d9pPihkfX4s8rkX9YLZ8FKBAhfY78Yx/VTuf5VoUWnk3NR
b0uleXu1UfIAJJpgJG9tYeFP4JQS30hsy0KxLbMrnFeY6KaNYp4lHBJmNaOfrXRt7/EYMswkjWwn
Ugys714ZnHIzcg6UY6BPMbYqbZYd66veXP8NG7c+h3e3HuWuGU4htb/Ry0JVTuA1ifmRYdN6Nc/V
akzlFGG2vHeNnd6C1jmxENsp0y3fNQ1Kf6V27Kh92Rt8cf+Wz4KIdCiDaVqcsGUWorZj02MVhRx+
gp5YTxjNh0561Cnxj0LFBomckV4nNdFpGhoskkUrD+oYjl3T88tefmzVCDmpEtk8nMmORkdN/zJS
/RM7bQewR8z57xIGh15vyBJLhKA2a0nLxzRSxOd/oekEUIVK4PzwuilzQCabYOO06zjodxpClJNz
idv2ePIIUy63QTQ2DKozcXwEOnxmoxPtC9ajXRzg31YteZiBUh1ZhwOEQ4HDbta+IWjjUT/zjT4e
e8kdYWKP5bwxxGG5j2Pa/Ct3yEtF+o2LosbMWUHgkNvIPi9bcMeuyPyzpoR367/0o2/oWZ4cA1iI
BkCWVG5Yg4YNBaOU0Wv44o4Hc1mvcut2JZo/PVXdFrRrzH6jj/u882H1MxPWOlbt3xY6/ZGsthzA
CIKuPRjqPSSHmYXF7LixSEWeKlq1E7f7oxWA5A88Qlomc9yCitRKUIWbjAk8wsdCGe2QC91Gj0li
06v7hWVVHKv59eubxtXABc/jpGiIZQOzZ/RVTHZv242D2ZUpt/W1Rv6mj1OjfMb5cW8kZ7QI+W56
iUbQvusAygoGQFiDmLBouCxLQYvCIRkTeRy+txMpJuzQYYzTUJ5f8LwndDzFtfwh
Mfo=
`protect end_protected
| gpl-3.0 | 1b2acdf76fa5ef0cfb5a19ccc4787d05 | 0.947545 | 1.856547 | false | false | false | false |
gregani/la16fw | test_clockmux.vhd | 1 | 3,220 | --
-- This file is part of the lafw16 project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_clockmux is
end test_clockmux;
architecture behavior of test_clockmux is
-- Component Declaration for the Unit Under Test (UUT)
component clockmux
port(
clk_ctl : in std_logic;
clk_sel : in std_logic_vector(1 downto 0);
clk_in : in std_logic_vector(3 downto 0);
clk_out : out std_logic
);
end component;
--Inputs
signal clk_ctl : std_logic := '0';
signal clk_sel : unsigned(1 downto 0) := (others => '0');
signal clk_in : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal clk_out : std_logic;
-- Clock period definitions
constant clk_ctl_period : time := 10 ns;
constant clk_in_0_period : time := 3 ns;
constant clk_in_1_period : time := 17 ns;
constant clk_in_2_period : time := 37 ns;
constant clk_in_3_period : time := 113 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: clockmux port map (
clk_ctl => clk_ctl,
clk_sel => std_logic_vector(clk_sel),
clk_in => clk_in,
clk_out => clk_out
);
-- Clock process definitions
clk_ctl_process :process
begin
clk_ctl <= '0';
wait for clk_ctl_period/2;
clk_ctl <= '1';
wait for clk_ctl_period/2;
end process;
clk_in_0_process :process
begin
clk_in(0) <= '0';
wait for clk_in_0_period/2;
clk_in(0) <= '1';
wait for clk_in_0_period/2;
end process;
clk_in_1_process :process
begin
clk_in(1) <= '0';
wait for clk_in_1_period/2;
clk_in(1) <= '1';
wait for clk_in_1_period/2;
end process;
clk_in_2_process :process
begin
clk_in(2) <= '0';
wait for clk_in_2_period/2;
clk_in(2) <= '1';
wait for clk_in_2_period/2;
end process;
clk_in_3_process :process
begin
clk_in(3) <= '0';
wait for clk_in_3_period/2;
clk_in(3) <= '1';
wait for clk_in_3_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
clk_sel <= to_unsigned(0, clk_sel'length);
wait for 1 us;
clk_sel <= to_unsigned(1, clk_sel'length);
wait for 1 us;
clk_sel <= to_unsigned(2, clk_sel'length);
wait for 1 us;
clk_sel <= to_unsigned(3, clk_sel'length);
wait for 1 us;
wait;
end process;
end;
| gpl-2.0 | 603448b5bd5a527442a4dedca7bab06f | 0.612112 | 3.269036 | false | false | false | false |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/bd/BD_PR_3/hdl/BD_PR_3.vhd | 1 | 353,093 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Aug 5 18:37:52 2017
--Host : knuff running 64-bit Debian GNU/Linux 9.0 (stretch)
--Command : generate_target BD_PR_3.bd
--Design : BD_PR_3
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1HAU9EB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1HAU9EB;
architecture STRUCTURE of m00_couplers_imp_1HAU9EB is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1LIOGCX is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1LIOGCX;
architecture STRUCTURE of m00_couplers_imp_1LIOGCX is
component BD_PR_3_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component BD_PR_3_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(2 downto 0) <= auto_pc_to_m00_couplers_ARID(2 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(2 downto 0) <= auto_pc_to_m00_couplers_AWID(2 downto 0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0);
M_AXI_wid(2 downto 0) <= auto_pc_to_m00_couplers_WID(2 downto 0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(2 downto 0) <= m00_couplers_to_auto_pc_BID(2 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rid(2 downto 0) <= m00_couplers_to_auto_pc_RID(2 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(2 downto 0) <= S_AXI_arid(2 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(2 downto 0) <= S_AXI_awid(2 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component BD_PR_3_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => auto_pc_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => auto_pc_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(2 downto 0) => auto_pc_to_m00_couplers_BID(2 downto 0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(2 downto 0) => auto_pc_to_m00_couplers_RID(2 downto 0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0),
m_axi_wid(2 downto 0) => auto_pc_to_m00_couplers_WID(2 downto 0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(2 downto 0) => m00_couplers_to_auto_pc_ARID(2 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(2 downto 0) => m00_couplers_to_auto_pc_AWID(2 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(2 downto 0) => m00_couplers_to_auto_pc_BID(2 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rid(2 downto 0) => m00_couplers_to_auto_pc_RID(2 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_JWNH3K is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_JWNH3K;
architecture STRUCTURE of m01_couplers_imp_JWNH3K is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_5L8CES is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_5L8CES;
architecture STRUCTURE of m02_couplers_imp_5L8CES is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_JQPSWF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_JQPSWF;
architecture STRUCTURE of s00_couplers_imp_JQPSWF is
component BD_PR_3_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component BD_PR_3_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component BD_PR_3_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_K3N03X is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_K3N03X;
architecture STRUCTURE of s00_couplers_imp_K3N03X is
component BD_PR_3_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component BD_PR_3_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component BD_PR_3_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1LNYXAM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1LNYXAM;
architecture STRUCTURE of s01_couplers_imp_1LNYXAM is
component BD_PR_3_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component BD_PR_3_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s01_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_WVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s01_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s01_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_awready <= s01_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID;
S_AXI_wready <= s01_couplers_to_auto_us_WREADY;
auto_us_to_s01_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s01_couplers_to_auto_us_BREADY <= S_AXI_bready;
s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component BD_PR_3_auto_us_1
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s01_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s01_couplers_AWVALID,
m_axi_bready => auto_us_to_s01_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s01_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s01_couplers_WLAST,
m_axi_wready => auto_us_to_s01_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s01_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1,
s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s01_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s01_couplers_to_auto_us_AWVALID,
s_axi_bready => s01_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s01_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s01_couplers_to_auto_us_WLAST,
s_axi_wready => s01_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s01_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_17DAXZE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s02_couplers_imp_17DAXZE;
architecture STRUCTURE of s02_couplers_imp_17DAXZE is
component BD_PR_3_auto_us_2 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component BD_PR_3_auto_us_2;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s02_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s02_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s02_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s02_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s02_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s02_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s02_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s02_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s02_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s02_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s02_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_us_RVALID;
auto_us_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s02_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s02_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s02_couplers_RVALID <= M_AXI_rvalid;
s02_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component BD_PR_3_auto_us_2
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s02_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s02_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s02_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s02_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s02_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s02_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s02_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s02_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s02_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s02_couplers_RLAST,
m_axi_rready => auto_us_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s02_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s02_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s02_couplers_to_auto_us_RLAST,
s_axi_rready => s02_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s03_couplers_imp_7QRBGP is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s03_couplers_imp_7QRBGP;
architecture STRUCTURE of s03_couplers_imp_7QRBGP is
component BD_PR_3_auto_us_3 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component BD_PR_3_auto_us_3;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s03_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s03_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s03_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s03_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s03_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s03_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s03_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s03_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s03_couplers_WVALID : STD_LOGIC;
signal s03_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s03_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s03_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s03_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s03_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s03_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s03_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s03_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s03_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s03_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s03_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s03_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s03_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s03_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s03_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s03_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s03_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s03_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s03_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s03_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s03_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_awready <= s03_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s03_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s03_couplers_to_auto_us_BVALID;
S_AXI_wready <= s03_couplers_to_auto_us_WREADY;
auto_us_to_s03_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s03_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s03_couplers_WREADY <= M_AXI_wready;
s03_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s03_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s03_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s03_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s03_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s03_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s03_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s03_couplers_to_auto_us_BREADY <= S_AXI_bready;
s03_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s03_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s03_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s03_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component BD_PR_3_auto_us_3
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s03_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s03_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s03_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s03_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s03_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s03_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s03_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s03_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s03_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s03_couplers_AWVALID,
m_axi_bready => auto_us_to_s03_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s03_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s03_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s03_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s03_couplers_WLAST,
m_axi_wready => auto_us_to_s03_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s03_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s03_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1,
s_axi_awaddr(31 downto 0) => s03_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s03_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s03_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s03_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s03_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s03_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s03_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s03_couplers_to_auto_us_AWVALID,
s_axi_bready => s03_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s03_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s03_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s03_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s03_couplers_to_auto_us_WLAST,
s_axi_wready => s03_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s03_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s03_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s04_couplers_imp_GI3P8I is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s04_couplers_imp_GI3P8I;
architecture STRUCTURE of s04_couplers_imp_GI3P8I is
component BD_PR_3_auto_us_4 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component BD_PR_3_auto_us_4;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s04_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s04_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s04_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s04_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s04_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s04_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s04_couplers_RVALID : STD_LOGIC;
signal s04_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s04_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s04_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s04_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s04_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s04_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s04_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s04_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s04_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s04_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s04_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s04_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s04_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s04_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s04_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s04_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s04_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s04_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s04_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s04_couplers_to_auto_us_RVALID;
auto_us_to_s04_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s04_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s04_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s04_couplers_RVALID <= M_AXI_rvalid;
s04_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s04_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s04_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s04_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s04_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s04_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s04_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s04_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component BD_PR_3_auto_us_4
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s04_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s04_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s04_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s04_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s04_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s04_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s04_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s04_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s04_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s04_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s04_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s04_couplers_RLAST,
m_axi_rready => auto_us_to_s04_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s04_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s04_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s04_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s04_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s04_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s04_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s04_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s04_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s04_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s04_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s04_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s04_couplers_to_auto_us_RLAST,
s_axi_rready => s04_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s04_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s04_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s05_couplers_imp_1GEI3EP is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s05_couplers_imp_1GEI3EP;
architecture STRUCTURE of s05_couplers_imp_1GEI3EP is
component BD_PR_3_auto_us_5 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component BD_PR_3_auto_us_5;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s05_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s05_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s05_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s05_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s05_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s05_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s05_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s05_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s05_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s05_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s05_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s05_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s05_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s05_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s05_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s05_couplers_WVALID : STD_LOGIC;
signal s05_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s05_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s05_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s05_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s05_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s05_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s05_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s05_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s05_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s05_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s05_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s05_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s05_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s05_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s05_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s05_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s05_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s05_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s05_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s05_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s05_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s05_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s05_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s05_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s05_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s05_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s05_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s05_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s05_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s05_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_awready <= s05_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s05_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s05_couplers_to_auto_us_BVALID;
S_AXI_wready <= s05_couplers_to_auto_us_WREADY;
auto_us_to_s05_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s05_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s05_couplers_WREADY <= M_AXI_wready;
s05_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s05_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s05_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s05_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s05_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s05_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s05_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s05_couplers_to_auto_us_BREADY <= S_AXI_bready;
s05_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s05_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s05_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s05_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component BD_PR_3_auto_us_5
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s05_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s05_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s05_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s05_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s05_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s05_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s05_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s05_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s05_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s05_couplers_AWVALID,
m_axi_bready => auto_us_to_s05_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s05_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s05_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s05_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s05_couplers_WLAST,
m_axi_wready => auto_us_to_s05_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s05_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s05_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1,
s_axi_awaddr(31 downto 0) => s05_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s05_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s05_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s05_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s05_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s05_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s05_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s05_couplers_to_auto_us_AWVALID,
s_axi_bready => s05_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s05_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s05_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s05_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s05_couplers_to_auto_us_WLAST,
s_axi_wready => s05_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s05_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s05_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BD_PR_3_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S03_ACLK : in STD_LOGIC;
S03_ARESETN : in STD_LOGIC;
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awready : out STD_LOGIC;
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_wvalid : in STD_LOGIC;
S04_ACLK : in STD_LOGIC;
S04_ARESETN : in STD_LOGIC;
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arready : out STD_LOGIC;
S04_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rvalid : out STD_LOGIC;
S05_ACLK : in STD_LOGIC;
S05_ARESETN : in STD_LOGIC;
S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S05_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awready : out STD_LOGIC;
S05_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awvalid : in STD_LOGIC;
S05_AXI_bready : in STD_LOGIC;
S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_bvalid : out STD_LOGIC;
S05_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S05_AXI_wlast : in STD_LOGIC;
S05_AXI_wready : out STD_LOGIC;
S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_wvalid : in STD_LOGIC
);
end BD_PR_3_axi_mem_intercon_0;
architecture STRUCTURE of BD_PR_3_axi_mem_intercon_0 is
component BD_PR_3_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 47 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 383 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 47 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 47 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 383 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component BD_PR_3_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC;
signal S02_ACLK_1 : STD_LOGIC;
signal S02_ARESETN_1 : STD_LOGIC;
signal S03_ACLK_1 : STD_LOGIC;
signal S03_ARESETN_1 : STD_LOGIC;
signal S04_ACLK_1 : STD_LOGIC;
signal S04_ARESETN_1 : STD_LOGIC;
signal S05_ACLK_1 : STD_LOGIC;
signal S05_ARESETN_1 : STD_LOGIC;
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s05_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s05_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s05_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s05_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 191 downto 128 );
signal s02_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s03_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s03_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s03_couplers_to_xbar_BREADY : STD_LOGIC;
signal s03_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 7 downto 6 );
signal s03_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s03_couplers_to_xbar_WLAST : STD_LOGIC;
signal s03_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_xbar_WVALID : STD_LOGIC;
signal s04_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s04_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s04_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 319 downto 256 );
signal s04_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_RREADY : STD_LOGIC;
signal s04_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 9 downto 8 );
signal s04_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal s05_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s05_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s05_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s05_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s05_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s05_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s05_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s05_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal s05_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s05_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s05_couplers_to_xbar_BREADY : STD_LOGIC;
signal s05_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 11 downto 10 );
signal s05_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal s05_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s05_couplers_to_xbar_WLAST : STD_LOGIC;
signal s05_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal s05_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s05_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 383 downto 64 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(2 downto 0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(2 downto 0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0);
M00_AXI_wid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(2 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1 <= S01_ARESETN;
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
S02_ACLK_1 <= S02_ACLK;
S02_ARESETN_1 <= S02_ARESETN;
S02_AXI_arready <= axi_mem_intercon_to_s02_couplers_ARREADY;
S02_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rlast <= axi_mem_intercon_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= axi_mem_intercon_to_s02_couplers_RVALID;
S03_ACLK_1 <= S03_ACLK;
S03_ARESETN_1 <= S03_ARESETN;
S03_AXI_awready <= axi_mem_intercon_to_s03_couplers_AWREADY;
S03_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0);
S03_AXI_bvalid <= axi_mem_intercon_to_s03_couplers_BVALID;
S03_AXI_wready <= axi_mem_intercon_to_s03_couplers_WREADY;
S04_ACLK_1 <= S04_ACLK;
S04_ARESETN_1 <= S04_ARESETN;
S04_AXI_arready <= axi_mem_intercon_to_s04_couplers_ARREADY;
S04_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0);
S04_AXI_rlast <= axi_mem_intercon_to_s04_couplers_RLAST;
S04_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0);
S04_AXI_rvalid <= axi_mem_intercon_to_s04_couplers_RVALID;
S05_ACLK_1 <= S05_ACLK;
S05_ARESETN_1 <= S05_ARESETN;
S05_AXI_awready <= axi_mem_intercon_to_s05_couplers_AWREADY;
S05_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s05_couplers_BRESP(1 downto 0);
S05_AXI_bvalid <= axi_mem_intercon_to_s05_couplers_BVALID;
S05_AXI_wready <= axi_mem_intercon_to_s05_couplers_WREADY;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net <= ARESETN;
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
axi_mem_intercon_to_s02_couplers_RREADY <= S02_AXI_rready;
axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0) <= S03_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0) <= S03_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0) <= S03_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0) <= S03_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0) <= S03_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0) <= S03_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWVALID <= S03_AXI_awvalid;
axi_mem_intercon_to_s03_couplers_BREADY <= S03_AXI_bready;
axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0) <= S03_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s03_couplers_WLAST <= S03_AXI_wlast;
axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0) <= S03_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s03_couplers_WVALID <= S03_AXI_wvalid;
axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0) <= S04_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0) <= S04_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0) <= S04_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0) <= S04_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0) <= S04_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0) <= S04_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARVALID <= S04_AXI_arvalid;
axi_mem_intercon_to_s04_couplers_RREADY <= S04_AXI_rready;
axi_mem_intercon_to_s05_couplers_AWADDR(31 downto 0) <= S05_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s05_couplers_AWBURST(1 downto 0) <= S05_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s05_couplers_AWCACHE(3 downto 0) <= S05_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s05_couplers_AWLEN(7 downto 0) <= S05_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s05_couplers_AWPROT(2 downto 0) <= S05_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s05_couplers_AWSIZE(2 downto 0) <= S05_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s05_couplers_AWVALID <= S05_AXI_awvalid;
axi_mem_intercon_to_s05_couplers_BREADY <= S05_AXI_bready;
axi_mem_intercon_to_s05_couplers_WDATA(31 downto 0) <= S05_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s05_couplers_WLAST <= S05_AXI_wlast;
axi_mem_intercon_to_s05_couplers_WSTRB(3 downto 0) <= S05_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s05_couplers_WVALID <= S05_AXI_wvalid;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1LIOGCX
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(2 downto 0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(2 downto 0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0),
M_AXI_wid(2 downto 0) => m00_couplers_to_axi_mem_intercon_WID(2 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN => axi_mem_intercon_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
S_AXI_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_K3N03X
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID
);
s01_couplers: entity work.s01_couplers_imp_1LNYXAM
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN => S01_ARESETN_1,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_17DAXZE
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s02_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s02_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s02_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s02_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arsize(2 downto 0) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s02_couplers_to_xbar_RDATA(191 downto 128),
M_AXI_rlast => s02_couplers_to_xbar_RLAST(2),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
S_ACLK => S02_ACLK_1,
S_ARESETN => S02_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s02_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s02_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s02_couplers_RVALID
);
s03_couplers: entity work.s03_couplers_imp_7QRBGP
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_awaddr(31 downto 0) => s03_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s03_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s03_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s03_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s03_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s03_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s03_couplers_to_xbar_AWREADY(3),
M_AXI_awsize(2 downto 0) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s03_couplers_to_xbar_AWVALID,
M_AXI_bready => s03_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s03_couplers_to_xbar_BRESP(7 downto 6),
M_AXI_bvalid => s03_couplers_to_xbar_BVALID(3),
M_AXI_wdata(63 downto 0) => s03_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s03_couplers_to_xbar_WLAST,
M_AXI_wready => s03_couplers_to_xbar_WREADY(3),
M_AXI_wstrb(7 downto 0) => s03_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s03_couplers_to_xbar_WVALID,
S_ACLK => S03_ACLK_1,
S_ARESETN => S03_ARESETN_1,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s03_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s03_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s03_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s03_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s03_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s03_couplers_WVALID
);
s04_couplers: entity work.s04_couplers_imp_GI3P8I
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s04_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s04_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s04_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s04_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s04_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s04_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s04_couplers_to_xbar_ARREADY(4),
M_AXI_arsize(2 downto 0) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s04_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s04_couplers_to_xbar_RDATA(319 downto 256),
M_AXI_rlast => s04_couplers_to_xbar_RLAST(4),
M_AXI_rready => s04_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s04_couplers_to_xbar_RRESP(9 downto 8),
M_AXI_rvalid => s04_couplers_to_xbar_RVALID(4),
S_ACLK => S04_ACLK_1,
S_ARESETN => S04_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s04_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s04_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s04_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s04_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s04_couplers_RVALID
);
s05_couplers: entity work.s05_couplers_imp_1GEI3EP
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_awaddr(31 downto 0) => s05_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s05_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s05_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s05_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s05_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s05_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s05_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s05_couplers_to_xbar_AWREADY(5),
M_AXI_awsize(2 downto 0) => s05_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s05_couplers_to_xbar_AWVALID,
M_AXI_bready => s05_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s05_couplers_to_xbar_BRESP(11 downto 10),
M_AXI_bvalid => s05_couplers_to_xbar_BVALID(5),
M_AXI_wdata(63 downto 0) => s05_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s05_couplers_to_xbar_WLAST,
M_AXI_wready => s05_couplers_to_xbar_WREADY(5),
M_AXI_wstrb(7 downto 0) => s05_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s05_couplers_to_xbar_WVALID,
S_ACLK => S05_ACLK_1,
S_ARESETN => S05_ARESETN_1,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s05_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s05_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s05_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s05_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s05_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s05_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s05_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s05_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s05_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s05_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s05_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s05_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s05_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s05_couplers_WVALID
);
xbar: component BD_PR_3_xbar_1
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net,
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(191 downto 160) => B"00000000000000000000000000000000",
s_axi_araddr(159 downto 128) => s04_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(127 downto 96) => B"00000000000000000000000000000000",
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(11 downto 10) => B"00",
s_axi_arburst(9 downto 8) => s04_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(7 downto 6) => B"00",
s_axi_arburst(5 downto 4) => s02_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(23 downto 20) => B"0000",
s_axi_arcache(19 downto 16) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(15 downto 12) => B"0000",
s_axi_arcache(11 downto 8) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(17 downto 0) => B"000000000000000000",
s_axi_arlen(47 downto 40) => B"00000000",
s_axi_arlen(39 downto 32) => s04_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(31 downto 24) => B"00000000",
s_axi_arlen(23 downto 16) => s02_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(5) => '0',
s_axi_arlock(4) => s04_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(3) => '0',
s_axi_arlock(2) => s02_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(1) => '0',
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(17 downto 15) => B"000",
s_axi_arprot(14 downto 12) => s04_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(11 downto 9) => B"000",
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(23 downto 20) => B"0000",
s_axi_arqos(19 downto 16) => s04_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(15 downto 12) => B"0000",
s_axi_arqos(11 downto 8) => s02_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(7 downto 4) => B"0000",
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(5) => NLW_xbar_s_axi_arready_UNCONNECTED(5),
s_axi_arready(4) => s04_couplers_to_xbar_ARREADY(4),
s_axi_arready(3) => NLW_xbar_s_axi_arready_UNCONNECTED(3),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(17 downto 15) => B"000",
s_axi_arsize(14 downto 12) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(11 downto 9) => B"000",
s_axi_arsize(8 downto 6) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(5) => '0',
s_axi_arvalid(4) => s04_couplers_to_xbar_ARVALID,
s_axi_arvalid(3) => '0',
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(191 downto 160) => s05_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(159 downto 128) => B"00000000000000000000000000000000",
s_axi_awaddr(127 downto 96) => s03_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(95 downto 64) => B"00000000000000000000000000000000",
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(11 downto 10) => s05_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(9 downto 8) => B"00",
s_axi_awburst(7 downto 6) => s03_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(5 downto 4) => B"00",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(23 downto 20) => s05_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(19 downto 16) => B"0000",
s_axi_awcache(15 downto 12) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(11 downto 8) => B"0000",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(17 downto 0) => B"000000000000000000",
s_axi_awlen(47 downto 40) => s05_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(39 downto 32) => B"00000000",
s_axi_awlen(31 downto 24) => s03_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(23 downto 16) => B"00000000",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(5) => s05_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(4) => '0',
s_axi_awlock(3) => s03_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(2) => '0',
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => '0',
s_axi_awprot(17 downto 15) => s05_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(14 downto 12) => B"000",
s_axi_awprot(11 downto 9) => s03_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(8 downto 6) => B"000",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(23 downto 20) => s05_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(19 downto 16) => B"0000",
s_axi_awqos(15 downto 12) => s03_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(11 downto 8) => B"0000",
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(5) => s05_couplers_to_xbar_AWREADY(5),
s_axi_awready(4) => NLW_xbar_s_axi_awready_UNCONNECTED(4),
s_axi_awready(3) => s03_couplers_to_xbar_AWREADY(3),
s_axi_awready(2) => NLW_xbar_s_axi_awready_UNCONNECTED(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(17 downto 15) => s05_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(14 downto 12) => B"000",
s_axi_awsize(11 downto 9) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(8 downto 6) => B"000",
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(5) => s05_couplers_to_xbar_AWVALID,
s_axi_awvalid(4) => '0',
s_axi_awvalid(3) => s03_couplers_to_xbar_AWVALID,
s_axi_awvalid(2) => '0',
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => '0',
s_axi_bid(17 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(17 downto 0),
s_axi_bready(5) => s05_couplers_to_xbar_BREADY,
s_axi_bready(4) => '0',
s_axi_bready(3) => s03_couplers_to_xbar_BREADY,
s_axi_bready(2) => '0',
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => '0',
s_axi_bresp(11 downto 10) => s05_couplers_to_xbar_BRESP(11 downto 10),
s_axi_bresp(9 downto 8) => NLW_xbar_s_axi_bresp_UNCONNECTED(9 downto 8),
s_axi_bresp(7 downto 6) => s03_couplers_to_xbar_BRESP(7 downto 6),
s_axi_bresp(5 downto 4) => NLW_xbar_s_axi_bresp_UNCONNECTED(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(5) => s05_couplers_to_xbar_BVALID(5),
s_axi_bvalid(4) => NLW_xbar_s_axi_bvalid_UNCONNECTED(4),
s_axi_bvalid(3) => s03_couplers_to_xbar_BVALID(3),
s_axi_bvalid(2) => NLW_xbar_s_axi_bvalid_UNCONNECTED(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(383 downto 320) => NLW_xbar_s_axi_rdata_UNCONNECTED(383 downto 320),
s_axi_rdata(319 downto 256) => s04_couplers_to_xbar_RDATA(319 downto 256),
s_axi_rdata(255 downto 192) => NLW_xbar_s_axi_rdata_UNCONNECTED(255 downto 192),
s_axi_rdata(191 downto 128) => s02_couplers_to_xbar_RDATA(191 downto 128),
s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64),
s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
s_axi_rid(17 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(17 downto 0),
s_axi_rlast(5) => NLW_xbar_s_axi_rlast_UNCONNECTED(5),
s_axi_rlast(4) => s04_couplers_to_xbar_RLAST(4),
s_axi_rlast(3) => NLW_xbar_s_axi_rlast_UNCONNECTED(3),
s_axi_rlast(2) => s02_couplers_to_xbar_RLAST(2),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(5) => '0',
s_axi_rready(4) => s04_couplers_to_xbar_RREADY,
s_axi_rready(3) => '0',
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(11 downto 10) => NLW_xbar_s_axi_rresp_UNCONNECTED(11 downto 10),
s_axi_rresp(9 downto 8) => s04_couplers_to_xbar_RRESP(9 downto 8),
s_axi_rresp(7 downto 6) => NLW_xbar_s_axi_rresp_UNCONNECTED(7 downto 6),
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(5) => NLW_xbar_s_axi_rvalid_UNCONNECTED(5),
s_axi_rvalid(4) => s04_couplers_to_xbar_RVALID(4),
s_axi_rvalid(3) => NLW_xbar_s_axi_rvalid_UNCONNECTED(3),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(383 downto 320) => s05_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(319 downto 256) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wdata(255 downto 192) => s03_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(191 downto 128) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wlast(5) => s05_couplers_to_xbar_WLAST,
s_axi_wlast(4) => '1',
s_axi_wlast(3) => s03_couplers_to_xbar_WLAST,
s_axi_wlast(2) => '1',
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => '1',
s_axi_wready(5) => s05_couplers_to_xbar_WREADY(5),
s_axi_wready(4) => NLW_xbar_s_axi_wready_UNCONNECTED(4),
s_axi_wready(3) => s03_couplers_to_xbar_WREADY(3),
s_axi_wready(2) => NLW_xbar_s_axi_wready_UNCONNECTED(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(47 downto 40) => s05_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(39 downto 32) => B"11111111",
s_axi_wstrb(31 downto 24) => s03_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(23 downto 16) => B"11111111",
s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(7 downto 0) => B"11111111",
s_axi_wvalid(5) => s05_couplers_to_xbar_WVALID,
s_axi_wvalid(4) => '0',
s_axi_wvalid(3) => s03_couplers_to_xbar_WVALID,
s_axi_wvalid(2) => '0',
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BD_PR_3_ps7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end BD_PR_3_ps7_0_axi_periph_0;
architecture STRUCTURE of BD_PR_3_ps7_0_axi_periph_0 is
component BD_PR_3_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end component BD_PR_3_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_ACLK_net : STD_LOGIC;
signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_ps7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_ps7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_ps7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_ps7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_ps7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_ps7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_ps7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_ps7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_ps7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_ps7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_ps7_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_ps7_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_ps7_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_ps7_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_ps7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_ps7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_ps7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_ps7_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
ps7_0_axi_periph_ACLK_net <= ACLK;
ps7_0_axi_periph_ARESETN_net <= ARESETN;
ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1HAU9EB
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m00_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_JWNH3K
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m01_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_5L8CES
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m02_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m02_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m02_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
s00_couplers: entity work.s00_couplers_imp_JQPSWF
port map (
M_ACLK => ps7_0_axi_periph_ACLK_net,
M_ARESETN => ps7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component BD_PR_3_xbar_0
port map (
aclk => ps7_0_axi_periph_ACLK_net,
aresetn => ps7_0_axi_periph_ARESETN_net,
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(11 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(11 downto 0),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Processing_System_imp_1I881SN is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
IRQ_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
IRQ_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
IRQ_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
IRQ_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
IRQ_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
IRQ_5 : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ARESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awready : out STD_LOGIC;
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_wvalid : in STD_LOGIC;
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arready : out STD_LOGIC;
S04_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rvalid : out STD_LOGIC;
S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S05_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awready : out STD_LOGIC;
S05_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awvalid : in STD_LOGIC;
S05_AXI_bready : in STD_LOGIC;
S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_bvalid : out STD_LOGIC;
S05_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S05_AXI_wlast : in STD_LOGIC;
S05_AXI_wready : out STD_LOGIC;
S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_wvalid : in STD_LOGIC
);
end Processing_System_imp_1I881SN;
architecture STRUCTURE of Processing_System_imp_1I881SN is
component BD_PR_3_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 5 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component BD_PR_3_processing_system7_0_0;
component BD_PR_3_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component BD_PR_3_rst_ps7_0_100M_0;
component BD_PR_3_IRQ_Concat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component BD_PR_3_IRQ_Concat_0;
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn1_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn1_ARREADY : STD_LOGIC;
signal Conn1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn1_ARVALID : STD_LOGIC;
signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_RLAST : STD_LOGIC;
signal Conn1_RREADY : STD_LOGIC;
signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_RVALID : STD_LOGIC;
signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn2_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_AWREADY : STD_LOGIC;
signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_AWVALID : STD_LOGIC;
signal Conn2_BREADY : STD_LOGIC;
signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_BVALID : STD_LOGIC;
signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_WLAST : STD_LOGIC;
signal Conn2_WREADY : STD_LOGIC;
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_WVALID : STD_LOGIC;
signal Conn3_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn3_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn3_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn3_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn3_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn3_ARREADY : STD_LOGIC;
signal Conn3_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn3_ARVALID : STD_LOGIC;
signal Conn3_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn3_RLAST : STD_LOGIC;
signal Conn3_RREADY : STD_LOGIC;
signal Conn3_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn3_RVALID : STD_LOGIC;
signal Conn4_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn4_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn4_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn4_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn4_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn4_AWREADY : STD_LOGIC;
signal Conn4_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn4_AWVALID : STD_LOGIC;
signal Conn4_BREADY : STD_LOGIC;
signal Conn4_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn4_BVALID : STD_LOGIC;
signal Conn4_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn4_WLAST : STD_LOGIC;
signal Conn4_WREADY : STD_LOGIC;
signal Conn4_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn4_WVALID : STD_LOGIC;
signal Conn5_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn5_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn5_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn5_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn5_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn5_ARREADY : STD_LOGIC;
signal Conn5_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn5_ARVALID : STD_LOGIC;
signal Conn5_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn5_RLAST : STD_LOGIC;
signal Conn5_RREADY : STD_LOGIC;
signal Conn5_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn5_RVALID : STD_LOGIC;
signal Conn6_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn6_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn6_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn6_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal Conn6_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn6_AWREADY : STD_LOGIC;
signal Conn6_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn6_AWVALID : STD_LOGIC;
signal Conn6_BREADY : STD_LOGIC;
signal Conn6_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn6_BVALID : STD_LOGIC;
signal Conn6_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn6_WLAST : STD_LOGIC;
signal Conn6_WREADY : STD_LOGIC;
signal Conn6_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn6_WVALID : STD_LOGIC;
signal IRQ_Concat_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_dma_0_mm2s_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_s2mm_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_mm2s_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_s2mm_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_2_mm2s_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_2_s2mm_introut : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Conn1_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
Conn1_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
Conn1_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
Conn1_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
Conn1_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
Conn1_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
Conn1_ARVALID <= S00_AXI_arvalid;
Conn1_RREADY <= S00_AXI_rready;
Conn2_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
Conn2_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
Conn2_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
Conn2_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
Conn2_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
Conn2_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
Conn2_AWVALID <= S01_AXI_awvalid;
Conn2_BREADY <= S01_AXI_bready;
Conn2_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
Conn2_WLAST <= S01_AXI_wlast;
Conn2_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
Conn2_WVALID <= S01_AXI_wvalid;
Conn3_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
Conn3_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
Conn3_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
Conn3_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
Conn3_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
Conn3_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
Conn3_ARVALID <= S02_AXI_arvalid;
Conn3_RREADY <= S02_AXI_rready;
Conn4_AWADDR(31 downto 0) <= S03_AXI_awaddr(31 downto 0);
Conn4_AWBURST(1 downto 0) <= S03_AXI_awburst(1 downto 0);
Conn4_AWCACHE(3 downto 0) <= S03_AXI_awcache(3 downto 0);
Conn4_AWLEN(7 downto 0) <= S03_AXI_awlen(7 downto 0);
Conn4_AWPROT(2 downto 0) <= S03_AXI_awprot(2 downto 0);
Conn4_AWSIZE(2 downto 0) <= S03_AXI_awsize(2 downto 0);
Conn4_AWVALID <= S03_AXI_awvalid;
Conn4_BREADY <= S03_AXI_bready;
Conn4_WDATA(31 downto 0) <= S03_AXI_wdata(31 downto 0);
Conn4_WLAST <= S03_AXI_wlast;
Conn4_WSTRB(3 downto 0) <= S03_AXI_wstrb(3 downto 0);
Conn4_WVALID <= S03_AXI_wvalid;
Conn5_ARADDR(31 downto 0) <= S04_AXI_araddr(31 downto 0);
Conn5_ARBURST(1 downto 0) <= S04_AXI_arburst(1 downto 0);
Conn5_ARCACHE(3 downto 0) <= S04_AXI_arcache(3 downto 0);
Conn5_ARLEN(7 downto 0) <= S04_AXI_arlen(7 downto 0);
Conn5_ARPROT(2 downto 0) <= S04_AXI_arprot(2 downto 0);
Conn5_ARSIZE(2 downto 0) <= S04_AXI_arsize(2 downto 0);
Conn5_ARVALID <= S04_AXI_arvalid;
Conn5_RREADY <= S04_AXI_rready;
Conn6_AWADDR(31 downto 0) <= S05_AXI_awaddr(31 downto 0);
Conn6_AWBURST(1 downto 0) <= S05_AXI_awburst(1 downto 0);
Conn6_AWCACHE(3 downto 0) <= S05_AXI_awcache(3 downto 0);
Conn6_AWLEN(7 downto 0) <= S05_AXI_awlen(7 downto 0);
Conn6_AWPROT(2 downto 0) <= S05_AXI_awprot(2 downto 0);
Conn6_AWSIZE(2 downto 0) <= S05_AXI_awsize(2 downto 0);
Conn6_AWVALID <= S05_AXI_awvalid;
Conn6_BREADY <= S05_AXI_bready;
Conn6_WDATA(31 downto 0) <= S05_AXI_wdata(31 downto 0);
Conn6_WLAST <= S05_AXI_wlast;
Conn6_WSTRB(3 downto 0) <= S05_AXI_wstrb(3 downto 0);
Conn6_WVALID <= S05_AXI_wvalid;
FCLK_CLK0 <= processing_system7_0_FCLK_CLK0;
M00_AXI_araddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= ps7_0_axi_periph_M00_AXI_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= ps7_0_axi_periph_M00_AXI_AWVALID(0);
M00_AXI_bready(0) <= ps7_0_axi_periph_M00_AXI_BREADY(0);
M00_AXI_rready(0) <= ps7_0_axi_periph_M00_AXI_RREADY(0);
M00_AXI_wdata(31 downto 0) <= ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= ps7_0_axi_periph_M00_AXI_WVALID(0);
M01_AXI_araddr(31 downto 0) <= ps7_0_axi_periph_M01_AXI_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= ps7_0_axi_periph_M01_AXI_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= ps7_0_axi_periph_M01_AXI_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= ps7_0_axi_periph_M01_AXI_AWVALID(0);
M01_AXI_bready(0) <= ps7_0_axi_periph_M01_AXI_BREADY(0);
M01_AXI_rready(0) <= ps7_0_axi_periph_M01_AXI_RREADY(0);
M01_AXI_wdata(31 downto 0) <= ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0);
M01_AXI_wvalid(0) <= ps7_0_axi_periph_M01_AXI_WVALID(0);
M02_AXI_araddr(31 downto 0) <= ps7_0_axi_periph_M02_AXI_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= ps7_0_axi_periph_M02_AXI_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= ps7_0_axi_periph_M02_AXI_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= ps7_0_axi_periph_M02_AXI_AWVALID(0);
M02_AXI_bready(0) <= ps7_0_axi_periph_M02_AXI_BREADY(0);
M02_AXI_rready(0) <= ps7_0_axi_periph_M02_AXI_RREADY(0);
M02_AXI_wdata(31 downto 0) <= ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0);
M02_AXI_wvalid(0) <= ps7_0_axi_periph_M02_AXI_WVALID(0);
S00_ARESETN(0) <= rst_ps7_0_100M_peripheral_aresetn(0);
S00_AXI_arready <= Conn1_ARREADY;
S00_AXI_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0);
S00_AXI_rlast <= Conn1_RLAST;
S00_AXI_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0);
S00_AXI_rvalid <= Conn1_RVALID;
S01_AXI_awready <= Conn2_AWREADY;
S01_AXI_bresp(1 downto 0) <= Conn2_BRESP(1 downto 0);
S01_AXI_bvalid <= Conn2_BVALID;
S01_AXI_wready <= Conn2_WREADY;
S02_AXI_arready <= Conn3_ARREADY;
S02_AXI_rdata(31 downto 0) <= Conn3_RDATA(31 downto 0);
S02_AXI_rlast <= Conn3_RLAST;
S02_AXI_rresp(1 downto 0) <= Conn3_RRESP(1 downto 0);
S02_AXI_rvalid <= Conn3_RVALID;
S03_AXI_awready <= Conn4_AWREADY;
S03_AXI_bresp(1 downto 0) <= Conn4_BRESP(1 downto 0);
S03_AXI_bvalid <= Conn4_BVALID;
S03_AXI_wready <= Conn4_WREADY;
S04_AXI_arready <= Conn5_ARREADY;
S04_AXI_rdata(31 downto 0) <= Conn5_RDATA(31 downto 0);
S04_AXI_rlast <= Conn5_RLAST;
S04_AXI_rresp(1 downto 0) <= Conn5_RRESP(1 downto 0);
S04_AXI_rvalid <= Conn5_RVALID;
S05_AXI_awready <= Conn6_AWREADY;
S05_AXI_bresp(1 downto 0) <= Conn6_BRESP(1 downto 0);
S05_AXI_bvalid <= Conn6_BVALID;
S05_AXI_wready <= Conn6_WREADY;
axi_dma_0_mm2s_introut(0) <= IRQ_0(0);
axi_dma_0_s2mm_introut(0) <= IRQ_1(0);
axi_dma_1_mm2s_introut(0) <= IRQ_2(0);
axi_dma_1_s2mm_introut(0) <= IRQ_3(0);
axi_dma_2_mm2s_introut(0) <= IRQ_4(0);
axi_dma_2_s2mm_introut(0) <= IRQ_5(0);
ps7_0_axi_periph_M00_AXI_ARREADY(0) <= M00_AXI_arready(0);
ps7_0_axi_periph_M00_AXI_AWREADY(0) <= M00_AXI_awready(0);
ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
ps7_0_axi_periph_M00_AXI_BVALID(0) <= M00_AXI_bvalid(0);
ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
ps7_0_axi_periph_M00_AXI_RVALID(0) <= M00_AXI_rvalid(0);
ps7_0_axi_periph_M00_AXI_WREADY(0) <= M00_AXI_wready(0);
ps7_0_axi_periph_M01_AXI_ARREADY(0) <= M01_AXI_arready(0);
ps7_0_axi_periph_M01_AXI_AWREADY(0) <= M01_AXI_awready(0);
ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
ps7_0_axi_periph_M01_AXI_BVALID(0) <= M01_AXI_bvalid(0);
ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
ps7_0_axi_periph_M01_AXI_RVALID(0) <= M01_AXI_rvalid(0);
ps7_0_axi_periph_M01_AXI_WREADY(0) <= M01_AXI_wready(0);
ps7_0_axi_periph_M02_AXI_ARREADY(0) <= M02_AXI_arready(0);
ps7_0_axi_periph_M02_AXI_AWREADY(0) <= M02_AXI_awready(0);
ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
ps7_0_axi_periph_M02_AXI_BVALID(0) <= M02_AXI_bvalid(0);
ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
ps7_0_axi_periph_M02_AXI_RVALID(0) <= M02_AXI_rvalid(0);
ps7_0_axi_periph_M02_AXI_WREADY(0) <= M02_AXI_wready(0);
IRQ_Concat: component BD_PR_3_IRQ_Concat_0
port map (
In0(0) => axi_dma_0_mm2s_introut(0),
In1(0) => axi_dma_0_s2mm_introut(0),
In2(0) => axi_dma_1_mm2s_introut(0),
In3(0) => axi_dma_1_s2mm_introut(0),
In4(0) => axi_dma_2_mm2s_introut(0),
In5(0) => axi_dma_2_s2mm_introut(0),
dout(5 downto 0) => IRQ_Concat_dout(5 downto 0)
);
axi_mem_intercon: entity work.BD_PR_3_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
M00_AXI_wid(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => Conn1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => Conn1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => Conn1_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => Conn1_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => Conn1_ARPROT(2 downto 0),
S00_AXI_arready => Conn1_ARREADY,
S00_AXI_arsize(2 downto 0) => Conn1_ARSIZE(2 downto 0),
S00_AXI_arvalid => Conn1_ARVALID,
S00_AXI_rdata(31 downto 0) => Conn1_RDATA(31 downto 0),
S00_AXI_rlast => Conn1_RLAST,
S00_AXI_rready => Conn1_RREADY,
S00_AXI_rresp(1 downto 0) => Conn1_RRESP(1 downto 0),
S00_AXI_rvalid => Conn1_RVALID,
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => Conn2_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => Conn2_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => Conn2_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => Conn2_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => Conn2_AWPROT(2 downto 0),
S01_AXI_awready => Conn2_AWREADY,
S01_AXI_awsize(2 downto 0) => Conn2_AWSIZE(2 downto 0),
S01_AXI_awvalid => Conn2_AWVALID,
S01_AXI_bready => Conn2_BREADY,
S01_AXI_bresp(1 downto 0) => Conn2_BRESP(1 downto 0),
S01_AXI_bvalid => Conn2_BVALID,
S01_AXI_wdata(31 downto 0) => Conn2_WDATA(31 downto 0),
S01_AXI_wlast => Conn2_WLAST,
S01_AXI_wready => Conn2_WREADY,
S01_AXI_wstrb(3 downto 0) => Conn2_WSTRB(3 downto 0),
S01_AXI_wvalid => Conn2_WVALID,
S02_ACLK => processing_system7_0_FCLK_CLK0,
S02_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S02_AXI_araddr(31 downto 0) => Conn3_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => Conn3_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => Conn3_ARCACHE(3 downto 0),
S02_AXI_arlen(7 downto 0) => Conn3_ARLEN(7 downto 0),
S02_AXI_arprot(2 downto 0) => Conn3_ARPROT(2 downto 0),
S02_AXI_arready => Conn3_ARREADY,
S02_AXI_arsize(2 downto 0) => Conn3_ARSIZE(2 downto 0),
S02_AXI_arvalid => Conn3_ARVALID,
S02_AXI_rdata(31 downto 0) => Conn3_RDATA(31 downto 0),
S02_AXI_rlast => Conn3_RLAST,
S02_AXI_rready => Conn3_RREADY,
S02_AXI_rresp(1 downto 0) => Conn3_RRESP(1 downto 0),
S02_AXI_rvalid => Conn3_RVALID,
S03_ACLK => processing_system7_0_FCLK_CLK0,
S03_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S03_AXI_awaddr(31 downto 0) => Conn4_AWADDR(31 downto 0),
S03_AXI_awburst(1 downto 0) => Conn4_AWBURST(1 downto 0),
S03_AXI_awcache(3 downto 0) => Conn4_AWCACHE(3 downto 0),
S03_AXI_awlen(7 downto 0) => Conn4_AWLEN(7 downto 0),
S03_AXI_awprot(2 downto 0) => Conn4_AWPROT(2 downto 0),
S03_AXI_awready => Conn4_AWREADY,
S03_AXI_awsize(2 downto 0) => Conn4_AWSIZE(2 downto 0),
S03_AXI_awvalid => Conn4_AWVALID,
S03_AXI_bready => Conn4_BREADY,
S03_AXI_bresp(1 downto 0) => Conn4_BRESP(1 downto 0),
S03_AXI_bvalid => Conn4_BVALID,
S03_AXI_wdata(31 downto 0) => Conn4_WDATA(31 downto 0),
S03_AXI_wlast => Conn4_WLAST,
S03_AXI_wready => Conn4_WREADY,
S03_AXI_wstrb(3 downto 0) => Conn4_WSTRB(3 downto 0),
S03_AXI_wvalid => Conn4_WVALID,
S04_ACLK => processing_system7_0_FCLK_CLK0,
S04_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S04_AXI_araddr(31 downto 0) => Conn5_ARADDR(31 downto 0),
S04_AXI_arburst(1 downto 0) => Conn5_ARBURST(1 downto 0),
S04_AXI_arcache(3 downto 0) => Conn5_ARCACHE(3 downto 0),
S04_AXI_arlen(7 downto 0) => Conn5_ARLEN(7 downto 0),
S04_AXI_arprot(2 downto 0) => Conn5_ARPROT(2 downto 0),
S04_AXI_arready => Conn5_ARREADY,
S04_AXI_arsize(2 downto 0) => Conn5_ARSIZE(2 downto 0),
S04_AXI_arvalid => Conn5_ARVALID,
S04_AXI_rdata(31 downto 0) => Conn5_RDATA(31 downto 0),
S04_AXI_rlast => Conn5_RLAST,
S04_AXI_rready => Conn5_RREADY,
S04_AXI_rresp(1 downto 0) => Conn5_RRESP(1 downto 0),
S04_AXI_rvalid => Conn5_RVALID,
S05_ACLK => processing_system7_0_FCLK_CLK0,
S05_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S05_AXI_awaddr(31 downto 0) => Conn6_AWADDR(31 downto 0),
S05_AXI_awburst(1 downto 0) => Conn6_AWBURST(1 downto 0),
S05_AXI_awcache(3 downto 0) => Conn6_AWCACHE(3 downto 0),
S05_AXI_awlen(7 downto 0) => Conn6_AWLEN(7 downto 0),
S05_AXI_awprot(2 downto 0) => Conn6_AWPROT(2 downto 0),
S05_AXI_awready => Conn6_AWREADY,
S05_AXI_awsize(2 downto 0) => Conn6_AWSIZE(2 downto 0),
S05_AXI_awvalid => Conn6_AWVALID,
S05_AXI_bready => Conn6_BREADY,
S05_AXI_bresp(1 downto 0) => Conn6_BRESP(1 downto 0),
S05_AXI_bvalid => Conn6_BVALID,
S05_AXI_wdata(31 downto 0) => Conn6_WDATA(31 downto 0),
S05_AXI_wlast => Conn6_WLAST,
S05_AXI_wready => Conn6_WREADY,
S05_AXI_wstrb(3 downto 0) => Conn6_WSTRB(3 downto 0),
S05_AXI_wvalid => Conn6_WVALID
);
processing_system7_0: component BD_PR_3_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(5 downto 0) => IRQ_Concat_dout(5 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 3) => B"000",
S_AXI_HP0_ARID(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 3) => B"000",
S_AXI_HP0_AWID(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 3) => B"000",
S_AXI_HP0_WID(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
ps7_0_axi_periph: entity work.BD_PR_3_ps7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => ps7_0_axi_periph_M00_AXI_ARREADY(0),
M00_AXI_arvalid(0) => ps7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => ps7_0_axi_periph_M00_AXI_AWREADY(0),
M00_AXI_awvalid(0) => ps7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => ps7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => ps7_0_axi_periph_M00_AXI_BVALID(0),
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => ps7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => ps7_0_axi_periph_M00_AXI_RVALID(0),
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => ps7_0_axi_periph_M00_AXI_WREADY(0),
M00_AXI_wvalid(0) => ps7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => ps7_0_axi_periph_M01_AXI_ARREADY(0),
M01_AXI_arvalid(0) => ps7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => ps7_0_axi_periph_M01_AXI_AWREADY(0),
M01_AXI_awvalid(0) => ps7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => ps7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => ps7_0_axi_periph_M01_AXI_BVALID(0),
M01_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => ps7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => ps7_0_axi_periph_M01_AXI_RVALID(0),
M01_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => ps7_0_axi_periph_M01_AXI_WREADY(0),
M01_AXI_wvalid(0) => ps7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => ps7_0_axi_periph_M02_AXI_ARREADY(0),
M02_AXI_arvalid(0) => ps7_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => ps7_0_axi_periph_M02_AXI_AWREADY(0),
M02_AXI_awvalid(0) => ps7_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => ps7_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => ps7_0_axi_periph_M02_AXI_BVALID(0),
M02_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => ps7_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => ps7_0_axi_periph_M02_AXI_RVALID(0),
M02_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => ps7_0_axi_periph_M02_AXI_WREADY(0),
M02_AXI_wvalid(0) => ps7_0_axi_periph_M02_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_ps7_0_100M: component BD_PR_3_rst_ps7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BD_PR_3 is
port (
AXIS_CLK : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
m_axis_data_0_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_0_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_0_tlast : out STD_LOGIC;
m_axis_data_0_tready : in STD_LOGIC;
m_axis_data_0_tvalid : out STD_LOGIC;
m_axis_data_1_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_1_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_1_tlast : out STD_LOGIC;
m_axis_data_1_tready : in STD_LOGIC;
m_axis_data_1_tvalid : out STD_LOGIC;
m_axis_data_2_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_2_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_data_2_tlast : out STD_LOGIC;
m_axis_data_2_tready : in STD_LOGIC;
m_axis_data_2_tvalid : out STD_LOGIC;
s_axis_data_0_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_0_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_0_tlast : in STD_LOGIC;
s_axis_data_0_tready : out STD_LOGIC;
s_axis_data_0_tvalid : in STD_LOGIC;
s_axis_data_1_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_1_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_1_tlast : in STD_LOGIC;
s_axis_data_1_tready : out STD_LOGIC;
s_axis_data_1_tvalid : in STD_LOGIC;
s_axis_data_2_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_data_2_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_data_2_tlast : in STD_LOGIC;
s_axis_data_2_tready : out STD_LOGIC;
s_axis_data_2_tvalid : in STD_LOGIC
);
attribute core_generation_info : string;
attribute core_generation_info of BD_PR_3 : entity is "BD_PR_3,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=BD_PR_3,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=30,numReposBlks=16,numNonXlnxBlks=0,numHierBlks=14,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=10,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute hw_handoff : string;
attribute hw_handoff of BD_PR_3 : entity is "BD_PR_3.hwdef";
end BD_PR_3;
architecture STRUCTURE of BD_PR_3 is
component BD_PR_3_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component BD_PR_3_axi_dma_0_0;
component BD_PR_3_axi_dma_1_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component BD_PR_3_axi_dma_1_0;
component BD_PR_3_axi_dma_2_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component BD_PR_3_axi_dma_2_0;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_0_mm2s_introut : STD_LOGIC;
signal axi_dma_0_s2mm_introut : STD_LOGIC;
signal axi_dma_1_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_1_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_1_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_1_mm2s_introut : STD_LOGIC;
signal axi_dma_1_s2mm_introut : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_2_mm2s_introut : STD_LOGIC;
signal axi_dma_2_s2mm_introut : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_axis_data_0_1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s_axis_data_0_1_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s_axis_data_0_1_TLAST : STD_LOGIC;
signal s_axis_data_0_1_TREADY : STD_LOGIC;
signal s_axis_data_0_1_TVALID : STD_LOGIC;
signal s_axis_data_1_1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s_axis_data_1_1_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s_axis_data_1_1_TLAST : STD_LOGIC;
signal s_axis_data_1_1_TREADY : STD_LOGIC;
signal s_axis_data_1_1_TVALID : STD_LOGIC;
signal s_axis_data_2_1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s_axis_data_2_1_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s_axis_data_2_1_TLAST : STD_LOGIC;
signal s_axis_data_2_1_TREADY : STD_LOGIC;
signal s_axis_data_2_1_TVALID : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
begin
AXIS_CLK <= processing_system7_0_FCLK_CLK0;
axi_dma_0_M_AXIS_MM2S_TREADY <= m_axis_data_0_tready;
axi_dma_1_M_AXIS_MM2S_TREADY <= m_axis_data_1_tready;
axi_dma_2_M_AXIS_MM2S_TREADY <= m_axis_data_2_tready;
m_axis_data_0_tdata(31 downto 0) <= axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0);
m_axis_data_0_tkeep(3 downto 0) <= axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0);
m_axis_data_0_tlast <= axi_dma_0_M_AXIS_MM2S_TLAST;
m_axis_data_0_tvalid <= axi_dma_0_M_AXIS_MM2S_TVALID;
m_axis_data_1_tdata(31 downto 0) <= axi_dma_1_M_AXIS_MM2S_TDATA(31 downto 0);
m_axis_data_1_tkeep(3 downto 0) <= axi_dma_1_M_AXIS_MM2S_TKEEP(3 downto 0);
m_axis_data_1_tlast <= axi_dma_1_M_AXIS_MM2S_TLAST;
m_axis_data_1_tvalid <= axi_dma_1_M_AXIS_MM2S_TVALID;
m_axis_data_2_tdata(31 downto 0) <= axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0);
m_axis_data_2_tkeep(3 downto 0) <= axi_dma_2_M_AXIS_MM2S_TKEEP(3 downto 0);
m_axis_data_2_tlast <= axi_dma_2_M_AXIS_MM2S_TLAST;
m_axis_data_2_tvalid <= axi_dma_2_M_AXIS_MM2S_TVALID;
s_axis_data_0_1_TDATA(31 downto 0) <= s_axis_data_0_tdata(31 downto 0);
s_axis_data_0_1_TKEEP(3 downto 0) <= s_axis_data_0_tkeep(3 downto 0);
s_axis_data_0_1_TLAST <= s_axis_data_0_tlast;
s_axis_data_0_1_TVALID <= s_axis_data_0_tvalid;
s_axis_data_0_tready <= s_axis_data_0_1_TREADY;
s_axis_data_1_1_TDATA(31 downto 0) <= s_axis_data_1_tdata(31 downto 0);
s_axis_data_1_1_TKEEP(3 downto 0) <= s_axis_data_1_tkeep(3 downto 0);
s_axis_data_1_1_TLAST <= s_axis_data_1_tlast;
s_axis_data_1_1_TVALID <= s_axis_data_1_tvalid;
s_axis_data_1_tready <= s_axis_data_1_1_TREADY;
s_axis_data_2_1_TDATA(31 downto 0) <= s_axis_data_2_tdata(31 downto 0);
s_axis_data_2_1_TKEEP(3 downto 0) <= s_axis_data_2_tkeep(3 downto 0);
s_axis_data_2_1_TLAST <= s_axis_data_2_tlast;
s_axis_data_2_1_TVALID <= s_axis_data_2_tvalid;
s_axis_data_2_tready <= s_axis_data_2_1_TREADY;
Processing_System: entity work.Processing_System_imp_1I881SN
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
IRQ_0(0) => axi_dma_0_mm2s_introut,
IRQ_1(0) => axi_dma_0_s2mm_introut,
IRQ_2(0) => axi_dma_1_mm2s_introut,
IRQ_3(0) => axi_dma_1_s2mm_introut,
IRQ_4(0) => axi_dma_2_mm2s_introut,
IRQ_5(0) => axi_dma_2_s2mm_introut,
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => ps7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => ps7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => ps7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => ps7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => ps7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => ps7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => ps7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => ps7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => ps7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid(0) => ps7_0_axi_periph_M00_AXI_WVALID(0),
M01_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => ps7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => ps7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => ps7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => ps7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => ps7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => ps7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => ps7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => ps7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => ps7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wvalid(0) => ps7_0_axi_periph_M01_AXI_WVALID(0),
M02_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => ps7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => ps7_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => ps7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => ps7_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => ps7_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => ps7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => ps7_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => ps7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => ps7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wvalid(0) => ps7_0_axi_periph_M02_AXI_WVALID(0),
S00_ARESETN(0) => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
S02_AXI_araddr(31 downto 0) => axi_dma_1_M_AXI_MM2S_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => axi_dma_1_M_AXI_MM2S_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => axi_dma_1_M_AXI_MM2S_ARCACHE(3 downto 0),
S02_AXI_arlen(7 downto 0) => axi_dma_1_M_AXI_MM2S_ARLEN(7 downto 0),
S02_AXI_arprot(2 downto 0) => axi_dma_1_M_AXI_MM2S_ARPROT(2 downto 0),
S02_AXI_arready => axi_dma_1_M_AXI_MM2S_ARREADY,
S02_AXI_arsize(2 downto 0) => axi_dma_1_M_AXI_MM2S_ARSIZE(2 downto 0),
S02_AXI_arvalid => axi_dma_1_M_AXI_MM2S_ARVALID,
S02_AXI_rdata(31 downto 0) => axi_dma_1_M_AXI_MM2S_RDATA(31 downto 0),
S02_AXI_rlast => axi_dma_1_M_AXI_MM2S_RLAST,
S02_AXI_rready => axi_dma_1_M_AXI_MM2S_RREADY,
S02_AXI_rresp(1 downto 0) => axi_dma_1_M_AXI_MM2S_RRESP(1 downto 0),
S02_AXI_rvalid => axi_dma_1_M_AXI_MM2S_RVALID,
S03_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S03_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S03_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S03_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S03_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S03_AXI_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
S03_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S03_AXI_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
S03_AXI_bready => axi_dma_1_M_AXI_S2MM_BREADY,
S03_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S03_AXI_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
S03_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S03_AXI_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
S03_AXI_wready => axi_dma_1_M_AXI_S2MM_WREADY,
S03_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S03_AXI_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
S04_AXI_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
S04_AXI_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
S04_AXI_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
S04_AXI_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
S04_AXI_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
S04_AXI_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
S04_AXI_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
S04_AXI_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
S04_AXI_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
S04_AXI_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
S04_AXI_rready => axi_dma_2_M_AXI_MM2S_RREADY,
S04_AXI_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
S04_AXI_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
S05_AXI_awaddr(31 downto 0) => axi_dma_2_M_AXI_S2MM_AWADDR(31 downto 0),
S05_AXI_awburst(1 downto 0) => axi_dma_2_M_AXI_S2MM_AWBURST(1 downto 0),
S05_AXI_awcache(3 downto 0) => axi_dma_2_M_AXI_S2MM_AWCACHE(3 downto 0),
S05_AXI_awlen(7 downto 0) => axi_dma_2_M_AXI_S2MM_AWLEN(7 downto 0),
S05_AXI_awprot(2 downto 0) => axi_dma_2_M_AXI_S2MM_AWPROT(2 downto 0),
S05_AXI_awready => axi_dma_2_M_AXI_S2MM_AWREADY,
S05_AXI_awsize(2 downto 0) => axi_dma_2_M_AXI_S2MM_AWSIZE(2 downto 0),
S05_AXI_awvalid => axi_dma_2_M_AXI_S2MM_AWVALID,
S05_AXI_bready => axi_dma_2_M_AXI_S2MM_BREADY,
S05_AXI_bresp(1 downto 0) => axi_dma_2_M_AXI_S2MM_BRESP(1 downto 0),
S05_AXI_bvalid => axi_dma_2_M_AXI_S2MM_BVALID,
S05_AXI_wdata(31 downto 0) => axi_dma_2_M_AXI_S2MM_WDATA(31 downto 0),
S05_AXI_wlast => axi_dma_2_M_AXI_S2MM_WLAST,
S05_AXI_wready => axi_dma_2_M_AXI_S2MM_WREADY,
S05_AXI_wstrb(3 downto 0) => axi_dma_2_M_AXI_S2MM_WSTRB(3 downto 0),
S05_AXI_wvalid => axi_dma_2_M_AXI_S2MM_WVALID
);
axi_dma_0: component BD_PR_3_axi_dma_0_0
port map (
axi_resetn => rst_ps7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_0_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => axi_dma_0_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_lite_bready => ps7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => ps7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => ps7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => ps7_0_axi_periph_M00_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => s_axis_data_0_1_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => s_axis_data_0_1_TKEEP(3 downto 0),
s_axis_s2mm_tlast => s_axis_data_0_1_TLAST,
s_axis_s2mm_tready => s_axis_data_0_1_TREADY,
s_axis_s2mm_tvalid => s_axis_data_0_1_TVALID
);
axi_dma_1: component BD_PR_3_axi_dma_1_0
port map (
axi_resetn => rst_ps7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_1_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_1_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_1_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_1_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_1_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_1_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_1_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_1_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_1_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_1_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_1_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_1_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_1_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_1_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_1_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_1_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_1_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_1_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_1_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_1_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => axi_dma_1_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => ps7_0_axi_periph_M01_AXI_ARREADY,
s_axi_lite_arvalid => ps7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => ps7_0_axi_periph_M01_AXI_AWREADY,
s_axi_lite_awvalid => ps7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_lite_bready => ps7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => ps7_0_axi_periph_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => ps7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => ps7_0_axi_periph_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => ps7_0_axi_periph_M01_AXI_WREADY,
s_axi_lite_wvalid => ps7_0_axi_periph_M01_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => s_axis_data_1_1_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => s_axis_data_1_1_TKEEP(3 downto 0),
s_axis_s2mm_tlast => s_axis_data_1_1_TLAST,
s_axis_s2mm_tready => s_axis_data_1_1_TREADY,
s_axis_s2mm_tvalid => s_axis_data_1_1_TVALID
);
axi_dma_2: component BD_PR_3_axi_dma_2_0
port map (
axi_resetn => rst_ps7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_2_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_2_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_2_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_2_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_2_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_2_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_2_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_2_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_2_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_2_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_2_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_2_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_2_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_2_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_2_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_2_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_2_M_AXI_S2MM_WVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_2_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_2_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_2_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_2_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_2_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => axi_dma_2_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_2_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => ps7_0_axi_periph_M02_AXI_ARREADY,
s_axi_lite_arvalid => ps7_0_axi_periph_M02_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => ps7_0_axi_periph_M02_AXI_AWREADY,
s_axi_lite_awvalid => ps7_0_axi_periph_M02_AXI_AWVALID(0),
s_axi_lite_bready => ps7_0_axi_periph_M02_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => ps7_0_axi_periph_M02_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_lite_rready => ps7_0_axi_periph_M02_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => ps7_0_axi_periph_M02_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_lite_wready => ps7_0_axi_periph_M02_AXI_WREADY,
s_axi_lite_wvalid => ps7_0_axi_periph_M02_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => s_axis_data_2_1_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => s_axis_data_2_1_TKEEP(3 downto 0),
s_axis_s2mm_tlast => s_axis_data_2_1_TLAST,
s_axis_s2mm_tready => s_axis_data_2_1_TREADY,
s_axis_s2mm_tvalid => s_axis_data_2_1_TVALID
);
end STRUCTURE;
| mit | c49a1f9343eea4ac5da30a62cc143d8e | 0.664182 | 2.720013 | false | false | false | false |
6769/VHDL | Lab_5/__FromSaru/lab50/lab50.vhd | 1 | 1,971 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab50 is
port(reset,rb,clk_50m,clk_28m:in bit;
win,lose:out bit;
led1,led2:out bit_vector(7 downto 0));
end lab50;
architecture allmap of lab50 is
component counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end component;
component decoder_1_6 IS
PORT(m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
end component;
component adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end component;
component point_register is
port(sp:in bit;
point:out std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0));
end component;
component comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end component;
component test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end component;
component control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end component;
signal roll,eq,d7,d711,d2312,sp:bit;
signal count1,count2,sum,point:std_logic_vector(3 downto 0);
begin
decoder1:decoder_1_6 port map(m=>count1,led_vector=>led1);
decoder2:decoder_1_6 port map(m=>count2,led_vector=>led2);
counter1:counter_1_6 port map(clk_50m=>clk_50m,roll=>roll,out_count=>count1);
counter2:counter_1_6 port map(clk_50m=>clk_28m,roll=>roll,out_count=>count2);
add:adder port map(addend1=>count1,addend2=>count2,sum=>sum);
pr:point_register port map(sp=>sp,point=>point,sum=>sum);
compare:comparator port map(point=>point,sum=>sum,eq=>eq);
test:test_logic port map(sum=>sum,d7=>d7,d711=>d711,d2312=>d2312);
con:control port map(reset=>reset,rb=>rb,
eq=>eq,d7=>d7,d711=>d711,d2312=>d2312,
roll=>roll,win=>win,lose=>lose,sp=>sp);
end allmap; | gpl-2.0 | 2240dff35f75d7aaa462b39f6d0fb70c | 0.695586 | 2.791785 | false | false | false | false |
6769/VHDL | Lab_5/__FromSaru/lab50/test_logic.vhd | 1 | 534 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end test_logic;
architecture test of test_logic is
begin
process(sum)
begin
if sum="0111" then
d7<='1';
else d7<='0';
end if;
if sum="0111" or sum="1011" then
d711<='1';
else d711<='0';
end if;
if sum="0010" or sum="0011" or sum="1100" then
d2312<='1';
else d2312<='0';
end if;
end process;
end test; | gpl-2.0 | ab3ccfb7c006aac06950b858e0a3a347 | 0.604869 | 2.934066 | false | true | false | false |
6769/VHDL | Lab_2_part2/cyclic_reg_with_clock.vhd | 1 | 1,136 | entity cyclic_reg_with_clock is
port(clk,reset:in bit;
hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7:out bit_vector(7 downto 0)
);
end entity cyclic_reg_with_clock;
architecture combine of cyclic_reg_with_clock is
component clock_second is
port(clk:in bit ;
second:buffer bit);
end component;
component rotate_shift_register
port(clk,reset: in bit;
--problem is that the predefined value seems didn't assigned
hex0:buffer bit_vector(7 downto 0):="10000001"; --O
hex1:buffer bit_vector(7 downto 0):="10001111"; --L
hex2:buffer bit_vector(7 downto 0):="10001111"; --L
hex3:buffer bit_vector(7 downto 0):="00001101"; --E
hex4:buffer bit_vector(7 downto 0):="00010011"; --H
hex5:buffer bit_vector(7 downto 0):="11111111"; --nothing
hex6:buffer bit_vector(7 downto 0):="11111111"; --
hex7:buffer bit_vector(7 downto 0):="11111111" --nothing
);
end component;
signal midline:bit;
begin
clock0:clock_second port map(clk,midline);
reg0:rotate_shift_register port map(midline,reset,hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7);
end architecture combine; | gpl-2.0 | bb32902b6f5305b72331e5b84e543208 | 0.68662 | 3.129477 | false | false | false | false |
gregani/la16fw | input_shiftreg.vhd | 1 | 1,992 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_shiftreg is
port(
clk : in std_logic;
shift_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
shift_out : in std_logic;
data_out : out std_logic_vector(15 downto 0)
);
end input_shiftreg;
architecture behavioral of input_shiftreg is
subtype vector16_t is std_logic_vector(15 downto 0);
type vector16_arr_t is array (natural range <>) of vector16_t;
signal shiftreg : vector16_arr_t(15 downto 0);
signal vector16_null : vector16_t;
begin
vector16_null <= (others=>'0');
data_out <= shiftreg(0);
process(clk)
begin
if (rising_edge(clk)) then
if (shift_in = '1') then
-- shift input data into shift regs (msb is first sample)
for i in 0 to 15 loop
shiftreg(i) <= shiftreg(i)(14 downto 0) & data_in(i);
end loop;
elsif (shift_out = '1') then
shiftreg <= vector16_null & shiftreg(15 downto 1);
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 94def24ef7ccb0d360a7ea732afe4825 | 0.637048 | 3.852998 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/cdc_sync.vhd | 14 | 25,049 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
s_out_d5 <= '0';
s_out_d6 <= '0';
s_out_d7 <= '0';
scndry_out <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
s_out_d5 <= s_out_d4;
s_out_d6 <= s_out_d5;
s_out_d7 <= s_out_d6;
scndry_out <= s_out_re;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= s_out_d2 xor s_out_d3;
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= s_out_d3 xor s_out_d4;
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= s_out_d4 xor s_out_d5;
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= s_out_d5 xor s_out_d6;
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= s_out_d6 xor s_out_d7;
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_bus_d1_cdc_from <= (others => '0');
else
p_level_in_bus_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_bus_d1_cdc_to <= (others => '0');
s_level_out_bus_d2 <= (others => '0');
s_level_out_bus_d3 <= (others => '0');
s_level_out_bus_d4 <= (others => '0');
s_level_out_bus_d5 <= (others => '0');
s_level_out_bus_d6 <= (others => '0');
else
s_level_out_bus_d1_cdc_to <= p_level_in_bus_int;
s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
s_level_out_bus_d3 <= s_level_out_bus_d2;
s_level_out_bus_d4 <= s_level_out_bus_d3;
s_level_out_bus_d5 <= s_level_out_bus_d4;
s_level_out_bus_d6 <= s_level_out_bus_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
p_level_out_d3 <= '0';
p_level_out_d4 <= '0';
p_level_out_d5 <= '0';
p_level_out_d6 <= '0';
p_level_out_d7 <= '0';
prmry_ack <= '0';
else
p_level_out_d1_cdc_to <= scndry_out_int;
p_level_out_d2 <= p_level_out_d1_cdc_to;
p_level_out_d3 <= p_level_out_d2;
p_level_out_d4 <= p_level_out_d3;
p_level_out_d5 <= p_level_out_d4;
p_level_out_d6 <= p_level_out_d5;
p_level_out_d7 <= p_level_out_d6;
prmry_ack <= prmry_pulse_ack;
end if;
end if;
end process CROSS_PLEVEL_SCNDRY2PRMRY;
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| mit | 1d9e4854bbd9b018d9eb2b4488c1cf08 | 0.471955 | 3.649862 | false | false | false | false |
6769/VHDL | Lab_5/Compartor.vhd | 1 | 361 | entity Compartor is
port(
Sum,LockedSum:in integer range 2 to 12;
Eq,D7,D711,D2312:out bit
);
end entity Compartor;
architecture Behavior of Compartor is
begin
Eq<='1' when Sum=LockedSum else '0';
D7<='1' when Sum=7 else '0';
D711<='1' when Sum=7 or Sum=11 else '0';
D2312<='1' when Sum=2 or Sum=3 or Sum=12 else '0';
end architecture Behavior;
| gpl-2.0 | 4a1eb265c5c170dc007d8a993c4f90ce | 0.684211 | 2.714286 | false | false | false | false |
Project-Bonfire/EHA | Test/credit_based/TB_Package_32_bit_credit_based.vhd | 3 | 16,938 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)) & XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source, 14)) &
std_logic_vector(to_unsigned(destination, 14)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
destination_id := to_integer(unsigned(not std_logic_vector(to_unsigned(source, network_size))));
if destination_id = source then
wait;
end if;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
file DIAGNOSIS_FILE : text is out "DIAGNOSIS.txt";
variable DIAGNOSIS: std_logic;
variable DIAGNOSIS_vector: std_logic_vector(12 downto 0);
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
DIAGNOSIS := '0';
source_node := to_integer(unsigned(port_in(28 downto 15)));
destination_node := to_integer(unsigned(port_in(14 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
if port_in(28 downto 13) = "0100011001000100" then
DIAGNOSIS := '1';
DIAGNOSIS_vector(11 downto 0) := port_in(12 downto 1);
end if;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
if DIAGNOSIS = '1' then
DIAGNOSIS_vector(12) := port_in(28);
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(DIAGNOSIS_FILE, LINEVARIABLE);
else
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
end if;
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
| gpl-3.0 | d8a3e4713f6c4eeea758c6a430535194 | 0.5983 | 3.861833 | false | false | false | false |
1995parham/FPGA-Homework | HW-4/src/p5/p5.vhd | 1 | 687 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 07-05-2016
-- Module Name: p5.vhd
--------------------------------------------------------------------------------
process (sel, sel_2, sel_3, a, b)
begin
if sel = '1' then
f <= a;
if sel_2 = '1' then
g <= not a;
else
g <= not b;
if sel_3 = '1' then
g <= a xor b;
end if;
end if;
else
if sel_2 = '1' then
g <= a and b;
else
if sel_3 = '1' then
g <= a nand b;
-- preventing from transparent latch creation
else
g <= ...;
end if;
end if;
f <= b;
end if;
end process;
| gpl-3.0 | a40a8b780f63037b828940f4b69aa9e1 | 0.39738 | 3.108597 | false | false | false | false |
1995parham/FPGA-Homework | BCD/halfadder.vhd | 1 | 389 | library IEEE;
use IEEE.std_logic_1164.all;
entity halfadder is
port (a, b : in std_logic;
s : out std_logic;
c : out std_logic);
end entity;
architecture behavioral of halfadder is
begin
process (a, b)
begin
if a = b then
s <= '0';
if (a = '1') then
c <= '1';
else
c <= '0';
end if;
else
s <= '1';
c <= '0';
end if;
end process;
end architecture;
| gpl-3.0 | 19922d49cb01d109f415ad8b89454a91 | 0.570694 | 2.509677 | false | false | false | false |
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Arbiter_in_one_hot_checkers/RTL_and_Synthesis/arbiter_in_one_hot_with_checkers_top.vhd | 4 | 10,055 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_with_checkers_top is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_with_checkers_top;
architecture behavior of Arbiter_in_one_hot_with_checkers_top is
component arbiter_in_one_hot_pseudo is
port ( req_X_N, req_X_E, req_X_W, req_X_S, req_X_L:in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_in's FSM
X_N, X_E, X_W, X_S, X_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end component;
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
signal X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic;
signal state_in_sig: std_logic_vector (5 downto 0);
begin
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
state_in <= state_in_sig;
-- Arbiter instantiation
ARBITER_IN_ONE_HOT: arbiter_in_one_hot_pseudo port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
state_in => state_in_sig
);
-- Checkers instantiation
CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N,
req_X_E => req_X_E,
req_X_W => req_X_W,
req_X_S => req_X_S,
req_X_L => req_X_L,
state => state,
state_in => state_in_sig,
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
end behavior; | gpl-3.0 | b2c5ee8033e7211c6abd861299e22746 | 0.511885 | 2.72937 | false | false | false | false |
sunoc/vhdl-lz4-variation | z_old/lz4_fsm.vhdl | 1 | 1,693 | library ieee;
use ieee.std_logic_1164.all;
use work.lz4_pkg.all;
entity lz4_fsm is
port (
clk_i : in std_logic;
reset_i : in std_logic;
match : in std_logic;
eof : in std_logic;
Fs : out std_logic_vector(2 downto 0)
);
end lz4_fsm;
architecture behavior of lz4_fsm is
type States is (sBeginning, sMatch, sNoMatch, sNoMoreMatch, sEnding);
signal currentstate, nextstate: States;
begin
process (clk_i, reset_i)
begin
if (reset_i = '1') then
currentstate <= sBeginning;
end if;
case currentstate is
when sBeginning =>
Fs <= "000";
if (match = '0') then
nextstate <= sNoMatch;
elsif (match = '1') then
nextstate <= sMatch;
end if;
when sMatch =>
Fs <= "010";
if (match = '0') then
nextstate <= sNoMoreMatch;
elsif (match = '1') then
nextstate <= sMatch;
end if;
if (eof = '1') then
nextstate <= sEnding;
end if;
when sNoMatch =>
Fs <= "001";
if (match = '0') then
nextstate <= sNoMatch;
elsif (match = '1') then
nextstate <= sMatch;
end if;
if (eof = '1') then
nextstate <= sEnding;
end if;
when sNoMoreMatch =>
Fs <= "100";
nextstate <= sBeginning;
when sEnding =>
Fs <= "111";
nextstate <= sEnding;
end case;
if (rising_edge(clk_i)) then
currentstate <= nextstate;
end if;
end process;
end;
| gpl-3.0 | ca5b58803de946bb7c0f5517f3669017 | 0.479031 | 3.883028 | false | false | false | false |
quicky2000/top_mandelbrot_1b | mandel_iter.vhd | 1 | 2,031 | --
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mandel_iter is
Port ( x_n : in STD_LOGIC_VECTOR (15 downto 0);
y_n : in STD_LOGIC_VECTOR (15 downto 0);
x_square_in : in STD_LOGIC_VECTOR (15 downto 0);
y_square_in : in STD_LOGIC_VECTOR (15 downto 0);
a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
x_n_plus_1 : out STD_LOGIC_VECTOR (15 downto 0);
y_n_plus_1 : out STD_LOGIC_VECTOR (15 downto 0));
end mandel_iter;
architecture Behavioral of mandel_iter is
signal x_y : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
begin
x_y_mult : entity work.mult_16_8
port map (
a => x_n,
b => y_n,
p => x_y);
x_n_plus_1 <= std_logic_vector(signed(x_square_in) - signed(y_square_in) + signed(a));
y_n_plus_1 <= std_logic_vector((signed(x_y) sll 1) + signed(b));
end Behavioral;
| gpl-3.0 | 301698cb394001c20b81320557806089 | 0.658296 | 3.471795 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@p@b_@i@p/_primary.vhd | 3 | 9,959 | library verilog;
use verilog.vl_types.all;
entity MSS_APB_IP is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR : out vl_logic_vector(19 downto 0);
MSSPWDATA : out vl_logic_vector(31 downto 0);
MSSPWRITE : out vl_logic;
MSSPSEL : out vl_logic;
MSSPENABLE : out vl_logic;
MSSPRDATA : in vl_logic_vector(31 downto 0);
MSSPREADY : in vl_logic;
MSSPSLVERR : in vl_logic;
FABPADDR : in vl_logic_vector(31 downto 0);
FABPWDATA : in vl_logic_vector(31 downto 0);
FABPWRITE : in vl_logic;
FABPSEL : in vl_logic;
FABPENABLE : in vl_logic;
FABPRDATA : out vl_logic_vector(31 downto 0);
FABPREADY : out vl_logic;
FABPSLVERR : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
SDD0 : out vl_logic;
SDD1 : out vl_logic;
SDD2 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
ABPS2 : in vl_logic;
ABPS3 : in vl_logic;
ABPS4 : in vl_logic;
ABPS5 : in vl_logic;
ABPS6 : in vl_logic;
ABPS7 : in vl_logic;
ABPS8 : in vl_logic;
ABPS9 : in vl_logic;
ABPS10 : in vl_logic;
ABPS11 : in vl_logic;
TM0 : in vl_logic;
TM1 : in vl_logic;
TM2 : in vl_logic;
TM3 : in vl_logic;
TM4 : in vl_logic;
TM5 : in vl_logic;
CM0 : in vl_logic;
CM1 : in vl_logic;
CM2 : in vl_logic;
CM3 : in vl_logic;
CM4 : in vl_logic;
CM5 : in vl_logic;
GNDTM0 : in vl_logic;
GNDTM1 : in vl_logic;
GNDTM2 : in vl_logic;
VAREF0 : in vl_logic;
VAREF1 : in vl_logic;
VAREF2 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_APB_IP;
| gpl-3.0 | b6a7bf5093e1cf366ca5f359ec1cc8c2 | 0.398534 | 3.676264 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@b@f@m_@a@h@b@s@l@a@v@e@e@x@t/_primary.vhd | 3 | 1,635 | library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := 1;
NAME : string := ""
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
end MSS_BFM_AHBSLAVEEXT;
| gpl-3.0 | 8106b58df968c6f1891a34e3f25341f0 | 0.412232 | 3.987805 | false | false | false | false |
1995parham/FPGA-Homework | HW-4/src/p7/d-flipflop.vhd | 1 | 760 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: d-flipflop.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity d_flipflop is
port ( clk, reset, preset : in std_logic;
d : in std_logic;
q, qbar : out std_logic);
end entity d_flipflop;
architecture rtl of d_flipflop is
signal b : std_logic;
begin
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
b <= '0';
elsif preset = '1' then
b <= '1';
else
b <= d;
end if;
end if;
end process;
q <= b;
qbar <= not b;
end architecture;
| gpl-3.0 | 7de061caa9e4e75bdb0d0f253220fce1 | 0.484211 | 3.362832 | false | false | false | false |
quicky2000/top_mandelbrot_1b | image_generator.vhd | 1 | 4,801 | --
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_generator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
addr : out STD_LOGIC_VECTOR (18 downto 0);
write_enable : out STD_LOGIC;
data : out STD_LOGIC;
next_step : in std_logic);
end image_generator;
architecture Behavioral of image_generator is
type state_type is (reseting,computing,writing);
signal state :state_type := reseting;
signal next_state : state_type := reseting;
signal ready : std_logic := '0';
signal rst_mandel : std_logic := '0';
signal x : std_logic_vector(15 downto 0) := (others => '0');
signal y : std_logic_vector(15 downto 0) := (others => '0');
signal x_mandel : std_logic_vector(15 downto 0) := (others => '0');
signal y_mandel : std_logic_vector(15 downto 0) := (others => '0');
signal nb_iter_max : std_logic_vector(5 downto 0) := (others => '0');
constant max_iter : positive range 2 to 63 := 4;
constant x_ref : positive := 16#FE00#;
constant y_ref : positive := 16#FF10#;
begin
process (clk,rst)
begin
if rst = '1' then
nb_iter_max <= (others => '0');
elsif rising_edge(clk) then
if next_step = '1' then
if unsigned(nb_iter_max) >= 18 then
nb_iter_max <= (others => '0');
else
nb_iter_max <= std_logic_vector(unsigned(nb_iter_max)+1);
end if;
else
nb_iter_max <= nb_iter_max;
end if;
end if;
end process;
--state register
process(clk,rst)
begin
if rst = '1' then
state <= reseting;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
--state transition
process(state,ready)
begin
if state = reseting then
next_state <= computing;
elsif state = computing then
if ready = '1' then
next_state <= reseting;
else
next_state <= computing;
end if;
elsif state = writing then
next_state <= reseting;
end if;
end process;
--output function
rst_mandel <= '1' when state = reseting else '0';
write_enable <= ready;
-- nb_iter_max <= std_logic_vector(to_unsigned(16#4#,6));
-- nb_iter_max <= std_logic_vector(to_unsigned(max_iter-2,6));
x_mandel <= std_logic_vector(unsigned(x) + to_unsigned(x_ref,16));
y_mandel <= std_logic_vector(unsigned(y) + to_unsigned(y_ref,16));
inst_mandel_loop : entity work.mandel_loop port map (
clk => clk,
rst => rst_mandel,
x => x_mandel,
y => y_mandel,
nb_iter_max => nb_iter_max,
ok => data,
ready => ready);
process(clk,rst)
constant x_max : positive := 639;
constant y_max : positive := 479;
variable x_write : natural range 0 to x_max := 0;
variable y_write : natural range 0 to y_max := 0;
variable address : natural range 0 to 307199 := 0;
begin
if rst = '1' then
-- write_enable <= '0';
addr <= (others => '0');
-- data <= '0';
elsif rising_edge(clk) and ready = '1' then
-- Address management
if address /= 307199 then
address := address + 1;
else
address := 0;
end if; -- addr max
-- Coordinate management
if x_write /= x_max then
x_write := x_write + 1;
else --xmax
x_write := 0;
if y_write /= y_max then
y_write := y_write + 1;
else
y_write := 0;
end if; --ymax
end if; -- xmax
addr <= std_logic_vector(to_unsigned(address,19));
x <= std_logic_vector(to_unsigned(x_write,16));
y <= std_logic_vector(to_unsigned(y_write,16));
end if;-- clock rising edge
end process;
end Behavioral;
| gpl-3.0 | 85525b199cc87c8d363cfc095d643ae1 | 0.606332 | 3.548411 | false | false | false | false |
6769/VHDL | Lab_4/Part1/Segment7Decoder.vhd | 1 | 1,397 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(7 downto 1) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; | gpl-2.0 | f406e4912fcc8e987e4ddf11fb046673 | 0.586972 | 3.366265 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_blk_mem_gen_0_0/synth/zynq_1_blk_mem_gen_0_0.vhd | 1 | 13,743 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY zynq_1_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_blk_mem_gen_0_0;
ARCHITECTURE zynq_1_blk_mem_gen_0_0_arch OF zynq_1_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_1_blk_mem_gen_0_0_arch : ARCHITECTURE IS "zynq_1_blk_mem_gen_0_0,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "zynq_1_blk_mem_gen_0_0,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=512,C_READ_DEPTH_A=512,C_ADDRA_WIDTH=9,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=512,C_READ_DEPTH_B=512,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 512,
C_READ_DEPTH_A => 512,
C_ADDRA_WIDTH => 9,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 512,
C_READ_DEPTH_B => 512,
C_ADDRB_WIDTH => 9,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END zynq_1_blk_mem_gen_0_0_arch;
| mit | 300bf6838f00f72ed35d607e6dfdb9e8 | 0.633704 | 3.035115 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/reset_sync_module.vhd | 1 | 10,662 | -------------------------------------------------------------------------------
-- $Id: reset_sync_module.vhd
-------------------------------------------------------------------------------
-- reset_sync_module.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_sync_module.vhd
-- Version: v3.0
-- Description: This is the reset sync module.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity reset_sync_module is
--generic();
port(EXT_SPI_CLK : in std_logic;
Soft_Reset_frm_axi: in std_logic;
Rst_to_spi : out std_logic
);
end entity reset_sync_module;
architecture imp of reset_sync_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal Soft_Reset_frm_axi_d1 : std_logic;
signal Soft_Reset_frm_axi_d2 : std_logic;
signal Soft_Reset_frm_axi_d3 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is "TRUE";
-----
begin
-----
--RESET_SYNC_FROM_AXI_TO_SPI: process(EXT_SPI_CLK)is
-------
--begin
-------
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- Soft_Reset_frm_axi_d1 <= Soft_Reset_frm_axi;
-- Soft_Reset_frm_axi_d2 <= Soft_Reset_frm_axi_d1;
-- Soft_Reset_frm_axi_d3 <= Soft_Reset_frm_axi_d2;
-- end if;
--end process RESET_SYNC_FROM_AXI_TO_SPI;
-----------------------------------------
RESET_SYNC_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d1,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi,
R => '0'
);
RESET_SYNC_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d2,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi_d1,
R => '0'
);
Rst_to_spi <= Soft_Reset_frm_axi_d2;
---------------------------------------
end architecture imp;
------------------------------------------------------------------------------- | mit | c9d72e40a04d0d5e05bc47cb9fbf8d2a | 0.43369 | 4.619584 | false | false | false | false |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/NI.vhd | 3 | 22,786 | ---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(7 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(11 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(24 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= "000000000000";
state <= IDLE;
packet_counter_out <= "00000000";
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(write_byte_enable, address) begin
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
Rxy_reconf_PE <= data_write(7 downto 0);
Cx_reconf_PE <= data_write(4 downto 8);
Reconfig_command <= '1';
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1'then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
elsif (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults; -- turn_faults : 20 bits + link_faults : 5 bits => remaining : 7 bits (all zeros)
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= BODY_FLIT;
packet_length_counter_in <= ("0000" & FIFO_Data_out(23 downto 16))-1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - "000000000001";
if packet_length_counter_out = "000000000010" then
state_in <= TAIL_FLIT;
else
state_in <= BODY_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 25 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(12) & "000000000000000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag& "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
| gpl-3.0 | de01e5e8c2726f47016ad635e95dce47 | 0.580883 | 3.113267 | false | false | false | false |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/new/pr_axis_buffer.vhd | 1 | 6,483 | library ieee;
use ieee.std_logic_1164.all;
entity pr_axis_buffer is
generic (
DATAWIDTH : integer := 64
);
port (
static_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
static_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_m_axis_data_tready : out std_logic;
static_m_axis_data_tlast : in std_logic;
static_m_axis_data_tvalid : in std_logic;
pr_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
pr_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_m_axis_data_tready : out std_logic;
pr_m_axis_data_tlast : in std_logic;
pr_m_axis_data_tvalid : in std_logic;
static_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
static_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_s_axis_data_tready : in std_logic;
static_s_axis_data_tlast : out std_logic;
static_s_axis_data_tvalid : out std_logic;
pr_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
pr_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_s_axis_data_tready : in std_logic;
pr_s_axis_data_tlast : out std_logic;
pr_s_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end pr_axis_buffer;
architecture rtl of pr_axis_buffer is
component axis_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH;
BUFFER_SIZE : positive := 1
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
component axis_lut_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
signal m_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal m_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal m_axis_data_tlast : STD_LOGIC;
signal m_axis_data_tready : STD_LOGIC;
signal m_axis_data_tvalid : STD_LOGIC;
signal s_axis_data_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal s_axis_data_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal s_axis_data_tlast : STD_LOGIC;
signal s_axis_data_tready : STD_LOGIC;
signal s_axis_data_tvalid : STD_LOGIC;
begin
input_buffer: component axis_buffer
generic map (
DATAWIDTH => DATAWIDTH,
BUFFER_SIZE => 1
)
port map(
s_axis_data_tdata => static_m_axis_data_tdata,
s_axis_data_tkeep => static_m_axis_data_tkeep,
s_axis_data_tready => static_m_axis_data_tready,
s_axis_data_tlast => static_m_axis_data_tlast,
s_axis_data_tvalid => static_m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tkeep => m_axis_data_tkeep,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tvalid => m_axis_data_tvalid,
clk => clk
);
input_lut_buffer: component axis_lut_buffer
generic map (
DATAWIDTH => DATAWIDTH
)
port map(
s_axis_data_tdata => m_axis_data_tdata,
s_axis_data_tkeep => m_axis_data_tkeep,
s_axis_data_tready => m_axis_data_tready,
s_axis_data_tlast => m_axis_data_tlast,
s_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => pr_s_axis_data_tdata,
m_axis_data_tkeep => pr_s_axis_data_tkeep,
m_axis_data_tready => pr_s_axis_data_tready,
m_axis_data_tlast => pr_s_axis_data_tlast,
m_axis_data_tvalid => pr_s_axis_data_tvalid,
clk => clk
);
output_buffer: component axis_buffer
generic map (
DATAWIDTH => DATAWIDTH,
BUFFER_SIZE => 1
)
port map(
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tkeep => s_axis_data_tkeep,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
s_axis_data_tvalid => s_axis_data_tvalid,
m_axis_data_tdata => static_s_axis_data_tdata,
m_axis_data_tkeep => static_s_axis_data_tkeep,
m_axis_data_tready => static_s_axis_data_tready,
m_axis_data_tlast => static_s_axis_data_tlast,
m_axis_data_tvalid => static_s_axis_data_tvalid,
clk => clk
);
output_lut_buffer: component axis_lut_buffer
generic map (
DATAWIDTH => DATAWIDTH
)
port map(
s_axis_data_tdata => pr_m_axis_data_tdata,
s_axis_data_tkeep => pr_m_axis_data_tkeep,
s_axis_data_tready => pr_m_axis_data_tready,
s_axis_data_tlast => pr_m_axis_data_tlast,
s_axis_data_tvalid => pr_m_axis_data_tvalid,
m_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tkeep => s_axis_data_tkeep,
m_axis_data_tready => s_axis_data_tready,
m_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tvalid => s_axis_data_tvalid,
clk => clk
);
end architecture rtl; | mit | 0a1a3501002472f74b364586ca669501 | 0.583526 | 3.295882 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m3_@b@f@m/_primary.vhd | 3 | 5,944 | library verilog;
use verilog.vl_types.all;
entity M3_BFM is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 0;
DEBUGLEVEL : integer := 3;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
SYSREG_HRDATA : in vl_logic_vector(31 downto 0);
SYSREG_HREADY : in vl_logic;
SYSREG_HRESP : in vl_logic;
SYSREG_HADDR : out vl_logic_vector(11 downto 0);
SYSREG_HBURST : out vl_logic_vector(2 downto 0);
SYSREG_HMASTLOCK: out vl_logic;
SYSREG_HPROT : out vl_logic_vector(3 downto 0);
SYSREG_HSIZE : out vl_logic_vector(2 downto 0);
SYSREG_HTRANS : out vl_logic_vector(1 downto 0);
SYSREG_HWRITE : out vl_logic;
SYSREG_HWDATA : out vl_logic_vector(31 downto 0);
SYSREG_HSEL : out vl_logic;
INTERRUPT : in vl_logic_vector(255 downto 0)
);
end M3_BFM;
| gpl-3.0 | 30ced533e4631f0324543a99e3220646 | 0.459791 | 4.215603 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/VGA_top.vhd | 1 | 5,787 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:57:07 12/03/2013
-- Design Name:
-- Module Name: VGA_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_top is
port(
pc: in std_logic_vector(15 downto 0);
control: in std_logic_vector(15 downto 0);
vga_reg1: in std_logic_vector(15 downto 0);
CLK_0: in std_logic; -- must 50M
clk_out: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0'
);
end VGA_top;
architecture Behavioral of VGA_top is
component VGA_play
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end component;
-- display memory control
signal dwctrl: std_logic_vector(0 downto 0);
signal dwaddr : std_logic_vector(10 downto 0);
signal dwdata : std_logic_vector(7 downto 0);
signal dclk : std_logic;
type data is (
d1,
d2,
d3,
d4,
d5,
d6
);
type step is (
s1,
s2,
s3,
s4
);
signal datain : data := d1;
signal datast : step := s1;
begin
clk_out <= dclk;
vga : VGA_play port map(
CLK_0 => CLK_0,
clkout=> dclk,
reset=> reset,
-- vga port
R=> R,
G=> G,
B=> B,
Hs=> Hs,
Vs=> Vs,
-- fifo memory
wctrl=> dwctrl,
waddr=> dwaddr,
wdata => dwdata
);
process(dclk)
begin
if dclk'event and dclk = '1' then
dwctrl(0) <= '1';
case datain is
when d1 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0000";
dwdata <= "0001" & pc(15 downto 12);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0001";
dwdata <= "0001" & pc(11 downto 8);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0010";
dwdata <= "0001" & pc(7 downto 4);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0011";
dwdata <= "0001" & pc(3 downto 0);
datast <= s1;
datain <= d2;
end case;
when d2 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0100";
dwdata <= "0001000" & control(15);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0101";
dwdata <= "0001000" & control(14);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0110";
dwdata <= "0001000" & control(13);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0111";
dwdata <= "0001000" & control(12);
datast <= s1;
datain <= d3;
end case;
when d3 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1000";
dwdata <= "0001000" & control(11);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1001";
dwdata <= "0001000" & control(10);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1010";
dwdata <= "0001000" & control(9);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1011";
dwdata <= "0001000" & control(8);
datast <= s1;
datain <= d4;
end case;
when d4 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1100";
dwdata <= "0001000" & control(7);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1101";
dwdata <= "0001000" & control(6);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1110";
dwdata <= "0001000" & control(5);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1111";
dwdata <= "0001000" & control(4);
datast <= s1;
datain <= d5;
end case;
when d5 =>
case datast is
when s1 =>
dwaddr <= "0000001" & "0000";
dwdata <= "0001000" & control(3);
datast <= s2;
when s2 =>
dwaddr <= "0000001" & "0001";
dwdata <= "0001000" & control(2);
datast <= s3;
when s3 =>
dwaddr <= "0000001" & "0010";
dwdata <= "0001000" & control(1);
datast <= s4;
when s4 =>
dwaddr <= "0000001" & "0011";
dwdata <= "0001000" & control(0);
datast <= s1;
datain <= d6;
end case;
when d6 =>
case datast is
when s1 =>
dwaddr <= "0000100" & "0000";
dwdata <= "0001" & vga_reg1(15 downto 12);
datast <= s2;
when s2 =>
dwaddr <= "0000100" & "0001";
dwdata <= "0001" & vga_reg1(11 downto 8);
datast <= s3;
when s3 =>
dwaddr <= "0000100" & "0010";
dwdata <= "0001" & vga_reg1(7 downto 4);
datast <= s4;
when s4 =>
dwaddr <= "0000100" & "0011";
dwdata <= "0001" & vga_reg1(3 downto 0);
datast <= s1;
datain <= d1;
end case;
end case;
end if;
end process;
end Behavioral;
| mit | 318c2fb373861513411af8a8df5593cb | 0.522896 | 2.995342 | false | false | false | false |
1995parham/FPGA-Homework | Project-Phase1/src/concurrent/fitness.vhd | 1 | 870 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 31-03-2016
-- Module Name: main-concurrent.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fitness is
port (c1, c2 : in character;
a, b : out std_logic_vector (4 downto 0));
end entity fitness;
architecture rtl of fitness is
begin
process (c1, c2)
begin
if c1 = ' ' then
a <= "11010"; -- a = 26
else
a <= std_logic_vector(to_unsigned(character'pos(c1) - 96, 5)); -- a = s[i] - 'a'
end if;
if c2 = ' ' then
b <= "11010"; -- b = 26
else
b <= std_logic_vector(to_unsigned(character'pos(c2) - 96, 5)); -- b = s[i + 1] - 'a'
end if;
end process;
end architecture rtl;
| gpl-3.0 | 4f98270c21c3194d5d2c79ef06690be1 | 0.497701 | 3.175182 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/VGA_top.vhd | 1 | 4,691 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:57:07 12/03/2013
-- Design Name:
-- Module Name: VGA_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_top is
port(
KEY16_INPUT: in std_logic_vector(15 downto 0);
CLK_0: in std_logic; -- must 50M
clk_out: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0'
);
end VGA_top;
architecture Behavioral of VGA_top is
component VGA_play
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end component;
-- display memory control
signal dwctrl: std_logic_vector(0 downto 0);
signal dwaddr : std_logic_vector(10 downto 0);
signal dwdata : std_logic_vector(7 downto 0);
signal dclk : std_logic;
type data is (
d1,
d2,
d3,
d4
);
type step is (
s1,
s2,
s3,
s4
);
signal datain : data := d1;
signal datast : step := s1;
begin
clk_out <= dclk;
vga : VGA_play port map(
CLK_0 => CLK_0,
clkout=> dclk,
reset=> reset,
-- vga port
R=> R,
G=> G,
B=> B,
Hs=> Hs,
Vs=> Vs,
-- fifo memory
wctrl=> dwctrl,
waddr=> dwaddr,
wdata => dwdata
);
process(dclk)
begin
if dclk'event and dclk = '1' then
dwctrl(0) <= '1';
case datain is
when d1 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0000";
dwdata <= "0001" & input(15 downto 12);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0001";
dwdata <= "0001" & input(11 downto 8);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0010";
dwdata <= "0000000" & KEY16_INPUT(2);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0011";
dwdata <= "0000000" & KEY16_INPUT(3);
datast <= s1;
datain <= d2;
end case;
when d2 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "0100";
dwdata <= "0000000" & KEY16_INPUT(4);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "0101";
dwdata <= "0000000" & KEY16_INPUT(5);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "0110";
dwdata <= "0000000" & KEY16_INPUT(6);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "0111";
dwdata <= "0000000" & KEY16_INPUT(7);
datast <= s1;
datain <= d3;
end case;
when d3 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1000";
dwdata <= "0000000" & KEY16_INPUT(8);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1001";
dwdata <= "0000000" & KEY16_INPUT(9);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1010";
dwdata <= "0000000" & KEY16_INPUT(10);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1011";
dwdata <= "0000000" & KEY16_INPUT(11);
datast <= s1;
datain <= d4;
end case;
when d4 =>
case datast is
when s1 =>
dwaddr <= "0000000" & "1100";
dwdata <= "0000000" & KEY16_INPUT(12);
datast <= s2;
when s2 =>
dwaddr <= "0000000" & "1101";
dwdata <= "0000000" & KEY16_INPUT(13);
datast <= s3;
when s3 =>
dwaddr <= "0000000" & "1110";
dwdata <= "0000000" & KEY16_INPUT(14);
datast <= s4;
when s4 =>
dwaddr <= "0000000" & "1111";
dwdata <= "0000000" & KEY16_INPUT(15);
datast <= s1;
datain <= d1;
end case;
end case;
end if;
end process;
end Behavioral;
| mit | 8ae5910d056c1fc7d8b08d2dc9b0fc2f | 0.536133 | 2.976523 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/RegFile.vhd | 1 | 6,611 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:13:23 11/21/2013
-- Design Name:
-- Module Name: RegFile - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RegFile is
Port (
ReadAddress1 : in STD_LOGIC_VECTOR (3 downto 0);
ReadAddress2 : in STD_LOGIC_VECTOR (3 downto 0);
WriteAddress : in STD_LOGIC_VECTOR (3 downto 0);
WriteData : in STD_LOGIC_VECTOR (15 downto 0);
PCinput: in STD_LOGIC_VECTOR (15 downto 0);
Reg1 : out STD_LOGIC_VECTOR (15 downto 0);
Reg2 : out STD_LOGIC_VECTOR (15 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel: in std_logic_vector(3 downto 0);
LED_output: out std_logic_vector(15 downto 0);
debug: in std_logic_vector(15 downto 0);
vga_reg1: out std_logic_vector(15 downto 0)
);
end RegFile;
architecture Behavioral of RegFile is
signal control : std_logic_vector (15 downto 0);
signal opt0, opt1, opt2, opt3, opt4, opt5, opt6, opt7, opt8 : std_logic_vector (15 downto 0);
signal opt9, opt10, opt11, opt12, opt13, opt14, opt15 : std_logic_vector (15 downto 0);
component Reg16
port(
input: in std_logic_vector(15 downto 0);
output: out std_logic_vector(15 downto 0);
wrn: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end component;
signal debug_output: std_logic_vector(15 downto 0):= Int16_Zero;
component LED16 is
Port(
LED_output : out std_logic_vector(15 downto 0);
input : in std_logic_vector(15 downto 0)
);
end component;
begin
r0 : Reg16 port map(input => WriteData, output => opt0, wrn => control(0), clock => clk, reset => rst);
r1 : Reg16 port map(input => WriteData, output => opt1, wrn => control(1), clock => clk, reset => rst);
r2 : Reg16 port map(input => WriteData, output => opt2, wrn => control(2), clock => clk, reset => rst);
r3 : Reg16 port map(input => WriteData, output => opt3, wrn => control(3), clock => clk, reset => rst);
r4 : Reg16 port map(input => WriteData, output => opt4, wrn => control(4), clock => clk, reset => rst);
r5 : Reg16 port map(input => WriteData, output => opt5, wrn => control(5), clock => clk, reset => rst);
r6 : Reg16 port map(input => WriteData, output => opt6, wrn => control(6), clock => clk, reset => rst);
r7 : Reg16 port map(input => WriteData, output => opt7, wrn => control(7), clock => clk, reset => rst);
-- r8 Zero register
r9 : Reg16 port map(input => WriteData, output => opt9, wrn => control(9), clock => clk, reset => rst);
-- r10 PC register
opt10 <= PCinput;
-- r10 : Reg16 port map(input => PCinput, output => opt10, wrn => control(10), clock => clk, reset => rst);
-- r11 IH register (interrput ÖжÏ)
r11 : Reg16 port map(input => WriteData, output => opt11, wrn => control(11), clock => clk, reset => rst);
-- r12 RA register (return address)
r12 : Reg16 port map(input => WriteData, output => opt12, wrn => control(12), clock => clk, reset => rst);
-- r13 SP register (stack point)
r13 : Reg16 port map(input => WriteData, output => opt13, wrn => control(13), clock => clk, reset => rst);
r14 : Reg16 port map(input => WriteData, output => opt14, wrn => control(14), clock => clk, reset => rst);
r15 : Reg16 port map(input => WriteData, output => opt15, wrn => control(15), clock => clk, reset => rst);
-- because it's forever zero output (but can still write)
opt8 <= (others => '0'); --ZERO
with ReadAddress1 select
Reg1<=
opt0 when "0000",
opt1 when "0001",
opt2 when "0010",
opt3 when "0011",
opt4 when "0100",
opt5 when "0101",
opt6 when "0110",
opt7 when "0111",
opt8 when "1000",
opt9 when "1001",
opt10 when "1010",
opt11 when "1011",
opt12 when "1100",
opt13 when "1101",
opt14 when "1110",
opt15 when "1111",
opt0 when others;
with ReadAddress2 select
Reg2<=
opt0 when "0000",
opt1 when "0001",
opt2 when "0010",
opt3 when "0011",
opt4 when "0100",
opt5 when "0101",
opt6 when "0110",
opt7 when "0111",
opt8 when "1000",
opt9 when "1001",
opt10 when "1010",
opt11 when "1011",
opt12 when "1100",
opt13 when "1101",
opt14 when "1110",
opt15 when "1111",
opt0 when others;
with WriteAddress select control(0) <= (RegWrite) when "0000", '0' when others;
with WriteAddress select control(1) <= (RegWrite) when "0001", '0' when others;
with WriteAddress select control(2) <= (RegWrite) when "0010", '0' when others;
with WriteAddress select control(3) <= (RegWrite) when "0011", '0' when others;
with WriteAddress select control(4) <= (RegWrite) when "0100", '0' when others;
with WriteAddress select control(5) <= (RegWrite) when "0101", '0' when others;
with WriteAddress select control(6) <= (RegWrite) when "0110", '0' when others;
with WriteAddress select control(7) <= (RegWrite) when "0111", '0' when others;
with WriteAddress select control(8) <= (RegWrite) when "1000", '0' when others;
with WriteAddress select control(9) <= (RegWrite) when "1001", '0' when others;
with WriteAddress select control(10) <= (RegWrite) when "1010", '0' when others;
with WriteAddress select control(11) <= (RegWrite) when "1011", '0' when others;
with WriteAddress select control(12) <= (RegWrite) when "1100", '0' when others;
with WriteAddress select control(13) <= (RegWrite) when "1101", '0' when others;
with WriteAddress select control(14) <= (RegWrite) when "1110", '0' when others;
with WriteAddress select control(15) <= (RegWrite) when "1111", '0' when others;
LED16_test: LED16 port map(
LED_output => LED_output,
input => debug_output
);
vga_reg1 <= opt1;
with sel select
debug_output <=opt0 when "0000",
opt1 when "0001",
opt2 when "0010",
opt3 when "0011",
opt4 when "0100",
opt5 when "0101",
opt6 when "0110",
opt7 when "0111",
opt8 when "1000",
opt9 when "1001",
opt10 when "1010",
opt11 when "1011",
opt12 when "1100",
opt13 when "1101",
opt14 when "1110",
opt15 when "1111",
opt0 when others;
end Behavioral;
| mit | 1ed7441fc9a5df788d17062374eebbdd | 0.643776 | 3.115457 | false | false | false | false |
gregani/la16fw | fifo.vhd | 1 | 16,628 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
----------------------------------------------------------------------------------
--
-- fifo unit for sending data from the sample clock domain to the 48MHz/fx2 domain
--
-- multiple block rams are used which are filled one after the other and sent to
-- the read domain where they are consumed and sent back to the write domain
--
-- WARNING: the block ram acts strange so the input data must
-- be valid until 1 cylcle after the write!
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity fifo is
generic(
ram_count_log2 : integer := 3;
ram_size_log2 : integer := 10
);
port(
reset : in std_logic; -- sync'd to write clock
clk_read : in std_logic;
clk_write : in std_logic;
empty : out std_logic;
almost_empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0)
);
end fifo;
architecture behavioral of fifo is
subtype vector_t is std_logic_vector(2**ram_count_log2-1 downto 0);
subtype vector16_t is std_logic_vector(15 downto 0);
subtype addr_t is unsigned(ram_size_log2-1 downto 0);
type vector16_arr_t is array (natural range <>) of vector16_t;
type addr_arr_t is array (natural range <>) of addr_t;
-- read domain state
signal reset_read_get : std_logic;
signal reset_read_done_set : std_logic := '0';
signal data_out_valid : std_logic;
signal data_out_reg : vector16_t;
signal data_out_reg_valid : std_logic;
signal ram_read_index : unsigned(ram_count_log2-1 downto 0);
signal ram_in_read_domain : unsigned(ram_count_log2 downto 0);
signal ram_in_read_domain_get : std_logic;
signal ram_in_write_domain_set : std_logic := '0';
signal ram_enable_read : vector_t;
signal ram_read_addr : addr_t;
signal ram_read_end : std_logic;
signal ram_data_out : vector16_arr_t(2**ram_count_log2-1 downto 0);
signal ram_data_out_valid : std_logic;
-- write domain state
signal reset_last : std_logic := '0';
signal reset_done : std_logic := '1';
signal reset_read_set : std_logic := '0';
signal reset_read_done_get : std_logic;
signal full_int : std_logic;
signal ram_write_index : unsigned(ram_count_log2-1 downto 0);
signal ram_in_write_domain : unsigned(ram_count_log2 downto 0);
signal ram_in_read_domain_set : std_logic := '0';
signal ram_in_write_domain_get : std_logic;
signal ram_enable_write : vector_t;
signal ram_write_addr : addr_t;
signal ram_write_addr_at_end : std_logic;
signal ram_data_in : vector16_t;
signal will_read_data_out : boolean;
signal want_read_data_out_reg : boolean;
signal will_read_data_out_reg : boolean;
signal want_read_ram_data_out : boolean;
signal will_read_ram_data_out : boolean;
signal end_of_ram : boolean;
signal almost_end_of_ram : boolean;
signal want_read_ram_2 : boolean;
signal will_read_ram_2 : boolean;
begin
gen_ram : for i in 0 to 2**ram_count_log2-1 generate
begin
ramb16bwe_s18_s18_inst : ramb16bwe_s18_s18
port map (
doa => ram_data_out(i), -- port a 16-bit data output
dob => open, -- port b 16-bit data output
dopa => open, -- port a 2-bit parity output
dopb => open, -- port b 2-bit parity output
addra => std_logic_vector(ram_read_addr), -- port a 10-bit address input
addrb => std_logic_vector(ram_write_addr), -- port b 10-bit address input
clka => clk_read, -- port a 1-bit clock
clkb => clk_write, -- port b 1-bit clock
dia => (others=>'0'), -- port a 16-bit data input
dib => ram_data_in, -- port b 16-bit data input
dipa => (others=>'0'), -- port a 2-bit parity input
dipb => (others=>'0'), -- port-b 2-bit parity input
ena => ram_enable_read(i), -- port a 1-bit ram enable input
enb => ram_enable_write(i), -- port b 1-bit ram enable input
ssra => '0', -- port a 1-bit synchronous set/reset input
ssrb => '0', -- port b 1-bit synchronous set/reset input
wea => (others=>'0'), -- port a 2-bit write enable input
web => (others=>'1') -- port b 2-bit write enable input
);
end generate gen_ram;
flag_ram1_inst : entity work.syncflag
port map(
clk_input => clk_write,
clk_output => clk_read,
input => ram_in_read_domain_set,
output => ram_in_read_domain_get
);
flag_ram2_inst : entity work.syncflag
port map(
clk_input => clk_read,
clk_output => clk_write,
input => ram_in_write_domain_set,
output => ram_in_write_domain_get
);
empty <= not data_out_valid;
almost_empty <= (not data_out_valid) or
(data_out_valid and not (data_out_reg_valid or ram_data_out_valid));
full <= full_int;
--data_out <= ram_data_out(to_integer(ram_read_index));
-- synchronize reset signals
flag1_inst : entity work.syncflag
port map(
clk_input => clk_write,
clk_output => clk_read,
input => reset_read_set,
output => reset_read_get
);
flag2_inst : entity work.syncflag
port map(
clk_input => clk_read,
clk_output => clk_write,
input => reset_read_done_set,
output => reset_read_done_get
);
will_read_data_out <= (data_out_valid = '1') and (enable_read = '1');
want_read_data_out_reg <= (data_out_valid = '0') or will_read_data_out;
will_read_data_out_reg <= (data_out_reg_valid = '1') and want_read_data_out_reg;
want_read_ram_data_out <= (data_out_reg_valid = '0') or (will_read_data_out_reg and not will_read_data_out);
will_read_ram_data_out <= (ram_data_out_valid = '1') and want_read_ram_data_out;
almost_end_of_ram <= (data_out_valid = '1') and (unsigned(ram_read_addr) = 2**ram_size_log2-1);
end_of_ram <= (data_out_valid = '1') and (unsigned(ram_read_addr) = 0);
want_read_ram_2 <= (want_read_data_out_reg and (not will_read_data_out_reg)) or will_read_data_out;
will_read_ram_2 <= (ram_in_read_domain /= 0) and want_read_ram_2 and (ram_read_end = '0');
-- read domain
process(clk_read)
-- variable will_read_data_out : boolean;
-- variable want_read_data_out_reg : boolean;
-- variable will_read_data_out_reg : boolean;
-- variable want_read_ram_data_out : boolean;
-- variable will_read_ram_data_out : boolean;
-- variable want_read_ram_2 : boolean;
-- variable will_read_ram_2 : boolean;
variable ram_in_read_domain_inc : boolean;
variable ram_in_read_domain_dec : boolean;
begin
-- will_read_data_out := (data_out_valid = '1') and (enable_read = '1');
-- want_read_data_out_reg := (data_out_valid = '0') or will_read_data_out;
-- will_read_data_out_reg := (data_out_reg_valid = '1') and want_read_data_out_reg;
-- want_read_ram_data_out := (data_out_reg_valid = '0') or will_read_data_out;
-- will_read_ram_data_out := (ram_data_out_valid = '1') and want_read_ram_data_out;
-- --(will_read_data_out or want_read_data_out_reg);
-- --want_read_ram := want_read_ram_data_out;
-- want_read_ram_2 := want_read_data_out_reg and (not will_read_data_out_reg);
-- will_read_ram_2 := (unsigned(ram_in_read_domain) /= 0) and want_read_ram_2;
ram_in_read_domain_inc := false;
ram_in_read_domain_dec := false;
if rising_edge(clk_read) then
-- default value for signals
reset_read_done_set <= '0';
ram_in_write_domain_set <= '0';
ram_enable_read <= (others=>'0');
-- handle read from user
if will_read_data_out then
data_out_valid <= '0';
end if;
-- transfer data from output register to user
if will_read_data_out_reg then
data_out <= data_out_reg;
data_out_valid <= '1';
data_out_reg_valid <= '0';
end if;
-- transfer data from ram to output register or user
if will_read_ram_data_out then
if will_read_data_out then
data_out <= ram_data_out(to_integer(ram_read_index));
data_out_valid <= '1';
else
data_out_reg <= ram_data_out(to_integer(ram_read_index));
data_out_reg_valid <= '1';
end if;
ram_data_out_valid <= '0';
if (ram_read_addr = 0) then
-- ram is emptied with this clock cycle
ram_in_write_domain_set <= '1';
ram_in_read_domain_dec := true;
ram_read_index <= ram_read_index + 1;
end if;
end if;
-- read ram next cycle if data is available and can be transferred one step in the pipeline
if will_read_ram_2 then
-- ask ram to read data next cycle
ram_enable_read(to_integer(ram_read_index)) <= '1';
if (ram_read_addr = 2**ram_size_log2-1) then
ram_read_end <= '1';
if (unsigned(ram_enable_read) /= 0) then
-- already reading last address
ram_enable_read(to_integer(ram_read_index)) <= '0';
end if;
end if;
end if;
if (unsigned(ram_enable_read) /= 0) then
-- ram will read during this cycle, data valid next cycle
ram_data_out_valid <= '1';
ram_read_addr <= ram_read_addr + 1;
end if;
-- start reading next ram if it's available
if (data_out_valid = '0') and (ram_read_end = '1') then
ram_read_end <= '0';
end if;
-- handle flags from write domain
if (ram_in_read_domain_get = '1') then
ram_in_read_domain_inc := true;
end if;
-- increment or decrement ram count if needed
if ram_in_read_domain_inc and not ram_in_read_domain_dec then
ram_in_read_domain <= ram_in_read_domain + 1;
elsif ram_in_read_domain_dec and not ram_in_read_domain_inc then
ram_in_read_domain <= ram_in_read_domain - 1;
end if;
-- reset
if (reset_read_get = '1') then
-- initialize variables
data_out_valid <= '0';
data_out_reg_valid <= '0';
ram_read_index <= (others=>'0');
ram_in_read_domain <= (others=>'0');
ram_read_addr <= (others=>'0');
ram_read_end <= '0';
ram_data_out_valid <= '0';
-- default value for signals
ram_in_write_domain_set <= '0';
ram_enable_read <= (others=>'0');
-- tell write domain that read domain is reset
reset_read_done_set <= '1';
end if;
end if;
end process;
-- write domain
process(clk_write)
variable ram_in_write_domain_inc : boolean;
variable ram_in_write_domain_dec : boolean;
begin
ram_in_write_domain_inc := false;
ram_in_write_domain_dec := false;
if rising_edge(clk_write) then
-- default value for signals
reset_read_set <= '0';
ram_in_read_domain_set <= '0';
ram_enable_write <= (others=>'0');
-- write data to ram
if (full_int = '0') and (enable_write = '1') then
ram_data_in <= data_in;
ram_enable_write(to_integer(ram_write_index)) <= '1';
ram_write_addr <= ram_write_addr + 1;
if (ram_write_addr + 2 = 2**ram_size_log2-1) then
almost_full <= '1';
end if;
-- if (ram_write_addr + 1 = 2**ram_size_log2-1) then
ram_write_addr_at_end <= '0';
if (ram_write_addr + 2 = 2**ram_size_log2-1) then
ram_write_addr_at_end <= '1';
end if;
if (ram_write_addr_at_end = '1') then
-- ram is filled with this clock cycle
ram_in_read_domain_set <= '1';
ram_in_write_domain_dec := true;
ram_write_index <= ram_write_index + 1;
full_int <= '1';
end if;
end if;
-- don't set full/almost_full flag if next ram block is in write domain
if (ram_in_write_domain > 1) then
full_int <= '0';
almost_full <= '0';
end if;
-- handle flags from read domain
if (ram_in_write_domain_get = '1') then
ram_in_write_domain_inc := true;
full_int <= '0';
almost_full <= '0';
end if;
-- increment or decrement ram count if needed
if ram_in_write_domain_inc and not ram_in_write_domain_dec then
ram_in_write_domain <= ram_in_write_domain + 1;
elsif ram_in_write_domain_dec and not ram_in_write_domain_inc then
ram_in_write_domain <= ram_in_write_domain - 1;
end if;
-- reset
reset_last <= reset;
if (reset_last = '0') and (reset = '1') then
-- tell read domain to reset
reset_read_set <= '1';
reset_done <= '0';
end if;
if (reset_read_done_get = '1') then
-- read domain reset
reset_done <= '1';
end if;
if (reset = '1') or (reset_done = '0') then
full_int <= '1';
almost_full <= '1';
-- initialize variables
ram_write_index <= (others=>'0');
ram_in_write_domain <= to_unsigned(2**ram_count_log2, ram_in_write_domain'length);
ram_write_addr <= (others=>'1');
ram_write_addr_at_end <= '0';
-- default value for signals
ram_in_read_domain_set <= '0';
ram_enable_write <= (others=>'0');
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 583a48a5800470006206f5cc5e5094a2 | 0.507397 | 3.773088 | false | false | false | false |
6769/VHDL | Lab_4/Part2/View.vhd | 1 | 1,774 | library ieee;
use ieee.numeric_bit.all;
entity View is
port(Clk_original,Reset,Ldn:in bit;
Din:in unsigned(15 downto 0);
hex0,hex1,hex2,hex3,hex4,hex5:out unsigned(7 downto 0));
end entity View;
architecture Behave of View is
component clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end component;
component Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end component;
component H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end component;
signal mid_second:bit;
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
begin
--point. Hour.Mins.Second
hex0(0)<='1';
hex1(0)<='1';
hex2(0)<='0';
hex3(0)<='1';
hex4(0)<='0';
hex5(0)<='1';
High50Mhz:clock_signal_per_second port map(Clk_original,mid_second);
Core:H24_Min60_Sec60_v2 port map(mid_second,Ldn,Reset,Din,Q);
Hex0_display:Segment7Decoder port map(Second_low,hex0(7 downto 1));
Hex1_display:Segment7Decoder port map(Second_hig,hex1(7 downto 1));
Hex2_display:Segment7Decoder port map(Min_low, hex2(7 downto 1));
Hex3_display:Segment7Decoder port map(Min_hig,hex3(7 downto 1));
Hex4_display:Segment7Decoder port map(Hour_low,hex4(7 downto 1));
Hex5_display:Segment7Decoder port map(Hour_hig,hex5(7 downto 1));
end architecture Behave;
| gpl-2.0 | 1f390a0e2313738d8c8bc57ff1fd5cfd | 0.706313 | 2.8384 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/axi_bram_ctrl.vhd | 1 | 42,433 | -------------------------------------------------------------------------------
-- axi_bram_ctrl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_wrapper.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v3_0)
-- |
-- |--axi_bram_ctrl_top.vhd
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_top;
use work.axi_bram_ctrl_funcs.all;
--use work.coregen_comp_defs.all;
library blk_mem_gen_v8_1;
use blk_mem_gen_v8_1.blk_mem_gen_v8_1;
------------------------------------------------------------------------------
entity axi_bram_ctrl is
generic (
C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal
--determines whether the bmg is external or internal to axi bram ctrl wrapper
C_MEMORY_DEPTH : integer := 4096;
--Memory depth specified by the user
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
C_FAMILY : string := "virtex7";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 1;
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ecc_interrupt : out std_logic := '0';
ecc_ue : out std_logic := '0';
-- axi write address channel Signals (AW)
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi write data channel Signals (W)
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi write data response Channel Signals (B)
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi read address channel Signals (AR)
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi read data channel Signals (R)
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- axi-lite ecc register Interface Signals
-- axi-lite clock and Reset
-- note: axi-lite control IF and AXI IF share the same clock.
-- s_axi_ctrl_aclk : in std_logic;
-- s_axi_ctrl_aresetn : in std_logic;
-- axi-lite write address Channel Signals (AW)
s_axi_ctrl_awvalid : in std_logic;
s_axi_ctrl_awready : out std_logic;
s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- axi-lite write data Channel Signals (W)
s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_wvalid : in std_logic;
s_axi_ctrl_wready : out std_logic;
-- axi-lite write data Response Channel Signals (B)
s_axi_ctrl_bresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_bvalid : out std_logic;
s_axi_ctrl_bready : in std_logic;
-- axi-lite read address Channel Signals (AR)
s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_arvalid : in std_logic;
s_axi_ctrl_arready : out std_logic;
-- axi-lite read data Channel Signals (R)
s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_rresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_rvalid : out std_logic;
s_axi_ctrl_rready : in std_logic;
-- bram interface signals (Port A)
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- bram interface signals (Port B)
bram_rst_b : out std_logic;
bram_clk_b : out std_logic;
bram_en_b : out std_logic;
bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (data_value : integer) RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
-- Set internal parameters for ECC register enabling when C_ECC = 1
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
constant GND : std_logic := '0';
constant VCC : std_logic := '1';
constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0');
constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0');
constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0');
constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0');
constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0');
constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0');
constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0');
constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2);
CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1);
CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal clka_bram_clka_i : std_logic := '0';
signal rsta_bram_rsta_i : std_logic := '0';
signal ena_bram_ena_i : std_logic := '0';
signal REGCEA : std_logic := '0';
signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal clkb_bram_clkb_i : std_logic := '0';
signal rstb_bram_rstb_i : std_logic := '0';
signal enb_bram_enb_i : std_logic := '0';
signal REGCEB : std_logic := '0';
signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-----------------------------------------------------------------------
-- Architecture Body
-----------------------------------------------------------------------
begin
gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE
constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH);
signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal s_axi_dbiterr_bmg_int : STD_LOGIC;
signal s_axi_sbiterr_bmg_int : STD_LOGIC;
signal s_axi_rvalid_bmg_int : STD_LOGIC;
signal s_axi_rlast_bmg_int : STD_LOGIC;
signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_arready_bmg_int : STD_LOGIC;
signal s_axi_bvalid_bmg_int : STD_LOGIC;
signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_wready_bmg_int : STD_LOGIC;
signal s_axi_awready_bmg_int : STD_LOGIC;
signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal dbiterr_bmg_int : STD_LOGIC;
signal sbiterr_bmg_int : STD_LOGIC;
begin
bmgv81_inst : entity blk_mem_gen_v8_1.blk_mem_gen_v8_1
GENERIC MAP(
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_FAMILY,
---- C_ELABORATION_DIR => "NULL" ,
C_INTERFACE_TYPE => 0 ,
--General Memory Parameters:
----- C_ENABLE_32BIT_ADDRESS => 0 ,
C_MEM_TYPE => MEM_TYPE ,
C_BYTE_SIZE => 8 ,
C_ALGORITHM => 1 ,
C_PRIM_TYPE => 1 ,
--Memory Initialization Parameters:
C_LOAD_INIT_FILE => 0 ,
C_INIT_FILE_NAME => "no_coe_file_loaded" ,
C_USE_DEFAULT_DATA => 0 ,
C_DEFAULT_DATA => "NULL" ,
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA => 0 ,
--Enable Parameters:
C_HAS_ENA => 1 ,
C_HAS_REGCEA => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEA => 1 ,
C_WEA_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_A => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_A => C_MEMORY_DEPTH ,
C_READ_DEPTH_A => C_MEMORY_DEPTH ,
C_ADDRA_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB => 0 ,
--Enable Parameters:
C_HAS_ENB => 1 ,
C_HAS_REGCEB => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEB => BWE_B ,
C_WEB_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_B => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_B => C_MEMORY_DEPTH ,
C_READ_DEPTH_B => C_MEMORY_DEPTH ,
C_ADDRB_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A => 0 ,
C_HAS_MEM_OUTPUT_REGS_B => 0 ,
C_HAS_MUX_OUTPUT_REGS_A => 0 ,
C_HAS_MUX_OUTPUT_REGS_B => 0 ,
C_MUX_PIPELINE_STAGES => 0 ,
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 ,
--ECC Parameters
C_USE_ECC => 0 ,
C_USE_SOFTECC => 0 ,
C_HAS_INJECTERR => 0 ,
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK => "NONE" ,
C_COMMON_CLK => 1 ,
C_DISABLE_WARN_BHV_COLL => 1 ,
C_DISABLE_WARN_BHV_RANGE => 1
)
PORT MAP(
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
clka => clka_bram_clka_i ,
rsta => rsta_bram_rsta_i ,
ena => ena_bram_ena_i ,
regcea => GND ,
wea => wea_bram_wea_i ,
addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dina => dina_bram_dina_i ,
douta => douta_bram_douta_i ,
--port b:
clkb => clkb_bram_clkb_i ,
rstb => rstb_bram_rstb_i ,
enb => enb_bram_enb_i ,
regceb => GND ,
web => web_bram_web_i ,
addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dinb => dinb_bram_dinb_i ,
doutb => doutb_bram_doutb_i ,
--ecc:
injectsbiterr => GND ,
injectdbiterr => GND ,
sbiterr => sbiterr_bmg_int,
dbiterr => dbiterr_bmg_int,
rdaddrecc => rdaddrecc_bmg_int,
-- axi bmg input and output Port Declarations
-- axi global signals
s_aclk => GND ,
s_aresetn => GND ,
-- axi full/lite slave write (write side)
s_axi_awid => ZERO4 ,
s_axi_awaddr => ZERO32 ,
s_axi_awlen => ZERO8 ,
s_axi_awsize => ZERO3 ,
s_axi_awburst => ZERO2 ,
s_axi_awvalid => GND ,
s_axi_awready => s_axi_awready_bmg_int,
s_axi_wdata => ZERO64 ,
s_axi_wstrb => WSTRB_ZERO,
s_axi_wlast => GND ,
s_axi_wvalid => GND ,
s_axi_wready => s_axi_wready_bmg_int,
s_axi_bid => s_axi_bid_bmg_int,
s_axi_bresp => s_axi_bresp_bmg_int,
s_axi_bvalid => s_axi_bvalid_bmg_int,
s_axi_bready => GND ,
-- axi full/lite slave read (Write side)
s_axi_arid => ZERO4,
s_axi_araddr => "00000000000000000000000000000000",
s_axi_arlen => "00000000",
s_axi_arsize => "000",
s_axi_arburst => "00",
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready_bmg_int,
s_axi_rid => s_axi_rid_bmg_int,
s_axi_rdata => s_axi_rdata_bmg_int,
s_axi_rresp => s_axi_rresp_bmg_int,
s_axi_rlast => s_axi_rlast_bmg_int,
s_axi_rvalid => s_axi_rvalid_bmg_int,
s_axi_rready => GND ,
-- axi full/lite sideband Signals
s_axi_injectsbiterr => GND ,
s_axi_injectdbiterr => GND ,
s_axi_sbiterr => s_axi_sbiterr_bmg_int,
s_axi_dbiterr => s_axi_dbiterr_bmg_int,
s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int
);
abcv3_0_int_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR ,
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => S_AXI_AWSIZE ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY ,
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR ,
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => S_AXI_ARSIZE ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY ,
-- AXI Read Data Channel Signals (R)
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
-- BRAM Interface Signals (Port A)
BRAM_Rst_A => rsta_bram_rsta_i ,
BRAM_Clk_A => clka_bram_clka_i ,
BRAM_En_A => ena_bram_ena_i ,
BRAM_WE_A => wea_bram_wea_i ,
BRAM_Addr_A => addra_bram_addra_i,
BRAM_WrData_A => dina_bram_dina_i ,
BRAM_RdData_A => douta_bram_douta_i ,
-- BRAM Interface Signals (Port B)
BRAM_Rst_B => rstb_bram_rstb_i ,
BRAM_Clk_B => clkb_bram_clkb_i ,
BRAM_En_B => enb_bram_enb_i ,
BRAM_WE_B => web_bram_web_i ,
BRAM_Addr_B => addrb_bram_addrb_i ,
BRAM_WrData_B => dinb_bram_dinb_i ,
BRAM_RdData_B => doutb_bram_doutb_i
);
-- The following signals are driven 0's to remove the synthesis warnings
bram_rst_a <= '0';
bram_clk_a <= '0';
bram_en_a <= '0';
bram_we_a <= (others => '0');
bram_addr_a <= (others => '0');
bram_wrdata_a <= (others => '0');
bram_rst_b <= '0';
bram_clk_b <= '0';
bram_en_b <= '0';
bram_we_b <= (others => '0');
bram_addr_b <= (others => '0');
bram_wrdata_b <= (others => '0');
END GENERATE gint_inst; -- End of internal bram instance
gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE
abcv3_0_ext_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
ecc_interrupt => ecc_interrupt ,
ecc_ue => ecc_ue ,
-- axi write address channel signals (aw)
s_axi_awid => s_axi_awid ,
s_axi_awaddr => s_axi_awaddr ,
s_axi_awlen => s_axi_awlen ,
s_axi_awsize => s_axi_awsize ,
s_axi_awburst => s_axi_awburst ,
s_axi_awlock => s_axi_awlock ,
s_axi_awcache => s_axi_awcache ,
s_axi_awprot => s_axi_awprot ,
s_axi_awvalid => s_axi_awvalid ,
s_axi_awready => s_axi_awready ,
-- axi write data channel signals (w)
s_axi_wdata => s_axi_wdata ,
s_axi_wstrb => s_axi_wstrb ,
s_axi_wlast => s_axi_wlast ,
s_axi_wvalid => s_axi_wvalid ,
s_axi_wready => s_axi_wready ,
-- axi write data response channel signals (b)
s_axi_bid => s_axi_bid ,
s_axi_bresp => s_axi_bresp ,
s_axi_bvalid => s_axi_bvalid ,
s_axi_bready => s_axi_bready ,
-- axi read address channel signals (ar)
s_axi_arid => s_axi_arid ,
s_axi_araddr => s_axi_araddr ,
s_axi_arlen => s_axi_arlen ,
s_axi_arsize => s_axi_arsize ,
s_axi_arburst => s_axi_arburst ,
s_axi_arlock => s_axi_arlock ,
s_axi_arcache => s_axi_arcache ,
s_axi_arprot => s_axi_arprot ,
s_axi_arvalid => s_axi_arvalid ,
s_axi_arready => s_axi_arready ,
-- axi read data channel signals (r)
s_axi_rid => s_axi_rid ,
s_axi_rdata => s_axi_rdata ,
s_axi_rresp => s_axi_rresp ,
s_axi_rlast => s_axi_rlast ,
s_axi_rvalid => s_axi_rvalid ,
s_axi_rready => s_axi_rready ,
-- axi-lite ecc register interface signals
-- axi-lite write address channel signals (aw)
s_axi_ctrl_awvalid => s_axi_ctrl_awvalid ,
s_axi_ctrl_awready => s_axi_ctrl_awready ,
s_axi_ctrl_awaddr => s_axi_ctrl_awaddr ,
-- axi-lite write data channel signals (w)
s_axi_ctrl_wdata => s_axi_ctrl_wdata ,
s_axi_ctrl_wvalid => s_axi_ctrl_wvalid ,
s_axi_ctrl_wready => s_axi_ctrl_wready ,
-- axi-lite write data response channel signals (b)
s_axi_ctrl_bresp => s_axi_ctrl_bresp ,
s_axi_ctrl_bvalid => s_axi_ctrl_bvalid ,
s_axi_ctrl_bready => s_axi_ctrl_bready ,
-- axi-lite read address channel signals (ar)
s_axi_ctrl_araddr => s_axi_ctrl_araddr ,
s_axi_ctrl_arvalid => s_axi_ctrl_arvalid ,
s_axi_ctrl_arready => s_axi_ctrl_arready ,
-- axi-lite read data channel signals (r)
s_axi_ctrl_rdata => s_axi_ctrl_rdata ,
s_axi_ctrl_rresp => s_axi_ctrl_rresp ,
s_axi_ctrl_rvalid => s_axi_ctrl_rvalid ,
s_axi_ctrl_rready => s_axi_ctrl_rready ,
-- bram interface signals (port a)
bram_rst_a => bram_rst_a ,
bram_clk_a => bram_clk_a ,
bram_en_a => bram_en_a ,
bram_we_a => bram_we_a ,
bram_addr_a => bram_addr_a ,
bram_wrdata_a => bram_wrdata_a ,
bram_rddata_a => bram_rddata_a ,
-- bram interface signals (port b)
bram_rst_b => bram_rst_b ,
bram_clk_b => bram_clk_b ,
bram_en_b => bram_en_b ,
bram_we_b => bram_we_b ,
bram_addr_b => bram_addr_b ,
bram_wrdata_b => bram_wrdata_b ,
bram_rddata_b => bram_rddata_b
);
END GENERATE gext_inst; -- End of internal bram instance
end architecture implementation;
| mit | 337f93060215f991017835261f9152cd | 0.44119 | 3.967184 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/fifo_mem/simulation/checker.vhd | 69 | 5,607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit | 43101c207a698acfbbc810b097e0e506 | 0.589085 | 4.254173 | false | false | false | false |
6769/VHDL | Lab_5/Modelsim/Counter1to6.vhd | 1 | 635 | entity Counter1to6 is
port(clk,limit:in bit;
Carry:out bit;
Count:out integer range 6 downto 1);
end entity Counter1to6;
architecture CountInternal of Counter1to6 is
signal count_value:integer range 6 downto 1;
begin
Count<=count_value;
--Carry<='1' when count_value=6
--else '0';
process(clk,limit)
begin
if(clk'event and clk='1' and limit='1') then
if (count_value=6) then count_value<=1;
else count_value<=count_value+1;
end if;
if(count_value=5) then Carry<='1';
else Carry<='0';
end if;
end if;
end process;
end architecture CountInternal; | gpl-2.0 | 4234631e2a9d74dbba0ab2ec8b46be46 | 0.63937 | 3.395722 | false | false | false | false |
sorgelig/SAMCoupe_MIST | t80/T80_Pack.vhd | 1 | 8,316 | --------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-2.0 | 4cf2a2034a55e2d715a01af4f782a662 | 0.601371 | 3.053985 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/ID_EX.vhd | 1 | 3,225 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:13 11/21/2013
-- Design Name:
-- Module Name: ID_EX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EX is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
ALUopInput : in STD_LOGIC_VECTOR (2 downto 0);
ALUsrcInput : in STD_LOGIC;
TTypeInput : in STD_LOGIC;
TWriteInput : in STD_LOGIC;
MemReadInput : in STD_LOGIC;
MemWriteInput : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
ALUopOutput : out STD_LOGIC_VECTOR (2 downto 0);
ALUsrcOutput : out STD_LOGIC;
TTypeOutput : out STD_LOGIC;
TWriteOutput : out STD_LOGIC;
MemReadOutput : out STD_LOGIC;
MemWriteOutput : out STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
DataInput1 : in STD_LOGIC_VECTOR (15 downto 0);
DataInput2 : in STD_LOGIC_VECTOR (15 downto 0);
ImmediateInput : in STD_LOGIC_VECTOR (15 downto 0);
RegResult: out Int16;
ALUdata1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUdata2 : out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end ID_EX;
architecture Behavioral of ID_EX is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
ALUopOutput <= Int3_Zero;
RegWriteOutput <= '0';
ALUsrcOutput <= '0';
TTypeOutput <= '0';
TWriteOutput <= '0';
MemReadOutput <= '0';
MemWriteOutput <= '0';
MemtoRegOutput <= '0';
RegResult <= Int16_Zero;
retoutput <= '0';
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
ALUopOutput <= ALUopInput;
RegWriteOutput <= RegWriteInput;
ALUsrcOutput <= ALUsrcInput;
TTypeOutput <= TTypeInput;
TWriteOutput <= TWriteInput;
MemReadOutput <= MemReadInput;
MemWriteOutput <= MemWriteInput;
MemtoRegOutput <= MemtoRegInput;
ALUdata1 <= DataInput1;
RegResult <= DataInput2;
if ALUsrcInput = '0' then
ALUdata2 <= DataInput2;
else
ALUdata2 <= ImmediateInput;
end if;
RegReadOutput1 <= RegReadInput1;
RegReadOutput2 <= RegReadInput2;
RegWriteToOutput <= RegWriteToInput;
retoutput <= retinput;
end if;
end if;
end process;
end Behavioral;
| mit | 9ca8064d4d8906319d8d0dff8b090a82 | 0.64 | 3.434505 | false | false | false | false |
6769/VHDL | Lab_1/NumberAnDisplay.vhd | 1 | 1,813 | --partA
--file for first VHDL Documents.!!!
entity NumberAnDisplay is
port(
-- Input ports
V : in bit_vector(3 downto 0);
-- Output ports
z : buffer bit;
M : buffer bit_vector(3 downto 0);
-- 7 Segment Display
segment7:out bit_vector(6 downto 0);
--segment7:out bit_vector();
segment7_point:out bit :='1';
segment7_1:out bit_vector(6 downto 0);
segment7_1_point:out bit :='1'
);
end NumberAnDisplay;
architecture CircuitA_Mux of NumberAnDisplay is
signal midM : bit_vector(2 downto 0);
--assignment about <:='0000'> correspond?
begin
z<= V(3)and (V(2)or V(1));
--circuitA part
midM(0)<=V(0);
midM(1)<=not V(1);
midM(2)<=V(2)and V(1);
--Multiplexer part
M(3)<=(not z) and V(3) ;
M(2)<=((not z) and V(2)) or (z and midM(2));
M(1)<=((not z) and V(1)) or (z and midM(1));
M(0)<=((not z) and V(0)) or (z and midM(0));
--7 Segment Display
process (M)
BEGIN
case M is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
process (z)
BEGIN
case z is
when '0'=> segment7_1 <="1000000"; -- '0'
when '1'=> segment7_1 <="1111001"; -- '1'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end CircuitA_Mux;
| gpl-2.0 | 1f3434a10decc4fe7801f22da3c8d83c | 0.591285 | 2.784946 | false | false | false | false |
6769/VHDL | Lab_2_part2/rotate_shift_register.vhd | 1 | 1,314 | --round shift register;
entity rotate_shift_register is
port(clk,reset: in bit;
--problem is that the predefined value seems didn't assigned
hex0:buffer bit_vector(7 downto 0):="10000001"; --O
hex1:buffer bit_vector(7 downto 0):="10001111"; --L
hex2:buffer bit_vector(7 downto 0):="10001111"; --L
hex3:buffer bit_vector(7 downto 0):="00001101"; --E
hex4:buffer bit_vector(7 downto 0):="00010011"; --H
hex5:buffer bit_vector(7 downto 0):="11111111"; --nothing
hex6:buffer bit_vector(7 downto 0):="11111111"; --
hex7:buffer bit_vector(7 downto 0):="11111111" --nothing
);
end entity rotate_shift_register;
architecture realize of rotate_shift_register is
--component clock_second
-- port(clk:in bit ;
-- second:buffer bit);
--end
begin
process(reset,clk)
begin
if reset='0' then
hex0<="10000001"; --O
hex1<="10001111"; --L
hex2<="10001111"; --L
hex3<="00001101"; --E
hex4<="00010011"; --H
hex5<="11111111"; --nothing
hex6<="11111111"; --
hex7<="11111111"; --nothing
elsif clk'event and clk='1' then
hex0<=hex7;
hex1<=hex0;
hex2<=hex1;
hex3<=hex2;
hex4<=hex3;
hex5<=hex4;
hex6<=hex5;
hex7<=hex6;
end if;
end process;
end architecture realize; | gpl-2.0 | 1aeb78833c03b68f80104ea792909072 | 0.614155 | 3.173913 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/char_mem.vhd | 2 | 5,391 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file char_mem.vhd when simulating
-- the core, char_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY char_mem IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END char_mem;
ARCHITECTURE char_mem_a OF char_mem IS
-- synthesis translate_off
COMPONENT wrapped_char_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_char_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "char_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 24320,
c_read_depth_b => 24320,
c_read_width_a => 1,
c_read_width_b => 1,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 24320,
c_write_depth_b => 24320,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 1,
c_write_width_b => 1,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_char_mem
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END char_mem_a;
| mit | 6aa14cfb59e18b8b49f4ad5dc88767a9 | 0.528659 | 3.978598 | false | false | false | false |
sbates130272/capi-textswap | rtl/afu.vhd | 1 | 14,179 | --------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description:
-- This is the top-level afu block
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
use capi.psl.all;
use capi.std_logic_1164_additions.all;
entity afu is
port (
-- Command Interface
ah_cvalid : out std_logic;
ah_ctag : out std_logic_vector(0 to 7);
ah_ctagpar : out std_logic;
ah_com : out std_logic_vector(0 to 12);
ah_compar : out std_logic;
ah_cabt : out std_logic_vector(0 to 2);
ah_cea : out unsigned(0 to 63);
ah_ceapar : out std_logic;
ah_cch : out std_logic_vector(0 to 15);
ah_csize : out unsigned(0 to 11);
ha_croom : in unsigned(0 to 7);
-- Response Interface
ha_rvalid : in std_logic;
ha_rtag : in std_logic_vector(0 to 7);
ha_rtagpar : in std_logic;
ha_response : in std_logic_vector(0 to 7);
ha_rcredits : in signed(0 to 8);
ha_rcachestate : in std_logic_vector(0 to 1);
ha_rcachepos : in std_logic_vector(0 to 12);
-- Buffer Interface
ha_brvalid : in std_logic;
ha_brtag : in std_logic_vector(0 to 7);
ha_brtagpar : in std_logic;
ha_brad : in unsigned(0 to 5);
ah_brlat : out std_logic_vector(0 to 3);
ah_brdata : out std_logic_vector(0 to 511);
ah_brpar : out std_logic_vector(0 to 7);
ha_bwvalid : in std_logic;
ha_bwtag : in std_logic_vector(0 to 7);
ha_bwtagpar : in std_logic;
ha_bwad : in unsigned(0 to 5);
ha_bwdata : in std_logic_vector(0 to 511);
ha_bwpar : in std_logic_vector(0 to 7);
-- MMIO Interface
ha_mmval : in std_logic;
ha_mmcfg : in std_logic;
ha_mmrnw : in std_logic;
ha_mmdw : in std_logic;
ha_mmad : in unsigned(0 to 23);
ha_mmadpar : in std_logic;
ha_mmdata : in std_logic_vector(0 to 63);
ha_mmdatapar : in std_logic;
ah_mmack : out std_logic;
ah_mmdata : out std_logic_vector(0 to 63);
ah_mmdatapar : out std_logic;
-- Control Interface
ha_jval : in std_logic;
ha_jcom : in std_logic_vector(0 to 7);
ha_jcompar : in std_logic;
ha_jea : in unsigned(0 to 63);
ha_jeapar : in std_logic;
ah_jrunning : out std_logic := '0';
ah_jdone : out std_logic := '0';
ah_jcack : out std_logic := '0';
ah_jerror : out std_logic_vector(0 to 63) := (others=>'0');
ah_jyield : out std_logic := '0';
ah_tbreq : out std_logic := '0';
ah_paren : out std_logic := '1';
ha_pclock : in std_logic
);
end entity afu;
architecture main of afu is
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal reg_addr : unsigned(0 to 23);
signal reg_dw : std_logic;
signal reg_write : std_logic;
signal reg_wdata : std_logic_vector(0 to 63);
signal reg_read : std_logic;
signal reg_rdata : std_logic_vector(0 to 63);
signal reg_read_ack : std_logic;
signal reg_dead_read_ack : std_logic;
signal reg_bv_en : std_logic;
signal reg_bv_rdata : std_logic_vector(0 to 63);
signal reg_bv_read_ack : std_logic;
signal reg_wq_en : std_logic;
signal reg_wq_rdata : std_logic_vector(0 to 63);
signal reg_wq_read_ack : std_logic;
signal reg_sn_en : std_logic;
signal reg_sn_rdata : std_logic_vector(0 to 63);
signal reg_sn_read_ack : std_logic;
signal reg_pr_en : std_logic;
signal reg_pr_rdata : std_logic_vector(0 to 63);
signal reg_pr_read_ack : std_logic;
signal wed_base_addr : unsigned(0 to 63);
signal ah_jdone_next : std_logic;
signal wqueue_done : std_logic;
signal wqueue_done_last : std_logic;
signal proc_clear : std_logic;
signal proc_idata : std_logic_vector(0 to 511);
signal proc_ivalid : std_logic;
signal proc_iready : std_logic := '1';
signal proc_idone : std_logic;
signal proc_odata : std_logic_vector(0 to 511) := (others=>'0');
signal proc_ovalid : std_logic := '0';
signal proc_odirty : std_logic := '1';
signal proc_oready : std_logic;
signal proc_odone : std_logic;
signal proc_len : unsigned(0 to 31);
signal proc_flags : std_logic_vector(0 to 7);
signal ah_cvalid_i : std_logic;
signal ah_ctag_i : std_logic_vector(ah_ctag'range);
signal ah_com_i : std_logic_vector(ah_com'range);
signal ah_cea_i : unsigned(ah_cea'range);
signal ah_csize_i : unsigned(ah_csize'range);
signal timer : unsigned(0 to 63);
begin
ah_cvalid <= ah_cvalid_i;
ah_ctag <= ah_ctag_i;
ah_com <= ah_com_i;
ah_cea <= ah_cea_i;
ah_csize <= ah_csize_i;
JOB: process (ha_pclock) is
begin
if rising_edge(ha_pclock) then
start <= '0';
ah_jdone_next <= '0';
ah_jdone <= ah_jdone_next;
if reset = '1' then
ah_jrunning <= '0';
reset <= '0';
end if;
wqueue_done_last <= wqueue_done;
if wqueue_done = '1' and wqueue_done_last = '0' then
ah_jrunning <= '0';
ah_jdone_next <= '1';
end if;
if ha_jval = '1' then
case ha_jcom is
when PSL_CTRL_CMD_START =>
ah_jrunning <= '1';
wed_base_addr <= unsigned(ha_jea);
start <= '1';
when PSL_CTRL_CMD_RESET =>
ah_jrunning <= '0';
reset <= '1';
ah_jdone_next <= '1';
when others =>
report "Unsupported control command: " & to_hstring(ha_jcom)
severity WARNING;
end case;
end if;
end if;
end process JOB;
TIMER_P: process (ha_pclock) is
begin
if rising_edge(ha_pclock) then
if reset = '1' then
timer <= (others=>'0');
else
timer <= timer + 1;
end if;
end if;
end process TIMER_P;
mmio_i: entity capi.mmio
port map (
ha_pclock => ha_pclock,
reset => reset,
ha_mmval => ha_mmval,
ha_mmcfg => ha_mmcfg,
ha_mmrnw => ha_mmrnw,
ha_mmdw => ha_mmdw,
ha_mmad => ha_mmad,
ha_mmadpar => ha_mmadpar,
ha_mmdata => ha_mmdata,
ha_mmdatapar => ha_mmdatapar,
ah_mmack => ah_mmack,
ah_mmdata => ah_mmdata,
ah_mmdatapar => ah_mmdatapar,
reg_addr => reg_addr,
reg_dw => reg_dw,
reg_write => reg_write,
reg_wdata => reg_wdata,
reg_read => reg_read,
reg_rdata => reg_rdata,
reg_read_ack => reg_read_ack);
reg_rdata <= reg_bv_rdata or
reg_wq_rdata or
reg_sn_rdata or
reg_pr_rdata;
reg_read_ack <= reg_bv_read_ack or
reg_wq_read_ack or
reg_sn_read_ack or
reg_pr_read_ack or
reg_dead_read_ack;
REG_SEL: process (reg_addr, reg_read) is
begin
reg_bv_en <= '0';
reg_wq_en <= '0';
reg_sn_en <= '0';
reg_pr_en <= '0';
reg_dead_read_ack <= '0';
case to_integer(reg_addr(0 to 17)) is
when 0 => reg_bv_en <= '1';
when 1 => reg_wq_en <= '1';
when 2 => reg_sn_en <= '1';
when 3 => reg_pr_en <= '1';
when others => reg_dead_read_ack <= reg_read;
end case;
end process REG_SEL;
build_version_i: entity capi.build_version
port map (
clk => ha_pclock,
reg_en => reg_bv_en,
reg_addr => reg_addr(18 to 23),
reg_dw => reg_dw,
reg_write => reg_write,
reg_wdata => reg_wdata,
reg_read => reg_read,
reg_rdata => reg_bv_rdata,
reg_read_ack => reg_bv_read_ack);
wqueue_i: entity capi.wqueue
port map (
ha_pclock => ha_pclock,
reset => reset,
start => start,
timer => timer,
wed_base_addr => wed_base_addr,
wqueue_done => wqueue_done,
ah_cvalid => ah_cvalid_i,
ah_ctag => ah_ctag_i,
ah_ctagpar => ah_ctagpar,
ah_com => ah_com_i,
ah_compar => ah_compar,
ah_cabt => ah_cabt,
ah_cea => ah_cea_i,
ah_ceapar => ah_ceapar,
ah_cch => ah_cch,
ah_csize => ah_csize_i,
ha_croom => ha_croom,
ha_rvalid => ha_rvalid,
ha_rtag => ha_rtag,
ha_rtagpar => ha_rtagpar,
ha_response => ha_response,
ha_rcredits => ha_rcredits,
ha_rcachestate => ha_rcachestate,
ha_rcachepos => ha_rcachepos,
ha_brvalid => ha_brvalid,
ha_brtag => ha_brtag,
ha_brtagpar => ha_brtagpar,
ha_brad => ha_brad,
ah_brlat => ah_brlat,
ah_brdata => ah_brdata,
ah_brpar => ah_brpar,
ha_bwvalid => ha_bwvalid,
ha_bwtag => ha_bwtag,
ha_bwtagpar => ha_bwtagpar,
ha_bwad => ha_bwad,
ha_bwdata => ha_bwdata,
ha_bwpar => ha_bwpar,
reg_en => reg_wq_en,
reg_addr => reg_addr(18 to 23),
reg_dw => reg_dw,
reg_write => reg_write,
reg_wdata => reg_wdata,
reg_read => reg_read,
reg_rdata => reg_wq_rdata,
reg_read_ack => reg_wq_read_ack,
proc_clear => proc_clear,
proc_idata => proc_idata,
proc_ivalid => proc_ivalid,
proc_iready => proc_iready,
proc_idone => proc_idone,
proc_odata => proc_odata,
proc_ovalid => proc_ovalid,
proc_odirty => proc_odirty,
proc_oready => proc_oready,
proc_odone => proc_odone,
proc_len => proc_len,
proc_flags => proc_flags
);
processors_i: entity work.processors
port map (
clk => ha_pclock,
clear => proc_clear,
idata => proc_idata,
ivalid => proc_ivalid,
idone => proc_idone,
iready => proc_iready,
odata => proc_odata,
ovalid => proc_ovalid,
odirty => proc_odirty,
oready => proc_oready,
odone => proc_odone,
len => proc_len,
flags => proc_flags,
reg_en => reg_pr_en,
reg_addr => reg_addr(18 to 23),
reg_dw => reg_dw,
reg_write => reg_write,
reg_wdata => reg_wdata,
reg_read => reg_read,
reg_rdata => reg_pr_rdata,
reg_read_ack => reg_pr_read_ack);
snooper_i: entity capi.snooper
port map (
ha_pclock => ha_pclock,
reset => reset,
ah_cvalid => ah_cvalid_i,
ah_ctag => ah_ctag_i,
ah_com => ah_com_i,
ah_cea => ah_cea_i,
ah_csize => ah_csize_i,
ha_rvalid => ha_rvalid,
ha_rtag => ha_rtag,
ha_response => ha_response,
ha_rcredits => ha_rcredits,
ha_rcachestate => ha_rcachestate,
ha_rcachepos => ha_rcachepos,
ha_bwvalid => ha_bwvalid,
ha_bwdata => ha_bwdata,
reg_en => reg_sn_en,
reg_addr => reg_addr(18 to 23),
reg_dw => reg_dw,
reg_write => reg_write,
reg_wdata => reg_wdata,
reg_read => reg_read,
reg_rdata => reg_sn_rdata,
reg_read_ack => reg_sn_read_ack
);
end architecture main;
| apache-2.0 | b41f656fb3e47d8398e3db52e384c2a5 | 0.452218 | 3.685729 | false | false | false | false |
1995parham/FPGA-Homework | Project-Phase1/src/sequential/fitness.vhd | 1 | 1,070 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 31-03-2016
-- Module Name: fitness.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fitness is
port (s : in string (1 to 120);
clk, reset : in std_logic;
a, b : out std_logic_vector (4 downto 0);
done : out std_logic);
end entity fitness;
architecture rtl of fitness is
begin
process (clk)
variable I : integer := 1;
begin
if clk'event and clk = '1' then
if I < 120 then
if s(I) = ' ' then
a <= "11010"; -- a = 26
else
a <= std_logic_vector(to_unsigned(character'pos(s(I)) - 96, 5)); -- a = s[i] - 'a'
end if;
if s(I + 1) = ' ' then
b <= "11010"; -- b = 26
else
b <= std_logic_vector(to_unsigned(character'pos(s(I + 1)) - 96, 5)); -- b = s[i + 1] - 'a'
end if;
I := I + 1;
end if;
end if;
end process;
end architecture rtl;
| gpl-3.0 | a685f2fbd71dc3339eeebabdc75d661a | 0.486916 | 3.101449 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/sim/zynq_1_proc_sys_reset_1_0.vhd | 4 | 5,845 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY zynq_1_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zynq_1_proc_sys_reset_1_0;
ARCHITECTURE zynq_1_proc_sys_reset_1_0_arch OF zynq_1_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zynq_1_proc_sys_reset_1_0_arch;
| mit | 90fff818ed50cbb4846a5134dae146e2 | 0.70556 | 3.572738 | false | false | false | false |
frankvanbever/MIPS_processor | ALU.vhd | 1 | 3,635 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:28 02/27/2013
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: 0.1 - first version -- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
--! use logic elements
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_unsigned.all;
--! this is a 32-bit alu with 2 32-bit inputs and a 32 bit output, it also has a zero output bit, it needs 4 control bits from the ALU control to function
entity ALU is
Port ( ALU_Input_1 : in STD_LOGIC_VECTOR (31 downto 0); --! alu input 1 (rs)
ALU_Input_2 : in STD_LOGIC_VECTOR (31 downto 0); --! alu input 2 (rt)
ALU_Zero : out STD_LOGIC; --! alu zero output
ALU_Result : out STD_LOGIC_VECTOR (31 downto 0); --! alu 32 bit output
ALU_Control_In : in STD_LOGIC_VECTOR (3 downto 0) --! input from alu control
);
end ALU;
--! @brief This is a 32 bit ALU for the MIPS processor
--! @details the ALU is able to do following functions: AND,OR, add, substract, set on less then, NOR (see ALU_Control)
--! @details the zero output bit is set if the result of the ALU is 0
architecture Behavioral of ALU is
shared variable Result: Std_logic_vector (31 downto 0); --! Register to store Result of alu
shared variable Result64:Std_logic_vector(63 downto 0);
shared variable Hi:Std_logic_vector(31 downto 0); --! Hi reg for mult
shared variable Lo:Std_logic_vector(31 downto 0); --! Lo reg for mult
begin
ALU_Result_Calc: process(ALU_Input_1,ALU_Input_2,ALU_Control_In)
begin
if (ALU_Control_In = "0000") then
Result := ALU_Input_1 AND ALU_Input_2; -- AND
elsif(ALU_Control_In = "0001") then
Result := ALU_Input_1 OR ALU_Input_2; -- OR
elsif(ALU_Control_In = "0010") then
Result := ALU_Input_1 + ALU_Input_2; -- add
elsif (ALU_Control_In = "0110") then
Result := ALU_Input_1 - ALU_Input_2; -- substract
elsif (ALU_Control_In = "0111") then
if( ( ALU_Input_1 - ALU_Input_2 ) > X"80000000" ) then --if input2 > input1
Result:=X"00000001"; --set result to 1
else -- else (input2<=input1)
Result:=X"00000000"; -- set to zero
end if; -- set on les then calculation
elsif (ALU_Control_In = "1100") then
Result := ALU_Input_1 NOR ALU_Input_2; -- NOR
elsif (ALU_Control_In = "1101") then
Result64 := ALU_Input_1*ALU_Input_2; -- mult
Hi := Result64(63 downto 32);
Lo:=Result64(31 downto 0); -- puts data in registers
Result:=Lo; -- puts the Lo data also in result so can be used to directly write to rd
elsif(ALU_Control_In="1110")then --puts Lo out
Result:=Lo;
elsif(ALU_Control_In="1111")then --puts Hi out
Result:=Hi;
else
Result := X"10101010"; --error code
end if;
--why is the switch case gone here?
-- if(ALU_Control_In="0111")then -- set on less then changes the result
-- if(Result<X"00000000") then --if input2 > input1
-- Result:=X"00000001"; --set result to 1
-- else -- else (input2<=input1)
-- Result:=X"00000000"; -- set to zero
-- end if;
-- end if;
if(Result=X"00000000")then --set the zero line
ALU_Zero<='1';
else
ALU_Zero<='0';
end if;
ALU_Result <=Result;
end process ALU_Result_Calc;
end Behavioral;
| mit | 097ec33f5e9669ee13b7e3f8fad3bab4 | 0.602201 | 3.174672 | false | false | false | false |
sorgelig/SAMCoupe_MIST | sid/mult_acc.vhd | 6 | 7,965 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity mult_acc is
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice3_off_l : in std_logic;
voice3_off_r : in std_logic;
filter_en : in std_logic := '0';
enveloppe : in unsigned(7 downto 0);
waveform : in unsigned(11 downto 0);
--
osc3 : out std_logic_vector(7 downto 0);
env3 : out std_logic_vector(7 downto 0);
--
valid_out : out std_logic;
direct_out_L : out signed(17 downto 0);
direct_out_R : out signed(17 downto 0);
filter_out_L : out signed(17 downto 0);
filter_out_R : out signed(17 downto 0) );
end mult_acc;
-- architecture unsigned_wave of mult_acc is
-- signal filter_m : std_logic;
-- signal voice_m : unsigned(3 downto 0);
-- signal mult_m : unsigned(19 downto 0);
-- signal accu_f : unsigned(17 downto 0);
-- signal accu_u : unsigned(17 downto 0);
-- signal enable_d : std_logic;
-- signal direct_i : unsigned(17 downto 0);
-- signal filter_i : unsigned(17 downto 0);
-- begin
-- process(clock)
-- variable mult_ext : unsigned(21 downto 0);
-- variable mult_trunc : unsigned(21 downto 4);
-- begin
-- if rising_edge(clock) then
-- -- latch outputs
-- if reset='1' then
-- osc3 <= (others => '0');
-- env3 <= (others => '0');
-- elsif voice_i = X"2" then
-- osc3 <= std_logic_vector(waveform(11 downto 4));
-- env3 <= std_logic_vector(enveloppe);
-- end if;
--
-- mult_ext := extend(mult_m, mult_ext'length);
-- mult_trunc := mult_ext(mult_trunc'range);
-- filter_m <= filter_en;
-- voice_m <= voice_i;
-- mult_m <= enveloppe * waveform;
-- valid_out <= '0';
-- enable_d <= enable_i;
--
-- if enable_d='1' then
-- if voice_m = 0 then
-- valid_out <= '1';
-- direct_i <= accu_u;
-- filter_i <= accu_f;
-- if filter_m='1' then
-- accu_f <= mult_trunc;
-- accu_u <= (others => '0');
-- else
-- accu_f <= (others => '0');
-- accu_u <= mult_trunc;
-- end if;
-- else
-- valid_out <= '0';
-- if filter_m='1' then
-- accu_f <= sum_limit(accu_f, mult_trunc);
-- else
-- if (voice_m /= 2) or (voice3_off = '0') then
-- accu_u <= sum_limit(accu_u, mult_trunc);
-- end if;
-- end if;
-- end if;
-- end if;
--
-- if reset = '1' then
-- valid_out <= '0';
-- accu_u <= (others => '0');
-- accu_f <= (others => '0');
-- direct_i <= (others => '0');
-- filter_i <= (others => '0');
-- end if;
-- end if;
-- end process;
--
-- direct_out <= '0' & signed(direct_i(17 downto 1));
-- filter_out <= '0' & signed(filter_i(17 downto 1));
-- end unsigned_wave;
--
architecture signed_wave of mult_acc is
signal filter_m : std_logic;
signal voice_m : unsigned(3 downto 0);
signal mult_m : signed(20 downto 0);
signal accu_fl : signed(17 downto 0);
signal accu_fr : signed(17 downto 0);
signal accu_ul : signed(17 downto 0);
signal accu_ur : signed(17 downto 0);
signal enable_d : std_logic;
begin
process(clock)
variable mult_ext : signed(21 downto 0);
variable mult_trunc : signed(21 downto 4);
variable env_signed : signed(8 downto 0);
variable wave_signed: signed(11 downto 0);
begin
if rising_edge(clock) then
-- latch outputs
if reset='1' then
osc3 <= (others => '0');
env3 <= (others => '0');
elsif voice_i = X"2" then
osc3 <= std_logic_vector(waveform(11 downto 4));
env3 <= std_logic_vector(enveloppe);
end if;
env_signed := '0' & signed(enveloppe);
wave_signed := not waveform(11) & signed(waveform(10 downto 0));
mult_ext := extend(mult_m, mult_ext'length);
mult_trunc := mult_ext(mult_trunc'range);
filter_m <= filter_en;
voice_m <= voice_i;
mult_m <= env_signed * wave_signed;
valid_out <= '0';
enable_d <= enable_i;
if enable_d='1' then
if voice_m = 0 then
valid_out <= '1';
direct_out_l <= accu_ul;
direct_out_r <= accu_ur;
filter_out_l <= accu_fl;
filter_out_r <= accu_fr;
accu_fr <= (others => '0');
accu_ur <= (others => '0');
if filter_m='1' then
accu_fl <= mult_trunc;
accu_ul <= (others => '0');
else
accu_fl <= (others => '0');
accu_ul <= mult_trunc;
end if;
elsif voice_m(3)='0' then
valid_out <= '0';
if filter_m='1' then
accu_fl <= sum_limit(accu_fl, mult_trunc);
else
if (voice_m /= 2) or (voice3_off_l = '0') then
accu_ul <= sum_limit(accu_ul, mult_trunc);
end if;
end if;
else -- upper 8 voices go to right
valid_out <= '0';
if filter_m='1' then
accu_fr <= sum_limit(accu_fr, mult_trunc);
else
if (voice_m /= 10) or (voice3_off_r = '0') then
accu_ur <= sum_limit(accu_ur, mult_trunc);
end if;
end if;
end if;
end if;
if reset = '1' then
valid_out <= '0';
accu_ul <= (others => '0');
accu_fl <= (others => '0');
accu_ur <= (others => '0');
accu_fr <= (others => '0');
direct_out_l <= (others => '0');
direct_out_r <= (others => '0');
filter_out_l <= (others => '0');
filter_out_r <= (others => '0');
end if;
end if;
end process;
end signed_wave;
| gpl-2.0 | e30bc41cb820a43ce8e3a52d08324181 | 0.395355 | 3.900588 | false | false | false | false |
zzhou007/161lab | lab6/CAM_Wrapper.vhd | 1 | 2,264 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Wrapper is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 8 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0);
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end CAM_Wrapper;
architecture Behavioral of CAM_Wrapper is
component CAM_Array is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 4 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end component ;
signal rst_buffered : STD_LOGIC ;
signal we_decoded_row_address_buffered : STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
signal search_word_buffered, dont_care_mask_buffered : STD_LOGIC_VECTOR(CAM_WIDTH-1 downto 0) ;
signal decoded_match_address_sig, decoded_match_address_buffered : STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
begin
decoded_match_address <= decoded_match_address_buffered ;
process(clk, rst, we_decoded_row_address, search_word, dont_care_mask, decoded_match_address_sig)
begin
if(clk'event and clk='1')then
rst_buffered <= rst ;
we_decoded_row_address_buffered <= we_decoded_row_address ;
search_word_buffered <= search_word ;
dont_care_mask_buffered <= dont_care_mask ;
decoded_match_address_buffered <= decoded_match_address_sig ;
end if ;
end process ;
CAM_Array_pmX: CAM_Array generic map (
CAM_WIDTH => CAM_WIDTH,
CAM_DEPTH => CAM_DEPTH
)
port map (
clk => clk ,
rst => rst_buffered ,
we_decoded_row_address => we_decoded_row_address_buffered ,
search_word => search_word_buffered ,
dont_care_mask => dont_care_mask_buffered ,
decoded_match_address => decoded_match_address_sig
);
end Behavioral;
| gpl-2.0 | 192334ca47a3922ecc4f2f8e1abf0902 | 0.674912 | 3.157601 | false | false | false | false |
6769/VHDL | Lab_6/TheFinalCodeVersion/Control_unit.vhd | 2 | 3,986 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
| gpl-2.0 | d71780292469f1e1b95eb09c0f0deaa8 | 0.461114 | 3.697588 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb.vhd | 1 | 4,409 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruction_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruction_Memory_tb_ARCH OF Instruction_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruction_Memory_tb_synth_inst:ENTITY work.Instruction_Memory_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 80287d11321390e4e4882059d4344e16 | 0.609889 | 4.431156 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_SUB_8b.vhd | 1 | 1,906 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_SUB_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_SUB_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis ADD RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(8 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1( 7 downto 0)) - SIGNED('0' & INPUT_2( 7 downto 0)) );
rTemp2 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(15 downto 8)) - SIGNED('0' & INPUT_2(15 downto 8)) );
rTemp3 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(23 downto 16)) - SIGNED('0' & INPUT_2(23 downto 16)) );
rTemp4 := STD_LOGIC_VECTOR( SIGNED('0' & INPUT_1(31 downto 24)) - SIGNED('0' & INPUT_2(31 downto 24)) );
if( rTemp1(8) = '1' ) then rTemp1(7 downto 0) := "00000000"; end if;
if( rTemp2(8) = '1' ) then rTemp2(7 downto 0) := "00000000"; end if;
if( rTemp3(8) = '1' ) then rTemp3(7 downto 0) := "00000000"; end if;
if( rTemp4(8) = '1' ) then rTemp4(7 downto 0) := "00000000"; end if;
OUTPUT_1 <= (rTemp4(7 downto 0) & rTemp3(7 downto 0) & rTemp2(7 downto 0) & rTemp1(7 downto 0));
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 08d206a10a8223bd4bdab4d8ab3ffd3b | 0.538825 | 3.171381 | false | false | false | false |
siam28/neppielight | dvid_out/dvid_out_clocking.vhd | 2 | 4,094 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Description: Generate clocking for sending TMDS data use the OSERDES2
--
-- REMEMBER TO CHECK CLKIN_PERIOD ON PLL_BASE
-- For pixel rates between 25Mhz and 50MHz use the following PLL settings:
-- CLKFBOUT_MULT => 20,
-- CLKOUT0_DIVIDE => 2, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 10, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 20, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 20.0,
--
-- For pixel rates between 40Mhz and 100MHz use the following PLL settings:
-- CLKFBOUT_MULT => 10,
-- CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 10.0,
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity dvid_out_clocking is
Port ( clk_pixel : in STD_LOGIC;
clk_x1 : out STD_LOGIC;
clk_x2 : out STD_LOGIC;
clk_x10 : out STD_LOGIC;
serdes_strobe : out STD_LOGIC);
end dvid_out_clocking;
architecture Behavioral of dvid_out_clocking is
signal clock_local_x1 : std_logic;
signal clock_local_x2 : std_logic;
signal clock_local_x10 : std_logic;
signal clock_x10_unbuffered : std_logic;
signal clock_x2_unbuffered : std_logic;
signal clock_x1_unbuffered : std_logic;
signal clk_feedback : std_logic;
signal clk50_buffered : std_logic;
signal pll_locked : std_logic;
begin
clk_x1 <= clock_local_x1;
clk_x2 <= clock_local_x2;
clk_x10 <= clock_local_x10;
-- Multiply clk50m by 10, then :
-- * divide by 1 for the bit clock (pixel clock x10)
-- * divide by 5 for the pixel clock x2
-- * divide by 10 for the pixel clock
-- Because the all come from the same PLL the will all be in phase
PLL_BASE_inst : PLL_BASE
generic map (
CLKFBOUT_MULT => 10,
CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
CLK_FEEDBACK => "CLKFBOUT",
CLKIN_PERIOD => 10.0,
DIVCLK_DIVIDE => 1
)
port map (
CLKFBOUT => clk_feedback,
CLKOUT0 => clock_x10_unbuffered,
CLKOUT1 => clock_x2_unbuffered,
CLKOUT2 => clock_x1_unbuffered,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pll_locked,
CLKFBIN => clk_feedback,
CLKIN => clk_pixel,
RST => '0'
);
BUFG_pclockx2 : BUFG port map ( I => clock_x2_unbuffered, O => clock_local_x2);
BUFG_pclock : BUFG port map ( I => clock_x1_unbuffered, O => clock_local_x1);
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8) !!!! IMPORTANT TO CHANGE THIS AS NEEDED !!!!
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- should be true
)
port map (
IOCLK => clock_local_x10, -- Clock used to send bits
LOCK => open,
SERDESSTROBE => serdes_strobe, -- Clock use to load data into SERDES
GCLK => clock_local_x2, -- Global clock use as a reference for serdes_strobe
LOCKED => pll_locked, -- When the upstream PLL is locked
PLLIN => clock_x10_unbuffered -- What clock to use - this must be unbuffered
);
end Behavioral; | gpl-2.0 | 54d828f45d7337bfb065266c409a9a3d | 0.561065 | 3.759412 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_9_dir/exercise5_9.vhd | 1 | 1,674 | --!
--! @file: exercise5_9.vhd
--! @brief: alu using when
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity alu is
generic
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic_vector(N-1 downto 0);
opcode: in std_logic_vector(3 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity alu;
--------------------------------------
architecture circuit of alu is
signal a_sig, b_sig: signed(N-1 downto 0);
signal y_unsig: std_logic_vector(N-1 downto 0);
signal y_sig: signed(N-1 downto 0);
signal small_int: integer range 0 to 1;
begin
-- logic unit --
y_unsig <= not a when "000" else
not b when "001" else
a and b when "010" else
a or b when "011" else
a nand b when "100" else
a nor b when "101" else
a xor b when "110" else
a xnor b;
-- arithmetic unit
a_sig <= signed(a);
b_sig <= signed(b);
small_int <= 1 when cin='1' else 0;
y_sig <= a_sig when "000" else
b_sig when "001" else
a_sig + 1 when "010" else
b_sig + 1 when "011" else
a_sig - 1 when "100" else
b_sig - 1 when "101" else
a_sig + b_sig when "110" else
a_sig + b_sig + small_int;
-- mux
y <= y_unsig when opcode(3)='0' else std_logic_vector(y_sig);
end architecture circuit;
| gpl-3.0 | dcf74425cd2d7fec26031955d7d0728a | 0.479092 | 3.647059 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/sequ_alu_1.vhd | 1 | 6,726 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.mlite_pack.all;
entity sequ_alu_1 is
port(
clk : in std_logic;
reset_in : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in std_logic_vector( 5 downto 0);
c_alu : out std_logic_vector(31 downto 0);
pause_out : out std_logic
);
end; --sequ_alu_1
architecture logic of sequ_alu_1 is
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
-- COMPONENT PGDC_32b
-- PORT(
-- rst : in STD_LOGIC;
-- clk : in STD_LOGIC;
-- start : in STD_LOGIC;
-- INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
-- INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
-- working : out std_logic;
-- OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
-- );
-- END COMPONENT;
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
function chr_one_zero(int: std_logic) return character is
variable c: character;
begin
case int is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
return c;
end chr_one_zero;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function bin_char(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
variable bitv : std_logic;
begin
r := 1;
for i in slv'range loop
bitv := slv(i);
result(r) := chr_one_zero( bitv );
r := r + 1;
end loop;
return result;
end bin_char;
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
-- SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
-- SIGNAL sSTART_1 : STD_LOGIC;
-- SIGNAL PAUSE_1 : STD_LOGIC;
-- SIGNAL pPAUSE_1 : STD_LOGIC;
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
signal counter : unsigned(2 downto 0) := (others =>'0');
signal busy, count_busy, init_count : std_logic := '0';
signal tmp, tmp1 : std_logic_vector(31 downto 0) := (others =>'0');
type state_type is (s_wait,s_init_counter,s_processing); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset_in)
begin
if (reset_in='1') then
current_s <= s_wait; --default state on reset_in.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s, alu_function(0), count_busy)
begin
case current_s is
when s_wait =>
if((count_busy ='0') and (alu_function(0) = '0')) then
busy <= '0';
init_count <= '0';
next_s <= s_wait;
else
busy <= '1';
init_count <= '1';
next_s <= s_init_counter;
end if;
when s_init_counter =>
busy <= '1';
init_count <= '0';
next_s <= s_processing;
when s_processing =>
if(count_busy ='1') then
busy <= '1';
init_count <= '0';
next_s <= s_processing;
else
busy <= '0';
init_count <= '0';
next_s <= s_wait;
end if;
end case;
end process;
--assert (alu_function(0)/='1') severity error;
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
-- WAIT FOR 1 ns;
-- printmsg("(IMS) COMBINATOIRE EXTENSION (1) : ALLOCATION OK !");
-- WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
counting : process(clk, reset_in)
begin
if (reset_in = '1') then
counter <= (others =>'0');
count_busy <= '0';
elsif clk'event and clk = '1' then
if(init_count = '1') then
counter <= (others =>'0');
count_busy <= '1';
elsif(counter = "010") then
counter <= counter;
count_busy <= '0';
else
counter <= counter + to_unsigned(1,2);
count_busy <= '1';
end if;
end if;
end process;
--c_alu <= ("00000000000000000000000000000"&std_logic_vector(counter)) when busy = '1' or alu_function(0) = '1' else (others =>'0');
c_alu <= tmp1 when busy = '1' or alu_function(0) = '1' else (others =>'0');
pause_out <= busy;
--busy <= '1' when (counter /= "000") and (counter /= "111") else '0';
--pause_out <= '1' WHEN (alu_function(0) = '1') OR (busy= '1') ELSE '0';
mini_pipe : process(clk, reset_in)
begin
if (reset_in = '1') then
tmp <= (others =>'0');
tmp1 <= (others =>'0');
-- c_alu <= (others =>'0');
elsif clk'event and clk = '1' then
--if(busy = '1') then
tmp <= std_logic_vector(unsigned(a_in) + to_unsigned(3,2));
tmp1 <= std_logic_vector(unsigned(tmp) + to_unsigned(1,2));
-- if(busy = '1') then
-- report "tmp: "&bin_char(tmp);
-- report "a_in "&bin_char(a_in);
-- end if;
-- c_alu <= tmp1;
--end if;
end if;
end process;
-- --c_alu <= tmp when alu_function(0) = '1' else (others =>'0');
-- c_alu <= tmp when busy = '1' else (others =>'0');
--c_alu <= "00000000000000000000000000000000";
--sSTART_1 <= (not pPAUSE_1) AND alu_function(0);
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
-- RESOURCE_1 : PGDC_32b PORT MAP (reset_in, clk, sSTART_1, a_in, b_in, PAUSE_1, RESULT_1);
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-- REG : process(clk, reset_in)
-- begin
-- if (reset_in = '1') then
-- pPAUSE_1 <= '0';
-- elsif clk'event and clk = '1' then
-- pPAUSE_1 <= PAUSE_1;
-- end if;
-- end process;
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
--c_alu <=
--RESULT_1 WHEN pPAUSE_1 = '1' ELSE
--"00000000000000000000000000000000";
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
-- pause_out <= '0'; --PAUSE_1; -- OR (alu_function(0) AND (NOT pPAUSE_1(0)));
end; --architecture logic
| gpl-3.0 | c6c2252891bdb3ccbe82320e39d34306 | 0.515016 | 3.33631 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example4_dir/fsm_timer_tb.vhd | 1 | 2,555 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity fsm_timer_tb is
end entity fsm_timer_tb;
--------------------------------------
architecture circuit of fsm_timer_tb is
-- dut declaration
component simple_car_alarm is
port (
clk, rst, remote, sensors: in std_logic;
siren: out std_logic);
end component simple_car_alarm;
-- signal declaration
signal clk_tb: std_logic := '0';
signal rst_tb, remote_tb, sensors_tb: std_logic;
signal siren_tb: std_logic;
begin
-- dut instantiation
dut: simple_car_alarm port map (
clk => clk_tb,
rst => rst_tb,
remote => remote_tb,
sensors => sensors_tb,
siren => siren_tb
);
-- stimuli generation
-- clk
clk_tb <= not clk_tb after 20 ns;
-- rst
rst_tb <= '1', '0' after 40 ns;
-- remote
remote_tb <= '0', '1' after 160 ns, '0' after 200 ns, '1' after 240 ns, '0' after 320 ns, '1' after 400 ns, '0' after 480 ns, '1' after 680 ns, '0' after 800 ns;
-- sensors
sensors_tb <= '0', '1' after 560 ns, '0' after 640 ns;
-- output comparison check
--
-- process
-- --declarativepart
-- begin
--
-- -- 0 ns = disarmed
-- assert pr_state = disarmed
-- report "error initial state not disarmed"
-- severity failure;
--
--
-- -- 180 ns = armed
--
-- wait for 180 ns;
-- assert pr_state = armed
-- report "error state not armed"
-- severity failure;
--
--
-- -- 260 ns = disarmed
-- wait for 80 ns;
--
-- assert pr_state = disarmed
-- report "error state not disarmed"
-- severity failure;
--
--
-- -- 420 ns = armed
-- wait for 160 ns;
--
-- assert pr_state = armed
-- report "error state not armed"
-- severity failure;
--
-- -- 580 ns = intrusion
-- wait for 160 ns;
--
-- assert pr_state = intrusion
-- report "error state not intrusion"
-- severity failure;
--
-- -- 700 ns = intrusion
-- wait for 120 ns;
--
-- assert pr_state = disarmed
-- report "error state not intrusion"
-- severity failure;
--
--
-- -- testbench passed
-- assert false
-- report "testbench passed"
-- severity note;
--
-- -- wait forever
-- wait;
--
-- end process;
end architecture circuit;
| gpl-3.0 | 89902168f0d4ab3e77a1db10d9fd0430 | 0.508023 | 3.73538 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_gpio/src/gpio_vvc.vhd | 1 | 17,970 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.gpio_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity gpio_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH;
GC_INSTANCE_IDX : natural;
GC_DEFAULT_LINE_VALUE : std_logic_vector(GC_DATA_WIDTH-1 downto 0);
GC_GPIO_BFM_CONFIG : t_gpio_bfm_config := C_GPIO_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
gpio_vvc_if : inout std_logic_vector(GC_DATA_WIDTH-1 downto 0) := GC_DEFAULT_LINE_VALUE
);
end entity gpio_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of gpio_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_gpio_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_gpio_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_gpio_transaction_info(GC_INSTANCE_IDX);
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_GPIO_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
wait for 0 ns;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = SET or v_cmd.operation = GET or v_cmd.operation = CHECK or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is
when SET =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "gpio_set() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_set(data_value => v_normalised_data,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when GET =>
gpio_get(data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "gpio_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when EXPECT =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "gpio_expect() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH-1 downto 0) := v_normalised_data;
gpio_expect(data_exp => v_normalised_data,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
data_port => gpio_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
config => vvc_config.bfm_config,
msg_id_panel => vvc_config.msg_id_panel);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
end behave;
| mit | 8d7b6aa34ac109db6ed7fbbafe087e05 | 0.514691 | 4.352143 | false | true | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/alu.vhd | 1 | 3,653 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.numeric_std.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
sum <= STD_LOGIC_VECTOR( RESIZE(SIGNED(a_in), 33) + RESIZE(SIGNED(b_in), 33) ) WHEN alu_function = ALU_ADD
ELSE STD_LOGIC_VECTOR( RESIZE(SIGNED(a_in), 33) - RESIZE(SIGNED(b_in), 33) );
--sum <= bv_adder(a_in, b_in, do_add);
do_add <= '1' when alu_function = ALU_ADD else '0';
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
less_than <= sum(32) when (a_in(31) = b_in(31)) or (alu_function = ALU_LESS_THAN) else a_in(31);
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function = ALU_ADD or alu_function = ALU_SUBTRACT else
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
ZERO(31 downto 1) & less_than when alu_function = ALU_LESS_THAN or alu_function = ALU_LESS_THAN_SIGNED else
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
a_in or b_in when alu_function=ALU_OR else
-- BEGIN ENABLE_(AND,ANDI)
a_in and b_in when alu_function=ALU_AND else
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
a_in xor b_in when alu_function=ALU_XOR else
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
a_in nor b_in when alu_function=ALU_NOR else
-- END ENABLE_(NOR)
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum (31 downto 0) when alu_function = ALU_ADD or alu_function = ALU_SUBTRACT else (others => 'Z');
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
c_alu <= ZERO(31 downto 1) & less_than when alu_function = ALU_LESS_THAN or alu_function = ALU_LESS_THAN_SIGNED else (others => 'Z');
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
c_alu <= a_in or b_in when alu_function = ALU_OR else (others => 'Z');
-- BEGIN ENABLE_(AND,ANDI)
c_alu <= a_in and b_in when alu_function = ALU_AND else (others => 'Z');
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
c_alu <= a_in xor b_in when alu_function = ALU_XOR else (others => 'Z');
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
c_alu <= a_in nor b_in when alu_function = ALU_NOR else (others => 'Z');
-- END ENABLE_(NOR)
c_alu <= ZERO when alu_function = ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 | 84958e12edc24e8841757d41ef21ef4d | 0.530249 | 3.567383 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/example8_2_dir/example8_2.vhd | 1 | 2,967 | --!
--! @file: example8_2.vhd
--! @brief: circular shift register with component
--! @author: Antonio Gutierrez
--! @date: 2013-11-21
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
-- mux --
--------------------------------------
entity mux is
port (
a, b, sel: in bit;
x: out bit);
end entity mux;
--------------------------------------
architecture circuit of mux is
begin
x <= a when sel = '0' else b;
end architecture circuit;
--------------------------------------
-- flip flop --
--------------------------------------
entity flipflop is
port (
d, clk: in bit;
q: out bit);
end entity flipflop;
--------------------------------------
architecture circuit of flipflop is
begin
proc: process (clk)
begin
if (clk'event and clk = '1') then
q <= d;
end if;
end process proc;
end architecture circuit;
--------------------------------------
-- main code --
--------------------------------------
entity circular_shift is
port (
clk, load: in bit;
d: in bit_vector(0 to 3);
q: buffer bit_vector(0 to 3));
end entity circular_shift;
--------------------------------------
architecture circuit of circular_shift is
signal i: bit_vector(0 to 3);
--------------------------------------
-- component mux declaration --
component mux is
port (
a, b, sel: in bit;
x: out bit);
end component mux;
--------------------------------------
-- component flipflop declaration --
component flipflop is
port (
d, clk: in bit;
q: out bit);
end component flipflop;
--------------------------------------
begin
-- component mux instantiation
mux0: mux
port map (
a => q(3),
b => d(0),
sel => load,
x => i(0)
);
-- component mux instantiation
mux1: mux
port map (
a => q(0),
b => d(1),
sel => load,
x => i(1)
);
-- component mux instantiation
mux2: mux
port map (
a => q(1),
b => d(2),
sel => load,
x => i(2)
);
-- component mux instantiation
mux3: mux
port map (
a => q(2),
b => d(3),
sel => load,
x => i(3)
);
-- component flipflop instantiation
dff0: flipflop
port map (
d => i(0),
clk => clk,
q => q(0)
);
-- component flipflop instantiation
dff1: flipflop
port map (
d => i(1),
clk => clk,
q => q(1)
);
-- component flipflop instantiation
dff2: flipflop
port map (
d => i(2),
clk => clk,
q => q(2)
);
-- component flipflop instantiation
dff3: flipflop
port map (
d => i(3),
clk => clk,
q => q(3)
);
end architecture circuit;
| gpl-3.0 | 06383637a93e439a4a175379ad563c7d | 0.42029 | 4.287572 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/simulation/pcie_in.vhd | 1 | 3,236 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
--use work.mlite_pack.all;
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
LIBRARY work;
USE work.txt_util.ALL;
ENTITY PCIE_IN IS
PORT(
clk : IN STD_LOGIC;
fifo_out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_read_en : IN STD_LOGIC;
fifo_full : OUT STD_LOGIC;
fifo_empty : OUT STD_LOGIC;
fifo_valid : OUT STD_LOGIC
);
END;
ARCHITECTURE logic OF PCIE_IN IS
BEGIN
PROCESS
FILE data_file : TEXT OPEN read_mode IS "pcie_in.txt";
VARIABLE data_line : STRING(1 TO 32);
BEGIN
REPORT "COUCOU" SEVERITY note;
--
-- ON REGARDE SI LE FICHIER EST FOURNI ...
--
IF NOT endfile(data_file) THEN
str_read(data_file, data_line);
fifo_out_data <= TO_STD_LOGIC_VECTOR(data_line(1 TO 32));
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, 32));
fifo_full <= '0';
fifo_valid <= '1';
IF NOT endfile(data_file) THEN
fifo_empty <= '0';
ELSE
fifo_empty <= '1';
END IF;
ELSE
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_full <= '0';
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
--
-- TANT QU'IL RESTE DES DONNEES DANS LE FICHIER, ON ATTEND QUE LE PROCESSEUR
-- VIENNE LES LIRE ...
--
WAIT UNTIL RISING_EDGE(CLK);
WHILE NOT endfile(data_file) LOOP
WAIT UNTIL RISING_EDGE(CLK);
IF fifo_read_en = '1' THEN
--
-- ON SOUHAITE LE PASSAGE A LA DONNEE SUIVANTE.
--
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_valid <= '0';
fifo_empty <= '1';
-- REPORT "Waiting N clock cycles" SEVERITY note;
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
WAIT UNTIL RISING_EDGE(CLK);
IF NOT endfile(data_file) THEN
str_read(data_file, data_line);
fifo_out_data <= TO_STD_LOGIC_VECTOR(data_line(1 TO 32));
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, 32));
fifo_valid <= '1';
fifo_empty <= '0';
ELSE
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
END IF;
END LOOP;
WHILE endfile(data_file) LOOP
WAIT UNTIL RISING_EDGE(CLK);
IF fifo_read_en = '1' THEN
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
END LOOP;
--
-- UNE FOIS QUE TOUTES LES DONNEES ONT ETE TRAITEES, ON SE "BLOQUE"
--
-- REPORT "## ON N'A PLUS DE DONNEES ##";
WHILE endfile(data_file) LOOP
WAIT UNTIL rising_edge(clk);
fifo_valid <= '0';
fifo_empty <= '1';
-- if fifo_write_en = '1' then
-- end if;
END LOOP;
END PROCESS;
--fifo_valid <= '0';
fifo_full <= '0';
--fifo_compteur <= (OTHERS => '0');
END; --architecture logic
| gpl-3.0 | a5336b7b99b11aae8a67faccb88bbce5 | 0.619283 | 2.923216 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/synthese/ipbus_ldpc_asip_v2.vhd | 1 | 15,922 | -- Generic ipbus ram block for testing
--
-- generic addr_width defines number of significant address bits
--
-- In order to allow Xilinx block RAM to be inferred:
-- Reset does not clear the RAM contents (not implementable in Xilinx)
-- There is one cycle of latency on the read / write
--
-- Note that the synthesis tool should automatically infer block or distributed RAM
-- according to the size requested. It is likely that it will NOT choose
-- an efficient implementation in terms of area / speed / power, so don't use this
-- method to infer large RAMs (noting also that reads are enabled at all times).
-- It's best to use the block ram core generator explicitly.
--
-- Occupies addr_width bits of ipbus address space
-- This RAM cannot be used with 100% bus utilisation due to the wait state
--
-- Dave Newbold, March 2011
--
-- $Id: ipbus_ram.vhd 324 2011-04-25 19:37:43Z phdmn $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;
entity ipbus_ldpc_asip_v2 is
generic(addr_width : positive);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
i_uart : in STD_LOGIC;
o_uart : out STD_LOGIC;
gpio : out STD_LOGIC_VECTOR(7 DOWNTO 0);
ipbus_in : in ipb_wbus;
ipbus_out: out ipb_rbus
);
end ipbus_ldpc_asip_v2;
architecture rtl of ipbus_ldpc_asip_v2 is
COMPONENT fifo_256_words
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_1024_words
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_2048_words
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_4096_words
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_16384_words
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
COMPONENT plasma
GENERIC(
memory_type : string := "DUAL_PORT_";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '1';
use_cache : std_logic := '0'
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
uart_read : IN std_logic;
uart_write : OUT std_logic;
--
-- FIFO QUI CONTIENT LES INFORMATIONS DE PROGRAMMATION
--
fifo_1_out_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_empty : IN STD_LOGIC;
fifo_1_alm_empty : IN STD_LOGIC;
fifo_1_valid : IN STD_LOGIC;
fifo_1_full : IN STD_LOGIC;
fifo_1_read_en : OUT STD_LOGIC;
--
-- FIFO QUI CONTIENT LES LLRs A TRAITER
--
fifo_d_out_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
fifo_d_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_d_empty : IN STD_LOGIC;
fifo_d_alm_empty : IN STD_LOGIC;
fifo_d_valid : IN STD_LOGIC;
fifo_d_full : IN STD_LOGIC;
fifo_d_read_en : OUT STD_LOGIC;
--
-- FIFO QUI CONTIENDRA LES DECISIONS DURES
--
fifo_2_in_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_2_write_en : OUT STD_LOGIC;
fifo_2_full : IN STD_LOGIC;
gpioA_in : IN std_logic_vector(31 downto 0);
gpio0_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal w_ctr, r_ctr: unsigned(31 downto 0);
signal ack: std_logic;
signal sel: integer;
SIGNAL ififo_din : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FROM THE PC
SIGNAL ififo_wr_en : STD_LOGIC;
SIGNAL ififo_rd_en : STD_LOGIC;
SIGNAL ififo_empty : STD_LOGIC;
SIGNAL ififo_almty : STD_LOGIC;
SIGNAL ififo_full : STD_LOGIC;
SIGNAL ififo_dout : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL ififo_valid : STD_LOGIC;
SIGNAL ififo_data_count : STD_LOGIC_VECTOR( 8 DOWNTO 0);
SIGNAL ififo_compteur : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL dfifo_din : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FROM THE PC
SIGNAL dfifo_wr_en : STD_LOGIC;
SIGNAL dfifo_rd_en : STD_LOGIC;
SIGNAL dfifo_empty : STD_LOGIC;
SIGNAL dfifo_almty : STD_LOGIC;
SIGNAL dfifo_full : STD_LOGIC;
SIGNAL dfifo_dout : STD_LOGIC_VECTOR( 7 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL dfifo_valid : STD_LOGIC;
SIGNAL dfifo_data_count : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL dfifo_compteur : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL ofifo_din : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FROM THE PC
SIGNAL ofifo_wr_en : STD_LOGIC;
SIGNAL ofifo_rd_en : STD_LOGIC;
SIGNAL ofifo_empty : STD_LOGIC;
SIGNAL ofifo_almty : STD_LOGIC;
SIGNAL ofifo_full : STD_LOGIC;
SIGNAL ofifo_dout : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL ofifo_valid : STD_LOGIC;
SIGNAL ofifo_data_count : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL ofifo_compteur : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
SIGNAL soft_reset : STD_LOGIC;
SIGNAL reset_signal : STD_LOGIC;
SIGNAL gpio_sig : STD_LOGIC_VECTOR(31 DOWNTO 0); -- DATA FOR THE VHDL DESIGN
signal address: integer;
BEGIN
reset_signal <= soft_reset or reset;
process(clk)
begin
if rising_edge(clk) then
if reset_signal='1' then
w_ctr <= (others=>'0');
r_ctr <= (others=>'0');
elsif ipbus_in.ipb_strobe='1' then
if ipbus_in.ipb_write='1' then
w_ctr <= w_ctr + 1;
else
r_ctr <= r_ctr + 1;
end if;
end if;
-- ipbus_out.ipb_rdata <= std_logic_vector(w_ctr) & std_logic_vector(r_ctr);
-- ack <= ipbus_in.ipb_strobe and not ack;
end if;
end process;
-- CONNECTION DES SIGNAUX
sel <= to_integer(unsigned(ipbus_in.ipb_addr(addr_width-1 downto 0)));
WITH sel SELECT
ipbus_out.ipb_rdata <=
-- x"9ABCDEF0" WHEN 0,
ififo_compteur WHEN 1,
dfifo_compteur WHEN 2,
ofifo_compteur WHEN 3,
-- '1'; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- '1'; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
ofifo_dout WHEN 6,
std_logic_vector(r_ctr) WHEN 7,
std_logic_vector(w_ctr) WHEN 8,
-- '1';
"0000000000000000000000000000000" & ififo_empty WHEN 10,
"0000000000000000000000000000000" & ififo_full WHEN 11,
"0000000000000000000000000000000" & ififo_valid WHEN 12,
"0000000000000000000000000000000" & dfifo_empty WHEN 13,
"0000000000000000000000000000000" & dfifo_full WHEN 14,
"0000000000000000000000000000000" & dfifo_valid WHEN 15,
"0000000000000000000000000000000" & ofifo_empty WHEN 16,
"0000000000000000000000000000000" & ofifo_full WHEN 17,
"0000000000000000000000000000000" & ofifo_valid WHEN 18,
STD_LOGIC_VECTOR( TO_UNSIGNED( 256, 32) ) WHEN 19,
STD_LOGIC_VECTOR( TO_UNSIGNED(16384, 32) ) WHEN 20,
STD_LOGIC_VECTOR( TO_UNSIGNED( 2048, 32) ) WHEN 21,
x"9ABCDEF0" WHEN OTHERS;
WITH sel SELECT
ofifo_rd_en <= ipbus_in.ipb_strobe WHEN 6, '0' WHEN OTHERS;
process(clk)
begin
if rising_edge(clk) then
ififo_din <= ipbus_in.ipb_wdata;
ififo_wr_en <= '0';
dfifo_din <= ipbus_in.ipb_wdata;
dfifo_wr_en <= '0';
-- ofifo_rd_en <= '0';
soft_reset <= '0';
if ipbus_in.ipb_strobe='1' and ipbus_in.ipb_write='1' then
CASE sel IS
WHEN 4 => ififo_wr_en <= ipbus_in.ipb_strobe; --not ack; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
WHEN 5 => dfifo_wr_en <= ipbus_in.ipb_strobe; --not ack; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
WHEN 9 => soft_reset <= ipbus_in.ipb_strobe; --not ack;
WHEN OTHERS => NULL;
end case;
end if;
-- if ipbus_in.ipb_strobe='1' and ipbus_in.ipb_write='0' then
-- CASE sel IS
-- WHEN 0 => ipbus_out.ipb_rdata <= x"9ABCDEF0"; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 1 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(ififo_data_count), 32)); -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 2 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(dfifo_data_count), 32)); -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 3 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(ofifo_data_count), 32)); -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
---- WHEN 4 => ififo_wr_en <= '1'; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
---- WHEN 5 => dfifo_wr_en <= '1'; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 6 => ipbus_out.ipb_rdata <= ofifo_dout; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- ofifo_rd_en <= not ack;
-- WHEN 7 => ipbus_out.ipb_rdata <= std_logic_vector(r_ctr); -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 8 => ipbus_out.ipb_rdata <= std_logic_vector(w_ctr); -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
---- WHEN 9 => soft_reset <= '1';
-- WHEN 10 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ififo_empty; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 11 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ififo_full; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 12 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ififo_valid; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 13 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & dfifo_empty; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 14 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & dfifo_full; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 15 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & dfifo_valid; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 16 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ofifo_empty; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 17 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ofifo_full; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 18 => ipbus_out.ipb_rdata <= "0000000000000000000000000000000" & ofifo_valid; -- CODE SPECIFIQUE AU COMPOSANT VHDL CABLE
-- WHEN 19 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR( TO_UNSIGNED( 256, 32) );
-- WHEN 20 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR( TO_UNSIGNED(16384, 32) );
-- WHEN 21 => ipbus_out.ipb_rdata <= STD_LOGIC_VECTOR( TO_UNSIGNED( 2048, 32) );
-- WHEN OTHERS => NULL;
---- reg(sel) <= ipbus_in.ipb_wdata;
-- end case;
-- end if;
-- ipbus_out.ipb_rdata <= reg(sel);
-- ack <= ipbus_in.ipb_strobe and not ack;
end if;
end process;
ififo : fifo_256_words
PORT MAP (
clk => clk,
rst => reset_signal,
din => ififo_din, -- DATA FROM THE PC
wr_en => ififo_wr_en,
rd_en => ififo_rd_en,
dout => ififo_dout, -- DATA FOR THE VHDL DESIGN
full => ififo_full,
empty => ififo_empty,
almost_empty => ififo_almty,
valid => ififo_valid,
data_count => ififo_data_count
);
dfifo : fifo_16384_words
PORT MAP (
wr_clk => clk,
rd_clk => clk,
rst => reset_signal,
din => dfifo_din, -- DATA FROM THE PC
wr_en => dfifo_wr_en,
rd_en => dfifo_rd_en,
dout => dfifo_dout, -- DATA FOR THE VHDL DESIGN
full => dfifo_full,
empty => dfifo_empty,
almost_empty => dfifo_almty,
valid => dfifo_valid,
rd_data_count => open,
wr_data_count => dfifo_data_count
);
ofifo : fifo_2048_words
PORT MAP (
clk => clk,
rst => reset_signal,
din => ofifo_din, -- DATA FROM THE VHDL DESIGN
wr_en => ofifo_wr_en,
rd_en => ofifo_rd_en,
dout => ofifo_dout, -- DATA FOR THE PC
full => ofifo_full,
empty => ofifo_empty,
almost_empty => ofifo_almty,
valid => ofifo_valid,
data_count => ofifo_data_count
);
Inst_plasma: plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0'
)
PORT MAP(
clk => clk,
reset => reset_signal,
uart_write => o_uart,
uart_read => i_uart, --open,
fifo_1_out_data => ififo_dout,
fifo_1_compteur => ififo_compteur,
fifo_1_empty => ififo_empty,
fifo_1_alm_empty => ififo_almty,
fifo_1_valid => ififo_valid,
fifo_1_full => ififo_full,
fifo_1_read_en => ififo_rd_en,
--fifo_d_out_data => dfifo_dout,
fifo_d_compteur => dfifo_compteur,
fifo_d_empty => dfifo_empty,
fifo_d_alm_empty => dfifo_almty,
fifo_d_valid => dfifo_valid,
fifo_d_full => dfifo_full,
fifo_d_read_en => dfifo_rd_en,
fifo_2_in_data => ofifo_din,
fifo_2_write_en => ofifo_wr_en,
fifo_2_full => ofifo_full,
gpio0_out => open,
gpioA_in => x"00000000" --open
);
-- gpio <= gpio_sig(3 downto 0);
gpio(7) <= dfifo_valid;
gpio(6) <= dfifo_empty;
gpio(5) <= '1' WHEN TO_INTEGER(UNSIGNED(dfifo_data_count)) >= 2*4050 ELSE '0';
gpio(4) <= '1' WHEN TO_INTEGER(UNSIGNED(dfifo_data_count)) >= 1*4050 ELSE '0';
gpio(3) <= ofifo_valid;
gpio(2) <= ofifo_empty;
gpio(1) <= '1' WHEN TO_INTEGER(UNSIGNED(ofifo_data_count)) >= 2*506 ELSE '0';
gpio(0) <= '1' WHEN TO_INTEGER(UNSIGNED(ofifo_data_count)) >= 1*506 ELSE '0';
ififo_compteur <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(ififo_data_count), 32));
dfifo_compteur <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(dfifo_data_count), 32));
ofifo_compteur <= STD_LOGIC_VECTOR(RESIZE( UNSIGNED(ofifo_data_count), 32));
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe; --ack;
ipbus_out.ipb_err <= '0';
end rtl;
| gpl-3.0 | 8b057b224b23da637ceedade5c0e4d50 | 0.595465 | 3.17361 | false | false | false | false |
ryos36/polyphony-tutorial | Life/space_is_the_place.vhdl | 1 | 6,735 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity space_is_the_place is
generic
(
SHOW_MAX_X : integer := 70;
SHOW_MAX_Y : integer := 23
);
port(
clk : in std_logic;
clk_for_life : out std_logic;
data_src : out std_logic_vector(2 downto 0);
mark_src : out std_logic;
data_result : in std_logic;
mark_result : in std_logic
);
end space_is_the_place;
architecture sim of space_is_the_place is
subtype vram_line_t is std_logic_vector(255 downto 0);
type vram_t is array(0 to 255) of vram_line_t;
signal vram : vram_t;
type state_t is ( VRAM_INIT, SHOW_VRAM, PROCESS_STEP_TIME, CLOCK0, CLOCK1, CLOCK2, SHIFT_N, HALT );
signal state : state_t := VRAM_INIT;
signal xi : integer;
signal yi : integer;
signal yi1 : integer;
signal yi2 : integer;
signal l0, l1, l2, result_line : vram_line_t;
signal age_count : integer := 0;
type glider_gun_t is array(0 to 8) of std_logic_vector(46 downto 0);
constant glider_gun : glider_gun_t :=
( "00000000000000000000000001000000000000000000000",
"00000000000000000000000101000000000000000000000",
"00000000000001100000011000000000000110000000000",
"00000000000010001000011000000000000110000000000",
"01100000000100000100011000000000000000000000000",
"01100000000100010110000101000000000000000000000",
"00000000000100000100000001000000000000000000000",
"00000000000010001000000000000000000000000000000",
"00000000000001100000000000000000000000000000000" );
procedure make_blinker(
vram : inout vram_t;
x : integer;
y : integer
) is
variable vline : vram_line_t;
constant blinker : std_logic_vector(2 downto 0) := "111";
begin
vline := vram(y);
for i in 0 to 2 loop
vline(xi + i) := blinker(i);
end loop;
end make_blinker;
begin
process(clk)
variable line0 : line;
variable vline : vram_line_t;
variable d0, d1, d2 : std_logic;
begin
if clk'event and clk = '1' then
case state is
when VRAM_INIT =>
for y in 0 to 255 loop
vram(y) <= CONV_std_logic_vector(0, 256);
end loop;
-- make blinker
for i in 0 to 2 loop
--vram(2)(10 + i) <= '1';
end loop;
for gy in 0 to 8 loop
for gx in 0 to 46 loop
vram(3 + gy)(4 + gx) <= glider_gun(gy)(46 - gx);
end loop;
end loop;
state <= SHOW_VRAM;
when SHOW_VRAM =>
age_count <= age_count + 1;
write( line0, String'("age:"));
write( line0, age_count );
writeline( output, line0);
for y in 0 to SHOW_MAX_Y - 1 loop
vline := vram(y);
for x in 0 to SHOW_MAX_X - 1 loop
if vline(x) = '1' then
write( line0, String'("*"));
else
write( line0, String'(" "));
end if;
end loop;
writeline(output, line0);
end loop;
yi <= 1;
yi1 <= 2;
yi2 <= 3;
xi <= 0;
l0 <= vram(0);
l1 <= vram(1);
l2 <= vram(2);
state <= PROCESS_STEP_TIME;
if age_count = 2 then
--state <= HALT;
end if;
when PROCESS_STEP_TIME =>
if xi = 255 then
state <= CLOCK1;
else
state <= CLOCK0;
end if;
d0 := l0(xi);
d1 := l1(xi);
d2 := l2(xi);
-- write( line0, String'("data_result:"));
-- write( line0, data_result );
-- write( line0, String'(" xi:"));
-- write( line0, xi );
-- write( line0, String'(" d:"));
-- write( line0, d0 );
-- write( line0, String'("-"));
-- write( line0, d1 );
-- write( line0, String'("-"));
-- write( line0, d2 );
-- writeline( output, line0);
data_src <= d0 & d1 & d2;
clk_for_life <= '1';
when CLOCK0 =>
xi <= xi + 1;
if mark_result = '1' then
result_line(xi) <= '1';
else
result_line(xi) <= data_result;
end if;
clk_for_life <= '0';
state <= PROCESS_STEP_TIME;
when CLOCK1 =>
xi <= 0;
if mark_result = '1' then
result_line(xi) <= '1';
else
result_line(xi) <= data_result;
end if;
clk_for_life <= '0';
state <= CLOCK2;
when CLOCK2 =>
clk_for_life <= '1';
state <= SHIFT_N;
when SHIFT_N =>
if xi = 4 then
if yi = 255 - 2 then
--if age_count <= 10 then
state <= SHOW_VRAM;
--end if;
else
xi <= 0;
yi <= yi + 1;
yi1 <= yi1 + 1;
yi2 <= yi2 + 1;
l0 <= vram(yi);
l1 <= vram(yi1);
l2 <= vram(yi2);
vram(yi) <= result_line;
state <= PROCESS_STEP_TIME;
end if;
else
xi <= xi + 1;
if mark_result = '1' then
result_line <= '1' & result_line(255 downto 1);
else
result_line <= data_result & result_line(255 downto 1);
end if;
state <= CLOCK2;
end if;
clk_for_life <= '0';
when HALT =>
end case;
end if;
end process;
end sim;
| mit | 267de86a8b1b74df4c2b18f971b4c06d | 0.423608 | 4.381913 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_B.vhd | 1 | 1,472 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_B is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_B is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal C : std_logic_vector(31 downto 0);
signal t : std_logic;
begin
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
pipeline : process(clk) begin
if rising_edge(clk) then
if (holdn = '1') then
C <= A and B;
outp.nready <= inp.start;
end if;
end if;
end process;
outp.ready <= '0';
outp.result <= C;
outp.icc <= "0000";
end;
| gpl-3.0 | 7cc991a683cdd8dd7b751754ab9a3e67 | 0.57337 | 3.004082 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/HAMMING_DEC_24b.vhd | 1 | 7,206 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:04:29 02/20/2011
-- Design Name:
-- Module Name: hamming_decoder_26bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hamming_decoder_26b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end hamming_decoder_26b;
architecture Behavioral of hamming_decoder_26b is
SUBTYPE parity_ham_26bit IS std_logic_vector(5 DOWNTO 0);
SUBTYPE data_ham_26bit IS std_logic_vector(25 DOWNTO 0);
SUBTYPE coded_ham_26bit IS std_logic_vector(31 DOWNTO 0);
---------------------
-- HAMMING DECODER --
---------------------
PROCEDURE hamming_decoder_26bit(data_parity_in:coded_ham_26bit;
SIGNAL error_out : OUT std_logic_vector(1 DOWNTO 0);
SIGNAL decoded : OUT data_ham_26bit) IS
VARIABLE coded : coded_ham_26bit;
VARIABLE syndrome : integer RANGE 0 TO 31;
VARIABLE parity : parity_ham_26bit;
VARIABLE parity_in : parity_ham_26bit;
VARIABLE syn : parity_ham_26bit;
VARIABLE data_in : data_ham_26bit;
VARIABLE P0, P1 : std_logic;
BEGIN
data_in := data_parity_in(31 DOWNTO 6);
parity_in := data_parity_in(5 DOWNTO 0);
parity(5) := data_in(11) XOR data_in(12) XOR data_in(13) XOR data_in(14) XOR data_in(15) XOR
data_in(16) XOR data_in(17) XOR data_in(18) XOR data_in(19) XOR data_in(20) XOR
data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(4) := data_in(4) XOR data_in(5) XOR data_in(6) XOR data_in(7) XOR data_in(8) XOR
data_in(9) XOR data_in(10) XOR data_in(18) XOR data_in(19) XOR data_in(20) XOR
data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(3) := data_in(1) XOR data_in(2) XOR data_in(3) XOR data_in(7) XOR data_in(8) XOR
data_in(9) XOR data_in(10) XOR data_in(14) XOR data_in(15) XOR data_in(16) XOR
data_in(17) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR data_in(25);
parity(2) := data_in(0) XOR data_in(2) XOR data_in(3) XOR data_in(5) XOR data_in(6) XOR
data_in(9) XOR data_in(10) XOR data_in(12) XOR data_in(13) XOR data_in(16) XOR
data_in(17) XOR data_in(20) XOR data_in(21) XOR data_in(24) XOR data_in(25);
parity(1) := data_in(0) XOR data_in(1) XOR data_in(3) XOR data_in(4) XOR data_in(6) XOR
data_in(8) XOR data_in(10) XOR data_in(11) XOR data_in(13) XOR data_in(15) XOR
data_in(17) XOR data_in(19) XOR data_in(21) XOR data_in(23) XOR data_in(25);
parity(0) := data_in(0) XOR data_in(1) XOR data_in(2) XOR data_in(3) XOR data_in(4) XOR
data_in(5) XOR data_in(6) XOR data_in(7) XOR data_in(8) XOR data_in(9) XOR
data_in(10) XOR data_in(11) XOR data_in(12) XOR data_in(13) XOR data_in(14) XOR
data_in(15) XOR data_in(16) XOR data_in(17) XOR data_in(18) XOR data_in(19) XOR
data_in(20) XOR data_in(21) XOR data_in(22) XOR data_in(23) XOR data_in(24) XOR
data_in(25) XOR parity(1) XOR parity(2) XOR parity(3) XOR parity(4) XOR
parity(5) ;
coded(0) := data_parity_in(0);
coded(1) := data_parity_in(1);
coded(2) := data_parity_in(2);
coded(4) := data_parity_in(3);
coded(8) := data_parity_in(4);
coded(16) := data_parity_in(5);
coded(3) := data_parity_in(6);
coded(5) := data_parity_in(7);
coded(6) := data_parity_in(8);
coded(7) := data_parity_in(9);
coded(9) := data_parity_in(10);
coded(10) := data_parity_in(11);
coded(11) := data_parity_in(12);
coded(12) := data_parity_in(13);
coded(13) := data_parity_in(14);
coded(14) := data_parity_in(15);
coded(15) := data_parity_in(16);
coded(17) := data_parity_in(17);
coded(18) := data_parity_in(18);
coded(19) := data_parity_in(19);
coded(20) := data_parity_in(20);
coded(21) := data_parity_in(21);
coded(22) := data_parity_in(22);
coded(23) := data_parity_in(23);
coded(24) := data_parity_in(24);
coded(25) := data_parity_in(25);
coded(26) := data_parity_in(26);
coded(27) := data_parity_in(27);
coded(28) := data_parity_in(28);
coded(29) := data_parity_in(29);
coded(30) := data_parity_in(30);
coded(31) := data_parity_in(31);
-- syndorme generation
syn(5 DOWNTO 1) := parity(5 DOWNTO 1) XOR parity_in(5 DOWNTO 1);
P0 := '0';
P1 := '0';
FOR i IN 0 TO 5 LOOP
P0 := P0 XOR parity(i);
P1 := P1 XOR parity_in(i);
END LOOP;
syn(0) := P0 XOR P1;
CASE syn(5 DOWNTO 1) IS
WHEN "00011" => syndrome := 3;
WHEN "00101" => syndrome := 5;
WHEN "00110" => syndrome := 6;
WHEN "00111" => syndrome := 7;
WHEN "01001" => syndrome := 9;
WHEN "01010" => syndrome := 10;
WHEN "01011" => syndrome := 11;
WHEN "01100" => syndrome := 12;
WHEN "01101" => syndrome := 13;
WHEN "01110" => syndrome := 14;
WHEN "01111" => syndrome := 15;
WHEN "10001" => syndrome := 17;
WHEN "10010" => syndrome := 18;
WHEN "10011" => syndrome := 19;
WHEN "10100" => syndrome := 20;
WHEN "10101" => syndrome := 21;
WHEN "10110" => syndrome := 22;
WHEN "10111" => syndrome := 23;
WHEN "11000" => syndrome := 24;
WHEN "11001" => syndrome := 25;
WHEN "11010" => syndrome := 26;
WHEN "11011" => syndrome := 27;
WHEN "11100" => syndrome := 28;
WHEN "11101" => syndrome := 29;
WHEN "11110" => syndrome := 30;
WHEN "11111" => syndrome := 31;
WHEN OTHERS => syndrome := 0;
END CASE;
IF syn(0) = '1' THEN
coded(syndrome) := NOT(coded(syndrome));
error_out <= "01"; -- There is an error
ELSIF syndrome/= 0 THEN -- There are more than one error
coded := (OTHERS => '0');-- FATAL ERROR
error_out <= "11";
ELSE
error_out <= "00"; -- No errors detected
END IF;
decoded(0) <= coded(3);
decoded(1) <= coded(5);
decoded(2) <= coded(6);
decoded(3) <= coded(7);
decoded(4) <= coded(9);
decoded(5) <= coded(10);
decoded(6) <= coded(11);
decoded(7) <= coded(12);
decoded(8) <= coded(13);
decoded(9) <= coded(14);
decoded(10) <= coded(15);
decoded(11) <= coded(17);
decoded(12) <= coded(18);
decoded(13) <= coded(19);
decoded(14) <= coded(20);
decoded(15) <= coded(21);
decoded(16) <= coded(22);
decoded(17) <= coded(23);
decoded(18) <= coded(24);
decoded(19) <= coded(25);
decoded(20) <= coded(26);
decoded(21) <= coded(27);
decoded(22) <= coded(28);
decoded(23) <= coded(29);
decoded(24) <= coded(30);
decoded(25) <= coded(31);
END;
SIGNAL error_out : std_logic_vector(1 DOWNTO 0);
SIGNAL decoded : std_logic_vector(25 DOWNTO 0);
begin
PROCESS(INPUT_1,error_out,decoded)
BEGIN
hamming_decoder_26bit( INPUT_1, error_out, decoded);
OUTPUT_1 <= "0000" & error_out & decoded;
END PROCESS;
end Behavioral;
| gpl-3.0 | 7a08ba6a8767c8f6ea80ff8f25e2658d | 0.606855 | 2.548091 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/INTERFACE_COMB_4.vhd | 1 | 9,787 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
ENTITY INTERFACE_COMB_4 IS
PORT (
rst : IN std_ulogic;
clk : IN std_ulogic;
holdn : IN std_ulogic;
cancel : IN std_ulogic;
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_4 IS
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
COMPONENT Q16_8_V_to_C_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_C_to_V_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_ROM_iPos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_ROM_2Pos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_RAM_576s
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_opr_CtoV_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_opr_VtoC_RAM
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_5 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_6 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_7 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL READ_EN_1 : STD_LOGIC;
SIGNAL READ_EN_2 : STD_LOGIC;
SIGNAL READ_EN_3 : STD_LOGIC;
SIGNAL READ_EN_4 : STD_LOGIC;
SIGNAL READ_EN_5 : STD_LOGIC;
SIGNAL READ_EN_6 : STD_LOGIC;
SIGNAL READ_EN_7 : STD_LOGIC;
SIGNAL WRITE_EN_1 : STD_LOGIC;
SIGNAL WRITE_EN_2 : STD_LOGIC;
SIGNAL WRITE_EN_3 : STD_LOGIC;
SIGNAL WRITE_EN_4 : STD_LOGIC;
SIGNAL WRITE_EN_5 : STD_LOGIC;
SIGNAL sINPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sINPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) INTERFACE_COMB_4 : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
sINPUT_1 <= inp.op1(31 downto 0);
sINPUT_2 <= inp.op2(31 downto 0);
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS(inp.instr, cancel)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
BEGIN
op := inp.instr(31 downto 30);
opf := inp.instr(13 downto 5);
op3 := inp.instr(24 downto 19);
READ_EN_1 <= '0';
READ_EN_2 <= '0';
READ_EN_3 <= '0';
READ_EN_4 <= '0';
READ_EN_5 <= '0';
READ_EN_6 <= '0';
READ_EN_7 <= '0';
WRITE_EN_1 <= '0';
WRITE_EN_2 <= '0';
WRITE_EN_3 <= '0';
WRITE_EN_4 <= '0';
WRITE_EN_5 <= '0';
if( op = "10" ) AND (cancel = '0') THEN
IF ( op3 = "011101" ) THEN
if opf = "000000001" THEN
READ_EN_1 <= '1'; -- 0x01
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_1 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000010" THEN
WRITE_EN_1 <= '1'; -- 0x02
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_1 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000011" THEN
READ_EN_2 <= '1'; -- 0x03
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_2 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000100" THEN
WRITE_EN_2 <= '1'; -- 0x04
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_2 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000101" THEN
READ_EN_3 <= '1'; -- 0x05
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_3 SIGNAL (ldipos)");
-- synthesis translate_on
ELSif opf = "000000110" THEN
READ_EN_4 <= '1'; -- 0x06
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_4 SIGNAL");
-- synthesis translate_on
ELSif opf = "000000111" THEN
READ_EN_5 <= '1'; -- 0x07
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_5 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001000" THEN
WRITE_EN_3 <= '1'; -- 0x08
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_3 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001001" THEN
READ_EN_6 <= '1'; -- 0x09
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_6 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001010" THEN
WRITE_EN_4 <= '1'; -- 0x0A
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE_4 SIGNAL (Q16_8_opr_VtoC_RAM)");
-- synthesis translate_on
ELSif opf = "000001011" THEN
READ_EN_7 <= '1'; -- 0x0B
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING READ_7 SIGNAL");
-- synthesis translate_on
ELSif opf = "000001100" THEN
-- synthesis translate_off
--printmsg("(INTERFACE_COMB_4) ===> GENERATING WRITE SIGNAL TO RESOURCE (7)");
-- synthesis translate_on
WRITE_EN_5 <= '1'; -- 0x0C
ELSE
-- synthesis translate_off
printmsg("(INTERFACE_COMB_4) ===> GENERATING AN OUPS PROBLEM");
-- synthesis translate_on
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
RESOURCE_1 : Q16_8_C_to_V_RAM PORT MAP (rst, clk, holdn, WRITE_EN_1, READ_EN_1, sINPUT_1, RESULT_1);
RESOURCE_2 : Q16_8_V_to_C_RAM PORT MAP (rst, clk, holdn, WRITE_EN_2, READ_EN_2, sINPUT_1, RESULT_2);
RESOURCE_3 : Q16_8_ROM_iPos PORT MAP (rst, clk, holdn, READ_EN_3, RESULT_3);
RESOURCE_4 : Q16_8_ROM_2Pos PORT MAP (rst, clk, holdn, READ_EN_4, RESULT_4);
RESOURCE_5 : Q16_8_opr_CtoV_RAM PORT MAP (rst, clk, holdn, WRITE_EN_3, READ_EN_5, sINPUT_1, sINPUT_2, RESULT_5);
RESOURCE_6 : Q16_8_opr_VtoC_RAM PORT MAP (rst, clk, holdn, WRITE_EN_4, READ_EN_6, sINPUT_1, sINPUT_2, RESULT_6);
RESOURCE_7 : Q16_8_RAM_576s PORT MAP (rst, clk, holdn, WRITE_EN_5, READ_EN_7, sINPUT_1, RESULT_7);
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
WITH inp.instr(13 downto 5) SELECT
outp.result <=
RESULT_1 WHEN "000000001",
RESULT_1 WHEN "000000010",
RESULT_2 WHEN "000000011",
RESULT_2 WHEN "000000100",
RESULT_3 WHEN "000000101",
RESULT_4 WHEN "000000110",
RESULT_5 WHEN "000000111",
RESULT_5 WHEN "000001000",
RESULT_6 WHEN "000001001",
RESULT_6 WHEN "000001010",
RESULT_7 WHEN "000001011",
RESULT_7 WHEN "000001100",
STD_LOGIC_VECTOR( TO_SIGNED(-1, 32) ) WHEN OTHERS;
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
end; | gpl-3.0 | da9bcc5673baf25e11c8cc93d13a042e | 0.523143 | 3.254739 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/FSM.vhd | 1 | 1,739 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2016 11:43:23
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
done : in STD_LOGIC;
stop : in std_logic;
start : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type type_etat is (init, inc,finish, calcul);
Signal etat_present, etat_futur : type_etat;
begin
process(clock,reset)
begin
if reset='1' then
etat_present<=init;
elsif rising_edge(clock) then
etat_present<=etat_futur;
end if;
end process;
process(etat_present, done, stop)
begin
case etat_present is
when init=> etat_futur<=inc;
when calcul=> if stop='1' then
etat_futur<=finish;
elsif done = '0' then
etat_futur<=calcul;
else
etat_futur<=inc;
end if;
when inc=> etat_futur<=calcul;
when finish=>etat_futur<=init;
end case;
end process;
process(etat_present)
begin
case etat_present is
when init=> start<='0';
when calcul=> start<='0';
when inc=> start<='1';
when finish=>start<='0';
end case;
end process;
end Behavioral; | gpl-3.0 | 4acef4c748d16b4718cae7f52c168093 | 0.53249 | 3.838852 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_Check_Processor.vhd | 1 | 27,098 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Q16_8_Check_Processor is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
-- SIGNAUX DE COMMANDE DU CO-PROCESSEUR
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
COMPUTE_NODE : in STD_LOGIC;
COMPUTE_MESG : in STD_LOGIC;
FIRST_NODE : in STD_LOGIC;
FIRST_CHECK : in STD_LOGIC;
MODE_LDST : in STD_LOGIC;
MODE_EXEC : in STD_LOGIC;
SOFT_RESET : in STD_LOGIC;
STORE_NODE_COUNT : in STD_LOGIC;
STORE_MESG_COUNT : in STD_LOGIC;
WRITE_NODE_INDEX : in STD_LOGIC;
-- INTERFACES D'E/S DU CO-PROCESSEUR
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture aQ16_8_Check_Processor of Q16_8_Check_Processor is
-- ON DEFINIT LES PARAMETRES DE L'ARCHITECTURE INTERNE
CONSTANT SAT_MIN_VARIABLE : SIGNED(19 downto 0) := TO_SIGNED(-32768, 20);
CONSTANT SAT_MAX_VARIABLE : SIGNED(19 downto 0) := TO_SIGNED( 32767, 20);
CONSTANT SAT_MIN_MESSAGE : SIGNED(19 downto 0) := TO_SIGNED(-32768, 20);
CONSTANT SAT_MAX_MESSAGE : SIGNED(19 downto 0) := TO_SIGNED( 32767, 20);
-- MEMOIRE QUI VA CONTENIR LES VALEURS DES NOEUDS
type ram_type is array (0 to 1024-1) of SIGNED (19 downto 0);
signal RAM_node : ram_type;
SIGNAL READ_node : UNSIGNED(15 downto 0);
SIGNAL WRITE_node : UNSIGNED(15 downto 0);
--SIGNAL READ_node : UNSIGNED(15 downto 0);
SIGNAL SORTIE_NODE : SIGNED(19 downto 0);
SIGNAL SORTIE_NEW_NODE : SIGNED(19 downto 0);
-- MEMOIRE QUI VA CONTENIR LES VALEURS DES MESSAGES
type ra2_type is array (0 to 2048-1) of SIGNED (15 downto 0);
signal RAM_msgs : ra2_type;
SIGNAL READ_msgs : UNSIGNED(15 downto 0);
SIGNAL WRITE_msgs : UNSIGNED(15 downto 0);
SIGNAL SORTIE_MESG : SIGNED(15 downto 0);
SIGNAL SORTIE_NEW_MESG : SIGNED(15 downto 0);
-- MEMOIRE QUI VA CONTENIR LA POSTION DES NOEUDS VARIABLES A
-- UTILISER EN FONCTION DU NOEUD CHECK COURANT
type ra3_type is array (0 to 59) of UNSIGNED (10 downto 0);
signal RAM_pNode : ra3_type;
SIGNAL READ_nPos : UNSIGNED(15 downto 0);
SIGNAL WRITE_nPos : UNSIGNED(15 downto 0);
SIGNAL SORTIE_pNode : UNSIGNED(10 downto 0);
-- FIFO QUI VA CONTENIR LA VALEUR DES CONTRIBUTIONS
type buffer_ancien is array (0 to 15) of SIGNED (19 downto 0);
SIGNAL RAM_CONTRIB : buffer_ancien;
SIGNAL READ_CONTRIB : UNSIGNED(3 downto 0);
SIGNAL WRITE_CONTRIB : UNSIGNED(3 downto 0);
SIGNAL LAST_CONTRIB : SIGNED (19 downto 0);
-- FIFO QUI VA CONTENIR LA VALEUR DES POSITIONS DES NOEUDS
type buffer_posVar is array (0 to 15) of UNSIGNED (10 downto 0);
signal RAM_POSVAR : buffer_posVar;
SIGNAL READ_POSVAR : UNSIGNED(3 downto 0);
SIGNAL WRITE_POSVAR : UNSIGNED(3 downto 0);
SIGNAL LAST_POSVAR : UNSIGNED(10 downto 0);
--
--
--
SIGNAL MAX_NODES : UNSIGNED(15 downto 0) := TO_UNSIGNED(32, 16);
SIGNAL MAX_MESGS : UNSIGNED(15 downto 0) := TO_UNSIGNED(32, 16);
SIGNAL SORTIE_CONTRIB : SIGNED(19 downto 0);
--SIGNAL MEMOIRE_CONTRIB : SIGNED (16 downto 0);
SIGNAL MEMOIRE_XOR_MIN1 : UNSIGNED(14 downto 0);
SIGNAL MEMOIRE_XOR_MIN2 : UNSIGNED(14 downto 0);
SIGNAL MEMOIRE_XOR_SIGN : STD_LOGIC;
SIGNAL STAGE_2_XOR_MIN1 : UNSIGNED(14 downto 0);
SIGNAL STAGE_2_XOR_MIN2 : UNSIGNED(14 downto 0);
SIGNAL STAGE_2_XOR_SIGN : STD_LOGIC;
SIGNAL mTAGE_2_XOR_MIN1 : UNSIGNED(14 downto 0);
SIGNAL mTAGE_2_XOR_MIN2 : UNSIGNED(14 downto 0);
SIGNAL mTAGE_2_XOR_SIGN : STD_LOGIC;
SIGNAL SORTIE_XOR_MIN1 : UNSIGNED(14 downto 0);
SIGNAL SORTIE_XOR_MIN2 : UNSIGNED(14 downto 0);
SIGNAL SORTIE_XOR_SIGN : STD_LOGIC;
SIGNAL pCOMPUTE_NODE : STD_LOGIC;
SIGNAL pCOMPUTE_MESG : STD_LOGIC;
SIGNAL ppOMPUTE_MESG : STD_LOGIC;
SIGNAL pFIRST_NODE : STD_LOGIC;
SIGNAL pFIRST_CHECK : STD_LOGIC;
--SIGNAL pFIRST_ITER : STD_LOGIC;
-- MEMORISATION DE L'ETAT COURANT DU CO-PROCESSEUR (CHARGEMENT ET
-- DECHARGEMENT DE DONNEES - OU - CALCUL). CELA MODIFIE LA MANIERE
-- D'ACCEDER A LA MEMOIRE VARIABLE.
SIGNAL IS_LOADING_MODE : STD_LOGIC;
-- SIGNAUX PERMETTANT DE SAVOIR SI L'ON REALISE LA PREMIERE ITERATION
-- DU DECODEUR (ON INHIBE LES SIGNAUX DE LA RAM MESSAGES).
SIGNAL FIRST_LOOP_COUNTER : UNSIGNED(15 downto 0);
SIGNAL IS_FIRST_LOOP : STD_LOGIC;
-- SIGNAL PERMETTANT D'IDENTIFIER L'INSTRUCTION QUE LE PROCESSEUR DE CALCUL
-- DOIT EXECUTER (UTILE POUR LA MISE AU POINT)
SIGNAL INSTRUCTION : STD_LOGIC_VECTOR(11 downto 0);
CONSTANT INSTR_WRITE_VARIABLE : STD_LOGIC_VECTOR(11 downto 0) := "100000000000";
CONSTANT INSTR_READ_VARIABLE : STD_LOGIC_VECTOR(11 downto 0) := "010000000000";
CONSTANT INSTR_EXEC_FIRST_NODE : STD_LOGIC_VECTOR(11 downto 0) := "001001000000";
CONSTANT INSTR_EXEC_NODE : STD_LOGIC_VECTOR(11 downto 0) := "001000000000";
CONSTANT INSTR_EXEC_FIRST_MESG : STD_LOGIC_VECTOR(11 downto 0) := "000110000000";
CONSTANT INSTR_EXEC_MESG : STD_LOGIC_VECTOR(11 downto 0) := "000100000000";
CONSTANT INSTR_SWITCH_LDST_MODE : STD_LOGIC_VECTOR(11 downto 0) := "000000100000";
CONSTANT INSTR_SWITCH_EXEC_MODE : STD_LOGIC_VECTOR(11 downto 0) := "000000010000";
CONSTANT INSTR_SOFT_RESET : STD_LOGIC_VECTOR(11 downto 0) := "000000001000";
CONSTANT INSTR_STORE_NODE_COUNT : STD_LOGIC_VECTOR(11 downto 0) := "000000000100";
CONSTANT INSTR_STORE_MESG_COUNT : STD_LOGIC_VECTOR(11 downto 0) := "000000000010";
CONSTANT INSTR_WRITE_NODE_INDEX : STD_LOGIC_VECTOR(11 downto 0) := "000000000001";
CONSTANT INSTR_EXEC_NOP : STD_LOGIC_VECTOR(11 downto 0) := "000000000000";
-- INSTUCTION POUR LE MODE PIPELINE
CONSTANT INSTR_EXEC_F_NODE_MESG : STD_LOGIC_VECTOR(11 downto 0) := "001111000000";
CONSTANT INSTR_EXEC_NODE_MESG : STD_LOGIC_VECTOR(11 downto 0) := "001100000000";
-- SIGNAL PERMETTANT DE SAVOIR DANS QUEL ETAT SE TROUVE ACTUELLEMENT LE CIRCUIT
type instr is (s_reset, h_reset, ld_node, st_pvar, c_node, c_msg, c_fnode, c_fmsg, nop, maxN, maxM, ld_var, st_var, set_ldst, set_exec, oups, c_node_msg, c_fnode_fmsg);
SIGNAL etat : instr := nop;
BEGIN
-- ON COMPOSE LE CODE INSTRUCTION A PARTIR DES SIGNAUX DE BASE
INSTRUCTION <= WRITE_EN & READ_EN & COMPUTE_NODE & COMPUTE_MESG & FIRST_NODE & FIRST_CHECK & MODE_LDST & MODE_EXEC & SOFT_RESET & STORE_NODE_COUNT & STORE_MESG_COUNT & WRITE_NODE_INDEX;
-- EN FONCTION DE LA VALEUR DE L'INSTRUCTION ON MEMORISE (POUR AFFICHAGE UNIQUEMENT)
-- LE NOM DE L'ACTION REALISEE PAR LE CO-PROCESSEUR
PROCESS (INSTRUCTION, RESET)
BEGIN
if reset = '0' then
etat <= h_reset;
ELSE
CASE INSTRUCTION IS
WHEN INSTR_WRITE_VARIABLE => etat <= st_var;
WHEN INSTR_READ_VARIABLE => etat <= ld_var;
WHEN INSTR_EXEC_FIRST_NODE => etat <= c_fnode;
WHEN INSTR_EXEC_NODE => etat <= c_node;
WHEN INSTR_EXEC_FIRST_MESG => etat <= c_fmsg;
WHEN INSTR_EXEC_MESG => etat <= c_msg;
WHEN INSTR_SWITCH_LDST_MODE => etat <= set_ldst;
WHEN INSTR_SWITCH_EXEC_MODE => etat <= set_exec;
WHEN INSTR_SOFT_RESET => etat <= s_reset;
WHEN INSTR_STORE_NODE_COUNT => etat <= maxN;
WHEN INSTR_STORE_MESG_COUNT => etat <= maxM;
WHEN INSTR_WRITE_NODE_INDEX => etat <= st_pvar;
WHEN INSTR_EXEC_F_NODE_MESG => etat <= c_fnode_fmsg;
WHEN INSTR_EXEC_NODE_MESG => etat <= c_node_msg;
WHEN INSTR_EXEC_NOP => etat <= nop;
WHEN OTHERS => etat <= oups;
END CASE;
END IF;
END PROCESS;
PROCESS(clock, reset)
BEGIN
IF reset = '0' then
pCOMPUTE_NODE <= '0';
pCOMPUTE_MESG <= '0';
pFIRST_NODE <= '0';
pFIRST_CHECK <= '0';
--pFIRST_ITER <= '0';
ppOMPUTE_MESG <= '0';
ELSIF clock'event and clock = '1' then
pCOMPUTE_NODE <= COMPUTE_NODE;
pCOMPUTE_MESG <= COMPUTE_MESG;
pFIRST_NODE <= FIRST_NODE;
pFIRST_CHECK <= FIRST_CHECK;
--pFIRST_ITER <= FIRST_ITER;
ppOMPUTE_MESG <= pCOMPUTE_MESG;
END IF;
END PROCESS;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LE BASCULEMENT DU CO-PROCESSEUR DU MODE DE CHARGEMENT
-- DECHARGEMENT DES DONNEES VERS LE MODE DE CALCUL ET VICE ET VERSA.
--
process(clock, reset)
begin
if reset = '0' then
IS_LOADING_MODE <= '1';
elsif clock'event and clock = '1' then
IF MODE_LDST = '1' THEN
IS_LOADING_MODE <= '1';
ELSIF MODE_EXEC = '1' THEN
IS_LOADING_MODE <= '0';
ELSE
IS_LOADING_MODE <= IS_LOADING_MODE;
END IF;
end if;
END process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LE BASCULEMENT DU MODE PREMIERE ITERATION DU DECODEUR
-- LDPC (TRANSITOIRE) VERS LE MODE EXECUTION CONTINUE (RAM MESSAGE)
--
PROCESS(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
BEGIN
IF reset = '0' THEN
FIRST_LOOP_COUNTER <= TO_UNSIGNED(0, 15);
IS_FIRST_LOOP <= '1';
ELSIF clock'event AND clock = '1' THEN
TEMP := FIRST_LOOP_COUNTER;
IF pCOMPUTE_NODE = '1' AND holdn = '1' THEN -- ON UTILISE PCOMPUTE_NODE POUR DECALER D'UN CYCLE
TEMP := TEMP + TO_UNSIGNED(1, 16); -- LA TRANSITION SUR IS_FIRST_LOOP SINON ON A UN SOUCIS
IF TEMP >= MAX_MESGS THEN
TEMP := MAX_MESGS;
IS_FIRST_LOOP <= '0';
ELSE
IS_FIRST_LOOP <= IS_FIRST_LOOP;
END IF;
END IF;
FIRST_LOOP_COUNTER <= TEMP;
END IF;
END PROCESS;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LA RECEPTION DU NOMBRE DE NOEUDS VARIABLES DANS LE
-- DECODEUR LDPC COURANT
--
process(clock, reset)
begin
if reset = '0' then
MAX_NODES <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
if STORE_NODE_COUNT = '1' AND holdn = '1' then
MAX_NODES <= UNSIGNED( INPUT_1(15 downto 0) );
ELSE
MAX_NODES <= MAX_NODES;
end if;
end if;
END process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LA RECEPTION DU NOMBRE DE MESSAGES A CALCULER ET
-- A TRANSMETTRE DANS LE DECODEUR LDPC COURANT
--
process(clock, reset)
begin
if reset = '0' then
MAX_MESGS <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
if STORE_MESG_COUNT = '1' AND holdn = '1' then
MAX_MESGS <= UNSIGNED( INPUT_1(15 downto 0) );
ELSE
MAX_MESGS <= MAX_MESGS;
end if;
end if;
END process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT L'ECRITURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LA VALEUR DES NOEUDS VARIABLES
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
WRITE_nPos <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
-- ON MEMORISE LA DONNEE DANS LA MEMOIRE
if WRITE_NODE_INDEX = '1' AND holdn = '1' then
RAM_pNode( to_integer(WRITE_nPos) ) <= UNSIGNED( INPUT_1(10 downto 0) );
END IF;
-- ON FAIT AVANCER LE COMPTEUR SI NECESSAIRE
TEMP := WRITE_nPos;
if WRITE_NODE_INDEX = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_MESGS THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
END IF;
WRITE_nPos <= TEMP;
end if;
end process;
--
-- PROCESSUS GERANT LA LECTURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LA VALEUR DES NOEUDS VARIABLES
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
READ_nPos <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
TEMP := READ_nPos;
if COMPUTE_NODE = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_MESGS THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
end if;
READ_nPos <= TEMP;
SORTIE_pNode <= UNSIGNED( RAM_pNode( to_integer(TEMP) ) );
end if;
end process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT L'ECRITURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LA VALEUR DES NOEUDS VARIABLES
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
VARIABLE ADRESSE : UNSIGNED(15 downto 0);
VARIABLE DONNEE : SIGNED(19 downto 0);
begin
if reset = '0' then
WRITE_node <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
-- ON GERE L'ECRITURE DES DONNEES DANS LA MEMOIRE (DONNEES PROVENANT DE L'EXTERIEUR)
--if WRITE_EN = '1' AND holdn = '1' then
-- RAM_node( to_integer(WRITE_node ) ) <= SIGNED( INPUT_1(19 downto 0) );
-- ON GERE L'ECRITURE DES DONNEES DANS LA MEMOIRE (DONNEES INTERNES DE CALCUL)
--elsif ppOMPUTE_MESG = '1' AND holdn = '1' then
-- RAM_node( to_integer(LAST_POSVAR) ) <= SIGNED( sortie_new_node );
--end if;
-- ON SELECTIONNE L'ADRESSE ET LA DONNEE EN FONCTION DU MODE DANS LEQUEL
-- SE TROUVE LE CO-PROCESSEUR
IF IS_LOADING_MODE = '1' THEN
ADRESSE := WRITE_node;
DONNEE := SIGNED( INPUT_1(19 downto 0) );
ELSE
ADRESSE := "00000" & LAST_POSVAR;
DONNEE := SIGNED( sortie_new_node );
END IF;
-- ON ECRIT LA DONNEE DANS LA MEMOIRE SI CELA EST NECESSAIRE
IF ((WRITE_EN = '1' AND holdn = '1') AND IS_LOADING_MODE = '1') OR
((ppOMPUTE_MESG = '1' AND holdn = '1') AND IS_LOADING_MODE = '0') THEN
RAM_node( to_integer(ADRESSE) ) <= SIGNED( DONNEE );
END IF;
-- ON GERE L'EVOLUTION DU COMPTEUR QUI NOUS DIT OU ECRIRE
TEMP := WRITE_node;
if WRITE_EN = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_NODES THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
end if;
WRITE_node <= TEMP;
end if;
end process;
--
-- PROCESSUS GERANT LA LECTURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LA VALEUR DES NOEUDS VARIABLES
--
process(clock, reset)
VARIABLE ADRESSE : UNSIGNED(15 downto 0);
begin
if reset = '0' then
elsif clock'event and clock = '1' then
-- ON SELECTIONNE L'ADRESSE ET LA DONNEE EN FONCTION DU MODE DANS LEQUEL
-- SE TROUVE LE CO-PROCESSEUR
IF IS_LOADING_MODE = '1' THEN
ADRESSE := READ_node;
ELSE
ADRESSE := "00000" & SORTIE_pNode;
END IF;
SORTIE_NODE <= RAM_node( to_integer(ADRESSE) );
-- TEMP := READ_node;
-- if read_en = '1' AND holdn = '1' then
-- TEMP := TEMP + TO_UNSIGNED(1, 16);
-- IF TEMP = MAX_NODES THEN
-- TEMP := TO_UNSIGNED(0, 16);
-- END IF;
-- end if;
-- READ_node <= TEMP;
-- SORTIE_NODE <= RAM_node( to_integer(TEMP) );
end if;
end process;
--
-- COMPTEUR UTILISE POUR GENERER LES ADRESSES DE LECTURE DES DONNEES (VARIABLE)
-- EN VUE DE LA RESTITUTION DE CES DERNIERES VERS LE SYSTEME (DECISION)
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
READ_node <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
TEMP := READ_node;
if READ_EN = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_NODES THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
END IF;
READ_node <= TEMP;
end if;
end process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT L'ECRITURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LES MESSAGES (CHECK => NODE)
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
WRITE_msgs <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
-- ON GERE L'ECRITURE DES DONNEES DANS LA MEMOIRE
if ppOMPUTE_MESG = '1' AND holdn = '1' then
RAM_msgs( to_integer(WRITE_msgs) ) <= SIGNED( sortie_new_mesg(15 downto 0) );
end if;
-- ON FAIT EVOLUTER LE COMPTEUR EN CONSEQUENCE
TEMP := WRITE_msgs;
if ppOMPUTE_MESG = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_MESGS THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
end if;
WRITE_msgs <= TEMP;
end if;
end process;
--
-- PROCESSUS GERANT LA LECTURE DES DONNEES DANS LA MEMOIRE
-- CONTENANT LES MESSAGES (CHECK => NODE)
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
READ_msgs <= TO_UNSIGNED(0, 16);
elsif clock'event and clock = '1' then
TEMP := READ_msgs;
if pCOMPUTE_NODE = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 16);
IF TEMP = MAX_MESGS THEN
TEMP := TO_UNSIGNED(0, 16);
END IF;
end if;
READ_msgs <= TEMP;
SORTIE_MESG <= SIGNED(RAM_msgs( to_integer(TEMP) ));
end if;
end process;
-------------------------------------------------------------------------
--
-- PROCESSUS ASSURANT LE CALCUL DES CONTRIBUTIONS EN SORTIE DES MEMOIRES
--
PROCESS (SORTIE_NODE, SORTIE_MESG, IS_FIRST_LOOP)
BEGIN
IF ( IS_FIRST_LOOP = '0' ) THEN
--IF ( pFIRST_ITER = '0' ) THEN
SORTIE_CONTRIB <= SORTIE_NODE - SORTIE_MESG;
ELSE
SORTIE_CONTRIB <= SORTIE_NODE; --RESIZE(SORTIE_NODE, 17);
END IF;
END PROCESS;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LE CALCUL DE LA VALEUR DE LA SORTIE DU PROCESSEUR
-- DE CALCUL (PRISE DE DECISION SUR LA VALEUR DU BIT RECU PAR LE DECODEUR).
--
PROCESS(SORTIE_NODE, IS_LOADING_MODE)
begin
IF IS_LOADING_MODE = '1' THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(SORTIE_NODE, 32) );
--if SORTIE_NODE > TO_SIGNED(0, 16) then
-- OUTPUT_1 <= "1000000000" & STD_LOGIC_VECTOR(SORTIE_NODE); --STD_LOGIC_VECTOR( TO_UNSIGNED(1, 32) );
--else
-- OUTPUT_1 <= "0000000000" & STD_LOGIC_VECTOR(SORTIE_NODE); --STD_LOGIC_VECTOR( TO_UNSIGNED(0, 32) );
--end if;
ELSE
OUTPUT_1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
END IF;
end process;
-------------------------------------------------------------------------
--
-- PROCESSUS GERANT LE CALCUL DE LA VALEUR XOR_MIN
--
PROCESS (SORTIE_CONTRIB, MEMOIRE_XOR_MIN1, MEMOIRE_XOR_MIN2, MEMOIRE_XOR_SIGN, pFIRST_CHECK)
VARIABLE OPT : SIGNED(16 downto 0);
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE vP1 : UNSIGNED(14 downto 0);
VARIABLE MIN1 : UNSIGNED(14 downto 0);
VARIABLE MIN2 : UNSIGNED(14 downto 0);
VARIABLE SIGN : STD_LOGIC;
BEGIN
-- ON CALCULE LA CONTRIBUTION DU NOEUD VARIABLE (MESSAGE NODE => CHECK)
-- CALCUL SATURE [-32768, 32767]
OPT := SORTIE_CONTRIB(16 downto 0);
IF OPT > TO_SIGNED( 32767, 17) THEN
OPT := TO_SIGNED( 32767, 17);
ELSIF OPT < TO_SIGNED(-32768, 17) THEN
OPT := TO_SIGNED(-32767, 17);
END IF;
-- ON RECUPERE NOS OPERANDES
OP1 := SIGNED( OPT (15 downto 0));
IF pFIRST_CHECK = '0' THEN
MIN1 := MEMOIRE_XOR_MIN1; -- VALEUR ABSOLUE => PAS DE BIT DE SIGNE (TJS POSITIF)
MIN2 := MEMOIRE_XOR_MIN2; -- VALEUR ABSOLUE => PAS DE BIT DE SIGNE (TJS POSITIF)
SIGN := MEMOIRE_XOR_SIGN;
ELSE
MIN1 := TO_UNSIGNED(32767, 15);
MIN2 := TO_UNSIGNED(32767, 15);
SIGN := '0';
END IF;
-- ON CALCULE LA VALEUR ABSOLUE DE L'ENTREE
OP1 := abs( OP1 );
vP1 := UNSIGNED(OP1(14 downto 0));
-- ON CALCULE LE MIN QUI VA BIEN
IF vP1 < MIN1 THEN
MIN2 := MIN1;
MIN1 := vP1;
ELSIF UNSIGNED(OP1(14 downto 0)) < MIN2 THEN
MIN2 := vP1;
END IF;
-- ON S'OCCUPE DU BIT DE SIGNE DU RESULTAT
SIGN := SIGN XOR ( NOT SORTIE_CONTRIB(15) );
-- ON REFORME LE RESULTAT AVANT DE LE RENVOYER
SORTIE_XOR_MIN1 <= MIN1;
SORTIE_XOR_MIN2 <= MIN2;
SORTIE_XOR_SIGN <= SIGN;
END PROCESS;
-------------------------------------------------------------------------
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
STAGE_2_XOR_MIN1 <= TO_UNSIGNED(0, 15);
STAGE_2_XOR_MIN2 <= TO_UNSIGNED(0, 15);
STAGE_2_XOR_SIGN <= '0';
mTAGE_2_XOR_MIN1 <= TO_UNSIGNED(0, 15);
mTAGE_2_XOR_MIN2 <= TO_UNSIGNED(0, 15);
mTAGE_2_XOR_SIGN <= '0';
elsif clock'event and clock = '1' then
--IF pFIRST_NODE = '1' THEN
IF FIRST_NODE = '1' THEN
mTAGE_2_XOR_MIN1 <= SORTIE_XOR_MIN1;
mTAGE_2_XOR_MIN2 <= SORTIE_XOR_MIN2;
mTAGE_2_XOR_SIGN <= SORTIE_XOR_SIGN;
END IF;
STAGE_2_XOR_MIN1 <= mTAGE_2_XOR_MIN1;
STAGE_2_XOR_MIN2 <= mTAGE_2_XOR_MIN2;
STAGE_2_XOR_SIGN <= mTAGE_2_XOR_SIGN;
end if;
end process;
-------------------------------------------------------------------------
--
-- PROCESSUS EN CHARGE DE LA MEMORISATION DE LA VALEUR DE SORTIE DE L'OPERATEUR
-- XOR_MIN LORSQUE CELA EST NECESSAIRE (CALCUL D'UN NOEUD CHECK EN COURS).
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(15 downto 0);
begin
if reset = '0' then
MEMOIRE_XOR_MIN1 <= TO_UNSIGNED(0, 15);
MEMOIRE_XOR_MIN2 <= TO_UNSIGNED(0, 15);
MEMOIRE_XOR_SIGN <= '0';
elsif clock'event and clock = '1' then
-- IF COMPUTE_NODE = '1' THEN
IF pCOMPUTE_NODE = '1' THEN
MEMOIRE_XOR_MIN1 <= SORTIE_XOR_MIN1;
MEMOIRE_XOR_MIN2 <= SORTIE_XOR_MIN2;
MEMOIRE_XOR_SIGN <= SORTIE_XOR_SIGN;
ELSE
MEMOIRE_XOR_MIN1 <= MEMOIRE_XOR_MIN1;
MEMOIRE_XOR_MIN2 <= MEMOIRE_XOR_MIN2;
MEMOIRE_XOR_SIGN <= MEMOIRE_XOR_SIGN;
END IF;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- PROCESSUS EN CHARGE DU CALCUL DE LA NOUVELLE VALEUR DU NOEUD VARIABLE
-- ET DE LA NOUVELLE VALEUR DU MESSAGE (CHECK => NODE).
--
PROCESS (LAST_CONTRIB, STAGE_2_XOR_MIN1, STAGE_2_XOR_MIN2, STAGE_2_XOR_SIGN)
VARIABLE OPT : SIGNED(16 downto 0);
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE aOP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
VARIABLE CST1 : SIGNED(15 downto 0);
VARIABLE CST2 : SIGNED(15 downto 0);
VARIABLE RESU : SIGNED(15 downto 0);
VARIABLE RESUp : SIGNED(15 downto 0);
VARIABLE MESSG : SIGNED(15 downto 0);
VARIABLE TEMPV : SIGNED(19 downto 0);
VARIABLE iSIGN : STD_LOGIC;
VARIABLE sSIGN : STD_LOGIC;
BEGIN
--
-- ON RECUPERE NOS OPERANDES
--
OPT := LAST_CONTRIB(16 downto 0);
IF( OPT > TO_SIGNED( 32767, 17) ) THEN OPT := TO_SIGNED( 32767, 17);
ELSIF OPT < TO_SIGNED(-32768, 17) THEN OPT := TO_SIGNED(-32767, 17);
END IF;
OP1 := OPT(15 downto 0); -- DONNEE SIGNEE SUR 16 bits
MIN1 := SIGNED('0' & STAGE_2_XOR_MIN1); -- DONNEE TJS POSITIVE SUR 16 BITS
MIN2 := SIGNED('0' & STAGE_2_XOR_MIN2); -- DONNEE TJS POSITIVE SUR 16 BITS
iSIGN := OPT(15); -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
sSIGN := STAGE_2_XOR_SIGN; -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
--
aOP1 := abs( OP1 );
--
CST1 := MIN2 - TO_SIGNED(38, 16); -- BETA_FIX;
CST2 := MIN1 - TO_SIGNED(38, 16); -- BETA_FIX;
IF CST1 < TO_SIGNED(0, 16) THEN CST1 := TO_SIGNED(0, 16); END IF;
IF CST2 < TO_SIGNED(0, 16) THEN CST2 := TO_SIGNED(0, 16); END IF;
--
if ( aOP1 = MIN1 ) THEN
RESU := CST1;
ELSE
RESU := CST2;
END IF;
--
RESUp := -RESU;
iSIGN := iSIGN XOR sSIGN;
--
IF( iSIGN = '0' ) THEN
MESSG := RESU;
ELSE
MESSG := RESUp;
END IF;
-- ON CALCULE LA NOUVELLE VALEUR DU MESSAGE (CHECK => NODE)
SORTIE_NEW_MESG <= MESSG;
-- ON CALCULE LA NOUVELLE VALEUR DU NOEUD VARIABLE
TEMPV := LAST_CONTRIB + MESSG;
IF TEMPV > TO_SIGNED( 32767, 20) THEN
TEMPV := TO_SIGNED( 32767, 20);
ELSIF TEMPV < TO_SIGNED(-32768, 20) THEN
TEMPV := TO_SIGNED(-32767, 20);
END IF;
SORTIE_NEW_NODE <= TEMPV; --(15 downto 0);
END PROCESS;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
--
-- DESCRIPTION DE LA MEMOIRE EN CHARGE DE LA MEMORISATION DES CONTRIBUTIONS
-- (CALCULS TEMPORAIRES NECESSAIRES POUR L'ETAPES DE XOR_MIN)
--
--
-------------------------------------------------------------------------
-- ON MEMORISE LA CALCUL TEMPORAIRE DE LA CONTRIBUTION DANS UNE MEMOIRE TAMPON
process(clock)
VARIABLE AW : INTEGER RANGE 0 to 15;
begin
if reset = '0' then
WRITE_CONTRIB <= TO_UNSIGNED(0, 4);
elsif clock'event and clock = '1' then
-- ON MEMORISE LA PREMIERE CONTRIBUTION
if pCOMPUTE_NODE = '1' AND holdn = '1' then
AW := to_integer( WRITE_CONTRIB );
RAM_CONTRIB( AW ) <= SORTIE_CONTRIB;
WRITE_CONTRIB <= WRITE_CONTRIB + TO_UNSIGNED(1, 4);
-- ON NE MEMORISE RIEN DU TOUT...
ELSE
WRITE_CONTRIB <= WRITE_CONTRIB;
end if;
end if;
end process;
-- ON RESTITUE LES CALCULS TEMPORAIRES DE LA CONTRIBUTION
process(clock)
begin
if reset = '0' then
READ_CONTRIB <= TO_UNSIGNED(0, 4);
elsif clock'event and clock = '1' then
IF pCOMPUTE_MESG = '1' AND holdn = '1' then
READ_CONTRIB <= READ_CONTRIB + TO_UNSIGNED(1, 4);
ELSE
READ_CONTRIB <= READ_CONTRIB;
END IF;
LAST_CONTRIB <= RAM_CONTRIB( to_integer(READ_CONTRIB) );
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
--
-- DESCRIPTION DE LA MEMOIRE EN CHARGE DE LA MEMORISATION DES CONTRIBUTIONS
-- (CALCULS TEMPORAIRES NECESSAIRES POUR L'ETAPES DE XOR_MIN)
--
--
-------------------------------------------------------------------------
-- ON MEMORISE LA CALCUL TEMPORAIRE DE LA CONTRIBUTION DANS UNE MEMOIRE TAMPON
process(clock)
VARIABLE AW : INTEGER RANGE 0 to 15;
begin
if reset = '0' then
WRITE_POSVAR <= TO_UNSIGNED(0, 4);
elsif clock'event and clock = '1' then
-- ON MEMORISE LA PREMIERE CONTRIBUTION
if COMPUTE_NODE = '1' AND holdn = '1' then
AW := to_integer( WRITE_POSVAR );
RAM_POSVAR( AW ) <= SORTIE_pNODE;
WRITE_POSVAR <= WRITE_POSVAR + TO_UNSIGNED(1, 4);
-- ON NE MEMORISE RIEN DU TOUT...
ELSE
WRITE_POSVAR <= WRITE_POSVAR;
end if;
end if;
end process;
-- ON RESTITUE LES CALCULS TEMPORAIRES DE LA CONTRIBUTION
process(clock)
begin
if reset = '0' then
READ_POSVAR <= TO_UNSIGNED(0, 4);
elsif clock'event and clock = '1' then
IF pCOMPUTE_MESG = '1' AND holdn = '1' then
READ_POSVAR <= READ_POSVAR + TO_UNSIGNED(1, 4);
ELSE
READ_POSVAR <= READ_POSVAR;
END IF;
LAST_POSVAR <= RAM_POSVAR( to_integer(READ_POSVAR) );
end if;
end process;
-------------------------------------------------------------------------
END aQ16_8_Check_Processor; | gpl-3.0 | 797d453ac0532e053506bfea95f65051 | 0.587792 | 3.209523 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_avalon_mm/src/vvc_methods_pkg.vhd | 1 | 21,019 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.avalon_mm_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SBI VVC
--===============================================================================================
constant C_VVC_NAME : string := "AVALON_MM_VVC";
signal AVALON_MM_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AVALON_MM_VVCT;
alias t_bfm_config is t_avalon_mm_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_AVALON_MM_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity cmd_queue_count_threshold_severity will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_bfm_config; -- Configuration for Avalon-MM BFM. See quick reference for Avalon-MM BFM
use_read_pipeline : boolean; -- When true, allows sending multiple read_requests before receiving a read_response
num_pipeline_stages : natural; -- Max read_requests in pipeline
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AVALON_MM_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AVALON_MM_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AVALON_MM_BFM_CONFIG_DEFAULT,
use_read_pipeline => TRUE,
num_pipeline_stages => 5,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'),
msg => (others => ' ')
);
shared variable shared_avalon_mm_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_AVALON_MM_VVC_CONFIG_DEFAULT);
shared variable shared_avalon_mm_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_avalon_mm_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
-- Without byte enable
procedure avalon_mm_write (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- With byte enable
procedure avalon_mm_write (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure avalon_mm_read (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure avalon_mm_check (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure avalon_mm_reset (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure avalon_mm_lock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure avalon_mm_unlock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
procedure avalon_mm_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX)
& ", " & to_string(byte_enable, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
variable v_normalised_byte_ena : std_logic_vector(shared_vvc_cmd.byte_enable'length-1 downto 0) :=
normalize_and_check(byte_enable, shared_vvc_cmd.byte_enable, ALLOW_WIDER_NARROWER, "byte_enable", "shared_vvc_cmd.byte_enable", proc_call & " called with to wide byte_enable. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.byte_enable := v_normalised_byte_ena;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_read";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr",proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ);
shared_vvc_cmd.operation := READ;
shared_vvc_cmd.addr := v_normalised_addr;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_check";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_reset(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_reset";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(num_rst_cycles) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, RESET);
shared_vvc_cmd.gen_integer_array(0) := num_rst_cycles;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_lock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_lock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, LOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure;
procedure avalon_mm_unlock (
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "avalon_mm_unlock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, UNLOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure;
end package body vvc_methods_pkg;
| mit | 01baa94157253fd9fd0e998032dce6b2 | 0.590371 | 4.061643 | false | false | false | false |
ryos36/polyphony-tutorial | Life/life.vhdl | 1 | 4,448 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity life is
port(
clk : in std_logic;
din : in std_logic_vector(2 downto 0);
mark_in : in std_logic;
dout : out std_logic;
mark_out : out std_logic
);
end life;
architecture RTL of life is
signal me : std_logic_vector(1 downto 0);
signal din_d_sum : std_logic_vector( 1 downto 0 );
signal d101_d : std_logic_vector( 1 downto 0 );
signal mark_shift : std_logic_vector(2 downto 0);
signal sum0: std_logic_vector(1 downto 0);
signal sum01: std_logic_vector(2 downto 0);
signal dout_reg : std_logic;
begin
dout <= dout_reg;
mark_out <= mark_shift(2);
process(clk)
begin
if clk'event and clk = '1' then
me(0) <= din(1);
me(1) <= me(0);
d101_d <= din(2) & din(0);
case din is
when "000" =>
din_d_sum <= "00";
when "001" =>
din_d_sum <= "01";
when "010" =>
din_d_sum <= "01";
when "100" =>
din_d_sum <= "01";
when "111" =>
din_d_sum <= "11";
when others =>
din_d_sum <= "10";
end case;
sum0 <= din_d_sum;
if sum01(2) = '1' then
dout_reg <= '0';
else
case sum01(1 downto 0) is
when "00" =>
if din_d_sum(1) = '1' then
if din_d_sum(0) = '0' then
dout_reg <= me(1);
else
dout_reg <= '0';
end if;
else
dout_reg <= '0';
end if;
when "01" =>
if (din_d_sum(1) xor din_d_sum(0)) = '1' then
if din_d_sum(0) = '1' then
dout_reg <= me(1);
else
dout_reg <= '1';
end if;
else
dout_reg <= '0';
end if;
when "10" =>
if din_d_sum(1) = '0' then
if din_d_sum(0) = '0' then
dout_reg <= me(1);
else
dout_reg <= '1';
end if;
else
dout_reg <= '0';
end if;
when others =>
if din_d_sum = "00" then
dout_reg <= '1';
else
dout_reg <= '0';
end if;
end case;
end if;
case sum0 is
when "00" =>
sum01 <= "0" & (d101_d(1) and d101_d(0)) & (d101_d(1) xor d101_d(0));
when "01" =>
if (d101_d(1) xor d101_d(0)) = '0' then
if d101_d(0) = '0' then
sum01 <= "001";
else
sum01 <= "100";
end if;
else
sum01 <= "010";
end if;
when "10" =>
if (d101_d(1) xor d101_d(0)) = '0' then
if d101_d(0) = '0' then
sum01 <= "010";
else
sum01 <= "100";
end if;
else
sum01 <= "011";
end if;
when others =>
if d101_d = "00" then
sum01 <= "011";
else
sum01 <= "100";
end if;
end case;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
mark_shift(2) <= mark_shift(1);
mark_shift(1) <= mark_shift(0);
mark_shift(0) <= mark_in;
end if;
end process;
end RTL;
| mit | 1dfdc3163fb43931454013e713897e27 | 0.31205 | 4.369352 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_vvc_framework/src_target_dependent/td_vvc_framework_common_methods_pkg.vhd | 1 | 43,570 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Note: This package will be compiled into every single VVC library.
-- As the type t_vvc_target_record is already compiled into every single VVC library,
-- the type definition will be unique for every library, and thus result in a unique
-- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will
-- refer to only the shared variable defined in the given library.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result
use work.td_target_support_pkg.all;
package td_vvc_framework_common_methods_pkg is
--======================================================================
-- Common Methods
--======================================================================
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_any_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Waits for the first of multiple VVCs to finish :
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Overload with wanted_idx
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Disables the specified msg_id for the VVC
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- See description above
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Enables the specified msg_id for the VVC
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- See description above
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Flushes the command queue of the specified VVC
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- See description above
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- fetch_result
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Fetches result from a VVC
-- - Requires that result is available (i.e. already executed in respective VVC)
-- - Logs with ID ID_UVVM_CMD_RESULT
-- The 'result' parameter is of type t_vvc_result to
-- support that the BFM returns something other than a std_logic_vector.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- -- - This version does not use vvc_channel.
-- -- - Fetches result from a VVC
-- -- - Requires that result is available (i.e. already executed in respective VVC)
-- -- - Logs with ID ID_UVVM_CMD_RESULT
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for 'delay' clock cycles
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for a given time
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_current_command
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_all_commands
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor, and
-- flushes the command queue
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) return natural;
end package td_vvc_framework_common_methods_pkg;
package body td_vvc_framework_common_methods_pkg is
--=========================================================================================
-- Methods
--=========================================================================================
-- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local vvc_cmd_pkg.
-- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.)
-- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either
-- a) include the new operator(s) in its t_operation, or
-- b) change the use-reference to an older common_methods package.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout, scope);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, timeout, msg, scope);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout, scope);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg, scope);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
shared_vvc_cmd.gen_boolean := true; -- LAST
else
shared_vvc_cmd.gen_boolean := false; -- NOT_LAST
end if;
send_command_to_vvc(vvc_target, timeout, scope); -- sets vvc_target.trigger, then waits until global_vvc_ack = '1' for timeout
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, lastness, timeout, msg, awaiting_completion_idx, scope);
end procedure;
-- The two below are as the two above, except with wanted_idx as parameter
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
-- LAST
shared_vvc_cmd.gen_boolean := true;
else
-- NOT_LAST : Timeout must be handled in interpreter_await_any_completion
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
shared_vvc_cmd.gen_boolean := false;
end if;
send_command_to_vvc(vvc_target, timeout, scope);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0; -- Useful when being called by multiple sequencers
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx, scope);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness, scope);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness, scope);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE);
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, NA, msg, scope);
end procedure;
-- Requires that result is available (i.e. already executed in respective VVC)
-- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
await_semaphore_in_delta_cycles(protected_response_semaphore);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
send_command_to_vvc(vvc_target, scope => scope);
-- Post process
result := shared_vvc_response.result;
fetch_is_accepted := shared_vvc_response.fetch_is_accepted;
if caller_name = "base_procedure" then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), scope); -- Get and ack the new command
end if;
release_semaphore(protected_response_semaphore);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
variable v_fetch_is_accepted : boolean;
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok", scope);
if v_fetch_is_accepted then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & format_command_idx(shared_cmd_idx), scope); -- Get and ack the new command
else
alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." &
" Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), scope);
end if;
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level, scope);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level, scope);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.gen_integer_array(0) := delay;
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg, scope);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.delay := delay;
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg, scope);
end procedure;
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND);
send_command_to_vvc(vvc_target, scope => scope);
end procedure;
-- Overload without VVC channel
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant vvc_channel : t_channel := NA;
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx) -- First part common for all
& ")";
begin
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg, scope);
end procedure;
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel,msg);
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg, scope);
end procedure;
-- Overload without VVC channel
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant vvc_channel : t_channel := NA;
begin
terminate_all_commands(vvc_target, vvc_instance_idx, vvc_channel, msg, scope);
end procedure;
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) return natural is
variable v_cmd_idx : integer := -1;
begin
v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx);
check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, scope, ID_NEVER);
if v_cmd_idx /= -1 then
return v_cmd_idx;
else
-- return 0 in case of failure
return 0;
end if;
end function;
end package body td_vvc_framework_common_methods_pkg;
| mit | be615f2ce07b038da838f8ffcdb452c6 | 0.582121 | 4.146759 | false | false | false | false |
makestuff/swled | fifo/vhdl/fifo_rtl.vhdl | 1 | 5,834 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of swled is
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- FIFOs implementing the channels
signal fifoCount : std_logic_vector(15 downto 0); -- MSB=writeFifo, LSB=readFifo
-- Write FIFO:
signal writeFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal writeFifoInputValid : std_logic; -- valid flag
signal writeFifoInputReady : std_logic; -- ready flag
signal writeFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal writeFifoOutputValid : std_logic; -- valid flag
signal writeFifoOutputReady : std_logic; -- ready flag
-- Read FIFO:
signal readFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal readFifoInputValid : std_logic; -- valid flag
signal readFifoInputReady : std_logic; -- ready flag
signal readFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal readFifoOutputValid : std_logic; -- valid flag
signal readFifoOutputReady : std_logic; -- ready flag
-- Counter which endlessly puts items into the read FIFO for the host to read
signal count, count_next : std_logic_vector(7 downto 0) := (others => '0');
-- Producer and consumer timers
signal producerSpeed : std_logic_vector(3 downto 0);
signal consumerSpeed : std_logic_vector(3 downto 0);
begin --BEGIN_SNIPPET(fifos)
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
count <= (others => '0');
else
count <= count_next;
end if;
end if;
end process;
-- Wire up write FIFO to channel 0 writes:
-- flags(2) driven by writeFifoOutputValid
-- writeFifoOutputReady driven by consumer_timer
-- LEDs driven by writeFifoOutputData
writeFifoInputData <=
h2fData_in;
writeFifoInputValid <=
'1' when h2fValid_in = '1' and chanAddr_in = "0000000"
else '0';
h2fReady_out <=
'0' when writeFifoInputReady = '0' and chanAddr_in = "0000000"
else '1';
-- Wire up read FIFO to channel 0 reads:
-- readFifoInputValid driven by producer_timer
-- flags(0) driven by readFifoInputReady
count_next <=
std_logic_vector(unsigned(count) + 1) when readFifoInputValid = '1'
else count;
readFifoInputData <=
count;
f2hValid_out <=
'0' when readFifoOutputValid = '0' and chanAddr_in = "0000000"
else '1';
readFifoOutputReady <=
'1' when f2hReady_in = '1' and chanAddr_in = "0000000"
else '0';
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
readFifoOutputData when "0000000", -- get from read FIFO
fifoCount(15 downto 8) when "0000001", -- get depth of write FIFO
fifoCount(7 downto 0) when "0000010", -- get depth of read FIFO
x"00" when others; --END_SNIPPET(fifos)
-- Write FIFO: written by host, read by LEDs
write_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(15 downto 8),
-- Production end
inputData_in => writeFifoInputData,
inputValid_in => writeFifoInputValid,
inputReady_out => writeFifoInputReady,
-- Consumption end
outputData_out => writeFifoOutputData,
outputValid_out => writeFifoOutputValid,
outputReady_in => writeFifoOutputReady
);
-- Read FIFO: written by counter, read by host
read_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(7 downto 0),
-- Production end
inputData_in => readFifoInputData,
inputValid_in => readFifoInputValid,
inputReady_out => readFifoInputReady,
-- Consumption end
outputData_out => readFifoOutputData,
outputValid_out => readFifoOutputValid,
outputReady_in => readFifoOutputReady
);
-- Producer timer: how fast stuff is put into the read FIFO
producerSpeed <= not(sw_in(3 downto 0));
producer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => producerSpeed,
tick_out => readFifoInputValid
);
-- Consumer timer: how fast stuff is drained from the write FIFO
consumerSpeed <= not(sw_in(7 downto 4));
consumer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => consumerSpeed,
tick_out => writeFifoOutputReady
);
-- LEDs and 7-seg display
led_out <= writeFifoOutputData;
flags <= '0' & writeFifoOutputValid & '0' & readFifoInputReady;
seven_seg : entity work.seven_seg
port map(
clk_in => clk_in,
data_in => fifoCount,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
| gpl-3.0 | 58b88038e662849b13eb747dee8db90c | 0.64107 | 3.683081 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_4_dir/exercise6_4.vhd | 1 | 1,387 | --!
--! @file: exercise6_3.vhd
--! @brief: registered multiplexer
--! @author: Antonio Gutierrez
--! @date: 2013-10-24
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
use work.my_data_types.all;
--------------------------------------
entity reg_mux is
generic (M: integer := 5; -- number of inputs
N: integer := 8); -- number of bits per input
port (
x: in matrix(0 to M-1, N-1 downto 0);
sel: in std_logic_vector(M-1 downto 0); ;
y: out std_logic_vector(N-1 downto 0));
end entity reg_mux;
--------------------------------------
architecture circuit of reg_mux is
signal mux_out: std_logic_vector(N-1 downto 0);
signal sel_un: unsigned(M-1 downto 0);
begin
-- using sel as an index we need to use an unsigned
sel_un <= unsigned(sel);
-- assign depending on sel each one of bits in the selected input to the output
gen: for i in N-1 downto 0 generate
mux_out(i) <= x(sel_un, i);
end generate gen;
proc: process (clk)
begin
if (clk'event and clk='1') then
y <= mux_out;
end if;
end process label;
-- maybe this can work as well
-- with sel_un select
-- mux_out <= x(0) when 0,
-- x(sel_un) when others;
end architecture circuit;
--------------------------------------
| gpl-3.0 | af8f404658df26f00f852d8633f9b1c1 | 0.533526 | 3.659631 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/shift_register_dir/shift_register.vhd | 1 | 909 | -- author: Antonio Gutierrez
-- date: 03/10/13
-- description: shift register
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity shift_register is
generic (N: integer := 4;); ---- number of stages
port (
din, clk, rst: in std_logic;
dout: out std_logic);
end entity shift_register;
--------------------------------------
architecture shift_register of shift_register is
--signals and declarations
begin
main: process (clk, rst)
variable q: std_logic_vector(0 to N-1);
begin
if (rst = '1') then
q := (others => '0');
elsif (clk'event and clk = '1') then
q := din & q(0 to N-2); ---- concatenate din to three least significant bits of q
end if;
dout <= q(N-1); -- dout is the msb of q
end process main;
end architecture shift_register;
| gpl-3.0 | d3fed53b8d929a719a61cb43c2dfc87e | 0.532453 | 4.058036 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/std/std_pkg.vhd | 1 | 9,924 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
PACKAGE std_pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
component sram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component sram_4en generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component dsram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
function v_or(d : std_logic_vector) return std_logic;
function is_zero(d : std_logic_vector) return std_logic;
function is_not_zero(d : std_logic_vector) return std_logic;
function my_conv_integer(a: std_logic_vector) return integer;
function notx(d : std_logic_vector) return boolean;
function compare(a, b : std_logic_vector) return std_logic;
function multiply(a, b : std_logic_vector) return std_logic_vector;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
function increment(a : std_logic_vector) return std_logic_vector;
function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
end std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
function v_or(d : std_logic_vector) return std_logic is
variable z : std_logic;
begin
z := '0';
if notx (d) then
for i in d'range loop
z := z or d(i);
end loop;
end if;
return z;
end;
-- Check for ones in the vector
function is_not_zero(d : std_logic_vector) return std_logic is
variable z : std_logic_vector(d'range);
begin
z := (others => '0');
if notx(d) then
if d = z then
return '0';
else
return '1';
end if;
else
return '0';
end if;
end;
-- Check for ones in the vector
function is_zero(d : std_logic_vector) return std_logic is
begin
return not is_not_zero(d);
end;
-- rewrite conv_integer to avoid modelsim warnings
function my_conv_integer(a : std_logic_vector) return integer is
variable res : integer range 0 to 2**a'length-1;
begin
res := 0;
if (notx(a)) then
res := to_integer(unsigned(a));
end if;
return res;
end;
function compare(a, b : std_logic_vector) return std_logic is
variable z : std_logic;
begin
if notx(a & b) and a = b then
return '1';
else
return '0';
end if;
end;
-- Unary NOT X test
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) = (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) != 0 then
-- -- (rD)[0:(rB)[27:31]-1] = (rA)[0]
-- -- (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) = (rA)
-- -- else
-- -- (rD) = (rA) >> (rB)[27:31]
function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
begin
if s = '1' then
-- left arithmetic or logical shift
return shift_left(value, shamt);
else
if t = '1' then
-- right arithmetic shift
return shift_right(value, shamt, value(31));
else
-- right logical shift
return shift_right(value, shamt, '0');
end if;
end if;
end;
function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => '0');
result := value;
if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 ); end if;
return result;
end;
function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => padding);
result := value;
if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto 8); end if;
if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto 4); end if;
if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto 2); end if;
if (shamt(0) = '1') then result := paddings( 0 ) & result(31 downto 1); end if;
return result;
end;
function multiply(a, b: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector (a'length + b'length - 1 downto 0);
begin
x := std_logic_vector(signed(a) * signed(b));
return x(31 downto 0);
end;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
variable a: std_logic_vector (size - 1 downto 0);
begin
a(size - 1 downto value'length) := (others => fill);
a(value'length - 1 downto 0) := value;
return a;
end;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
variable x : std_logic_vector(a'length + 1 downto 0);
begin
x := (others => '0');
if notx (a & b & ci) then
x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
end if;
return x(a'length + 1 downto 1);
end;
function increment(a : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
begin
x := (others => '0');
if notx (a) then
x := std_logic_vector(signed(a) + 1);
end if;
return x;
end;
end std_pkg; | lgpl-3.0 | b178ee2d497df96e560364c8492891db | 0.540004 | 3.743493 | false | false | false | false |
makestuff/swled | fifo/vhdl/fifo-gen/fifo_wrapper_altera.vhdl | 1 | 2,005 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
depth_out : out std_logic_vector(7 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.altera_fifo
port map(
clock => clk_in,
usedw => depth_out,
-- Production end
data => inputData_in,
wrreq => inputValid_in,
full => inputFull,
-- Consumption end
q => outputData_out,
empty => outputEmpty,
rdreq => outputReady_in
);
end architecture;
| gpl-3.0 | b1b02149dff55d1af97257b6d3be1d6c | 0.686783 | 3.625678 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/example10_4_dir/reg_mux_tb.vhd | 1 | 2,736 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------
entity reg_mux_tb is
generic (tp: time := 10 ns);
end entity reg_mux_tb;
--------------------------------------
architecture circuit of reg_mux_tb is
-- DUT declaration
component reg_mux is
port( a, b, c, d: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0) ;
clk: in std_logic;
x, y: out std_logic_vector(3 downto 0));
end component reg_mux;
-- signals declarations
signal a_tb: std_logic_vector(3 downto 0) := "0010";
signal b_tb: std_logic_vector(3 downto 0) := "0100";
signal c_tb: std_logic_vector(3 downto 0) := "0110";
signal d_tb: std_logic_vector(3 downto 0) := "1000";
signal sel_tb: std_logic_vector(1 downto 0) := "00";
signal clk_tb: std_logic := '0';
signal x_tb: std_logic_vector(3 downto 0);
signal y_tb: std_logic_vector(3 downto 0);
signal expected: std_logic_vector(3 downto 0) := "0000";
begin
-- dut instantiation
dut: reg_mux port map (
a => a_tb,
b => b_tb,
c => c_tb,
d => d_tb,
sel => sel_tb,
clk => clk_tb,
x => x_tb,
y => y_tb
);
-- stimuli generation
clk_tb <= not clk_tb after 40 ns;
a_tb <= "0011" after 80 ns, "0000" after 640 ns;
b_tb <= "0101" after 240 ns;
c_tb <= "0111" after 400 ns;
d_tb <= "1001" after 560 ns;
sel_tb <= "01" after 160 ns,
"10" after 320 ns,
"11" after 480 ns,
"00" after 640 ns;
-- output verification
-- (i) generate template
expected <= "0010" after 40 ns + tp,
"0011" after 120 ns + tp,
"0100" after 200 ns + tp,
"0101" after 280 ns + tp,
"0110" after 360 ns + tp,
"0111" after 440 ns + tp,
"1000" after 520 ns + tp,
"1001" after 600 ns + tp,
"0000" after 680 ns + tp;
--(ii) make comparison:
process
begin
wait for 40 ns + tp; -- before 40ns (first rising edge) y_tb is X because it isn't assigned a proper value that's why I needed to modify the example code and add 40 ns
if (now < 800 ns) then
assert (y_tb = expected)
report "Mismatch at t=" & time'image(now) & " y_tb=" & integer'image(conv_integer(y_tb)) & " y_exp=" & integer'image(conv_integer(expected))
severity failure;
else
assert false
report "No error found (t=" & time'image(now) & ")"
severity note;
end if;
end process;
end architecture circuit;
| gpl-3.0 | 6bd1071d37f369c1370cec537c74f562 | 0.521199 | 3.567145 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/control.vhd | 1 | 24,459 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
calu_1_func : out std_logic_vector(5 downto 0);
salu_1_func : out std_logic_vector(5 downto 0);
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
variable func_alu_comb_1: std_logic_vector(5 downto 0);
variable func_alu_sequ_1: std_logic_vector(5 downto 0);
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
func_alu_comb_1 := "000000";
func_alu_sequ_1 := "000000";
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
-- B GIN ENABLE_(SLL)
when "000000" => --SLL r[rd] = r[rt] << re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
-- E D ENABLE_(SLL)
-- BEGIN ENABLE_(SRL)
when "000010" => --SRL r[rd] = u[rt] >> re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
-- END ENABLE_(SRL)
-- BEGIN ENABLE_(SRA)
when "000011" => --SRA r[rd] = r[rt] >> re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
-- END ENABLE_(SRA)
-- BEGIN ENABLE_(SLLV)
when "000100" => --SLLV r[rd] = r[rt] << r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
-- END ENABLE_(SLLV)
-- BEGIN ENABLE_(SRLV)
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
-- END ENABLE_(SRLV)
-- BEGIN ENABLE_(SRAV)
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
-- END ENABLE_(SRAV)
-- BEGIN ENABLE_(JR)
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
-- END ENABLE_(JR)
-- BEGIN ENABLE_(JALR)
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
-- END ENABLE_(JALR)
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
-- BEGIN ENABLE_(SYSCALL)
when "001100" => --SYSCALL
is_syscall := '1';
-- END ENABLE_(SYSCALL)
-- BEGIN 3NABLE_(BREAK)
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
if ( opcode(16) = '1' ) then
--ASSERT false REPORT "ON LANCE UN CRASH VOLONTAIRE (INSTR = CRASH) : SUCCESS" SEVERITY FAILURE;
ASSERT false REPORT "=> SUCCESS <=" SEVERITY FAILURE;
else
--ASSERT false REPORT "ON LANCE UN CRASH VOLONTAIRE (INSTR = CRASH) : FAILURE" SEVERITY FAILURE;
ASSERT false REPORT "=> FAILURE <=" SEVERITY FAILURE;
end if;
-- END 3NABLE_(BREAK)
-- BEGIN ENABLE_(SYNC)
--when "001111" => --SYNC s->wakeup=1;
-- END ENABLE_(SYNC)
-- BEGIN ENABLE_(MFHI)
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
-- END ENABLE_(MFHI)
-- BEGIN ENABLE_(MTHI)
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
-- END ENABLE_(MTHI)
-- BEGIN ENABLE_(MFLO)
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MTLO)
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
-- END ENABLE_(MTLO)
-- BEGIN ENABLE_(MULT)
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
-- END ENABLE_(MULT)
-- BEGIN ENABLE_(MULTU)
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
-- END ENABLE_(MULTU)
-- BEGIN ENABLE_(DIV)
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
-- END ENABLE_(DIV)
-- BEGIN ENABLE_(DIVU)
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
-- END ENABLE_(DIVU)
-- BEGIN ENABLE_(ADD)
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
-- END ENABLE_(ADD)
-- BEGIN ENABLE_(ADDU)
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
-- END ENABLE_(ADDU)
-- BEGIN ENABLE_(SUB)
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
-- END ENABLE_(SUB)
-- BEGIN ENABLE_(SUBU)
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
-- END ENABLE_(SUBU)
-- BEGIN ENABLE_(AND)
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
-- END ENABLE_(AND)
-- BEGIN ENABLE_(OR)
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
-- END ENABLE_(OR)
-- BEGIN ENABLE_(XOR)
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
-- END ENABLE_(XOR)
-- BEGIN ENABLE_(NOR)
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
-- END ENABLE_(NOR)
-- BEGIN ENABLE_(SLT)
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
-- END ENABLE_(SLT)
-- BEGIN ENABLE_(SLTU)
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
-- END ENABLE_(SLTU)
-- BEGIN ENABLE_(DADDU)
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
-- END ENABLE_(DADDU)
-- BEGIN ENABLE_(TGEU)
--when "110001" => --TGEU
-- END ENABLE_(TGEU)
-- BEGIN ENABLE_(TLT)
--when "110010" => --TLT
-- END ENABLE_(TLT)
-- BEGIN ENABLE_(TLTU)
--when "110011" => --TLTU
-- END ENABLE_(TLTU)
-- BEGIN ENABLE_(TEQ)
--when "110100" => --TEQ
-- END ENABLE_(TEQ)
-- BEGIN ENABLE_(TNE)
--when "110110" => --TNE
-- END ENABLE_(TNE)
-- BEGIN ENABLE_(COMB_ALU_1)
when "000001" => --X01
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "000101" => --X05
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "001010" => --X0A
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "011110" => --X1E
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "011111" => --X1F
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "101000" => --X28
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "101001" => --X29
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "101100" => --X2C
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "101110" => --X2E
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "101111" => --X2F
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "110000" => --X30
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "110101" => --X35
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "110111" => --X37
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111000" => --X38
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111001" => --X39
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111010" => --X3A
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111011" => --X3B
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111100" => --X3C
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111101" => --X3D
c_source := C_FROM_ALU;
func_alu_comb_1 := func;
when "111110" => --X3E
c_source := C_FROM_ALU;
func_alu_sequ_1 := "000001";
when "111111" => --X3F
c_source := C_FROM_ALU;
func_alu_sequ_1 := func;
-- END ENABLE_(COMB_ALU_1)
when others =>
--ASSERT false REPORT "INSTRUCTION INCONNUE (0)" SEVERITY WARNING;
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
-- BEGIN ENABLE_(BLTZAL)
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
-- END ENABLE_(BLTZAL)
-- BEGIN ENABLE_(BLTZ)
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
-- END ENABLE_(BLTZ)
-- BEGIN ENABLE_(BGEZAL)
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
-- END ENABLE_(BGEZAL)
-- BEGIN ENABLE_(BGEZ)
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
-- END ENABLE_(BGEZ)
-- BEGIN ENABLE_(BLTZALL)
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
-- END ENABLE_(BLTZALL)
-- BEGIN ENABLE_(BLTZL)
--when "00010" => --BLTZL lbranch=r[rs]<0;
-- END ENABLE_(BLTZL)
-- BEGIN ENABLE_(BGEZALL)
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
-- END ENABLE_(BGEZALL)
-- BEGIN ENABLE_(BGEZL)
--when "00011" => --BGEZL lbranch=r[rs]>=0;
-- END ENABLE_(BGEZL)
when others =>
--ASSERT false REPORT "INSTRUCTION INCONNUE (1)" SEVERITY WARNING;
end case;
-- BEGIN ENABLE_(JAL)
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
-- END ENABLE_(JAL)
-- BEGIN ENABLE_(J)
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
-- END ENABLE_(J)
-- BEGIN ENABLE_(BEQ)
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
-- END ENABLE_(BEQ)
-- BEGIN ENABLE_(BNE)
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
-- END ENABLE_(BNE)
-- BEGIN ENABLE_(BLEZ)
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
-- END ENABLE_(BLEZ)
-- BEGIN ENABLE_(BGTZ)
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
-- END ENABLE_(BGTZ)
-- BEGIN ENABLE_(ADDI)
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
-- END ENABLE_(ADDI)
-- BEGIN ENABLE_(ADDIU)
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
-- END ENABLE_(ADDIU)
-- BEGIN ENABLE_(SLTI)
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
-- END ENABLE_(SLTI)
-- BEGIN ENABLE_(SLTIU)
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
-- END ENABLE_(SLTIU)
-- BEGIN ENABLE_(ANDI)
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
-- END ENABLE_(ANDI)
-- BEGIN ENABLE_(ORI)
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
-- END ENABLE_(ORI)
-- BEGIN ENABLE_(XORI)
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
-- END ENABLE_(XORI)
-- BEGIN ENABLE_(LUI)
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
-- END ENABLE_(LUI)
-- BEGIN ENABLE_(COP0)
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
-- END ENABLE_(COP0)
-- BEGIN ENABLE_(COP1)
--when "010001" => --COP1
-- END ENABLE_(COP1)
-- BEGIN ENABLE_(COP2)
--when "010010" => --COP2
-- END ENABLE_(COP2)
-- BEGIN ENABLE_(COP3)
--when "010011" => --COP3
-- END ENABLE_(COP3)
-- BEGIN ENABLE_(BEQL)
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
-- END ENABLE_(BEQL)
-- BEGIN ENABLE_(BNEL)
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
-- END ENABLE_(BNEL)
-- BEGIN ENABLE_(BLEZL)
--when "010110" => --BLEZL lbranch=r[rs]<=0;
-- END ENABLE_(BLEZL)
-- BEGIN ENABLE_(BGTZL)
--when "010111" => --BGTZL lbranch=r[rs]>0;
-- END ENABLE_(BGTZL)
-- BEGIN ENABLE_(LB)
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
-- END ENABLE_(LB)
-- BEGIN ENABLE_(LH)
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
-- END ENABLE_(LH)
-- BEGIN ENABLE_(LWL)
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
-- END ENABLE_(LWL)
-- BEGIN ENABLE_(LW)
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
-- END ENABLE_(LW)
-- BEGIN ENABLE_(LBU)
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
-- END ENABLE_(LBU)
-- BEGIN ENABLE_(LHU)
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
-- END ENABLE_(LHU)
-- BEGIN ENABLE_(LWR)
--when "100110" => --LWR //Not Implemented
-- END ENABLE_(LWR)
-- BEGIN ENABLE_(SB)
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
-- END ENABLE_(SB)
-- BEGIN ENABLE_(SH)
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
-- END ENABLE_(SH)
-- BEGIN ENABLE_(SWL)
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
-- END ENABLE_(SWL)
-- BEGIN ENABLE_(SW)
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
-- END ENABLE_(SW)
-- BEGIN ENABLE_(SWR)
--when "101110" => --SWR //Not Implemented
-- END ENABLE_(SWR)
-- BEGIN ENABLE_(CACHE)
--when "101111" => --CACHE
-- END ENABLE_(CACHE)
-- BEGIN ENABLE_(LL)
--when "110000" => --LL r[rt]=*(long*)ptr;
-- END ENABLE_(LL)
-- BEGIN ENABLE_(LWC1)
--when "110001" => --LWC1
-- END ENABLE_(LWC1)
-- BEGIN ENABLE_(LWC2)
--when "110010" => --LWC2
-- END ENABLE_(LWC2)
-- BEGIN ENABLE_(LWC3)
--when "110011" => --LWC3
-- END ENABLE_(LWC3)
-- BEGIN ENABLE_(LDC1)
--when "110101" => --LDC1
-- END ENABLE_(LDC1)
-- BEGIN ENABLE_(LDC2)
--when "110110" => --LDC2
-- END ENABLE_(LDC2)
-- BEGIN ENABLE_(LDC3)
--when "110111" => --LDC3
-- END ENABLE_(LDC3)
-- BEGIN ENABLE_(SC)
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
-- END ENABLE_(SC)
-- BEGIN ENABLE_(SWC1)
--when "111001" => --SWC1
-- END ENABLE_(SWC1)
-- BEGIN ENABLE_(SWC2)
--when "111010" => --SWC2
-- END ENABLE_(SWC2)
-- BEGIN ENABLE_(SWC3)
--when "111011" => --SWC3
-- END ENABLE_(SWC3)
-- BEGIN ENABLE_(SDC1)
--when "111101" => --SDC1
-- END ENABLE_(SDC1)
-- BEGIN ENABLE_(SDC2)
--when "111110" => --SDC2
-- END ENABLE_(SDC2)
-- BEGIN ENABLE_(SDC3)
--when "111111" => --SDC3
-- END ENABLE_(SDC3)
when others =>
--IF op /= "XXXXXX" THEN
--ASSERT false REPORT "INSTRUCTION INCONNUE (2)" SEVERITY WARNING;
--END IF;
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
func_alu_comb_1 := "000000";
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH;
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
calu_1_func <= func_alu_comb_1;
salu_1_func <= func_alu_sequ_1;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
| gpl-3.0 | 2a17b6ec00f1a093704e352726ca0e2b | 0.510201 | 3.028228 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/mem_ctrl.vhd | 1 | 8,120 | ---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector( 3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
-- BEGIN ENABLE_(LHU)
when MEM_READ16 =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
--if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
--else
-- data_read_var(31 downto 16) := ONES(31 downto 16);
--end if;
-- END ENABLE_(LHU)
-- BEGIN ENABLE_(LH)
when MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
--if mem_source = MEM_READ16 or data_read_var(15) = '0' then
if data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
-- END ENABLE_(LH)
-- BEGIN ENABLE_(LBU)
when MEM_READ8 =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
--if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
--else
-- data_read_var(31 downto 8) := ONES(31 downto 8);
--end if;
-- END ENABLE_(LBU)
-- BEGIN ENABLE_(LB)
when MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
--if mem_source = MEM_READ8 or data_read_var(7) = '0' then
if data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
-- END ENABLE_(LB)
-- BEGIN ENABLE_(SW,SWL)
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
-- END ENABLE_(SW,SWL)
-- BEGIN ENABLE_(SH)
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
-- END ENABLE_(SH)
-- BEGIN ENABLE_(SB)
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
-- END ENABLE_(SB)
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
| gpl-3.0 | 2377a753ed6a3bca080c9088be00ddde | 0.546798 | 3.316993 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_stim_gen.vhd | 1 | 11,020 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.dist_mem_gen_v7_2_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.dist_mem_gen_v7_2_TB_PKG.ALL;
ENTITY dist_mem_gen_v7_2_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END dist_mem_gen_v7_2_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF dist_mem_gen_v7_2_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (16383 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"dist_mem_gen_v7_2.mif",
DEFAULT_DATA,
32,
16384);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.dist_mem_gen_v7_2_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.dist_mem_gen_v7_2_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| mit | f9abce2ed19a23bbdfd1cb25fb6970be | 0.573775 | 3.679466 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_1_dir/exercise8_1.vhd | 1 | 1,572 | --!
--! @file: exercise8_1.vhd
--! @brief: mux with compenent and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mux4to1 is
--generic declarations
port (
a, b, c, d: in std_logic;
sel: in std_logic_vector(1 downto 0);
x: out std_logic);
end entity mux4to1;
--------------------------------------
architecture circuit of mux4to1 is
--signals and declarations
begin
with sel select
x <= a when "00",
b when "01",
c when "10",
d when others;
end architecture circuit;
--------------------------------------
--------------------------------------
--------------------------------------
entity exercise8_1 is
generic (N: integer := 5);
port (
a, b, c, d: in std_logic_vector(N-1 downto 0);
sel: in std_logic_vector(1 downto 0);
x: out std_logic_vector(N-1 downto 0));
end entity exercise8_1;
--------------------------------------
architecture circuit of exercise8_1 is
component mux4to1 is
port (
a, b, c, d: in std_logic;
sel: in std_logic_vector(1 downto 0);
x: out std_logic);
end component mux4to1;
begin
gen1: for i in 0 to N-1 generate
mux1: mux port map (
a => a(i),
b => b(i),
c => c(i),
d => d(i)
);
end generate gen1;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 033ee584ec0514b5aa540780b381c44c | 0.459924 | 3.9202 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_9_dir/exercise6_9.vhd | 1 | 1,587 | --!
--! @file: exercise6_9.vhd
--! @brief: switch debouncer
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity switch_debouncer is
generic (FCLK: integer := 50; -- clock frequency in MHZ
twindow: integer := 10); -- time window in ms
port (
sw: in std_logic;
clk: in std_logic;
deb_sw: buffer std_logic);
end entity switch_debouncer;
--------------------------------------
architecture circuit of switch_debouncer is
constant max: integer := 50 * 10 * 1000; -- number of clock periods there are in 10ms
begin
proc: process (clk)
variable count: integer 0 to max; -- keeps count of how many clicks
begin
if (clk'event and clk = '1') then -- if there was a rising edge
if (deb_sw /= sw) then -- if there was a change in the switch, increment count
count <= count + 1;
if (count = max) then -- if 10ms passed
deb_sw <= sw; -- assign input to output and reset count
count <= 0;
end if;
else -- if there isn't any change in the switch then just reset the count
count := 0;
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 715b1af9bef7c74ca4fa947abb887368 | 0.47259 | 4.695266 | false | false | false | false |
chibby0ne/vhdl-book | Chapter3/multiplier_typeconversion_dir/multiplier_typeconversion.vhd | 1 | 1,382 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for arch1
-- use ieee.std_logic_arith.all; -- for arch2, arch3
-- best to use arch2 using numeric_std
------------------------------
entity signed_multiplier is
--generic declarations
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
prod: out std_vector_vector(7 downto 0);
);
end entity;
------------------------------
architecture arch1 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal a_sig: signed(3 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod <= std_logic_vector(a_sig * b_sig);
end architecture;
------------------------------
architecture arch2 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal b_sig: signed(3 downto 0);
signal prod: signed(7 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod_sig <= a_sig * b_sig;
prod <= std_logic_vector(prod_sig);
end architecture;
------------------------------
architecture arch2 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal b_sig: signed(3 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod <= std_logic_vector(signed(a_sig * b_sig));
end architecture;
------------------------------
| gpl-3.0 | a91af8dafe1a3c9469b3c38f5a6729a0 | 0.553546 | 3.656085 | false | false | false | false |
ryos36/polyphony-tutorial | Life/life_tb.vhdl | 1 | 2,666 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use iEEE.std_logic_arith.all;
use iEEE.std_logic_unsigned."-";
use iEEE.std_logic_unsigned."+";
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity life_tb is
end life_tb;
architecture behav of life_tb is
component life
port(
clk : in std_logic;
din : in std_logic_vector(2 downto 0);
mark_in : in std_logic;
dout : out std_logic;
mark_out : out std_logic
);
end component;
signal clk : std_logic;
signal data0 : std_logic_vector(31 downto 0) := "01111100001010101101110110101010";
signal data1 : std_logic_vector(31 downto 0) := "11000001111010101101110110001000";
signal data2 : std_logic_vector(31 downto 0) := "11100000001010101101110110101111";
signal din : std_logic_vector(2 downto 0);
signal result : std_logic;
signal mark_in : std_logic;
signal mark_out : std_logic;
signal counter : std_logic_vector(2 downto 0) := "000";
constant clk_period : time := 10 ns;
begin
-------------------------------------------------------------------
din <= data0(31) & data1(31) & data2(31);
life0 : life
port map (
clk => clk,
din => din,
mark_in => mark_in,
dout => result,
mark_out => mark_out
);
-------------------------------------------------------------------
clk_producer: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-------------------------------------------------------------------
kicker: process(clk)
variable line0 : line;
begin
if clk'event and clk = '1' then
write( line0, String'("din:"));
write( line0, din);
writeline( output, line0);
data0 <= data0(30 downto 0) & data0(31);
data1 <= data1(30 downto 0) & data1(31);
data2 <= data2(30 downto 0) & data2(31);
end if;
end process;
-------------------------------------------------------------------
cnt: process(clk)
begin
if clk'event and clk = '1' then
counter <= counter + 1;
if mark_in = '1' then
mark_in <= '0';
end if;
if counter = "000" then
mark_in <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------
data_cosumer: process(clk)
variable line0 : line;
begin
if clk'event and clk = '1' then
write( line0, String'("result:"));
write( line0, result );
write( line0, String'(" "));
write( line0, mark_out );
writeline( output, line0);
end if;
end process;
end behav;
| mit | 9183c3fe13e4469d36691ddd338b38a0 | 0.518005 | 3.692521 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_C.vhd | 1 | 2,542 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_C is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_C is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(2 downto 0);
begin
reg : process(clk)
variable vready, vnready : std_logic;
begin
vready := '0';
vnready := '0';
if rising_edge(clk) then
if (rst = '0') then
state <= "000";
elsif (inp.flush = '1') then
state <= "000";
elsif (holdn = '1') then
state <= state;
else
case state is
-- ON ATTEND LA COMMANDE DE START
when "000" =>
if (inp.start = '1') then
--v.x(64) := divi.y(32);
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "010";
else
state <= "000";
A <= A;
B <= B;
end if;
-- ON COMMENCE LE CALCUL
when "001" =>
if( SIGNED(A) > SIGNED(B) ) then
A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
else
B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
end if;
state <= "010";
-- ON TEST LES DONNEES (FIN D'ITERATION)
when "010" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "011";
vnready := '1';
else
state <= "001";
end if;
when others =>
-- ON INDIQUE QUE LE RESULTAT EST PRET
vready := '1';
-- ON RETOURNE DANS L'ETAT INTIAL
state <= "000";
end case;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
outp.result <= A;
outp.icc <= "0000";
end;
| gpl-3.0 | 3dc07781ed7d7a828fc215018e787170 | 0.525964 | 3.047962 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/Shared.vhd | 1 | 1,261 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package CONSTANTS is
-- Fixed format --
constant FIXED : INTEGER := 28; --Number of bits for , part
-- Data size --
constant XY_RANGE : INTEGER := 32; --Number of bits for x and y data
constant ITER_MAX : INTEGER := 256; --Max number of iteration
constant ITER_RANGE : INTEGER := 3;
constant QUATRE : SIGNED (XY_RANGE-1 downto 0) := to_signed(4,32) sll FIXED ;
constant bit_per_pixel : integer := 12;
constant COLOR_MAX : integer := 2047;
end CONSTANTS;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package FUNCTIONS is
function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR;
end FUNCTIONS;
package body FUNCTIONS is
--Maths functions
function mult(A : SIGNED; B : SIGNED; QF : integer) return SIGNED is
CONSTANT DMAX_R : integer := A'LENGTH + B'LENGTH;
CONSTANT PHI : integer := A'LENGTH - QF;
VARIABLE r : SIGNED(DMAX_R-1 DOWNTO 0);
begin
r := A*B;
return r(DMAX_R - PHI - 1 downto QF);
end mult;
function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(mult(SIGNED(A),SIGNED(B),QF));
end mult;
end FUNCTIONS; | gpl-3.0 | 0a7215459743d3d9de081a2c658eeae8 | 0.693101 | 3.105911 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/id_ex_segment_regfile.vhd | 1 | 2,978 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity id_ex_segment_regfile is
port
(
id_ex_segment_regfile_clk : in std_logic;
id_ex_segment_regfile_write_in : in std_logic;
id_ex_segment_regfile_rdata1_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata2_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata1_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_rdata2_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_pc_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_pc_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_alu_op_in : in std_logic_vector (2 downto 0);
id_ex_segment_regfile_alu_op_out : out std_logic_vector (2 downto 0);
id_ex_segment_regfile_reg_rx_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_reg_rx_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_mem_we_in : in std_logic;
id_ex_segment_regfile_mem_we_out : out std_logic;
id_ex_segment_regfile_pc_src_in : in std_logic_vector (2 downto 0);
id_ex_segment_regfile_pC_src_out : out std_logic_vector (2 downto 0);
id_ex_segment_regfile_reg_ry_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_reg_ry_out : out std_logic_vector (15 downto 0);
id_ex_segment_regfile_src_result_in : in std_logic_vector (1 downto 0);
id_ex_segment_regfile_src_result_out : out std_logic_vector (1 downto 0);
id_ex_segment_regfile_reg_we_in : in std_logic;
id_ex_segment_regfile_reg_we_out : out std_logic;
id_ex_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
id_ex_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
id_ex_segment_regfile_imm_in : in std_logic_vector (15 downto 0);
id_ex_segment_regfile_imm_out : out std_logic_vector (15 downto 0));
end id_ex_segment_regfile;
architecture Behavioral of id_ex_segment_regfile is
begin
process (id_ex_segment_regfile_clk, id_ex_segment_regfile_write_in)
begin
if (id_ex_segment_regfile_write_in = '1') then
id_ex_segment_regfile_rdata1_out <= id_ex_segment_regfile_rdata1_in;
id_ex_segment_regfile_rdata2_out <= id_ex_segment_regfile_rdata2_in;
id_ex_segment_regfile_pc_out <= id_ex_segment_regfile_pc_in;
id_ex_segment_regfile_alu_op_out <= id_ex_segment_regfile_alu_op_in;
id_ex_segment_regfile_reg_rx_out <= id_ex_segment_regfile_reg_rx_in;
id_ex_segment_regfile_reg_ry_out <= id_ex_segment_regfile_reg_ry_in;
id_ex_segment_regfile_mem_we_out <= id_ex_segment_regfile_mem_we_in;
id_ex_segment_regfile_pC_src_out <= id_ex_segment_regfile_pc_src_in;
id_ex_segment_regfile_src_result_out <= id_ex_segment_regfile_src_result_in;
id_ex_segment_regfile_reg_we_out <= id_ex_segment_regfile_reg_we_in;
id_ex_segment_regfile_imm_out <= id_ex_segment_regfile_imm_in;
end if;
end process;
end Behavioral; | apache-2.0 | 8bad7bc7d80d2582d225253d2771315f | 0.702821 | 2.619173 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/simulation/txt_util.vhd | 1 | 12,748 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
--procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
--
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
--
--end str_write;
end txt_util;
| gpl-3.0 | ffa32e362a0f0e5befa024eb37ec2734 | 0.471603 | 3.870067 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/MODULUS_32b.vhd | 1 | 2,800 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity MODULUS_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end MODULUS_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of MODULUS_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
begin
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
OUTPUT_1 <= buf1;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
else
sm <= sm;
end if;
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
| gpl-3.0 | eecc42e0746143696085b4924649b327 | 0.546786 | 3.149606 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_6_dir/exercise6_6.vhd | 1 | 1,133 | --!
--! @file: exercise6_6.vhd
--! @brief: Hamming Weight with LOOP
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity hamming_weight is
generic (N: integer := 5);
port (
x: in bit_vector(N-1 downto 0);
y: out integer range 0 to N);
end entity hamming_weight;
--------------------------------------
architecture circuit of hamming_weight is
signal
begin
proc: process (x)
variable count: integer := 0; -- temp variable that counts the number of 1s
begin
forloop: for i in 0 to N-1 loop -- for each one of the bits in the input vector
if (x(i) = '1') then -- if they are 1
count = count + 1; -- increment count
end if;
end loop forloop;
y <= count; -- once loop through all bits of input vector is finished, assign count to output
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 8319b8aad4b63a99d9157d2bc591eedf | 0.509267 | 4.357692 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/mlite_pack.vhd | 1 | 34,925 | ---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mlite_pack IS
-----------------------------------------------------------------------------------
--
--
CONSTANT ZERO : std_logic_vector(31 DOWNTO 0) :=
"00000000000000000000000000000000";
CONSTANT ONES : std_logic_vector(31 DOWNTO 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
CONSTANT HIGH_Z : std_logic_vector(31 DOWNTO 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-----------------------------------------------------------------------------------
--
--
--subtype alu_function_type is std_logic_vector(3 downto 0);
--constant ALU_NOTHING : alu_function_type := "0000";
--constant ALU_ADD : alu_function_type := "0001";
--constant ALU_SUBTRACT : alu_function_type := "0010";
--constant ALU_LESS_THAN : alu_function_type := "0011";
--constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
--constant ALU_OR : alu_function_type := "0101";
--constant ALU_AND : alu_function_type := "0110";
--constant ALU_XOR : alu_function_type := "0111";
--constant ALU_NOR : alu_function_type := "1000";
TYPE alu_function_type IS (
ALU_NOTHING
, ALU_ADD
, ALU_SUBTRACT
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
, ALU_LESS_THAN
, ALU_LESS_THAN_SIGNED
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
, ALU_OR
-- BEGIN ENABLE_(AND,ANDI)
, ALU_AND
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
, ALU_XOR
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
, ALU_NOR
-- END ENABLE_(NOR)
);
-----------------------------------------------------------------------------------
--
--
--subtype shift_function_type is std_logic_vector(1 downto 0);
--constant SHIFT_NOTHING : shift_function_type := "00";
--constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
--constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
--constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
TYPE shift_function_type IS (
SHIFT_NOTHING
-- IMPOSSIBLE A SUPPRIMER A CAUSE DE L'INSTRUCTION (NOP)
, SHIFT_LEFT_UNSIGNED
-- FIN DE NOP
-- BEGIN ENABLE_(SRA,SRAV)
, SHIFT_RIGHT_SIGNED
-- END ENABLE_(SRA,SRAV)
-- BEGIN ENABLE_(SRL,SRLV)
, SHIFT_RIGHT_UNSIGNED
-- END ENABLE_(SRL,SRLV)
);
-----------------------------------------------------------------------------------
--
--
-- subtype mult_function_type is std_logic_vector(3 downto 0);
-- constant MULT_NOTHING : mult_function_type := "0000";
-- constant MULT_READ_LO : mult_function_type := "0001";
-- constant MULT_READ_HI : mult_function_type := "0010";
-- constant MULT_WRITE_LO : mult_function_type := "0011";
-- constant MULT_WRITE_HI : mult_function_type := "0100";
-- constant MULT_MULT : mult_function_type := "0101";
-- constant MULT_SIGNED_MULT : mult_function_type := "0110";
-- constant MULT_DIVIDE : mult_function_type := "0111";
-- constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
TYPE mult_function_type IS (MULT_NOTHING
-- BEGIN ENABLE_(MFLO)
, MULT_READ_LO
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
, MULT_READ_HI
-- END ENABLE_(MFHI)
-- BEGIN ENABLE_(MTLO)
, MULT_WRITE_LO
-- END ENABLE_(MTLO)
-- BEGIN ENABLE_(MTHI)
, MULT_WRITE_HI
-- END ENABLE_(MTHI)
-- BEGIN ENABLE_(MULTU)
, MULT_MULT
-- END ENABLE_(MULTU)
-- BEGIN ENABLE_(MULT)
, MULT_SIGNED_MULT
-- END ENABLE_(MULT)
-- BEGIN ENABLE_(DIVU)
, MULT_DIVIDE
-- END ENABLE_(DIVU)
-- BEGIN ENABLE_(DIV)
, MULT_SIGNED_DIVIDE
-- END ENABLE_(DIV)
);
-----------------------------------------------------------------------------------
--
--
SUBTYPE a_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT A_FROM_REG_SOURCE : a_source_type := "00";
CONSTANT A_FROM_IMM10_6 : a_source_type := "01";
CONSTANT A_FROM_PC : a_source_type := "10";
-----------------------------------------------------------------------------------
--
--
SUBTYPE b_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT B_FROM_REG_TARGET : b_source_type := "00";
CONSTANT B_FROM_IMM : b_source_type := "01";
CONSTANT B_FROM_SIGNED_IMM : b_source_type := "10";
CONSTANT B_FROM_IMMX4 : b_source_type := "11";
-----------------------------------------------------------------------------------
--
--
SUBTYPE c_source_type IS std_logic_vector(2 DOWNTO 0);
CONSTANT C_FROM_NULL : c_source_type := "000";
CONSTANT C_FROM_ALU : c_source_type := "001";
CONSTANT C_FROM_SHIFT : c_source_type := "001"; --same as alu
CONSTANT C_FROM_MULT : c_source_type := "001"; --same as alu
CONSTANT C_FROM_MEMORY : c_source_type := "010";
CONSTANT C_FROM_PC : c_source_type := "011";
CONSTANT C_FROM_PC_PLUS4 : c_source_type := "100";
CONSTANT C_FROM_IMM_SHIFT16 : c_source_type := "101";
CONSTANT C_FROM_REG_SOURCEN : c_source_type := "110";
CONSTANT C_FROM_EXTENSIONS : c_source_type := "111";
-----------------------------------------------------------------------------------
--
--
SUBTYPE pc_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT FROM_INC4 : pc_source_type := "00";
CONSTANT FROM_OPCODE25_0 : pc_source_type := "01";
CONSTANT FROM_BRANCH : pc_source_type := "10";
CONSTANT FROM_LBRANCH : pc_source_type := "11";
-----------------------------------------------------------------------------------
--
--
-- subtype branch_function_type is std_logic_vector(2 downto 0);
-- constant BRANCH_LTZ : branch_function_type := "000";
-- constant BRANCH_LEZ : branch_function_type := "001";
-- constant BRANCH_EQ : branch_function_type := "010";
-- constant BRANCH_NE : branch_function_type := "011";
-- constant BRANCH_GEZ : branch_function_type := "100";
-- constant BRANCH_GTZ : branch_function_type := "101";
-- constant BRANCH_YES : branch_function_type := "110";
-- constant BRANCH_NO : branch_function_type := "111";
TYPE branch_function_type IS (
BRANCH_EQ
-- BEGIN ENABLE_(BLTZ,BLTZAL)
, BRANCH_LTZ
-- END ENABLE_(BLTZ,BLTZAL)
-- BEGIN ENABLE_(BLEZ)
, BRANCH_LEZ
-- END ENABLE_(BLEZ)
-- ON DEPLACE ,BRANCH_EQ
-- BEGIN ENABLE_(BNE)
, BRANCH_NE
-- END ENABLE_(BNE)
-- BEGIN ENABLE_(BGEZ,BGEZAL)
, BRANCH_GEZ
-- END ENABLE_(BGEZ,BGEZAL)
-- NE PEUT PAS ETRE ENLEVE FACILEMENT...
, BRANCH_GTZ
, BRANCH_YES
, BRANCH_NO
);
-----------------------------------------------------------------------------------
--
--
-- mode(32=1,16=2,8=3), signed, write
-- subtype mem_source_type is std_logic_vector(3 downto 0);
-- constant MEM_FETCH : mem_source_type := "0000";
-- constant MEM_READ32 : mem_source_type := "0100";
-- constant MEM_WRITE32 : mem_source_type := "0101";
-- constant MEM_READ16 : mem_source_type := "1000";
-- constant MEM_READ16S : mem_source_type := "1010";
-- constant MEM_WRITE16 : mem_source_type := "1001";
-- constant MEM_READ8 : mem_source_type := "1100";
-- constant MEM_READ8S : mem_source_type := "1110";
-- constant MEM_WRITE8 : mem_source_type := "1101";
TYPE mem_source_type IS (
MEM_FETCH
, MEM_READ32
, MEM_WRITE32
-- BEGIN ENABLE_(LHU)
, MEM_READ16
-- END ENABLE_(LHU)
-- BEGIN ENABLE_(LH)
, MEM_READ16S
-- END ENABLE_(LH)
-- BEGIN ENABLE_(SH)
, MEM_WRITE16
-- END ENABLE_(SH)
-- BEGIN ENABLE_(LBU)
, MEM_READ8
-- END ENABLE_(LBU)
-- BEGIN ENABLE_(LB)
, MEM_READ8S
-- END ENABLE_(LB)
-- BEGIN ENABLE_(SB)
, MEM_WRITE8
-- END ENABLE_(SB)
);
-----------------------------------------------------------------------------------
--
--
FUNCTION bv_adder(a : IN std_logic_vector;
b : IN std_logic_vector;
do_add : IN std_logic) RETURN std_logic_vector;
FUNCTION bv_negate(a : IN std_logic_vector) RETURN std_logic_vector;
FUNCTION bv_increment(a : IN std_logic_vector(31 DOWNTO 2)
) RETURN std_logic_vector;
FUNCTION bv_inc(a : IN std_logic_vector
) RETURN std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
PORT (
RDCLOCK : IN std_logic := '0';
RDCLKEN : IN std_logic := '1';
RDADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
RDEN : IN std_logic := '1';
DATA : IN std_logic_vector(LPM_WIDTH-1 DOWNTO 0);
WRADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
WREN : IN std_logic;
WRCLOCK : IN std_logic := '0';
WRCLKEN : IN std_logic := '1';
Q : OUT std_logic_vector(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;
-- For Altera
COMPONENT LPM_RAM_DQ
GENERIC (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
PORT (
DATA : IN std_logic_vector(LPM_WIDTH-1 DOWNTO 0);
ADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
INCLOCK : IN std_logic := '0';
OUTCLOCK : IN std_logic := '0';
WE : IN std_logic;
Q : OUT std_logic_vector(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;
-- For Xilinx
COMPONENT RAM16X1D
-- synthesis translate_off
GENERIC (INIT : bit_vector := X"16");
-- synthesis translate_on
PORT (DPO : OUT std_ulogic;
SPO : OUT std_ulogic;
A0 : IN std_ulogic;
A1 : IN std_ulogic;
A2 : IN std_ulogic;
A3 : IN std_ulogic;
D : IN std_ulogic;
DPRA0 : IN std_ulogic;
DPRA1 : IN std_ulogic;
DPRA2 : IN std_ulogic;
DPRA3 : IN std_ulogic;
WCLK : IN std_ulogic;
WE : IN std_ulogic);
END COMPONENT;
-- For Xilinx Virtex-5
COMPONENT RAM32X1D
-- synthesis translate_off
GENERIC (INIT : bit_vector := X"32");
-- synthesis translate_on
PORT (DPO : OUT std_ulogic;
SPO : OUT std_ulogic;
A0 : IN std_ulogic;
A1 : IN std_ulogic;
A2 : IN std_ulogic;
A3 : IN std_ulogic;
A4 : IN std_ulogic;
D : IN std_ulogic;
DPRA0 : IN std_ulogic;
DPRA1 : IN std_ulogic;
DPRA2 : IN std_ulogic;
DPRA3 : IN std_ulogic;
DPRA4 : IN std_ulogic;
WCLK : IN std_ulogic;
WE : IN std_ulogic);
END COMPONENT;
COMPONENT pc_next
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pc_new : IN std_logic_vector(31 DOWNTO 2);
take_branch : IN std_logic;
pause_in : IN std_logic;
opcode25_0 : IN std_logic_vector(25 DOWNTO 0);
pc_source : IN pc_source_type;
pc_future : OUT std_logic_vector(31 DOWNTO 2);
pc_current : OUT std_logic_vector(31 DOWNTO 2);
pc_plus4 : OUT std_logic_vector(31 DOWNTO 2));
END COMPONENT;
COMPONENT mem_ctrl
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pause_in : IN std_logic;
nullify_op : IN std_logic;
address_pc : IN std_logic_vector(31 DOWNTO 2);
opcode_out : OUT std_logic_vector(31 DOWNTO 0);
address_in : IN std_logic_vector(31 DOWNTO 0);
mem_source : IN mem_source_type;
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic;
address_next : OUT std_logic_vector(31 DOWNTO 2);
byte_we_next : OUT std_logic_vector(3 DOWNTO 0);
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_w : OUT std_logic_vector(31 DOWNTO 0);
data_r : IN std_logic_vector(31 DOWNTO 0));
END COMPONENT;
COMPONENT control
PORT(opcode : IN std_logic_vector(31 DOWNTO 0);
intr_signal : IN std_logic;
rs_index : OUT std_logic_vector(5 DOWNTO 0);
rt_index : OUT std_logic_vector(5 DOWNTO 0);
rd_index : OUT std_logic_vector(5 DOWNTO 0);
imm_out : OUT std_logic_vector(15 DOWNTO 0);
alu_func : OUT alu_function_type;
shift_func : OUT shift_function_type;
mult_func : OUT mult_function_type;
branch_func : OUT branch_function_type;
calu_1_func : OUT std_logic_vector(5 DOWNTO 0);
salu_1_func : OUT std_logic_vector(5 DOWNTO 0);
a_source_out : OUT a_source_type;
b_source_out : OUT b_source_type;
c_source_out : OUT c_source_type;
pc_source_out : OUT pc_source_type;
mem_source_out : OUT mem_source_type;
exception_out : OUT std_logic);
END COMPONENT;
COMPONENT reg_bank
GENERIC(memory_type : string := "XILINX_16X");
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pause : IN std_logic;
rs_index : IN std_logic_vector(5 DOWNTO 0);
rt_index : IN std_logic_vector(5 DOWNTO 0);
rd_index : IN std_logic_vector(5 DOWNTO 0);
reg_source_out : OUT std_logic_vector(31 DOWNTO 0);
reg_target_out : OUT std_logic_vector(31 DOWNTO 0);
reg_dest_new : IN std_logic_vector(31 DOWNTO 0);
intr_enable : OUT std_logic);
END COMPONENT;
COMPONENT bus_mux
PORT(imm_in : IN std_logic_vector(15 DOWNTO 0);
reg_source : IN std_logic_vector(31 DOWNTO 0);
a_mux : IN a_source_type;
a_out : OUT std_logic_vector(31 DOWNTO 0);
reg_target : IN std_logic_vector(31 DOWNTO 0);
b_mux : IN b_source_type;
b_out : OUT std_logic_vector(31 DOWNTO 0);
c_bus : IN std_logic_vector(31 DOWNTO 0);
c_memory : IN std_logic_vector(31 DOWNTO 0);
c_pc : IN std_logic_vector(31 DOWNTO 2);
c_pc_plus4 : IN std_logic_vector(31 DOWNTO 2);
c_mux : IN c_source_type;
reg_dest_out : OUT std_logic_vector(31 DOWNTO 0);
branch_func : IN branch_function_type;
take_branch : OUT std_logic);
END COMPONENT;
---------------------------------------------------------------------------------------
COMPONENT alu
GENERIC(
alu_type : string := "DEFAULT"
);
PORT(
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN alu_function_type;
c_alu : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT shifter
GENERIC(
shifter_type : string := "DEFAULT"
);
PORT(value : IN std_logic_vector(31 DOWNTO 0);
shift_amount : IN std_logic_vector(4 DOWNTO 0);
shift_func : IN shift_function_type;
c_shift : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT mult
GENERIC(
mult_type : string := "DEFAULT"
);
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a : IN std_logic_vector(31 DOWNTO 0);
b : IN std_logic_vector(31 DOWNTO 0);
mult_func : IN mult_function_type;
c_mult : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT pipeline
PORT(
clk : IN std_logic;
reset : IN std_logic;
a_bus : IN std_logic_vector(31 DOWNTO 0);
a_busD : OUT std_logic_vector(31 DOWNTO 0);
b_bus : IN std_logic_vector(31 DOWNTO 0);
b_busD : OUT std_logic_vector(31 DOWNTO 0);
alu_func : IN alu_function_type;
alu_funcD : OUT alu_function_type;
shift_func : IN shift_function_type;
shift_funcD : OUT shift_function_type;
mult_func : IN mult_function_type;
mult_funcD : OUT mult_function_type;
calu_1_func : IN std_logic_vector(5 DOWNTO 0);
calu_1_funcD : OUT std_logic_vector(5 DOWNTO 0);
salu_1_func : IN std_logic_vector(5 DOWNTO 0);
salu_1_funcD : OUT std_logic_vector(5 DOWNTO 0);
reg_dest : IN std_logic_vector(31 DOWNTO 0);
reg_destD : OUT std_logic_vector(31 DOWNTO 0);
rd_index : IN std_logic_vector(5 DOWNTO 0);
rd_indexD : OUT std_logic_vector(5 DOWNTO 0);
rs_index : IN std_logic_vector(5 DOWNTO 0);
rt_index : IN std_logic_vector(5 DOWNTO 0);
pc_source : IN pc_source_type;
mem_source : IN mem_source_type;
a_source : IN a_source_type;
b_source : IN b_source_type;
c_source : IN c_source_type;
c_bus : IN std_logic_vector(31 DOWNTO 0);
pause_any : IN std_logic;
pause_pipeline : OUT std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT mlite_cpu
GENERIC(
memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2
); --2 or 3
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
intr_in : IN std_logic;
address_next : OUT std_logic_vector(31 DOWNTO 2); --for synch ram
byte_we_next : OUT std_logic_vector(3 DOWNTO 0);
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_w : OUT std_logic_vector(31 DOWNTO 0);
data_r : IN std_logic_vector(31 DOWNTO 0);
mem_pause : IN std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT cache
GENERIC(
memory_type : string := "DEFAULT"
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
address_next : IN std_logic_vector(31 DOWNTO 2);
byte_we_next : IN std_logic_vector(3 DOWNTO 0);
cpu_address : IN std_logic_vector(31 DOWNTO 2);
mem_busy : IN std_logic;
cache_access : OUT std_logic; --access 4KB cache
cache_checking : OUT std_logic; --checking if cache hit
cache_miss : OUT std_logic
); --cache miss
END COMPONENT; --cache
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT ram
GENERIC(
memory_type : string := "DEFAULT";
plasma_code : string
);
PORT(
clk : IN std_logic;
enable : IN std_logic;
write_byte_enable : IN std_logic_vector(3 DOWNTO 0);
address : IN std_logic_vector(31 DOWNTO 2);
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --ram
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT uart
GENERIC(log_file : string := "UNUSED");
PORT(clk : IN std_logic;
reset : IN std_logic;
enable_read : IN std_logic;
enable_write : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
uart_read : IN std_logic;
uart_write : OUT std_logic;
busy_write : OUT std_logic;
data_avail : OUT std_logic
);
END COMPONENT; --uart
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT eth_dma
PORT(clk : IN std_logic; --25 MHz
reset : IN std_logic;
enable_eth : IN std_logic;
select_eth : IN std_logic;
rec_isr : OUT std_logic;
send_isr : OUT std_logic;
address : OUT std_logic_vector(31 DOWNTO 2); --to DDR
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_write : OUT std_logic_vector(31 DOWNTO 0);
data_read : IN std_logic_vector(31 DOWNTO 0);
pause_in : IN std_logic;
mem_address : IN std_logic_vector(31 DOWNTO 2); --from CPU
mem_byte_we : IN std_logic_vector(3 DOWNTO 0);
data_w : IN std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic;
E_RX_CLK : IN std_logic; --2.5 MHz receive
E_RX_DV : IN std_logic; --data valid
E_RXD : IN std_logic_vector(3 DOWNTO 0); --receive nibble
E_TX_CLK : IN std_logic; --2.5 MHz transmit
E_TX_EN : OUT std_logic; --transmit enable
E_TXD : OUT std_logic_vector(3 DOWNTO 0)
); --transmit nibble
END COMPONENT; --eth_dma
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT plasma
GENERIC(
memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '0';
use_cache : std_logic := '0';
plasma_code : string
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
uart_write : OUT std_logic;
uart_read : IN std_logic;
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_write : OUT std_logic_vector(31 DOWNTO 0);
data_read : IN std_logic_vector(31 DOWNTO 0);
mem_pause_in : IN std_logic;
no_ddr_start : OUT std_logic;
no_ddr_stop : OUT std_logic;
fifo_1_out_data : IN std_logic_vector (31 DOWNTO 0);
fifo_1_read_en : OUT std_logic;
fifo_1_empty : IN std_logic;
fifo_2_in_data : OUT std_logic_vector (31 DOWNTO 0);
fifo_1_write_en : OUT std_logic;
fifo_2_full : IN std_logic;
fifo_1_full : IN std_logic;
fifo_1_valid : IN std_logic;
fifo_2_empty : IN std_logic;
fifo_2_valid : IN std_logic;
fifo_1_compteur : IN std_logic_vector (31 DOWNTO 0);
fifo_2_compteur : IN std_logic_vector (31 DOWNTO 0);
data_enable :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0);
gpio0_out : OUT std_logic_vector(31 DOWNTO 0);
gpioA_in : IN std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --plasma
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT ddr_ctrl
PORT(clk : IN std_logic;
clk_2x : IN std_logic;
reset_in : IN std_logic;
address : IN std_logic_vector(25 DOWNTO 2);
byte_we : IN std_logic_vector(3 DOWNTO 0);
data_w : IN std_logic_vector(31 DOWNTO 0);
data_r : OUT std_logic_vector(31 DOWNTO 0);
active : IN std_logic;
no_start : IN std_logic;
no_stop : IN std_logic;
pause : OUT std_logic;
SD_CK_P : OUT std_logic; --clock_positive
SD_CK_N : OUT std_logic; --clock_negative
SD_CKE : OUT std_logic; --clock_enable
SD_BA : OUT std_logic_vector(1 DOWNTO 0); --bank_address
SD_A : OUT std_logic_vector(12 DOWNTO 0); --address(row or col)
SD_CS : OUT std_logic; --chip_select
SD_RAS : OUT std_logic; --row_address_strobe
SD_CAS : OUT std_logic; --column_address_strobe
SD_WE : OUT std_logic; --write_enable
SD_DQ : INOUT std_logic_vector(15 DOWNTO 0); --data
SD_UDM : OUT std_logic; --upper_byte_enable
SD_UDQS : INOUT std_logic; --upper_data_strobe
SD_LDM : OUT std_logic; --low_byte_enable
SD_LDQS : INOUT std_logic
); --low_data_strobe
END COMPONENT; --ddr
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT disassembler
PORT(
clk : IN std_logic;
reset : IN std_logic;
pause : IN std_logic;
opcode : IN std_logic_vector(31 DOWNTO 0);
pc_addr : IN std_logic_vector(31 DOWNTO 2)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT comb_alu_1
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN std_logic_vector(5 DOWNTO 0);
c_alu : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --comb_alu_1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT sequ_alu_1
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN std_logic_vector(5 DOWNTO 0);
c_alu : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic
);
END COMPONENT; --sequ_alu_1
---------------------------------------------------------------------------------------
END; --package mlite_pack
PACKAGE BODY mlite_pack IS
FUNCTION bv_adder(a : IN std_logic_vector;
b : IN std_logic_vector;
do_add : IN std_logic) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE bb : std_logic_vector(a'length-1 DOWNTO 0);
VARIABLE result : std_logic_vector(a'length DOWNTO 0);
BEGIN
IF do_add = '1' THEN
bb := b;
carry_in := '0';
ELSE
bb := NOT b;
carry_in := '1';
END IF;
FOR index IN 0 TO a'length-1 LOOP
result(index) := a(index) XOR bb(index) XOR carry_in;
carry_in := (carry_in AND (a(index) OR bb(index))) OR
(a(index) AND bb(index));
END LOOP;
result(a'length) := carry_in XNOR do_add;
RETURN result;
END; --function
FUNCTION bv_negate(a : IN std_logic_vector) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE not_a : std_logic_vector(a'length-1 DOWNTO 0);
VARIABLE result : std_logic_vector(a'length-1 DOWNTO 0);
BEGIN
not_a := NOT a;
carry_in := '1';
FOR index IN a'reverse_range LOOP
result(index) := not_a(index) XOR carry_in;
carry_in := carry_in AND not_a(index);
END LOOP;
RETURN result;
END; --function
FUNCTION bv_increment(a : IN std_logic_vector(31 DOWNTO 2)
) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE result : std_logic_vector(31 DOWNTO 2);
BEGIN
carry_in := '1';
FOR index IN 2 TO 31 LOOP
result(index) := a(index) XOR carry_in;
carry_in := a(index) AND carry_in;
END LOOP;
RETURN result;
END; --function
FUNCTION bv_inc(a : IN std_logic_vector
) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE result : std_logic_vector(a'length-1 DOWNTO 0);
BEGIN
carry_in := '1';
FOR index IN 0 TO a'length-1 LOOP
result(index) := a(index) XOR carry_in;
carry_in := a(index) AND carry_in;
END LOOP;
RETURN result;
END; --function
END; --package body
| gpl-3.0 | d2fdc2d99c58eb9b7826467d66a4bc00 | 0.43791 | 4.222074 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/decoder.vhd | 1 | 9,363 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
Port ( reg1 : out STD_LOGIC_VECTOR (3 downto 0);--¶Á³öµÄ¼Ä´æÆ÷
reg2 : out STD_LOGIC_VECTOR (3 downto 0);--¶Á³öµÄ¼Ä´æÆ÷
reg3 : out STD_LOGIC_VECTOR (3 downto 0);--д»ØµÄ¼Ä´æÆ÷
imm : out STD_LOGIC_VECTOR (15 downto 0);--À©Õ¹ºóµÄÁ¢¼´Êý
imm1 : out STD_LOGIC_VECTOR (15 downto 0);--À©Õ¹ºóµÄÁ¢¼´Êý
rw : out std_logic;--ÄÚ´æ¶Áд
we : out std_logic;
muxop1 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷1
muxop2 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷2
muxop3 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷3
muxop4 : out std_logic_vector(1 downto 0);--¶à·ѡÔñÆ÷4
muxpc : out std_logic_vector(2 downto 0);--¶à·ѡÔñÆ÷pc
aluop : out std_logic_vector(2 downto 0);--alu²Ù×÷Êý
instruction : in STD_LOGIC_VECTOR (15 downto 0)--Ö¸Áî
);
end decoder;
architecture Behavioral of decoder is
begin
process(instruction)
begin
case instruction(15 downto 11) is
when "00001"=> null;--NOP
when "11100"=>--ADDU,SUBU
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="00";
muxop3<="00";
muxop4<="00";
case instruction(1 downto 0) is
when "01"=>--ADDU
reg1<='0' & instruction(10 downto 8);--rx
reg2<='0' & instruction(7 downto 5);--ry
reg3<='0' & instruction(4 downto 2);--rz
aluop<="000";--¼Ó·¨ÔËËã
when "11"=>--SUBU
reg1<='0' & instruction(10 downto 8);--rx
reg2<='0' & instruction(7 downto 5);--ry
reg3<='0' & instruction(4 downto 2);--rz
AluOp<="001";--¼õ·¨ÔËËã
when others=>null;
end case;
when "11101"=>--AND,CMP,MFPC,OR,JR
muxop3<="00";
muxop4<="00";
case instruction(4 downto 0) is
when "01100"=>--AND
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="00";
reg1<='0' & instruction(10 downto 8);--rx
reg2<='0' & instruction(7 downto 5);--ry
reg3<='0' & instruction(10 downto 8);--rz
aluop<="010";--Âß¼Óë
when "01010"=>--CMP
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="00";
reg1<='0' & instruction(10 downto 8);--rx
reg2<='0' & instruction(7 downto 5);--ry
reg3<="1010";--T¼Ä´æÆ÷
aluop<="100";--Âß¼Òì»ò
when "01101"=>--OR
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="00";
reg1<='0' & instruction(10 downto 8);--rx
reg2<='0' & instruction(7 downto 5);--ry
reg3<='0' & instruction(10 downto 8);--rz
aluop<="011";--Âß¼»ò
when "00000"=>
if(instruction(6)='0')then--MFPC
we<='1';
muxpc<="000";
reg3<='0' & instruction(10 downto 8);
else --JR
muxop1<="00";
muxop2<="00";
muxpc<="000";
reg1<='0' & instruction(10 downto 8);--rx
end if;
when others=>null;
end case;
when "11110"=>--MFIH,MTIH
we<='1';
muxop1<="00";
muxop2<="00";
muxpc<="000";
muxop3<="00";
muxop4<="00";
case instruction(7 downto 0) is
when "00000000"=>--MFIH
reg3<='0' & instruction(10 downto 8);--rx
reg1<="1001";--IH¼Ä´æÆ÷
when "00000001"=>--MTIH
reg3<="1001";--IH¼Ä´æÆ÷
reg1<='0' & instruction(10 downto 8);--rx
when others=>null;
end case;
when "01100"=>--MTSP,BTEQZ,ADDSP
muxop3<="00";
muxop4<="00";
case instruction(10 downto 8) is
when "100"=>--MTSP
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="00";
reg1<='0' & instruction(7 downto 5);--rx
reg3<="1000";--SP
when "000"=>--BTEQZ
muxpc<="010";
reg1<="1010";--T¼Ä´æÆ÷
aluop<="000";--¼Ó·¨ÔËËã
muxop1<="01";
muxop2<="01";
IF(instruction(7)='1')then
imm<="11111111" & Instruction(7 downto 0);
else
imm<="00000000" & Instruction(7 downto 0);
end if;
when "011"=>--ADDSP
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="01";
reg1<="1000";--SP
reg3<="1000";--SP
aluop<="000";--¼Ó·¨ÔËËã
IF(instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & instruction(7 downto 0);
end if;
when others=>null;
end case;
when "00110"=>--SLL,SRA
we<='1';
muxop4<="00";
muxpc<="000";
muxop1<="00";
muxop2<="01";
muxop3<="00";
case instruction(1 downto 0) is
when "00"=>--SLL
reg3<='0' & instruction(10 downto 8);--rx
reg1<='0' & instruction(7 downto 5);
aluop<="101";--Âß¼×óÒÆ
if(instruction(4 downto 2)="000")then
imm<="0000000000001000";--×óÒÆ8λ
else
imm<="0000000000000" & instruction(4 downto 2);
end if;
when "11"=>--SRA
reg3<='0' & Instruction(10 downto 8);--rx
reg1<='0' & Instruction(7 downto 5);
aluop<="110";--Âß¼ÓÒÒÆ
if(instruction(4 downto 2)="000")then
imm<="0000000000001000";--ÓÒÒÆ8λ
else
imm<="0000000000000" & instruction(4 downto 2);
end if;
when others=>null;
end case;
when "01001"=>--ADDIU
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="01";
muxop3<="00";
muxop4<="00";
reg1<='0' & Instruction(10 downto 8);
reg3<='0' & Instruction(10 downto 8);
aluop<="000";--¼Ó·¨ÔËËã
IF(Instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & instruction(7 downto 0);
end if;
when "01000"=>--ADDIU3
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="01";
muxop3<="00";
muxop4<="00";
reg1<='0' & instruction(10 downto 8);
reg3<='0' & instruction(7 downto 5);
aluop<="000";--¼Ó·¨ÔËËã
IF(Instruction(3)='1')then
imm<="111111111111" & instruction(3 downto 0);
else
imm<="000000000000" & instruction(3 downto 0);
end if;
when "01101"=>--LI
we<='1';
muxpc<="000";
muxop2<="01";
muxop3<="00";
muxop4<="01";
reg3<='0' & instruction(10 downto 8);
imm1<="00000000" & instruction(7 downto 0);
when "10011"=>--LW
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="01";
muxop3<="01";
muxop4<="00";
reg1<='0' & instruction(10 downto 8);
reg3<='0' & instruction(7 downto 5);
aluop<="000";--¼Ó·¨ÔËËã
rw<='1';
IF(instruction(4)='1')then
imm<="11111111111" & instruction(4 downto 0);
else
Imm<="00000000000" & Instruction(4 downto 0);
end if;
when "10010"=>--LW_SP
we<='1';
muxpc<="000";
muxop1<="00";
muxop2<="01";
muxop3<="01";
muxop4<="00";
reg3<='0' & instruction(10 downto 8);
reg1<="1000";--SP
rw<='1';
aluop<="000";--¼Ó·¨ÔËËã
IF(instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & Instruction(7 downto 0);
end if;
when "11011"=>--SW
muxop1<="00";
muxop2<="01";
muxpc<="000";
muxop4<="00";
reg1<='0' & instruction(10 downto 8);--ÓÃÓÚ¼ÆËãµØÖ·
reg2<='0' & instruction(7 downto 5);--дÈëÄÚ´æµÄÄÚÈÝ
aluop<="000";--¼Ó·¨ÔËËã
rw<='0';
IF(instruction(4)='1')then
imm<="11111111111" & instruction(4 downto 0);
else
imm<="00000000000" & instruction(4 downto 0);
end if;
when "11010"=>--SW_SP
muxop1<="00";
muxop2<="01";
muxpc<="000";
muxop4<="00";
reg2<='0' & instruction(10 downto 8);
reg1<="1000";--SP
aluop<="000";--¼Ó·¨ÔËËã
rw<='0';
IF(instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & instruction(7 downto 0);
end if;
when "00010"=>--B
muxop1<="01";
muxop2<="01";
aluop<="000";--¼Ó·¨ÔËËã
muxpc<="100";
IF(instruction(10)='1')then
imm<="11111" & instruction(10 downto 0);
else
imm<="00000" & instruction(10 downto 0);
end if;
when "00100"=>--BEQZ
aluop<="000";
muxop1<="01";
muxop2<="01";
muxpc<="010";
reg1<='0' & instruction(10 downto 8);
IF(instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & instruction(7 downto 0);
end if;
when "00101"=>--BNEZ
aluop<="000";
muxop1<="01";
muxop2<="01";
muxpc<="011";
muxop4<="00";
reg1<='0' & instruction(10 downto 8);
IF(instruction(7)='1')then
imm<="11111111" & instruction(7 downto 0);
else
imm<="00000000" & instruction(7 downto 0);
end if;
when others=>null;
END CASE;
END PROCESS;
end Behavioral;
| apache-2.0 | 7399634a2567f1e289606832bb204c68 | 0.491509 | 3.569577 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_12_dir/exercise6_12.vhd | 1 | 1,631 | --!
--! @file: exercise6_12.vhd
--! @brief: Programmable Signal Generator
--! @author: Antonio Gutierrez
--! @date: 2013-10-28
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity programmable_signal_generator is
generic (fclk: integer := 50_000_000;); -- clock frequency
port (
clk: in std_logic;
freq: in std_logic;
sig_out: out std_logic);
end entity programmable_signal_generator;
--------------------------------------
architecture circuit of programmable_signal_generator is
signal desired_freq: integer 0 to 10000;
signal pulses: integer 0 to fclk / 1000;
begin
-- selecting the frequcny and the number of pulses required for that frequency
proc1: process (freq)
begin
if (freq'event and freq = '1') then
if (desired_freq = 10000) then
desired_freq <= 1000;
else
desired_freq <= desired_freq + 1000;
end if;
pulses <= fclk / desired_freq;
end if;
end process proc1;
-- outputing and counting the pulses
proc: process (clk)
variable count: integer 0 to fclk;
variable output: std_logic := '0'
begin
if (clk'event and clk = '1') then
count := count + 1;
if (count = pulses) then
count := 0;
output := not output;
end if;
end if;
sig_out <= output;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 3a5382d404d3fdfe5fc233009ddfaee4 | 0.525445 | 4.493113 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/vga4coeurs.vhd | 1 | 11,996 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(11 downto 0); -- iter output
ADDR1 : in std_logic_vector(16 downto 0);
data_in1 : in std_logic_vector(11 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(16 downto 0);
data_in2 : in std_logic_vector(11 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(16 downto 0);
data_in3 : in std_logic_vector(11 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(16 downto 0);
data_in4 : in std_logic_vector(11 downto 0);
data_write4 : in std_logic);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
component RAM_single_port
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(11 downto 0);
ADDR : in STD_LOGIC_VECTOR (16 downto 0);
data_out : out STD_LOGIC_VECTOR (11 downto 0));
end component;
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1, pix_read1 : integer range 0 to 76799:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 76799 := 0; -- the address at which displayed data is read
signal next_pixel1, data_temp1, data_temp2 , data_outtemp1, data_outtemp2,data_temp3, data_temp4 , data_outtemp3, data_outtemp4 : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel2 : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
--signal data_writetemp1, data_writetemp2 : std_logic;
signal ADDRtemp1, ADDRtemp2, ADDRtemp3, ADDRtemp4 : std_logic_vector(16 downto 0); -- the data coding the value of the pixel to be displayed
begin
--------------------------------------------------------------------------------
RAM1: RAM_single_port
port map (clk,
data_write1,
data_in1,
ADDRtemp1,
data_outtemp1);
RAM2: RAM_single_port
port map (clk,
data_write2,
data_in2,
ADDRtemp2,
data_outtemp2);
RAM3: RAM_single_port
port map (clk,
data_write3,
data_in3,
ADDRtemp3,
data_outtemp3);
RAM4: RAM_single_port
port map (clk,
data_write4,
data_in4,
ADDRtemp4,
data_outtemp4);
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 153599 else pix_read_addr - 153599;
ADDRtemp1<= ADDR1 when (data_write1 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp2<= ADDR2 when (data_write2 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp3<= ADDR3 when (data_write3 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp4<= ADDR4 when (data_write4 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
--data_writetemp1 <= clk_VGA when (data_write1 = '0') else '1' ;
--data_writetemp2 <= clk_VGA when (data_write2 = '0') else '1' ;
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel1 <= screen1(pix_read_addrb) ;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel2 <= screen2(pix_read_addrb);
-- end if;
-- end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF pix_read_addr < 76799 THEN
next_pixel <= data_outtemp1;
ELSif pix_read_addr < 153599 THEN
next_pixel <= data_outtemp2;
ELSif pix_read_addr < 230399 THEN
next_pixel <= data_outtemp3;
else
next_pixel <= data_outtemp4;
END IF;
end if;
end process;
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1;
-- next_pixel1 <= data_in1;
-- else
-- next_pixel1 <= screen1(to_integer(unsigned(ADDR1)));
-- end if;
-- end if;
--end process;
--
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2;
-- next_pixel2 <= data_in2;
-- else
-- next_pixel2 <= screen2(to_integer(unsigned(ADDR2));
-- end if;
-- end if;
--end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,18)(17) = '0' else screen2;
--------------------------------------------------------------------------------
--proc<='0' when (pix_read_addr <153599) else '1';
pixel_read_addr : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read1 : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read1 <= pix_read1 + 1;
elsif (pix_read1 = 76799) then
pix_read1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 153599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 153599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= (others=>'0');
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | 02f29c52b0eac3ee9c76125e77b3d518 | 0.546599 | 3.232552 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/GRAPHLAB/IEEE754_LIBRARY.vhd | 1 | 42,219 | ---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY EQUAL_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0);
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0);
OUTPUT_1 : OUT Std_Logic
);
END EQUAL_FLOAT_32 ;
ARCHITECTURE comportementale OF EQUAL_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
BEGIN
IF INPUT_1 = INPUT_2 THEN
OUTPUT_1 <= '1';
ELSE
OUTPUT_1 <= '0';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY NOT_EQUAL_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0);
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0);
OUTPUT_1 : OUT Std_Logic
);
END NOT_EQUAL_FLOAT_32 ;
ARCHITECTURE comportementale OF NOT_EQUAL_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
BEGIN
IF INPUT_1 /= INPUT_2 THEN
OUTPUT_1 <= '1';
ELSE
OUTPUT_1 <= '0';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY LESS_EQUAL_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0);
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0);
OUTPUT_1 : OUT Std_Logic
);
END LESS_EQUAL_FLOAT_32 ;
ARCHITECTURE comportementale OF LESS_EQUAL_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
VARIABLE sa, sb, sc : STD_LOGIC;
VARIABLE ea, eb, ec : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE ma, mb, mc : STD_LOGIC_VECTOR(22 DOWNTO 0);
BEGIN
-- DECOMPOSITION DU NOMBRE A
sa := INPUT_1( 31 );
ea := INPUT_1( 30 DOWNTO 23 );
ma := INPUT_1( 22 DOWNTO 0 );
--IF fonction = '0' THEN
sb := INPUT_2( 31 );
eb := INPUT_2( 30 DOWNTO 23 );
mb := INPUT_2( 22 DOWNTO 0 );
--
-- COMPARAISON DES SIGNES DES 2 NOMBRES
--
IF sa = '0' AND sb='1' THEN
OUTPUT_1 <= '0';
ELSIF sa = '1' AND sb='0' THEN
OUTPUT_1 <= '1';
--
-- COMPARAISON DES EXPOSANTS DES 2 NOMBRES
--
ELSIF UNSIGNED(ea) < UNSIGNED(eb) THEN
OUTPUT_1 <= '1';
ELSIF UNSIGNED(ea) > UNSIGNED(eb) THEN
OUTPUT_1 <= '0';
--
-- COMPARAISON DES MANTISSES DES 2 NOMBRES
--
ELSIF UNSIGNED(ma) <= UNSIGNED(mb) THEN
OUTPUT_1 <= '1';
ELSE
OUTPUT_1 <= '0';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY MORE_EQUAL_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0);
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0);
OUTPUT_1 : OUT Std_Logic
);
END MORE_EQUAL_FLOAT_32 ;
ARCHITECTURE comportementale OF MORE_EQUAL_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
VARIABLE sa, sb, sc : STD_LOGIC;
VARIABLE ea, eb, ec : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE ma, mb, mc : STD_LOGIC_VECTOR(22 DOWNTO 0);
BEGIN
-- DECOMPOSITION DU NOMBRE A
sa := INPUT_1( 31 );
ea := INPUT_1( 30 DOWNTO 23 );
ma := INPUT_1( 22 DOWNTO 0 );
--IF fonction = '0' THEN
sb := INPUT_2( 31 );
eb := INPUT_2( 30 DOWNTO 23 );
mb := INPUT_2( 22 DOWNTO 0 );
--
-- COMPARAISON DES SIGNES DES 2 NOMBRES
--
IF sa = '0' AND sb='1' THEN
OUTPUT_1 <= '1';
ELSIF sa = '1' AND sb='0' THEN
OUTPUT_1 <= '0';
--
-- COMPARAISON DES EXPOSANTS DES 2 NOMBRES
--
ELSIF UNSIGNED(ea) < UNSIGNED(eb) THEN
OUTPUT_1 <= '0';
ELSIF UNSIGNED(ea) > UNSIGNED(eb) THEN
OUTPUT_1 <= '1';
--
-- COMPARAISON DES MANTISSES DES 2 NOMBRES
--
ELSIF UNSIGNED(ma) <= UNSIGNED(mb) THEN
OUTPUT_1 <= '0';
ELSE
OUTPUT_1 <= '1';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY LESS_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0);
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0);
OUTPUT_1 : OUT Std_Logic
);
END LESS_FLOAT_32 ;
ARCHITECTURE comportementale OF LESS_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
VARIABLE sa, sb, sc : STD_LOGIC;
VARIABLE ea, eb, ec : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE ma, mb, mc : STD_LOGIC_VECTOR(22 DOWNTO 0);
BEGIN
-- DECOMPOSITION DU NOMBRE A
sa := INPUT_1( 31 );
ea := INPUT_1( 30 DOWNTO 23 );
ma := INPUT_1( 22 DOWNTO 0 );
--IF fonction = '0' THEN
sb := INPUT_2( 31 );
eb := INPUT_2( 30 DOWNTO 23 );
mb := INPUT_2( 22 DOWNTO 0 );
--
-- COMPARAISON DES SIGNES DES 2 NOMBRES
--
IF sa = '0' AND sb='1' THEN
OUTPUT_1 <= '0';
ELSIF sa = '1' AND sb='0' THEN
OUTPUT_1 <= '1';
--
-- COMPARAISON DES EXPOSANTS DES 2 NOMBRES
--
ELSIF UNSIGNED(ea) < UNSIGNED(eb) THEN
OUTPUT_1 <= '1';
ELSIF UNSIGNED(ea) > UNSIGNED(eb) THEN
OUTPUT_1 <= '0';
--
-- COMPARAISON DES MANTISSES DES 2 NOMBRES
--
ELSIF UNSIGNED(ma) < UNSIGNED(mb) THEN
OUTPUT_1 <= '1';
ELSE
OUTPUT_1 <= '0';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY MORE_FLOAT_32 IS
PORT (
INPUT_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC
);
END MORE_FLOAT_32 ;
ARCHITECTURE comportementale OF MORE_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
VARIABLE sa, sb, sc : STD_LOGIC;
VARIABLE ea, eb, ec : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE ma, mb, mc : STD_LOGIC_VECTOR(22 DOWNTO 0);
BEGIN
-- DECOMPOSITION DU NOMBRE A
sa := INPUT_1( 31 );
ea := INPUT_1( 30 DOWNTO 23 );
ma := INPUT_1( 22 DOWNTO 0 );
--IF fonction = '0' THEN
sb := INPUT_2( 31 );
eb := INPUT_2( 30 DOWNTO 23 );
mb := INPUT_2( 22 DOWNTO 0 );
--
-- COMPARAISON DES SIGNES DES 2 NOMBRES
--
IF sa = '0' AND sb='1' THEN
OUTPUT_1 <= '1';
ELSIF sa = '1' AND sb='0' THEN
OUTPUT_1 <= '0';
--
-- COMPARAISON DES EXPOSANTS DES 2 NOMBRES
--
ELSIF UNSIGNED(ea) < UNSIGNED(eb) THEN
OUTPUT_1 <= '0';
ELSIF UNSIGNED(ea) > UNSIGNED(eb) THEN
OUTPUT_1 <= '1';
--
-- COMPARAISON DES MANTISSES DES 2 NOMBRES
--
ELSIF UNSIGNED(ma) > UNSIGNED(mb) THEN
OUTPUT_1 <= '0';
ELSIF UNSIGNED(ma) < UNSIGNED(mb) THEN
OUTPUT_1 <= '1';
END IF;
END PROCESS ComputeProcess;
END comportementale ;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY CMOVE_FLOAT_32 IS
PORT (
INPUT_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_3 : IN STD_LOGIC;
OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END CMOVE_FLOAT_32 ;
ARCHITECTURE comportementale OF CMOVE_FLOAT_32 IS
BEGIN
ComputeProcess : PROCESS (INPUT_1, INPUT_2)
BEGIN
IF INPUT_3 = '1' THEN
OUTPUT_1 <= INPUT_1;
ELSE
OUTPUT_1 <= INPUT_2;
END IF;
END PROCESS ComputeProcess;
END comportementale ;
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity REG_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC;
INPUT_3 :in STD_LOGIC;
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of REG_FLOAT_32 is
SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
process (INPUT_2, INPUT_3)
begin
IF( INPUT_3 = '1' ) THEN
data <= "00000000000000000000000000000000";
ELSIF( INPUT_2'EVENT AND INPUT_2 = '1' ) THEN
data <= INPUT_1;
END IF;
OUTPUT_1 <= data;
end process;
end;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity MUX2_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_3 :in STD_LOGIC;
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of MUX2_FLOAT_32 is
begin
process (INPUT_1, INPUT_2)
begin
IF( INPUT_3 = '0' ) THEN
OUTPUT_1 <= INPUT_1;
ELSE
OUTPUT_1 <= INPUT_2;
END IF;
end process;
end;
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Company:
-- Engineer: Bertrand LE GAL
-- Create Date:ÊÊÊ 09:00:44 07/08/2008
-- Design Name:
-- Module Name:ÊÊÊ MyReceiver - Behavioral
-- Project Name:
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY MUL_FLOAT_32 IS
PORT (
INPUT_1 : IN Std_Logic_Vector(31 DOWNTO 0) ;
INPUT_2 : IN Std_Logic_Vector(31 DOWNTO 0) ;
OUTPUT_1 : OUT Std_Logic_Vector(31 DOWNTO 0)
);
END MUL_FLOAT_32 ;
ARCHITECTURE comportementale OF MUL_FLOAT_32 IS
BEGIN
END comportementale ;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL ;
--USE IEEE.STD_LOGIC_ARITH.ALL ;
library work;
use work.all;
entity MAC_FLOAT_32 is
port(
INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
INPUT_3: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end MAC_FLOAT_32;
architecture corps of MAC_FLOAT_32 is
component MUL_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end component;
component ADD_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end component;
SIGNAL TEMP : std_logic_vector(31 downto 0);
begin
MULT_OPR: MUL_FLOAT_32 port map (INPUT_1, INPUT_2, TEMP);
ADD_OPR: ADD_FLOAT_32 port map (TEMP, INPUT_3, OUTPUT_1);
end corps;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity MAX_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of MAX_FLOAT_32 is
begin
process (INPUT_1, INPUT_2)
begin
-- TRAVAIL SUR LE SIGNE DES 2 NOMBRES
IF INPUT_1( 31 ) > INPUT_2( 31 ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF INPUT_1( 31 ) < INPUT_2( 31 ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
-- TRAVAIL SUR L'EXPOSANT DES 2 NOMBRES
ELSE
IF UNSIGNED(INPUT_1(31 DOWNTO 23)) > UNSIGNED(INPUT_2(31 DOWNTO 23)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF UNSIGNED(INPUT_1(31 DOWNTO 23)) < UNSIGNED(INPUT_2(31 DOWNTO 23)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
-- TRAVAIL SUR LA MANTISSE DES 2 NOMBRES
ELSE
IF UNSIGNED(INPUT_1(22 DOWNTO 0)) > UNSIGNED(INPUT_2(22 DOWNTO 0)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF UNSIGNED(INPUT_1(22 DOWNTO 0)) < UNSIGNED(INPUT_2(22 DOWNTO 0)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
END IF;
END IF;
END IF;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity DEMUX4_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC_VECTOR(1 DOWNTO 0);
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_2 :out STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_3 :out STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_4 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of DEMUX4_FLOAT_32 is
begin
process (INPUT_1, INPUT_2)
begin
CASE INPUT_2 IS
WHEN "00" => OUTPUT_1 <= INPUT_1;
WHEN "01" => OUTPUT_2 <= INPUT_1;
WHEN "10" => OUTPUT_3 <= INPUT_1;
WHEN "11" => OUTPUT_4 <= INPUT_1;
WHEN OTHERS => NULL;
END CASE;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity DEMUX2_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC;
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_2 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of DEMUX2_FLOAT_32 is
begin
process (INPUT_1, INPUT_2)
begin
IF( INPUT_2 = '0' ) THEN
OUTPUT_1 <= INPUT_1;
ELSE
OUTPUT_2 <= INPUT_1;
END IF;
end process;
end;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity SQR_DIFF_FLOAT_32 is
port(
INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end SQR_DIFF_FLOAT_32;
architecture corps of SQR_DIFF_FLOAT_32 is
component SQR_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end component;
component SUB_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end component;
SIGNAL TEMP : std_logic_vector(31 downto 0);
begin
SUB_OPR: SUB_FLOAT_32 port map (INPUT_1, INPUT_2, TEMP);
SQR_OPR: SQR_FLOAT_32 port map (TEMP, OUTPUT_1);
end corps;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity SQR_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end SQR_FLOAT_32;
architecture corps of SQR_FLOAT_32 is
component MUL_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end component;
begin
MULT_OPR: MUL_FLOAT_32 port map (INPUT_1, INPUT_1, OUTPUT_1);
end corps;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity ADD_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end ADD_FLOAT_32;
Architecture corps of ADD_FLOAT_32 is
COMPONENT selection is
port(
INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
m_grand: out std_logic_vector(22 downto 0);
m_petit: out std_logic_vector(23 downto 0);
--expo_egal: out std_ulogic;
expo_grand: out std_logic_vector(7 downto 0);
diff_expo_bin: out std_logic_vector (4 downto 0);
sr: out std_logic);
end component;
COMPONENT aligneur_mantisse is
port(
m_grand: in std_logic_vector(22 downto 0);
m_petit: in std_logic_vector(23 downto 0);
--expo_egal: in std_ulogic;
diff_expo_bin: in std_logic_vector (4 downto 0);
grand_m: out Std_Logic_Vector (26 downto 0 );
petit_m: out Std_Logic_Vector (26 downto 0 )
);
end component;
COMPONENT renormalisation is
port(
somme_mantisse: in std_logic_vector(27 downto 0);
expo_grand: in std_logic_vector(7 downto 0);
Z : in Std_Logic_Vector (5 downto 0 );
m_finale: out std_logic_vector(22 downto 0);
--j: out integer;
expo_final: out std_logic_vector (7 downto 0)
);
end component;
component Addition_mantisse is
port( c: in std_logic;
d: in std_logic;
grand_m: in Std_Logic_Vector (26 downto 0 );
petit_m: in Std_Logic_Vector (26 downto 0 );
somme_mantisse: out std_logic_vector(27 downto 0);
Z: out Std_Logic_Vector (5 downto 0 )
);
end component;
signal m_grand: std_logic_vector (22 downto 0);
signal m_petit: std_logic_vector (23 downto 0);
signal petit_m,grand_m: std_logic_vector (26 downto 0);
--signal egalite: std_ulogic;
--signal j: integer;
signal signe: std_ulogic;
signal somme: std_logic_vector(27 downto 0);
signal somme_finale: std_logic_vector(22 downto 0);
signal expo: std_logic_vector (7 downto 0);
signal expo_diff: std_logic_vector (4 downto 0);
signal grand_expo:std_logic_vector(7 downto 0);
signal Z: Std_Logic_Vector (5 downto 0 );
begin
sel: selection port map(INPUT_1,INPUT_2,m_grand,m_petit,grand_expo,expo_diff, signe);
aligneur: aligneur_mantisse port map(m_grand, m_petit,expo_diff,grand_m,petit_m );
addition: Addition_mantisse port map(INPUT_1(31),INPUT_2(31),grand_m,petit_m,somme,Z);
norme: renormalisation port map(somme,grand_expo,Z,somme_finale,expo);
OUTPUT_1<= signe & expo & somme_finale;
end corps;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity MIN_FLOAT_32 is
port (
INPUT_1 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 :in STD_LOGIC_VECTOR(31 DOWNTO 0);
OUTPUT_1 :out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture behavior of MIN_FLOAT_32 is
begin
process (INPUT_1, INPUT_2)
begin
-- TRAVAIL SUR LE SIGNE DES 2 NOMBRES
IF INPUT_1( 31 ) < INPUT_2( 31 ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF INPUT_1( 31 ) > INPUT_2( 31 ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
-- TRAVAIL SUR L'EXPOSANT DES 2 NOMBRES
ELSE
IF UNSIGNED(INPUT_1(31 DOWNTO 23)) < UNSIGNED(INPUT_2(31 DOWNTO 23)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF UNSIGNED(INPUT_1(31 DOWNTO 23)) > UNSIGNED(INPUT_2(31 DOWNTO 23)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
-- TRAVAIL SUR LA MANTISSE DES 2 NOMBRES
ELSE
IF UNSIGNED(INPUT_1(22 DOWNTO 0)) < UNSIGNED(INPUT_2(22 DOWNTO 0)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
ELSIF UNSIGNED(INPUT_1(22 DOWNTO 0)) > UNSIGNED(INPUT_2(22 DOWNTO 0)) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_2 );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( INPUT_1 );
END IF;
END IF;
END IF;
end process;
end;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity ABS_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end ABS_FLOAT_32;
architecture corps of ABS_FLOAT_32 is
begin
OUTPUT_1 <= '0' & INPUT_1(30 DOWNTO 0);
end corps;
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc complet
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity SUB_FLOAT_32 is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
OUTPUT_1: out std_logic_vector(31 downto 0)
);
end SUB_FLOAT_32;
architecture corps of SUB_FLOAT_32 is
COMPONENT selection is
port(
INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
m_grand: out std_logic_vector(22 downto 0);
m_petit: out std_logic_vector(23 downto 0);
--expo_egal: out std_ulogic;
expo_grand: out std_logic_vector(7 downto 0);
diff_expo_bin: out std_logic_vector (4 downto 0);
sr: out std_logic);
end component;
COMPONENT aligneur_mantisse is
port(
m_grand: in std_logic_vector(22 downto 0);
m_petit: in std_logic_vector(23 downto 0);
--expo_egal: in std_ulogic;
diff_expo_bin: in std_logic_vector (4 downto 0);
grand_m: out Std_Logic_Vector (26 downto 0 );
petit_m: out Std_Logic_Vector (26 downto 0 )
);
end component;
COMPONENT renormalisation is
port(
somme_mantisse: in std_logic_vector(27 downto 0);
expo_grand: in std_logic_vector(7 downto 0);
Z : in Std_Logic_Vector (5 downto 0 );
m_finale: out std_logic_vector(22 downto 0);
--j: out integer;
expo_final: out std_logic_vector (7 downto 0)
);
end component;
component Addition_mantisse is
port( c: in std_logic;
d: in std_logic;
grand_m: in Std_Logic_Vector (26 downto 0 );
petit_m: in Std_Logic_Vector (26 downto 0 );
somme_mantisse: out std_logic_vector(27 downto 0);
Z: out Std_Logic_Vector (5 downto 0 )
);
end component;
signal m_grand: std_logic_vector (22 downto 0);
signal m_petit: std_logic_vector (23 downto 0);
signal petit_m,grand_m: std_logic_vector (26 downto 0);
signal signe: std_ulogic;
signal somme: std_logic_vector(27 downto 0);
signal somme_finale: std_logic_vector(22 downto 0);
signal expo: std_logic_vector (7 downto 0);
signal expo_diff: std_logic_vector (4 downto 0);
signal grand_expo:std_logic_vector(7 downto 0);
signal Z: Std_Logic_Vector (5 downto 0 );
signal NOT_INPUT_2: Std_Logic_Vector (31 downto 0 );
begin
NOT_INPUT_2 <= not(INPUT_2(31)) & INPUT_2(30 downto 0);
sel: selection port map(INPUT_1,NOT_INPUT_2,m_grand,m_petit,grand_expo,expo_diff, signe);
aligneur: aligneur_mantisse port map(m_grand, m_petit,expo_diff,grand_m,petit_m );
addition: Addition_mantisse port map(INPUT_1(31),NOT_INPUT_2(31),grand_m,petit_m,somme,Z);
norme: renormalisation port map(somme,grand_expo,Z,somme_finale,expo);
OUTPUT_1<= signe & expo & somme_finale;
end corps;
--------------------------------------------------------------------------------------
--IYAMBA ASSA Stage VHDL Juin 2007
--Bloc de sortie additionneur
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity renormalisation is
port( somme_mantisse: in std_logic_vector(27 downto 0);
expo_grand: in std_logic_vector(7 downto 0);
Z : in Std_Logic_Vector (5 downto 0 );
m_finale: out std_logic_vector(22 downto 0);
--j:out integer;
expo_final: out std_logic_vector (7 downto 0)
);
end renormalisation;
Architecture corps of renormalisation is
begin
process(somme_mantisse,expo_grand,Z)
variable expo_final_tmp: std_logic_vector (7 downto 0);
variable somme: std_logic_vector (27 downto 0);
variable sommebis:bit_vector (27 downto 0);
variable s:bit_vector (27 downto 0);
variable i:integer;
variable a: Std_Logic_Vector (5 downto 0 );
variable tmp:std_logic_vector (22 downto 0);
begin
i:=conv_integer(Z);
--j<=i;
somme:=somme_mantisse;
sommebis:=To_bitvector(somme);
s:= sommebis sll conv_integer(Z);
--test sur l'arrondi
if ((s(3)='1' and s(4)='1') or (s(3)='1' and (s(2)='1' or s(1)='1' or s(0)='1')) ) then
tmp:=To_stdlogicvector(s(26 downto 4))+"00000000000000000000001";
m_finale<=tmp;
-- elsif (s(3)='1' and (s(2)='1' or s(1)='1' or s(0)='1')) then
-- tmp:=To_stdlogicvector(s(26 downto 4))+"00000000000000000000001";
-- m_finale<=tmp;
else
m_finale<=To_stdlogicvector(s(26 downto 4));
end if;
-- if i=0 then
-- expo_final_tmp:=expo_grand+1;
if i=32 then
expo_final_tmp:=expo_grand;
else
expo_final_tmp:=expo_grand-conv_std_logic_vector(conv_integer(Z),8)+1;
end if;
expo_final<=expo_final_tmp;
end process;
end corps;
--------------------------------------------------------------------------------------
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc d'entrée
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.Numeric_Std.all;
library work;
use work.all;
entity selection is
port( INPUT_1: in std_logic_vector(31 downto 0);
INPUT_2: in std_logic_vector(31 downto 0);
m_grand: out std_logic_vector(22 downto 0);
m_petit: out std_logic_vector(23 downto 0);
--expo_egal: out std_ulogic;
expo_grand: out std_logic_vector(7 downto 0);
--expo_petit: out std_logic_vector(7 downto 0);
-- diff_expo: out integer;
diff_expo_bin: out std_logic_vector (4 downto 0);
sr: out std_logic);
end selection;
architecture corps of selection is
begin
process(INPUT_1,INPUT_2)
variable sa: std_ulogic;
variable sb: std_ulogic;
variable ea: std_logic_vector(7 downto 0);
variable eb:std_logic_vector(7 downto 0);
variable ma: std_logic_vector(22 downto 0);
variable mb: std_logic_vector(22 downto 0);
variable diff_expo_inter: integer;
begin
sa:=INPUT_1(31);
sb:=INPUT_2(31);
ea:=INPUT_1(30 downto 23);
eb:=INPUT_2(30 downto 23);
ma:=INPUT_1(22 downto 0);
mb:=INPUT_2(22 downto 0);
if (conv_integer(ea) = conv_integer(eb)) then
expo_grand<= ea;
diff_expo_inter:= 0;
if conv_integer(ma)>conv_integer(mb) then
m_grand<= ma;
m_petit<= '1' & mb;
sr<= sa ;
else
m_grand<=mb;
m_petit<='1' & ma;
sr<=sb;
end if;
elsif conv_integer(ea)>conv_integer(eb) then
expo_grand<= ea;
m_grand<= ma;
m_petit<= '1' & mb;
diff_expo_inter:= conv_integer(ea)-conv_integer(eb);
sr<= sa;
else --elsif conv_integer(ea)<conv_integer(eb) then
expo_grand<= eb;
m_grand<= mb;
m_petit<= '1' & ma;
diff_expo_inter:= conv_integer(eb)-conv_integer(ea);
sr<= sb;
end if;
if conv_integer(diff_expo_inter)>=27 then
diff_expo_inter:=27;
else
diff_expo_inter:=diff_expo_inter;
end if;
diff_expo_bin<=conv_std_logic_vector(diff_expo_inter,5);
end process;
end corps;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.txt_util.all;
library work;
use work.all;
entity Addition_mantisse is
port( c: in std_logic;
d: in std_logic;
grand_m: in Std_Logic_Vector (26 downto 0 );
petit_m: in Std_Logic_Vector (26 downto 0 );
somme_mantisse: out std_logic_vector(27 downto 0);
Z : out Std_Logic_Vector (5 downto 0 )
);
end Addition_mantisse;
architecture corps of Addition_mantisse is
component ZLC_32b is
port ( E : in Std_Logic_Vector (31 downto 0 ) ;
Z : out Std_Logic_Vector (5 downto 0 ) ) ;
end component;
signal E:Std_Logic_Vector (31 downto 0 );
begin
nb_Z: ZLC_32b port map(E,Z);
process (petit_m,grand_m,c,d)
variable somme: Std_Logic_Vector (27 downto 0 );
variable tmp1,tmp2: Std_Logic_Vector (27 downto 0 );
begin
tmp1:='0' & grand_m;
tmp2:='0' & petit_m;
if c=d then
somme:= tmp1 + tmp2;
somme_mantisse<=somme;
else
somme:= tmp1-tmp2;
somme_mantisse<=somme;
end if;
E<= somme & "0000";
end process;
end corps;
--------------------------------------------------------------------------------------
--IYAMBA ASSA Stage VHDL Juin 2007
--Unité d'addition:bloc d'entrée
--
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.Numeric_Std.all;
library work;
use work.all;
entity aligneur_mantisse is
port(
m_grand: in std_logic_vector(22 downto 0);
m_petit: in std_logic_vector(23 downto 0);
-- expo_egal: in std_ulogic;
diff_expo_bin: in std_logic_vector (4 downto 0);
grand_m: out Std_Logic_Vector (26 downto 0 );
petit_m: out Std_Logic_Vector (26 downto 0 )
--somme_mantisse: out std_logic_vector(27 downto 0)
);
end aligneur_mantisse;
architecture corps of aligneur_mantisse is
component Shift is
port ( Entree : in Std_Logic_Vector (23 downto 0 ) ; -- E : input
D : in Std_Logic_Vector (4 downto 0 ) ; -- D : positions
S : out Std_Logic_Vector (26 downto 0 ) ) ;
end component;
signal S: Std_Logic_Vector (26 downto 0 );
--signal entree: Std_Logic_Vector (23 downto 0 );
--signal D: Std_Logic_Vector (4 downto 0 );
signal pm,gm:std_logic_vector(26 downto 0);
begin
-- entree<='1' & m_petit;
--D<=conv_std_logic_vector(diff_expo,5);
decaleur: Shift port map (m_petit,diff_expo_bin ,S);
gm<='1' & m_grand & "000";
pm<= S ;
grand_m<=gm;
petit_m<=pm;
end corps;
--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--
--
-- Synthese OPAR Version 1 (Demo)
--
-- Compteur de zeros en tete
-- synthétisé le Lundi 18 Juin 2007
--
--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--
library IEEE;
use IEEE.STD_LOGIC_1164.All;
entity ZLC_32b is
port ( E : in Std_Logic_Vector (31 downto 0 ) ; -- E : bit string
--clk: in std_logic;
Z : out Std_Logic_Vector (5 downto 0 ) ) ; -- Z : number of leading zeroes
end ZLC_32b ;
architecture structural of ZLC_32b is
signal P : Std_Logic_Vector (119 downto 0) ; -- internal signals
begin
--process (clk)
--begin
--if clk'event and clk='1' then
P(119 downto 88) <= not E ; -- row of inverters
-- row 1
P(87) <= P(119) and P(118) ; P(86) <= P(119) and not P(118) ;
P(85) <= P(117) and P(116) ; P(84) <= P(117) and not P(116) ;
P(83) <= P(115) and P(114) ; P(82) <= P(115) and not P(114) ;
P(81) <= P(113) and P(112) ; P(80) <= P(113) and not P(112) ;
P(79) <= P(111) and P(110) ; P(78) <= P(111) and not P(110) ;
P(77) <= P(109) and P(108) ; P(76) <= P(109) and not P(108) ;
P(75) <= P(107) and P(106) ; P(74) <= P(107) and not P(106) ;
P(73) <= P(105) and P(104) ; P(72) <= P(105) and not P(104) ;
P(71) <= P(103) and P(102) ; P(70) <= P(103) and not P(102) ;
P(69) <= P(101) and P(100) ; P(68) <= P(101) and not P(100) ;
P(67) <= P(99) and P(98) ; P(66) <= P(99) and not P(98) ;
P(65) <= P(97) and P(96) ; P(64) <= P(97) and not P(96) ;
P(63) <= P(95) and P(94) ; P(62) <= P(95) and not P(94) ;
P(61) <= P(93) and P(92) ; P(60) <= P(93) and not P(92) ;
P(59) <= P(91) and P(90) ; P(58) <= P(91) and not P(90) ;
P(57) <= P(89) and P(88) ; P(56) <= P(89) and not P(88) ;
-- row 2
P(55) <= P(87) and P(85) ; P(54) <= P(87) and not P(85) ; P(53) <= P(86) or (P(87) and P(84)) ;
P(52) <= P(83) and P(81) ; P(51) <= P(83) and not P(81) ; P(50) <= P(82) or (P(83) and P(80)) ;
P(49) <= P(79) and P(77) ; P(48) <= P(79) and not P(77) ; P(47) <= P(78) or (P(79) and P(76)) ;
P(46) <= P(75) and P(73) ; P(45) <= P(75) and not P(73) ; P(44) <= P(74) or (P(75) and P(72)) ;
P(43) <= P(71) and P(69) ; P(42) <= P(71) and not P(69) ; P(41) <= P(70) or (P(71) and P(68)) ;
P(40) <= P(67) and P(65) ; P(39) <= P(67) and not P(65) ; P(38) <= P(66) or (P(67) and P(64)) ;
P(37) <= P(63) and P(61) ; P(36) <= P(63) and not P(61) ; P(35) <= P(62) or (P(63) and P(60)) ;
P(34) <= P(59) and P(57) ; P(33) <= P(59) and not P(57) ; P(32) <= P(58) or (P(59) and P(56)) ;
-- row 3
P(31) <= P(55) and P(52) ; P(30) <= P(55) and not P(52) ; P(29) <= P(54) or (P(55) and P(51)) ; P(28) <= P(53) or (P(55) and P(50)) ;
P(27) <= P(49) and P(46) ; P(26) <= P(49) and not P(46) ; P(25) <= P(48) or (P(49) and P(45)) ; P(24) <= P(47) or (P(49) and P(44)) ;
P(23) <= P(43) and P(40) ; P(22) <= P(43) and not P(40) ; P(21) <= P(42) or (P(43) and P(39)) ; P(20) <= P(41) or (P(43) and P(38)) ;
P(19) <= P(37) and P(34) ; P(18) <= P(37) and not P(34) ; P(17) <= P(36) or (P(37) and P(33)) ; P(16) <= P(35) or (P(37) and P(32)) ;
-- row 4
P(15) <= P(31) and P(27) ; P(14) <= P(31) and not P(27) ; P(13) <= P(30) or (P(31) and P(26)) ; P(12) <= P(29) or (P(31) and P(25)) ; P(11) <= P(28) or (P(31) and P(24)) ;
P(10) <= P(23) and P(19) ; P(9) <= P(23) and not P(19) ; P(8) <= P(22) or (P(23) and P(18)) ; P(7) <= P(21) or (P(23) and P(17)) ; P(6) <= P(20) or (P(23) and P(16)) ;
-- row 5
P(5) <= P(15) and P(10) ; P(4) <= P(15) and not P(10) ; P(3) <= P(14) or (P(15) and P(9)) ; P(2) <= P(13) or (P(15) and P(8)) ; P(1) <= P(12) or (P(15) and P(7)) ; P(0) <= P(11) or (P(15) and P(6)) ;
Z <= P(5 downto 0) ;
--end if;
--end process;
end structural;
--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--
--
-- Synthese OPAR Version 1 (Demo)
--
-- Decaleur
-- synthétisé le Lundi 18 Juin 2007
--
--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--
library IEEE;
use IEEE.STD_LOGIC_1164.All;
entity Shift is
port ( Entree : in Std_Logic_Vector (23 downto 0 ) ; -- E : input
D : in Std_Logic_Vector (4 downto 0 ) ; -- D : positions
--clk:in std_logic;
S : out Std_Logic_Vector (26 downto 0 ) ) ; -- Z : E shifted D positions
end Shift ;
architecture structural of Shift is
signal sticky : Std_Logic ; -- sticky bit
signal P0, P1, P2, P3, P4, P5 : Std_Logic_Vector (25 downto 0) ; -- internal signals
begin
--process (clk)
--begin
--if clk'event and clk='1' then
P5 <= Entree & "00" ; -- guard and round bits
with D(4) select P4 <= P5 when '0' , "0000000000000000" & P5(25 downto 16) when others ;
with D(3) select P3 <= P4 when '0' , "00000000" & P4(25 downto 8 ) when others ;
with D(2) select P2 <= P3 when '0' , "0000" & P3(25 downto 4) when others ;
with D(1) select P1 <= P2 when '0' , "00" & P2(25 downto 2) when others ;
with D(0) select P0 <= P1 when '0' , "0" & P1(25 downto 1) when others ;
sticky <= ((P5(15) or P5(14) or P5(13) or P5(12) or P5(11) or P5(10) or P5(9) or P5(8) or
P5(7) or P5(6) or P5(5) or P5(4) or P5(3) or P5(2) or P5(1) or P5(0)) and D(4)) or
((P4(7) or P4(6) or P4(5) or P4(4) or P4(3) or P4(2) or P4(1) or P4(0)) and D(3)) or
((P3(3) or P3(2) or P3(1) or P3(0)) and D(2)) or
((P2(1) or P2(0)) and D(1)) or (P1(0) and D(0)) ;
S <= P0 & sticky ;
--end if;
--end process;
end structural ; | gpl-3.0 | 2eca7b0912dfab04ea1443f626ae8c13 | 0.520477 | 3.226026 | false | false | false | false |
siam28/neppielight | dvid_in/tmds_decode.vhd | 2 | 4,037 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tmds_decode - Behavioral
--
-- Description: TMDS decode as per Digital Display Working Groups Digital Visual
-- Interface Revision 1.0 section 3.3.3
--
-- This doesn't seem 100% correct - "elsif sometimes_inverted(8) = '0' then" should
-- be "elsif sometimes_inverted(8) = '1' then" according to the standard.
--
-- However it does actually work!
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tmds_decode is
Port ( clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (9 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
c : out STD_LOGIC_VECTOR (1 downto 0);
active_data : out std_logic);
end tmds_decode;
architecture Behavioral of tmds_decode is
signal data_delayed : STD_LOGIC_VECTOR(9 downto 0);
signal data_delayed_active : STD_LOGIC := '0';
signal data_delayed_c : STD_LOGIC_VECTOR(1 downto 0);
signal sometimes_inverted : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
signal sometimes_inverted_c : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
signal sometimes_inverted_active : STD_LOGIC := '0';
begin
process(clk)
begin
if rising_edge(clk) then
-- Final stage in the pipeline
if sometimes_inverted_active = '0' then
c <= sometimes_inverted_c;
active_data <= '0';
data_out <= (others => '0');
elsif sometimes_inverted(8) = '0' then
c <= sometimes_inverted_c;
active_data <= '1';
data_out(0) <= sometimes_inverted(0);
data_out(1) <= sometimes_inverted(1) XOR sometimes_inverted(0);
data_out(2) <= sometimes_inverted(2) XOR sometimes_inverted(1);
data_out(3) <= sometimes_inverted(3) XOR sometimes_inverted(2);
data_out(4) <= sometimes_inverted(4) XOR sometimes_inverted(3);
data_out(5) <= sometimes_inverted(5) XOR sometimes_inverted(4);
data_out(6) <= sometimes_inverted(6) XOR sometimes_inverted(5);
data_out(7) <= sometimes_inverted(7) XOR sometimes_inverted(6);
else
c <= sometimes_inverted_c;
active_data <= '1';
data_out(0) <= sometimes_inverted(0);
data_out(1) <= sometimes_inverted(1) XNOR sometimes_inverted(0);
data_out(2) <= sometimes_inverted(2) XNOR sometimes_inverted(1);
data_out(3) <= sometimes_inverted(3) XNOR sometimes_inverted(2);
data_out(4) <= sometimes_inverted(4) XNOR sometimes_inverted(3);
data_out(5) <= sometimes_inverted(5) XNOR sometimes_inverted(4);
data_out(6) <= sometimes_inverted(6) XNOR sometimes_inverted(5);
data_out(7) <= sometimes_inverted(7) XNOR sometimes_inverted(6);
end if;
sometimes_inverted_active <= data_delayed_active;
sometimes_inverted_c <= data_delayed_c;
if data_delayed(9) = '1' then
sometimes_inverted <= data_delayed(8 downto 0) xor "011111111";
else
sometimes_inverted <= data_delayed(8 downto 0);
end if;
--- first step in the pipeline
case data_in is
when "0010101011" => data_delayed_c <= "01"; data_delayed_active <= '0';
when "1101010100" => data_delayed_c <= "00"; data_delayed_active <= '0';
when "0101010100" => data_delayed_c <= "10"; data_delayed_active <= '0';
when "1010101011" => data_delayed_c <= "11"; data_delayed_active <= '0';
when others => data_delayed_c <= "00"; data_delayed_active <= '1';
end case;
data_delayed <= data_in;
end if;
end process;
end Behavioral;
| gpl-2.0 | 46805044a3b0103639964a27ccb2621c | 0.54917 | 3.904255 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/vga4ram.vhd | 1 | 11,991 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(--clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(7 downto 0); -- iter output
ADDR1 : in std_logic_vector(17 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(17 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(17 downto 0);
data_in3 : in std_logic_vector(7 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(17 downto 0);
data_in4 : in std_logic_vector(7 downto 0);
data_write4 : in std_logic);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
component RAM_single_port
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
ADDR : in STD_LOGIC_VECTOR (17 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1, pix_read1 : integer range 0 to 76799:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 76799 := 0; -- the address at which displayed data is read
signal next_pixel1, data_temp1, data_temp2 , data_outtemp1, data_outtemp2,data_temp3, data_temp4 , data_outtemp3, data_outtemp4 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel2 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
--signal data_writetemp1, data_writetemp2 : std_logic;
signal ADDRtemp1, ADDRtemp2, ADDRtemp3, ADDRtemp4 : std_logic_vector(17 downto 0); -- the data coding the value of the pixel to be displayed
begin
--------------------------------------------------------------------------------
RAM1: RAM_single_port
port map (clk_vga,
data_write1,
data_in1,
ADDRtemp1,
data_outtemp1);
RAM2: RAM_single_port
port map (clk_vga,
data_write2,
data_in2,
ADDRtemp2,
data_outtemp2);
RAM3: RAM_single_port
port map (clk_vga,
data_write3,
data_in3,
ADDRtemp3,
data_outtemp3);
RAM4: RAM_single_port
port map (clk_vga,
data_write4,
data_in4,
ADDRtemp4,
data_outtemp4);
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 153599 else pix_read_addr - 153599;
ADDRtemp1<= ADDR1 when (data_write1 = '1') else std_logic_vector(to_unsigned(pix_read1, 18)) ;
ADDRtemp2<= ADDR2 when (data_write2 = '1') else std_logic_vector(to_unsigned(pix_read1, 18)) ;
ADDRtemp3<= ADDR3 when (data_write3 = '1') else std_logic_vector(to_unsigned(pix_read1, 18)) ;
ADDRtemp4<= ADDR4 when (data_write4 = '1') else std_logic_vector(to_unsigned(pix_read1, 18)) ;
--data_writetemp1 <= clk_VGA when (data_write1 = '0') else '1' ;
--data_writetemp2 <= clk_VGA when (data_write2 = '0') else '1' ;
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel1 <= screen1(pix_read_addrb) ;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel2 <= screen2(pix_read_addrb);
-- end if;
-- end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF pix_read_addr < 76799 THEN
next_pixel <= data_outtemp1;
ELSif pix_read_addr < 153599 THEN
next_pixel <= data_outtemp2;
ELSif pix_read_addr < 230399 THEN
next_pixel <= data_outtemp3;
else
next_pixel <= data_outtemp4;
END IF;
end if;
end process;
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1;
-- next_pixel1 <= data_in1;
-- else
-- next_pixel1 <= screen1(to_integer(unsigned(ADDR1)));
-- end if;
-- end if;
--end process;
--
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2;
-- next_pixel2 <= data_in2;
-- else
-- next_pixel2 <= screen2(to_integer(unsigned(ADDR2));
-- end if;
-- end if;
--end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,18)(17) = '0' else screen2;
--------------------------------------------------------------------------------
--proc<='0' when (pix_read_addr <153599) else '1';
pixel_read_addr : process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read1 : process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read1 <= pix_read1 + 1;
elsif (pix_read1 = 76799) then
pix_read1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 153599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 153599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= "00000000";
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | ef7ef530322de30540e7599de93a8184 | 0.546577 | 3.229464 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_RAM_288s.vhd | 1 | 2,115 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
--library ims;
--use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_RAM_288s is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture aQ16_8_RAM_288s of Q16_8_RAM_288s is
type ram_type is array (0 to 288-1) of STD_LOGIC_VECTOR (15 downto 0);
signal RAM : ram_type;
SIGNAL READ_C : UNSIGNED(8 downto 0);
SIGNAL WRITE_C : UNSIGNED(8 downto 0);
BEGIN
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(8 downto 0);
begin
if reset = '0' then
WRITE_C <= TO_UNSIGNED(0, 9);
elsif clock'event and clock = '1' then
if write_en = '1' then
TEMP := WRITE_C + TO_UNSIGNED(1, 9);
IF TEMP = 288 THEN
TEMP := TO_UNSIGNED(0, 9);
END IF;
WRITE_C <= TEMP;
else
WRITE_C <= WRITE_C;
end if;
end if;
end process;
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(8 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 9);
elsif clock'event and clock = '1' then
if read_en = '1' then
TEMP := READ_C + TO_UNSIGNED(1, 9);
IF TEMP = 288 THEN
TEMP := TO_UNSIGNED(0, 9);
END IF;
READ_C <= TEMP;
else
READ_C <= READ_C;
end if;
end if;
end process;
--
--
--
process(clock)
VARIABLE AR : INTEGER RANGE 0 to 287;
VARIABLE AW : INTEGER RANGE 0 to 287;
begin
if clock'event and clock = '1' then
AR := to_integer( READ_C );
AW := to_integer( WRITE_C );
if WRITE_EN = '1' then
RAM( AW ) <= INPUT_1(15 downto 0);
end if;
OUTPUT_1(15 downto 0) <= RAM( AR );
end if;
end process;
OUTPUT_1(31 downto 16) <= "0000000000000000";
END aQ16_8_RAM_288s;
| gpl-3.0 | 5023bd3c51a28665df68140f66a50dba | 0.545626 | 2.873641 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/example_design/Font_exdes.vhd | 1 | 3,903 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Font_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end Font_exdes;
architecture xilinx of Font_exdes is
component Font is
PORT (
SPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Font
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | 8558c4076e147350b54290dbf51d7288 | 0.569562 | 4.602594 | false | false | false | false |
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