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masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/rdpfifo_dp_cntl.vhd | 3 | 32,987 | -------------------------------------------------------------------------------
-- $Id: rdpfifo_dp_cntl.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--rdpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** but not limited to any warranties or representations that this **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
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-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Read Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
--
-- rdpfifo_dp_cntl.vhd
-- |
-- |
-- |-- proc_common_v2_00_a.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET August 15, 2001 -- Initial version adapted from pt design
--
-- DET Sept. 21, 2001 -- Size Optimized redesign and parameterization
--
--
-- DET 4/1/2004 proc_common V2 conversion
-- ~~~~~~
-- - Added reference to proc_common_v2_00_a for support modules.
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_counter_top;
Use opb_v20_v1_10_d.pf_occ_counter_top;
Use opb_v20_v1_10_d.pf_adder;
-------------------------------------------------------------------------------
entity rdpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 9;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port (
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_rd_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end rdpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
-- shared signals
signal sig_normal_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
----------------- start architecture logic ------------------------------------
begin
------------------------------------------------------------------------------
-- Generate the Read PFIFO with packetizing features included
------------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (
reset1,
normal_op,
packet_op,
rest1,
mark1,
rls1,
pkt_update,
nml_update
);
--INTERNAL SIGNALS
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_write : std_logic;
signal ld_addr_write_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-----------------------------------------------------------------------
-- Main Transition sequence state machine
-----------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
Case trans_state Is
When reset1 =>
trans_state <= normal_op;
hold_ack <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_addr_mark_into_write <= '1'; -- load the mark address into
-- the wr cntr
ld_occ_mark_into_norm <= '1'; -- load the marked occupancy
-- into the normal occupancy
-- cntr
When mark1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When rls1 =>
trans_state <= nml_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When nml_update =>
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking operations
-- This counter establishes the empty flag states
--------------------------------------------------------------------------
inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc <= decr_rd_addr or inc_mark_addr;
I_MARK_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
--------------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(hold_ack)
and not(rd_backup and int_almost_full)
and enable_wr_addr_inc;
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_write,
Load_value => mark_address,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Read Address Counter Logic
-----------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
-----------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_wr_addr
and enable_mark_addr_inc;
I_MARKREG_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_write_into_mark,
Load_value => write_address,
Count_Down => '0',
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
--------------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
------------------------------------------------------------------------------
-- Generate the Read PFIFO with no packetizing features
------------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
--Internal Signals
signal int_almost_full : std_logic;
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal occ_load_value : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_normal_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at the
-- same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty and full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
-----------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(rd_backup and int_almost_full);
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
-------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Read Address Counter Logic
--------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
--------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1);
decr_rd_addr <= rd_backup;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
----------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_v20_v1_10_d.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
--Carry_Out => ,
Ain => slv_max_vacancy,
Bin => sig_normal_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
| bsd-3-clause | dead09701ba8de2c052c2c77aa9f9342 | 0.408555 | 4.607766 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/gen_sync_bram.vhd | 2 | 5,339 | -------------------------------------------------------------------------------
-- $Id: gen_sync_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- gen_sync_bram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2004-03-24 New Version
--
-- Description:
-- Code to infer synchronous dual port bram and separate read/write clock dual
-- port bram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Sync_BRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
-- Write port
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
-- Read port
dpra_en : in std_logic;
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end Sync_BRAM;
architecture syn of Sync_BRAM is
type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
-- signal ram_mem : ram_type := (others => (others => '0'));
signal ram_mem : ram_type;
signal read_a : std_logic_vector(C_AWIDTH-1 downto 0);
signal read_dpra : std_logic_vector(C_AWIDTH-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
ram_mem(conv_integer(a)) <= di;
end if;
read_a <= a;
if (dpra_en = '1') then
read_dpra <= dpra;
end if;
end if;
end process;
dpo <= ram_mem(conv_integer(read_dpra));
end syn;
| bsd-3-clause | d7992f469d52bb9363ce018dda509166 | 0.564151 | 4.2712 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/testbench.vhd | 11 | 11,805 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity testbench is
end testbench;
architecture behavior of testbench is
-- Synch Manager Configuration Constants
constant SCHED_BADDR : std_logic_vector(0 to 31) := x"60000000";
constant SCHED_HADDR : std_logic_vector(0 to 31) := x"6FFFFFFF";
constant MUTEX_BADDR : std_logic_vector(0 to 31) := x"70000000";
constant MUTEX_HADDR : std_logic_vector(0 to 31) := x"7FFFFFFF";
constant SYNCH_THREADS : integer := 256;
constant SYNCH_MUTEXES : integer := 64;
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(SYNCH_MUTEXES);
constant THREAD_BITS : integer := log2(SYNCH_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
constant DATA_BITS : integer := 32;
--Inputs
signal OPB_Clk : std_logic := '0';
signal OPB_Rst : std_logic := '0';
signal OPB_RNW : std_logic := '0';
signal OPB_select : std_logic := '0';
signal OPB_seqAddr : std_logic := '0';
signal OPB_errAck : std_logic := '0';
signal OPB_MGrant : std_logic := '0';
signal OPB_retry : std_logic := '0';
signal OPB_timeout : std_logic := '0';
signal OPB_xferAck : std_logic := '0';
signal OPB_ABus : std_logic_vector(0 to 31) := (others=>'0');
signal OPB_BE : std_logic_vector(0 to 3) := (others=>'0');
signal OPB_DBus : std_logic_vector(0 to 31) := (others=>'0');
--Outputs
signal Sl_DBus : std_logic_vector(0 to 31);
signal Sl_errAck : std_logic;
signal Sl_retry : std_logic;
signal Sl_toutSup : std_logic;
signal Sl_xferAck : std_logic;
signal M_ABus : std_logic_vector(0 to 31);
signal M_BE : std_logic_vector(0 to 3);
signal M_busLock : std_logic;
signal M_request : std_logic;
signal M_RNW : std_logic;
signal M_select : std_logic;
signal M_seqAddr : std_logic;
-- Reset signals
signal system_reset : std_logic;
signal system_resetdone : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
synch : entity work.opb_synchmanager
generic map
(
C_NUM_THREADS => SYNCH_THREADS,
C_NUM_MUTEXES => SYNCH_MUTEXES,
C_SCHED_BADDR => SCHED_BADDR,
C_SCHED_HADDR => SCHED_HADDR,
C_BASEADDR => MUTEX_BADDR,
C_HIGHADDR => MUTEX_HADDR
)
port map
(
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
Sl_DBus => Sl_DBus,
Sl_errAck => Sl_errAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus => OPB_DBus,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
OPB_errAck => OPB_errAck,
OPB_MGrant => OPB_MGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
system_reset => system_reset,
system_resetdone => system_resetdone
);
tb : process
procedure bus_trans( rnw : in std_logic;
abus : in std_logic_vector(0 to 31);
dbus : in std_logic_vector(0 to 31) ) is
begin
wait until OPB_Clk = '1';
OPB_ABus <= abus;
OPB_DBus <= dbus;
OPB_RNW <= rnw;
OPB_select <= '1';
OPB_BE <= (others => '1');
wait until Sl_xferAck = '1' and OPB_Clk = '1';
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
OPB_BE <= (others => '0');
wait until OPB_Clk = '1';
end procedure bus_trans;
procedure bus_reset is
begin
wait until OPB_Clk = '1';
OPB_Rst <= '1';
OPB_select <= '0';
OPB_seqAddr <= '0';
OPB_RNW <= '0';
OPB_BE <= (others => '0');
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
wait until OPB_Clk = '1';
OPB_Rst <= '0';
end procedure bus_reset;
procedure sys_reset is
begin
-- Issue a bus reset first
bus_reset;
-- Assert the system reset signal
system_reset <= '1';
-- Wait until the core is finished resetting
wait until system_resetdone = '1';
-- Deassert the system reset signal
system_reset <= '0';
end procedure sys_reset;
function synch_cmd( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1);
cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to 31);
begin
addr := MUTEX_BADDR;
addr(30-MUTEX_BITS to 29) := mid;
addr(30-MUTEX_BITS-THREAD_BITS to 29-MUTEX_BITS) := tid;
addr(30-MUTEX_BITS-THREAD_BITS-COMMAND_BITS to 29-MUTEX_BITS-THREAD_BITS) := cmd;
return addr;
end function synch_cmd;
procedure synchm_lock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_LOCK),x"FFFFFFFF");
end procedure synchm_lock;
procedure synchm_unlock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_UNLOCK),x"FFFFFFFF");
end procedure synchm_unlock;
procedure synchm_trylock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_TRY),x"FFFFFFFF");
end procedure synchm_trylock;
procedure synchm_kind( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_KIND),x"FFFFFFFF");
end procedure synchm_kind;
procedure synchm_count( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_COUNT),x"FFFFFFFF");
end procedure synchm_count;
procedure synchm_owner( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_OWNER),x"FFFFFFFF");
end procedure synchm_owner;
procedure synchm_setkind( mid : in std_logic_vector(0 to MUTEX_BITS-1);
kind : in std_logic_vector(0 to KIND_BITS-1)) is
variable data : std_logic_vector(0 to DATA_BITS-1);
begin
data := (others => '0');
data(DATA_BITS-KIND_BITS to DATA_BITS-1) := kind;
bus_trans('0',synch_cmd(x"00",mid,SYNCH_KIND),data);
end procedure synchm_setkind;
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Send a bus reset command
sys_reset;
-- Setup the mutex kinds
synchm_setkind( "000000", SYNCH_FAST );
synchm_setkind( "000001", SYNCH_FAST );
synchm_setkind( "000010", SYNCH_ERROR );
synchm_setkind( "000011", SYNCH_RECURS );
-- Test standard locking and unlocking
synchm_lock( x"01", "000000" );
synchm_lock( x"02", "000000" );
synchm_trylock( x"03", "000000" );
synchm_lock( x"04", "000000" );
synchm_unlock( x"01", "000000" );
synchm_unlock( x"02", "000000" );
synchm_unlock( x"04", "000000" );
-- Test that fast mutex locking method works properly
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
-- Test that error checking mutex locking method works properly
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
-- Test that recursive mutex locking method works properly
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
-- Test that getting the owner works properly
synchm_owner( "000001" );
synchm_owner( "000010" );
synchm_owner( "000011" );
-- Test that getting the count works properly
synchm_count( "000011" );
-- Test that getting the kind works properly
synchm_kind( "000000" );
synchm_kind( "000001" );
synchm_kind( "000010" );
synchm_kind( "000011" );
-- Test that recursive mutex unlocking works
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
wait; -- will wait forever
end process;
clk : process
begin
OPB_Clk <= '0';
wait for 10 ns;
loop
OPB_Clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
end process;
end;
| bsd-3-clause | 04990a0fcd1a869b9858410e9aa1b70e | 0.557052 | 3.76315 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/xps_intc_v2_01_a/hdl/vhdl/intc_core.vhd | 2 | 42,046 | -------------------------------------------------------------------------------
-- intc_core - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v2.01a
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- xps_intc.vhd (wrapper for top level)
-- -- plbv46_slave_single
-- -plb_slave_attachment
-- -plb_address_decoder
-- -- intc_core
--
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 2/23/2007 First version
-- ^^^^^^^
-- Version intc_core v1.00a functionality is based on intc_core v1.00d wherein
-- the design is completed recoded for better readiabilty, save resources,
-- increase frequecny and remove the structural code.
-- ~~~~~~~
-- NSK 6/07/2007
-- ^^^^^^^
-- Correct the logic for generation of ivr_data_in. This is now depend on isr
-- and ier. Removed irq_gen dependency on this signal.
-- The problem reported by Rick - When interrupt(2) and interrupt(3) are active
-- but only interrupt(3) is enabled. IVR reads 0x2 instead of 0x3.
-- ~~~~~~~
-- NSK 7/31/2007
-- ^^^^^^^
-- 1. Valid_rd and Valid_wr changed to 7-bit vector length.
-- 2. Deleted process decoding Reg_add to register_en. Removed signal
-- register_en.
-- 3. Added signal read and used for generation of rd_data_int.
-- 4. Deleted the output ports Wr_ack & Rd_ack. Also the logic to generate
-- these signals.
-- ~~~~~~~
-- NSK 8/10/2007
-- ^^^^^^^
-- Updated to fix CR #445886 (by Rick). IVR need to be 32-bit to work with the
-- existing SW. Note that the reason of changing 32-bit register to width
-- equal to C_NUM_INTR is to save resources (Flip Flops).
-- 1. Signals mer, ipr & ivr is changed to width equal to C_DWIDTH from
-- REG_WIDTH.
-- 2. Added signals ier_out & isr_out of width equal to C_DWIDTH.
-- 3. Replaced the two generate statement MER_EQ_GEN & MER_NOT_EQ_GEN with
-- the direct assignment as mer is of width equal to C_DWIDTH.
-- 4. Added two generate blocks for signals ier_out & isr_out
-- REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR (C_NUM_INTR_INPUTS /= C_DWIDTH) &
-- REG_OUT_GEN_DWIDTH_EQ_NUM_INTR (C_NUM_INTR_INPUTS = C_DWIDTH).
-- 5. In the process IPR_P generating ipr; isr & ier changed to isr_out &
-- ier_out respectively.
-- 6. In the generate block IVR_GEN signal ivr_data_in changed to width equal
-- to C_DWIDTH.
-- 7. In the process IVR_DATA_GEN_P variable ivr_in changed to width equal
-- to C_DWIDTH.
-- 8. Removed the two different generate statement (OUTPUT_DATA_ONE_INTR_GEN &
-- OUTPUT_DATA_MULTI_INTR_GEN) for generating rd_data_int.
-- 9. Rd_data is directly generate in process OUTPUT_DATA_GEN_P; not
-- not depending on rd_data_int.
-- 10. Removed the unused signal rd_data_int.
-- ~~~~~~~
-- NSK 9/13/2008 version v2.00.a
-- ^^^^^^^
-- NSK 9/13/2008
-- ^^^^^^^
-- 1. Rolled to revision v2.00.a.
-- 2. Changed the library proc_common from v2_00_a to v3_00_a.
-- 3. Fixed CR #442790 to support edge on Irq.
-- I. Added generic C_IRQ_IS_LEVEL
-- a. If set to 0 generates edge interrupt
-- b. If set to 1 generates level interrupt
-- II. Changed the definition of generic C_IRQ_ACTIVE
-- a. Defines the edge for output interrupt if C_IRQ_IS_LEVEL=0
-- -- "0" = FALLING EDGE
-- -- "1" = RISING EDGE
-- b. Defines the level for output interrupt if C_IRQ_IS_LEVEL=1
-- -- "0" = LOW LEVEL
-- -- "1" = HIGH LEVEL
-- III. Added generic C_IRQ_IS_LEVEL in generic map of instance INTC_CORE_I
-- for component "intc_core" from library "xps_intc_v2_00_a."
-- IV. Added "C_IRQ_IS_LEVEL" in Definition of Generics section in
-- comments.
-- V. Modified the logic for edge generation on Irq.
-- a. Variable "irq_int" in process "IRQ_GEN_P" is changed to
-- irq_gen_int.
-- b. Added to seperate generate statement for generating Irq
-- -- IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1)
-- -- IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0)
-- ~~~~~~~
-- NSK 9/15/2008
-- ^^^^^^^
-- Removed unused parameter C_FAMILY.
-- ~~~~~~~
-- NSK 9/17/2008
-- ^^^^^^^
-- Update for linting: -
-- 1. Removed unused constant "REG_WIDTH" & function "get_reg_width".
-- 2. Process in generate block "RISING_EDGE_GEN" & "FALLING_EDGE_GEN" given
-- two different names "REG_INTR_RISE_P" & "REG_INTR_FALL_P" respectively.
-- 3. Corrected the same name conflict in the generate block "SIE_GEN" &
-- "CIE_GEN": -
-- a. Generate label in generate block "SIE_GEN" is chagned from "SIE_BIT"
-- to "SIE_BIT_GEN".
-- b. Generate label in generate block "CIE_GEN" is chagned from "SIE_BIT"
-- to "CIE_BIT_GEN".
-- ~~~~~~~
-- NSK 9/30/2008
-- ^^^^^^^
-- Type changed for the parameter C_DWIDTH & C_NUM_INTR_INPUTS from positive
-- to integer to have consistency with xps_intc.vhd.
-- ~~~~~~~
-- NSK 10/01/2008
-- ^^^^^^^
-- Updated the latest Copyright and removed XCS label.
-- ~~~~~~~
-- NSK 11/17/2008
-- ^^^^^^^
-- Update to fix IR #496531 - Irq toggles when C_IRQ_IS_LEVEL = 0
-- 1. Seperate generate blocks
-- a. ONE_INTR_IRQ_EDGE_GEN when C_IRQ_IS_LEVEL=0 & C_NUM_INTR_INPUTS=1.
-- b. MULTI_INTR_IRQ_EDGE_GEN when C_IRQ_IS_LEVEL=0 & C_NUM_INTR_INPUTS>1.
-- 2. Behavior of Irq is changed from pulse to a signal kind of level but goes
-- LOW when interrupt is ACKNOWLEDGED or DISABLED.
-- 3. For MULTI_INTR_IRQ_EDGE_GEN: -
-- a. Signal "active_intr" ANDing of ISE and IER detects active interrupts.
-- b. Signal "active_intr_d1" registers "active_intr".
-- c. Signal "deactive_intr_edge" detects the falling edge of "active_intr".
-- This means either the interrupt is acknowledge or disabled.
-- d. Signal "ack_disabled_detected" is ORed of "deactive_intr_edge". This
-- means any one of the active interrupt is acknowledge or disabled.
-- e. Signal "irq_int" goes to RESET when "ack_disabled_detected"=HIGH
--4. For ONE_INTR_IRQ_EDGE_GEN: -
-- Behavior is same as C_IRQ_IS_LEVEL=1 & C_NUM_INTR_INPUTS=1
-- ~~~~~~~
-- NSK 12/10/2008
-- ^^^^^^^
-- Update to fix IR #497895 - IRQ o/p for edge based interrupts does not
-- toggle to default value after a clock edge.
-- 1. Removed the logic added as above (Date - 11/17/2008) to fix IR #496531.
-- 2. Used generate block "ACK_OR_GEN" to generate the "ack_or" signal to
-- find if the current interrupt is acknowleged.
-- 3. Used state machine "GEN_CS_P" to generate "Irq".
-- ~~~~~~~--
-- NSK 12/11/2008
-- ^^^^^^^
-- Update for compile errors.
-- ~~~~~~~--
-- NSK 01/05/2009
-- ^^^^^^^
-- Update to fix IR #501183 - XPS INTC sometimes misses falling edge
-- interrupts, needs input synchronization
-- Below are the updates in generate block - INTR_DETECT_GEN/EDGE_DETECT_GEN
-- 1. Added signals
-- a. intr_sync - Assigned HIGH/LOW (depend on C_KIND_OF_EDGE) on event on
-- Intr (used as clock)
-- b. intr_p1 - register of intr_sync (Clk - used as clock)
-- c. intr_p2 - register of intr_p1 (Clk - used as clock)
-- 2. Assignment for intr_d1(i) is changed to intr_p2(i) (from Intr(i))
-- ~~~~~~~
-- NSK 01/07/2009
-- ^^^^^^^
-- Corrected:-
-- For intr_edge(i) assignment Intr(old) is changed to intr_p2(new).
-- ~~~~~~~
-- ~~~~~~~
-- BSB 01/31/2010
-- ^^^^^^^
-- New version v2.01.a created. attribute buffer type added on signal Intr
-- ~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
library proc_common_v3_00_a;
-------------------------------------------------------------------------
-- Package proc_common_pkg is used because it contains the RESET_ACTIVE
-- constant used to assign reset as active high status.
-------------------------------------------------------------------------
use proc_common_v3_00_a.proc_common_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-------------------------------------------------------------------------------
-- Definition of Ports:
-- -- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- -- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Valid_rd -- Read
-- Valid_wr -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1'
);
port
(
-- Inputs
Clk : in std_logic;
Rst : in std_logic;
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(2 downto 0);
Valid_rd : in std_logic_vector(0 to 7);
Valid_wr : in std_logic_vector(0 to 7);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Irq : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Signal declaration
-- ==================
signal wr_data_int : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or : std_logic;
-- Begin of architecture
begin
read <= Valid_rd(0) or Valid_rd(1) or Valid_rd(2) or Valid_rd(6) or
Valid_rd(7);
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (Valid_wr(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((Valid_wr(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (Valid_wr(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (Valid_wr(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or Valid_wr(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR_INPUTS
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
----------------------------------------------------------------------
-- Process IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_BIT_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
iar(i) <= '0';
elsif (Valid_wr(3) = '1') then
iar(i) <= wr_data_int(i);
end if;
end if;
end process IAR_BIT_P;
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (Valid_wr(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
end if;
end process ISR_P;
end generate REG_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR_INPUTS /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR_INPUTS /= C_DWIDTH)
generate
ier_out(C_NUM_INTR_INPUTS - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR_INPUTS) <= (others => '0');
isr_out(C_NUM_INTR_INPUTS - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR_INPUTS) <= (others => '0');
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR_INPUTS = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR_INPUTS = C_DWIDTH)
generate
ier_out <= ier;
isr_out <= isr;
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
end generate IPR_GEN;
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1)
--------------------------------------------------------------------------
IVR_GEN: if (C_HAS_IVR = 1) generate
signal ivr_data_in : std_logic_vector(C_DWIDTH - 1 downto 0);
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier)
variable ivr_in : std_logic_vector(C_DWIDTH - 1 downto 0)
:= (others => '1');
begin
for i in 0 to (C_NUM_INTR_INPUTS - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
ivr_in := CONV_STD_LOGIC_VECTOR(i, C_DWIDTH);
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ZEROS if (C_HAS_IVR = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if (C_HAS_IVR = 0) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
-----------------------------------------------------------------------
-- Generating the edge trigeered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if (C_KIND_OF_INTR(i) = '1') generate
signal intr_d1 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_edge : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_sync : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_p1 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_p2 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
begin
-------------------------------------------------------------------
-- Generating the rising edge interrupts if C_KIND_OF_EDGE(i) = 1
-------------------------------------------------------------------
RISING_EDGE_GEN: if (C_KIND_OF_EDGE(i) = '1') generate
---------------------------------------------------------------
-- Process SYNC_INTR_RISE_P to synchronize the interrupt signal
---------------------------------------------------------------
SYNC_INTR_RISE_P : process (Rst, Intr, iar) is
begin
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
intr_sync(i) <= '0';
elsif(Intr(i)'event and Intr(i)='1') then
intr_sync(i) <= '1';
end if;
end process SYNC_INTR_RISE_P;
---------------------------------------------------------------
-- Process REG_INTR_P to regiter the interrupt signal
---------------------------------------------------------------
REG_INTR_RISE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if (Rst = RESET_ACTIVE) then
intr_p1(i) <= '0';
intr_p2(i) <= '0';
intr_d1(i) <= '1';
else
intr_p1(i) <= intr_sync(i);
intr_p2(i) <= intr_p1(i);
intr_d1(i) <= intr_p2(i);
end if;
end if;
end process REG_INTR_RISE_P;
-- Creating one-shot rising edge triggered interrupts
intr_edge(i) <= '1' when ( (intr_p2(i) = '1') and
(intr_d1(i) = '0') )
else '0';
end generate RISING_EDGE_GEN;
-------------------------------------------------------------------
-- Generating the falling edge interrupts if C_KIND_OF_EDGE(i) = 0
-------------------------------------------------------------------
FALLING_EDGE_GEN: if (C_KIND_OF_EDGE(i) = '0') generate
---------------------------------------------------------------
-- Process SYNC_INTR_FALL_P to synchronize the interrupt signal
---------------------------------------------------------------
SYNC_INTR_FALL_P : process (Rst, Intr, iar) is
begin
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
intr_sync(i) <= '1';
elsif(Intr(i)'event and Intr(i)='0') then
intr_sync(i) <= '0';
end if;
end process SYNC_INTR_FALL_P;
---------------------------------------------------------------
-- Process REG_INTR_P to regiter the interrupt signal
---------------------------------------------------------------
REG_INTR_FALL_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if (Rst = RESET_ACTIVE) then
intr_p1(i) <= '1';
intr_p2(i) <= '1';
intr_d1(i) <= '0';
else
intr_p1(i) <= intr_sync(i);
intr_p2(i) <= intr_p1(i);
intr_d1(i) <= intr_p2(i);
end if;
end if;
end process REG_INTR_FALL_P;
-- Creating one-shot falling edge triggered interrupts
intr_edge(i) <= '1' when ( (intr_p2(i) = '0') and
(intr_d1(i) = '1') )
else '0';
end generate FALLING_EDGE_GEN;
------------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge trigeered interrupts
------------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif (intr_edge(i) = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if (C_KIND_OF_INTR(i) = '0') generate
------------------------------------------------------------------
-- Generating the active high interrupts if C_KIND_OF_LVL(i) = 1
------------------------------------------------------------------
ACTIVE_HIGH_GEN: if (C_KIND_OF_LVL(i) = '1') generate
--------------------------------------------------------------
-- Process ACTIVE_HIGH_LVL_P to generate hw_intr (active high)
--------------------------------------------------------------
ACTIVE_HIGH_LVL_P : process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif(Intr(i) = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process ACTIVE_HIGH_LVL_P;
end generate ACTIVE_HIGH_GEN;
------------------------------------------------------------------
-- Generating the active low interrupts if C_KIND_OF_LVL(i) = 0
------------------------------------------------------------------
ACTIVE_LOW_GEN: if (C_KIND_OF_LVL(i) = '0') generate
--------------------------------------------------------------
-- Process ACTIVE_LOW_LVL_P to generate hw_intr (active low)
--------------------------------------------------------------
ACTIVE_LOW_LVL_P : process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif(Intr(i) = '0') then
hw_intr(i) <= '1';
end if;
end if;
end process ACTIVE_LOW_LVL_P;
end generate ACTIVE_LOW_GEN;
end generate LVL_DETECT_GEN;
-----------------------------------------------------------------------
-- Generating All Interrupr Zero if C_KIND_OF_INTR(i) /= 1 or 0
-----------------------------------------------------------------------
NO_DETECT_GEN: if ( (C_KIND_OF_INTR(i) /= '1') and
(C_KIND_OF_INTR(i) /= '0') )
generate
hw_intr(i) <= '0';
end generate NO_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR_INPUTS = 1) generate
irq_gen <= isr(0) and ier(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR_INPUTS > 1) generate
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier)
variable irq_gen_int : std_logic := '0';
begin
irq_gen_int := isr(0) and ier(0);
for i in 1 to (isr'length - 1) loop
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen <= irq_gen_int;
end process IRQ_GEN_P;
end generate IRQ_MULTI_INTR_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (irq_gen = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen = '1') and (mer(0) = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
end generate IRQ_LEVEL_GEN;
--------------------------------------------------------------------------
-- Generating ack_or for edge output interrupt (if C_IRQ_IS_LEVEL = 0)
--------------------------------------------------------------------------
ACK_OR_GEN: if (C_IRQ_IS_LEVEL = 0) generate
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR_INPUTS = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR_INPUTS = 1) generate
ack_or <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR_INPUTS > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR_INPUTS > 1) generate
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
end generate ACK_OR_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
signal irq_int : std_logic;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst = '1') then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen='1') and (mer(0)='1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE => current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
Irq <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
end generate IRQ_EDGE_GEN;
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out, ivr,
mer) is
begin
if (read = '1') then
case Reg_addr is
when "000" => Rd_data <= isr_out; -- ISR (R/W)
when "001" => Rd_data <= ipr; -- IPR (Read only)
when "010" => Rd_data <= ier_out; -- IER (R/W)
when "110" => Rd_data <= ivr; -- IVR (Read only)
when "111" => Rd_data <= mer; -- MER (R/W)
-- IAR, SIE, CIE (Write only)
when others => Rd_data <= (others => '0');
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end imp;
| bsd-3-clause | 8920b25ae20e4d8861dc0cfbad188450 | 0.406674 | 4.574693 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/pcores/plb_thread_manager_tb_v1_00_a/simhdl/vhdl/plb_thread_manager_tb.vhd | 3 | 14,573 | ------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_thread_manager_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Tue Apr 14 15:01:55 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_thread_manager_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_thread_manager_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_thread_manager_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_thread_manager_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant INTERRUPT : integer := 31;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_thread_manager_v1_00_a.plb_thread_manager
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ
);
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
| bsd-3-clause | ca9c8d4429eeb85e72e0f36d83a64f7b | 0.427297 | 4.73303 | false | true | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo3.vhd | 2 | 67,511 | -------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- JAM 2002-02-02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
--
-- JAM 2002-04-12 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 Added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- JAM 2002-05-01 Changed FIFO_Empty output from buffer_Empty, which had
-- a clock delay, to the not of data_Exists_I, which
-- doesn't have any delay
--
-- DCW 2004-10-15 Changed unisim.all to unisim.vcomponents.
-- Added C_FAMILY generic.
-- Added C_AWIDTH generic.
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
use proc_common_v3_00_a.family.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_FAMILY : string := "virtex4"; -- latest and greatest
C_DWIDTH : positive := 8; -- changed to positive
C_AWIDTH : positive := 4; -- changed to positive
C_DEPTH : positive := 16 -- changed to positive
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH LESS THAN 17
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_LT_17 : if (C_DEPTH < 17) generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic
);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Depth check and assertion
--------------------------------------------------------------------------
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
Addr_Counters : for i in 0 to 3 generate
hsum_A(i) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAM
--------------------------------------------------------------------------
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I) -- [out std_logic]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from
-- the srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account
end loop; -- for srl16 addr
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_VE : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and not
(FIFO_Read and not(FIFO_Write) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3)));
FIFO_Write_1 <= FIFO_Write;
FIFO_Write_2 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Read_2 <= FIFO_Read;
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_2 when (data_Exists_I_2 = '1') else Data_Out_1;
Data_In_2 <= Data_Out_1;
Data_In_1 <= Data_In;
FIFO_Full <= buffer_Full_2;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2)) and not
(addr_i_2(3)) and (buffer_Full_1)) or data_Exists_I_2)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_2(0)) and not(addr_i_2(1)) and
not(addr_i_2(2)) and not(addr_i_2(3)));
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
FIFO_Empty <= not next_Data_Exists_1 and not next_Data_Exists_2;
-- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, data_Exists_I_2)
begin
if (data_Exists_I_2 = '0') then
Addr <= '0' & addr_i_1;
else
Addr <= '1' & addr_i_2;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(i) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(i) -- [out std_logic]
);
end generate FIFO_RAM_2;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_V2 : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 4) :=
conv_std_logic_vector(C_DEPTH-1,5);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 4);
signal sum_A : std_logic_vector(0 to 4);
signal addr_cy : std_logic_vector(0 to 5);
signal D_Out_ls : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
--buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(4) and
addr_i(1) = DEPTH(3) and
addr_i(2) = DEPTH(2) and
addr_i(3) = DEPTH(1) and
addr_i(4) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "00000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_i, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write,
I0 => FIFO_Write,
I1 => FIFO_Read,
I2 => buffer_Full
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 4 generate
hsum_A(I) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls(i),
Q15 => q15(i),
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
CE => valid_Write,
CLK => Clk,
D => Data_In(i)
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write,
D => q15(i),
Clk => Clk,
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
Q => D_Out_ms(i)
);
MUXF5_I: MUXF5
port map (
O => Data_Out(i), --[out]
I0 => D_Out_ls(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(4 - i); --flip the bits to account for srl16 addr
end loop;
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_VE : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_3 : std_logic_vector(3 downto 0);
signal buffer_Full_3 : std_logic;
signal next_buffer_Full_3 : std_logic;
signal next_Data_Exists_3 : std_logic;
signal data_Exists_I_3 : std_logic;
signal FIFO_Write_3 : std_logic;
signal Data_In_3 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_3 : std_logic;
signal Data_Out_3 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_4 : std_logic_vector(3 downto 0);
signal buffer_Full_4 : std_logic;
signal next_buffer_Full_4 : std_logic;
signal next_Data_Exists_4 : std_logic;
signal data_Exists_I_4 : std_logic;
signal FIFO_Write_4 : std_logic;
signal Data_In_4 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_4 : std_logic;
signal Data_Out_4 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
FIFO_Write_1 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Write_2 <= FIFO_Write and buffer_Full_1;
FIFO_Read_2 <= FIFO_Read;
FIFO_Write_3 <= FIFO_Write and buffer_Full_2;
FIFO_Read_3 <= FIFO_Read;
FIFO_Write_4 <= FIFO_Write and buffer_Full_3;
FIFO_Read_4 <= FIFO_Read;
Data_In_1 <= Data_In;
Data_In_2 <= Data_Out_1;
Data_In_3 <= Data_Out_2;
Data_In_4 <= Data_Out_3;
FIFO_Full <= buffer_Full_4;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
next_buffer_Full_3 <= '1' when (addr_i_3 = "1111") else '0';
next_buffer_Full_4 <= '1' when (addr_i_4 = "1111") else '0';
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and
not(FIFO_Read and not(FIFO_Write)
and not(addr_i_1(0)) and not(addr_i_1(1)) and not
(addr_i_1(2)) and not(addr_i_1(3)));
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2))
and not(addr_i_2(3)) and (buffer_Full_1)) or
data_Exists_I_2) and not(FIFO_Read and not(FIFO_Write)
and not(addr_i_2(0)) and not(addr_i_2(1)) and not
(addr_i_2(2)) and not(addr_i_2(3)));
next_Data_Exists_3 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_3(0))
and not(addr_i_3(1)) and not(addr_i_3(2)) and not
(addr_i_3(3)) and (buffer_Full_2)) or data_Exists_I_3)
and not(FIFO_Read and not(FIFO_Write) and not
(addr_i_3(0)) and not(addr_i_3(1)) and not
(addr_i_3(2)) and not(addr_i_3(3)));
next_Data_Exists_4 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_4(0))
and not(addr_i_4(1)) and not(addr_i_4(2)) and not
(addr_i_4(3)) and (buffer_Full_3)) or data_Exists_I_4)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_4(0)) and not(addr_i_4(1)) and
not(addr_i_4(2)) and not(addr_i_4(3)));
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_4 when (data_Exists_I_4 = '1') else
Data_Out_3 when (data_Exists_I_3 = '1') else
Data_Out_2 when (data_Exists_I_2 = '1') else
Data_Out_1;
FIFO_Empty <= not data_Exists_I_1;
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_3='0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDRS_3 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_3 <= "0000";
elsif ((buffer_Full_3='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_2 = '1') and
(data_Exists_I_3='1')) then
addr_i_3 <= addr_i_3 + 1;
elsif (not(addr_i_3 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_4='0')) then
addr_i_3 <= addr_i_3 - 1;
else
null;
end if;
end if;
end process;
ADDRS_4 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_4 <= "0000";
elsif ((buffer_Full_4='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_3 = '1') and
(data_Exists_I_4='1')) then
addr_i_4 <= addr_i_4 + 1;
elsif (not(addr_i_4 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_4 <= addr_i_4 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, addr_i_3, addr_i_4,
data_Exists_I_2, data_Exists_I_3, data_Exists_I_4)
begin
if ( (data_Exists_I_2 = '0') and
(data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "00" & addr_i_1;
elsif ( (data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "01" & addr_i_2;
elsif ( (data_Exists_I_4 = '0') )
then
Addr <= "10" & addr_i_3;
else
Addr <= "11" & addr_i_4;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_3_DFF : FDR
port map (
Q => data_Exists_I_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_4_DFF : FDR
port map (
Q => data_Exists_I_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_3_DFF : FDR
port map (
Q => buffer_Full_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_4_DFF : FDR
port map (
Q => buffer_Full_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(I) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(I) -- [out std_logic]
);
end generate FIFO_RAM_2;
FIFO_RAM_3 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_3, -- [in std_logic]
D => Data_In_3(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_3(0), -- [in std_logic]
A1 => addr_i_3(1), -- [in std_logic]
A2 => addr_i_3(2), -- [in std_logic]
A3 => addr_i_3(3), -- [in std_logic]
Q => Data_Out_3(I) -- [out std_logic]
);
end generate FIFO_RAM_3;
FIFO_RAM_4 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_4, -- [in std_logic]
D => Data_In_4(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_4(0), -- [in std_logic]
A1 => addr_i_4(1), -- [in std_logic]
A2 => addr_i_4(2), -- [in std_logic]
A3 => addr_i_4(3), -- [in std_logic]
Q => Data_Out_4(I) -- [out std_logic]
);
end generate FIFO_RAM_4;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_V2 : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 5) :=
conv_std_logic_vector(C_DEPTH-1,6);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 5);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 5);
signal sum_A : std_logic_vector(0 to 5);
signal addr_cy : std_logic_vector(0 to 6);
signal D_Out_ls_1 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_2 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_3 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ls : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15_1 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_2 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_3 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component MUXF6
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
-- XST WA for CR183399
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(5) and
addr_i(1) = DEPTH(4) and
addr_i(2) = DEPTH(3) and
addr_i(3) = DEPTH(2) and
addr_i(4) = DEPTH(1) and
addr_i(5) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "000000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write, -- [out std_logic]
I0 => FIFO_Write, -- [in std_logic]
I1 => FIFO_Read, -- [in std_logic]
I2 => buffer_Full -- [in std_logic]
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 5 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate ADDR_COUNTERS;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS1 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_1(i), --[out]
Q15 => q15_1(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => Data_In(i) --[in]
);
SRLC16E_LS2 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_2(i), --[out]
Q15 => q15_2(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_1(i) --[in]
);
MUXF5_LS: MUXF5
port map (
O => Data_O_LS(i), --[out]
I0 => D_Out_ls_1(I), --[in]
I1 => D_Out_ls_2(I), --[in]
S => addr_i(4) --[in]
);
SRLC16E_LS3 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_3(i), --[out]
Q15 => q15_3(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_2(i) --[in]
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, --[in]
D => q15_3(i), --[in]
Clk => Clk, --[in]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
Q => D_Out_ms(I) --[out]
);
MUXF5_MS: MUXF5
port map (
O => Data_O_MS(i), --[out]
I0 => D_Out_ls_3(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
MUXF6_I: MUXF6
port map (
O => Data_out(i), --[out]
I0 => Data_O_ls(i), --[in]
I1 => Data_O_ms(i), --[in]
S => addr_i(5) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(5 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end generate;
end architecture imp;
| bsd-3-clause | be2dedb9a1ebc177dda5cd94a2558727 | 0.361956 | 4.363149 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/master.vhd | 10 | 10,243 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity master is
generic
(
C_BASEADDR : std_logic_vector := x"00000000";
C_HIGHADDR : std_logic_vector := x"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := x"00000000";
C_RESULT_BASEADDR : std_logic_vector := x"00000000";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 6;
C_NUM_CE : integer := 4
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus2IP_MstLastAck : in std_logic;
-- IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
-- IP2Bus_MstBurst : out std_logic;
-- IP2Bus_MstBusLock : out std_logic;
-- IP2Bus_MstRdReq : out std_logic;
-- IP2Bus_MstWrReq : out std_logic;
-- IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : in std_logic;
send_id : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : out std_logic;
saddr : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sena : out std_logic;
swea : out std_logic;
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end master;
architecture behavioral of master is
constant THR_BIT : integer := log2( C_NUM_THREADS );
type send_state is
(
IDLE,
SENDING,
FINISH
);
type queue_state is
(
IDLE,
DONE,
GETWAIT,
GETDONE
);
signal mst_cmplt : std_logic;
signal send_cs : send_state;
signal send_ns : send_state;
signal queue_cs : queue_state;
signal queue_ns : queue_state;
signal send_rdy : std_logic;
signal send_valid : std_logic;
signal send_validn : std_logic;
signal send_cur : std_logic_vector(0 to THR_BIT-1);
signal send_curn : std_logic_vector(0 to THR_BIT-1);
signal send_first : std_logic_vector(0 to THR_BIT-1);
signal send_firstn : std_logic_vector(0 to THR_BIT-1);
signal send_last : std_logic_vector(0 to THR_BIT-1);
signal send_lastn : std_logic_vector(0 to THR_BIT-1);
signal send_count : std_logic_vector(0 to THR_BIT-1);
signal send_countn : std_logic_vector(0 to THR_BIT-1);
begin
-- System reset only takes one clock cycle so were always "done"
system_resetdone <= '1';
queue_update : process(Bus2IP_Clk) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
queue_cs <= IDLE;
send_count <= (others => '0');
send_first <= (others => '0');
send_last <= (others => '0');
send_cur <= (others => '0');
send_valid <= '0';
else
queue_cs <= queue_ns;
send_count <= send_countn;
send_first <= send_firstn;
send_last <= send_lastn;
send_cur <= send_curn;
send_valid <= send_validn;
end if;
end if;
end process queue_update;
queue_controller : process(Bus2IP_Clk,queue_cs, send_cur, send_last, send_first, send_count, send_ena, send_id, send_rdy, sinext) is
begin
sena <= '0';
swea <= '0';
saddr <= (others => '0');
sonext <= (others => '0');
queue_ns <= queue_cs;
send_curn <= send_cur;
send_lastn <= send_last;
send_firstn <= send_first;
send_countn <= send_count;
send_validn <= '0';
case queue_cs is
when IDLE =>
if( send_ena = '1' ) then
if( send_count = zero(THR_BIT) ) then
send_firstn <= send_id;
else
sena <= '1';
swea <= '1';
saddr <= send_last;
sonext <= send_id;
end if;
send_lastn <= send_id;
send_countn <= send_count+1;
send_ack <= '1';
queue_ns <= DONE;
elsif( send_rdy = '1' and send_count /= zero(THR_BIT) ) then
send_curn <= send_first;
send_validn <= '1';
sena <= '1';
saddr <= send_first;
queue_ns <= GETWAIT;
end if;
when DONE =>
send_ack <= '1';
if( send_ena = '0' ) then
queue_ns <= IDLE;
end if;
when GETWAIT => null;
queue_ns <= GETDONE;
when GETDONE =>
send_firstn <= sinext;
send_countn <= send_count-1;
queue_ns <= IDLE;
end case;
end process queue_controller;
send_update : process (Bus2IP_Clk,send_ns) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
send_cs <= IDLE;
else
send_cs <= send_ns;
end if;
end if;
end process send_update;
send_controller : process (Bus2IP_Mst_CmdAck, Bus2IP_MstRd_src_rdy_n, send_cs,send_valid,send_cur) is
begin
send_ns <= send_cs;
send_rdy <= '0';
IP2Bus_Mst_Addr <= (others => '0');
IP2Bus_Mst_BE <= (others => '0');
IP2Bus_MstRd_Req <= '0';
case send_cs is
when IDLE =>
send_rdy <= '1';
if( send_valid = '1' ) then
send_ns <= SENDING;
end if;
when SENDING =>
-- Capture the Bus2IP_Mst_Cmplt value for later.
if (mst_cmplt = '0') then
mst_cmplt <= Bus2IP_Mst_Cmplt;
end if;
if (Bus2IP_Mst_CmdAck = '1') then
send_ns <= FINISH;
else
IP2Bus_Mst_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRd_Req <= '1';
IP2Bus_Mst_BE <= "1111";
send_ns <= SENDING;
end if;
when FINISH =>
if ((mst_cmplt = '1') or (Bus2IP_Mst_Cmplt = '1')) then
send_ns <= IDLE;
else
send_ns <= FINISH;
end if;
end case;
end process send_controller;
end behavioral;
| bsd-3-clause | 6675cabad7a35985ee93fe9d80fc5c9b | 0.496632 | 3.917017 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/fifo_async_almost_full.vhd | 1 | 11,092 | -- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async_almost_full is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector(DWIDTH - 1 downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector(DWIDTH - 1 downto 0); -- dob delay = 2 clk compared with rdb
empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
dn : out std_logic_vector(AWIDTH -1 downto 0)
);
end fifo_async_almost_full;
architecture fast_read of fifo_async_almost_full is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal wea_sync : std_logic := '0';
signal wp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- wp <= (others => '0');
-- elsif full_flag = '0' and wea = '1' then
if full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ASYNCWRITE_wea_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clka,
sync_clk => clkb,
async_wren => wea,
trigger => '1',
sync_wren => wea_sync,
over => open,
flag => open
);
WritePointorCtrl_sync : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
wp_sync <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- wp_sync <= (others => '0');
-- elsif full_flag = '0' and wea_sync = '1' then
if full_flag = '0' and wea_sync = '1' then
wp_sync <= wp_sync + 1;
end if;
end if;
end process;
ReadPointorCtrl : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- rp <= (others => '0');
-- elsif empty_flag = '0' and rdb = '1' then
if empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
empty_flag <= '1';
elsif rising_edge(clkb) then
-- if clr = '1' then
-- empty_flag <= '1';
-- elsif (wp_sync = rp) and (wea_sync = '1') then
if (wp_sync = rp) and (wea_sync = '1') then
empty_flag <= '0';
elsif (wp_sync = rp + 1) and (rdb = '1'and wea_sync = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
full_flag <= '0';
elsif rising_edge(clkb) then
-- if clr = '1' then
-- full_flag <= '0';
-- elsif (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
if (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
full_flag <= '1';
elsif (wp_sync = rp) and (rdb = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp_sync - rp;
end fast_read;
---------------------------------------------------------------------------------
architecture fast_write of fifo_async_almost_full is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal rdb_sync : std_logic := '0';
signal rp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- wp <= (others => '0');
-- elsif full_flag = '0' and wea = '1' then
if full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ReadPointorCtrl : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- rp <= (others => '0');
-- elsif empty_flag = '0' and rdb = '1' then
if empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
ASYNCWRITE_rdb_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clkb,
sync_clk => clka,
async_wren => rdb,
trigger => '1',
sync_wren => rdb_sync,
over => open,
flag => open
);
ReadPointorCtrl_sync : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
rp_sync <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- rp_sync <= (others => '0');
-- elsif empty_flag = '0' and rdb_sync = '1' then
if empty_flag = '0' and rdb_sync = '1' then
rp_sync <= rp_sync + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
empty_flag <= '1';
elsif rising_edge(clka) then
-- if clr = '1' then
-- empty_flag <= '1';
-- elsif (wp = rp_sync) and (wea = '1') then
if (wp = rp_sync) and (wea = '1') then
empty_flag <= '0';
elsif (wp = rp_sync + 1) and (rdb_sync = '1'and wea = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
full_flag <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
-- if clr = '1' then
-- full_flag <= '0';
-- elsif (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
if (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
full_flag <= '1';
elsif (wp = rp_sync) and (rdb_sync = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
GetAlmostFull : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
almost_full <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
-- if clr = '1' then
-- almost_full <= '0';
-- elsif (wp = rp_sync - 2) and (wea = '1' and rdb_sync = '0') then
if (wp = rp_sync - 2) and (wea = '1' and rdb_sync = '0') then
almost_full <= '1';
elsif (wp = rp_sync - 1) and (wea = '0' and rdb_sync = '1') then
almost_full <= '0';
end if;
end if;
end process;
dn <= wp - rp_sync;
end fast_write;
| gpl-2.0 | a0c1efbe7689e53f52209ab42af8fe05 | 0.549225 | 2.675995 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd | 2 | 22,674 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause | 8a3c6eb55228c1204e13a9358ea29153 | 0.418762 | 3.90527 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_dpram_select.vhd | 3 | 93,792 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| bsd-3-clause | 36411cb5d93867a8d9589396d44b5ca5 | 0.472066 | 3.802019 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutexattr_init_3.vhd | 2 | 15,019 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutexattr_init_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- retVal = hthread_mutexattr_init( mutexattr );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 220acb141b87b4daea64f6d72da1daba | 0.537719 | 3.865894 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_master_lite_v1_00_a/hdl/vhdl/axi_master_lite_reset.vhd | 2 | 5,868 | -------------------------------------------------------------------------------
-- axi_master_lite_reset.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_master_lite_reset.vhd
--
-- Description:
--
-- This VHDL file implements the reset module for the AXI Master lite.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_lite_reset.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.1 $
-- Date: $12/01/2010$
--
-- History:
-- DET 12/01/2010 Initial Version
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_lite_reset is
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
axi_aresetn : in std_logic ;
-----------------------------------------------------------------------
-- IPIC Reset Input
-----------------------------------------------------------------------
ip2bus_mst_reset : In std_logic ;
-----------------------------------------------------------------------
-- Combined Reset Output
-----------------------------------------------------------------------
rst2ip_reset_out : out std_logic
);
end entity axi_master_lite_reset;
architecture implementation of axi_master_lite_reset is
-- Signals
signal sig_axi_reset : std_logic := '0';
signal sig_ipic_reset : std_logic := '0';
signal sig_combined_reset : std_logic := '0';
begin --(architecture implementation)
-- Assign the output port
rst2ip_reset_out <= sig_combined_reset;
-- Generate an active high combined reset from the
-- axi reset input and the IPIC reset input
sig_axi_reset <= not(axi_aresetn);
sig_ipic_reset <= ip2bus_mst_reset;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RST_REG
--
-- Process Description:
-- Implements the register for the combined reset output.
--
-------------------------------------------------------------
IMP_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_reset = '1') then
sig_combined_reset <= '1';
else
sig_combined_reset <= sig_axi_reset or sig_ipic_reset;
end if;
end if;
end process IMP_RST_REG;
end implementation;
| bsd-3-clause | 1b193ab1c06fc530341076401bbb7423 | 0.480743 | 5.378552 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_mutexInitText.vhd | 2 | 14,239 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
FUNCTION_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal mutexAttrPtr, mutexAttrPtr_next : std_logic_vector(0 to 31);
signal mutexPtr, mutexPtr_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
mutexAttrPtr <= mutexAttrPtr_next;
mutexPtr <= mutexPtr_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_15 =>
current_state <= STATE_15;
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
mutexAttrPtr_next <= mutexAttrPtr;
mutexPtr_next <= mutexPtr;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
next_state <= STATE_1;
-- call malloc( 0x8 ) to allocate space for a mutexattr.
when STATE_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- store the returned pointer address
when STATE_3 =>
mutexAttrPtr_next <= toUser_value;
next_state <= STATE_4;
-- call hthread_mutexattr_init( *mutexattr );
when STATE_4 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_5;
when STATE_5 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- call hthread_mutexattr_setnum( *mutexattr, 4 )
when STATE_6 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= state_7;
when STATE_7 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_8;
when STATE_8 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_SETNUM;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
-- call malloc( 0x8 ) to allocate space for a mutex
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
-- store value of mutexPtr
when STATE_11 =>
mutexPtr_next <= toUser_value;
next_state <= STATE_12;
-- call hthread_mutex_init( *mutex, *mutexattr )
when STATE_12 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_13;
when STATE_13 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexPtr;
next_state <= WAIT_STATE;
return_state_next <= state_14;
when STATE_14 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fbba0d97d2a381931aff22def9d0f015 | 0.555446 | 3.999719 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/plb_hwti.vhd | 2 | 40,730 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library fsl_v20_v2_10_a;
use fsl_v20_v2_10_a.all;
entity plb_hwti is
generic
(
C_MANAG_BASE : std_logic_vector := x"60000000";
C_SCHED_BASE : std_logic_vector := x"61000000";
C_MUTEX_BASE : std_logic_vector := x"75000000";
C_CONDV_BASE : std_logic_vector := x"74000000";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
U2HLOW_M_WRITE : in std_logic;
U2HLOW_M_DATA : in std_logic_vector(0 to 31);
U2HLOW_M_CONTROL : in std_logic;
U2HLOW_M_FULL : out std_logic;
U2HHIGH_M_WRITE : in std_logic;
U2HHIGH_M_DATA : in std_logic_vector(0 to 31);
U2HHIGH_M_CONTROL : in std_logic;
U2HHIGH_M_FULL : out std_logic;
H2ULOW_S_READ : in std_logic;
H2ULOW_S_DATA : out std_logic_vector(0 to 31);
H2ULOW_S_CONTROL : out std_logic;
H2ULOW_S_EXISTS : out std_logic;
H2UHIGH_S_READ : in std_logic;
H2UHIGH_S_DATA : out std_logic_vector(0 to 31);
H2UHIGH_S_CONTROL : out std_logic;
H2UHIGH_S_EXISTS : out std_logic;
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity plb_hwti;
architecture IMP of plb_hwti is
signal USER2HWTIL_S_READ : std_logic;
signal USER2HWTIL_S_DATA : std_logic_vector(0 to 31);
signal USER2HWTIL_S_CONTROL : std_logic;
signal USER2HWTIL_S_EXISTS : std_logic;
signal USER2HWTIL_M_WRITE : std_logic;
signal USER2HWTIL_M_DATA : std_logic_vector(0 to 31);
signal USER2HWTIL_M_CONTROL : std_logic;
signal USER2HWTIL_M_FULL : std_logic;
signal USER2HWTIH_S_READ : std_logic;
signal USER2HWTIH_S_DATA : std_logic_vector(0 to 31);
signal USER2HWTIH_S_CONTROL : std_logic;
signal USER2HWTIH_S_EXISTS : std_logic;
signal USER2HWTIH_M_WRITE : std_logic;
signal USER2HWTIH_M_DATA : std_logic_vector(0 to 31);
signal USER2HWTIH_M_CONTROL : std_logic;
signal USER2HWTIH_M_FULL : std_logic;
signal USER2HWTI_S_READ : std_logic;
signal USER2HWTI_S_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_S_CONTROL : std_logic;
signal USER2HWTI_S_EXISTS : std_logic;
signal USER2HWTI_M_WRITE : std_logic;
signal USER2HWTI_M_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_M_CONTROL : std_logic;
signal USER2HWTI_M_FULL : std_logic;
signal HWTI2USERL_S_READ : std_logic;
signal HWTI2USERL_S_DATA : std_logic_vector(0 to 31);
signal HWTI2USERL_S_CONTROL : std_logic;
signal HWTI2USERL_S_EXISTS : std_logic;
signal HWTI2USERL_M_WRITE : std_logic;
signal HWTI2USERL_M_DATA : std_logic_vector(0 to 31);
signal HWTI2USERL_M_CONTROL : std_logic;
signal HWTI2USERL_M_FULL : std_logic;
signal HWTI2USERH_S_READ : std_logic;
signal HWTI2USERH_S_DATA : std_logic_vector(0 to 31);
signal HWTI2USERH_S_CONTROL : std_logic;
signal HWTI2USERH_S_EXISTS : std_logic;
signal HWTI2USERH_M_WRITE : std_logic;
signal HWTI2USERH_M_DATA : std_logic_vector(0 to 31);
signal HWTI2USERH_M_CONTROL : std_logic;
signal HWTI2USERH_M_FULL : std_logic;
signal HWTI2USER_S_READ : std_logic;
signal HWTI2USER_S_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_S_CONTROL : std_logic;
signal HWTI2USER_S_EXISTS : std_logic;
signal HWTI2USER_M_WRITE : std_logic;
signal HWTI2USER_M_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_M_CONTROL : std_logic;
signal HWTI2USER_M_FULL : std_logic;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_SLAVE : integer := USER_00;
constant USER_MASTER : integer := USER_10;
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_SLAVE, -- user logic slave space (s/w addressable constrol/status registers)
1 => USER_MASTER -- user logic master space (ip master model registers)
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant SLAVE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant SLAVE_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000020";
constant MASTER_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000002F";
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & SLAVE_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & SLAVE_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & MASTER_BASEADDR, -- user logic master space base address
ZERO_ADDR_PAD & MASTER_HIGHADDR -- user logic master space high address
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 64;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 32, -- user logic slave space data width
1 => 32 -- user logic master space data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_SLAVE_CE : integer := 8;
constant USER_NUM_MASTER_CE : integer := 8;
constant USER_NUM_CE : integer := USER_NUM_SLAVE_CE+USER_NUM_MASTER_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_SLAVE_CE), -- number of chip enableds for user logic slave space (one per register)
1 => pad_power2(USER_NUM_MASTER_CE) -- number of chip enables for user logic master space (one per register)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0), -- user logic slave space dependent properties (none defined)
1 => (others => 0) -- user logic master space dependent properties (none defined)
);
-- specify determinate timing parameters to be used during read
-- accesses for each address range, these values are used to optimize
-- data beat timing response for burst reads from addresses sources such
-- as ddr and sdram memory, each address space requires three integer
-- entries for mode [0-2], latency [0-31] and wait states [0-31].
constant ARD_DTIME_READ_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate read parameters
0, 0, 0 -- user logic master space determinate read parameters
);
-- specify determinate timing parameters to be used during write
-- accesses for each address range, they not used currently, so
-- all entries should be set to zeros.
constant ARD_DTIME_WRITE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate write parameters
0, 0, 0 -- user logic master space determinate write parameters
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the plb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- plb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 1;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 128.
constant DEV_MAX_BURST_SIZE : integer := 128;
-- specify size of the largest target burstable memory space (in
-- bytes and a power of 2), this is to optimize the size of the
-- internal burst address counters.
constant DEV_BURST_PAGE_SIZE : integer := 1024;
-- specify number of plb clock cycles are allowed before a
-- data phase transfer timeout, this feature is useful during
-- system integration and debug.
constant DEV_DPHASE_TIMEOUT : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a plb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of plb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify allowing dma busrt mode transactions or not.
constant DMA_ALLOW_BURST : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma, apply to software
-- design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000;
-- specify period of the plb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant PLB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the plb data bus width.
constant IPIF_DWIDTH : integer := C_PLB_DWIDTH;
-- specify ipif address bus size, used for future ipif optimization,
-- should be set equal to the plb address bus width.
constant IPIF_AWIDTH : integer := C_PLB_AWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_PLB_AWIDTH;
-- specify index for user logic slave/master spaces chip enable.
constant USER_SLAVE_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_SLAVE));
constant USER_MASTER_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_MASTER));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_Data : std_logic_vector(0 to C_PLB_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iBus2IP_Data : std_logic_vector(0 to C_PLB_DWIDTH - 1);
signal iBus2IP_BE : std_logic_vector(0 to (C_PLB_DWIDTH/8) - 1);
signal iBus2IP_Burst : std_logic;
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstBE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1) := (others => '0');
signal iIP2IP_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iIP2Bus_MstNum : std_logic_vector(0 to log2(DEV_MAX_BURST_SIZE/(C_PLB_DWIDTH/8))) := (others => '0');
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to find_id_dwidth(ARD_ID_ARRAY, ARD_DWIDTH_ARRAY, IPIF_RDFIFO_DATA, 32)-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
begin
------------------------------------------
-- instantiate the PLB IPIF
------------------------------------------
PLB_IPIF_I : entity plb_ipif_v2_01_a.plb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_ARD_DTIME_READ_ARRAY => ARD_DTIME_READ_ARRAY,
C_ARD_DTIME_WRITE_ARRAY => ARD_DTIME_WRITE_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_DEV_BURST_PAGE_SIZE => DEV_BURST_PAGE_SIZE,
C_DEV_DPHASE_TIMEOUT => DEV_DPHASE_TIMEOUT,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_ALLOW_BURST => DMA_ALLOW_BURST,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_CLK_PERIOD_PS => PLB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_IPIF_AWIDTH => IPIF_AWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
PLB_clk => PLB_Clk,
Reset => PLB_Rst,
Freeze => '0',
IP2INTC_Irpt => open,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
IP2Bus_Clk => '0',
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Freeze => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '0',
Bus2IP_Addr => open,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_IPMstTrans => open,
IP2RFIFO_WrReq => '0',
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_WrAck => open,
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_Data => open,
WFIFO2IP_RdAck => open,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
IP2Bus_DMA_Req => '0',
Bus2IP_DMA_Ack => open
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hwti_v1_00_a.user_logic
generic map
(
--C_MANAG_BASEADDR : std_logic_vector := x"00000000";
--C_SCHED_BASEADDR : std_logic_vector := x"00000000";
--C_MUTEX_BASEADDR : std_logic_vector := x"00000000";
--C_CONDV_BASEADDR : std_logic_vector := x"00000000";
USR_BASE => C_BASEADDR,
MTX_BASE => C_MUTEX_BASE,
CDV_BASE => C_CONDV_BASE,
SCH_BASE => C_SCHED_BASE,
MNG_BASE => C_MANAG_BASE,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
FSL_S_READ => USER2HWTI_S_READ,
FSL_S_DATA => USER2HWTI_S_DATA,
FSL_S_CONTROL => USER2HWTI_S_CONTROL,
FSL_S_EXISTS => USER2HWTI_S_EXISTS,
FSL_M_WRITE => HWTI2USER_M_WRITE,
FSL_M_DATA => HWTI2USER_M_DATA,
FSL_M_CONTROL => HWTI2USER_M_CONTROL,
FSL_M_FULL => HWTI2USER_M_FULL,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr
);
user2hwti_low : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => USER2HWTIL_M_Data,
FSL_M_Control => USER2HWTIL_M_Control,
FSL_M_Write => USER2HWTIL_M_Write,
FSL_M_Full => USER2HWTIL_M_Full,
FSL_S_Clk => '0',
FSL_S_Data => USER2HWTIL_S_Data,
FSL_S_Control => USER2HWTIL_S_Control,
FSL_S_Read => USER2HWTIL_S_Read,
FSL_S_Exists => USER2HWTIL_S_Exists,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
user2hwti_high : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => USER2HWTIH_M_DATA,
FSL_M_Control => USER2HWTIH_M_CONTROL,
FSL_M_Write => USER2HWTIH_M_WRITE,
FSL_M_Full => USER2HWTIH_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => USER2HWTIH_S_DATA,
FSL_S_Control => USER2HWTIH_S_CONTROL,
FSL_S_Read => USER2HWTIH_S_READ,
FSL_S_Exists => USER2HWTIH_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
hwti2user_low : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => HWTI2USERL_M_DATA,
FSL_M_Control => HWTI2USERL_M_CONTROL,
FSL_M_Write => HWTI2USERL_M_WRITE,
FSL_M_Full => HWTI2USERL_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => HWTI2USERL_S_DATA,
FSL_S_Control => HWTI2USERL_S_CONTROL,
FSL_S_Read => HWTI2USERL_S_READ,
FSL_S_Exists => HWTI2USERL_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
hwti2user_high : entity fsl_v20_v2_10_a.fsl_v20
generic map
(
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16
)
port map
(
FSL_Clk => PLB_Clk,
SYS_Rst => PLB_Rst,
FSL_Rst => open,
FSL_M_Clk => '0',
FSL_M_Data => HWTI2USERH_M_DATA,
FSL_M_Control => HWTI2USERH_M_CONTROL,
FSL_M_Write => HWTI2USERH_M_WRITE,
FSL_M_Full => HWTI2USERH_M_FULL,
FSL_S_Clk => '0',
FSL_S_Data => HWTI2USERH_S_DATA,
FSL_S_Control => HWTI2USERH_S_CONTROL,
FSL_S_Read => HWTI2USERH_S_READ,
FSL_S_Exists => HWTI2USERH_S_EXISTS,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
HWTI2USERL_M_DATA <= HWTI2USER_M_DATA(32 to 63);
HWTI2USERH_M_DATA <= HWTI2USER_M_DATA(0 to 31);
HWTI2USERL_M_CONTROL <= HWTI2USER_M_CONTROL;
HWTI2USERH_M_CONTROL <= HWTI2USER_M_CONTROL;
HWTI2USERL_M_WRITE <= HWTI2USER_M_WRITE;
HWTI2USERH_M_WRITE <= HWTI2USER_M_WRITE;
HWTI2USER_M_FULL <= HWTI2USERL_M_FULL or HWTI2USERH_M_FULL;
H2ULOW_S_DATA <= HWTI2USERL_S_DATA;
H2UHIGH_S_DATA <= HWTI2USERH_S_DATA;
H2ULOW_S_CONTROL <= HWTI2USERL_S_CONTROL;
H2UHIGH_S_CONTROL <= HWTI2USERH_S_CONTROL;
H2ULOW_S_EXISTS <= HWTI2USERL_S_EXISTS;
H2UHIGH_S_EXISTS <= HWTI2USERH_S_EXISTS;
HWTI2USERL_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
HWTI2USERH_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
USER2HWTIL_M_DATA <= U2HLOW_M_DATA;
USER2HWTIH_M_DATA <= U2HHIGH_M_DATA;
USER2HWTIL_M_CONTROL <= U2HLOW_M_CONTROL;
USER2HWTIH_M_CONTROL <= U2HHIGH_M_CONTROL;
USER2HWTIL_M_WRITE <= U2HLOW_M_WRITE;
USER2HWTIH_M_WRITE <= U2HHIGH_M_WRITE;
U2HLOW_M_FULL <= USER2HWTIL_M_FULL or USER2HWTIH_M_FULL;
U2HHIGH_M_FULL <= USER2HWTIL_M_FULL or USER2HWTIH_M_FULL;
USER2HWTI_S_DATA <= USER2HWTIH_S_DATA & USER2HWTIL_S_DATA;
USER2HWTI_S_CONTROL <= USER2HWTIL_S_CONTROL or USER2HWTIH_S_CONTROL;
USER2HWTI_S_EXISTS <= USER2HWTIL_S_EXISTS and USER2HWTIH_S_EXISTS;
USER2HWTIL_S_READ <= USER2HWTI_S_READ;
USER2HWTIH_S_READ <= USER2HWTI_S_READ;
--USER2HWTI_M_WRITE <= U2HLOW_M_WRITE and U2HHIGH_M_WRITE;
--USER2HWTI_M_DATA <= U2HLOW_M_DATA & U2HHIGH_M_DATA;
--USER2HWTI_M_CONTROL <= U2HLOW_M_CONTROL or U2HHIGH_M_CONTROL;
--USER2HWTI_M_FULL <= USER2HWTIH_M_FULL or USER2HWTIL_M_FULL;
--U2HLOW_M_FULL <= USER2HWTIL_M_FULL;
--U2HHIGH_M_FULL <= USER2HWTIH_M_FULL;
--HWTI2USER_S_READ <= H2ULOW_S_READ or H2UHIGH_S_READ;
--H2ULOW_S_DATA <= HWTI2USERL_S_DATA;
--H2ULOW_S_CONTROL <= HWTI2USERL_S_CONTROL;
--H2ULOW_S_EXISTS <= HWTI2USERL_S_EXISTS;
--H2UHIGH_S_DATA <= HWTI2USERH_S_DATA;
--H2UHIGH_S_CONTROL <= HWTI2USERH_S_CONTROL;
--H2UHIGH_S_EXISTS <= HWTI2USERH_S_EXISTS;
--USER2HWTIL_S_READ <= USER2HWTI_S_READ;
--USER2HWTIH_S_READ <= USER2HWTI_S_READ;
--USER2HWTI_S_DATA <= USER2HWTIH_S_DATA & USER2HWTIL_S_DATA;
--USER2HWTI_S_CONTROL <= USER2HWTIH_S_CONTROL or USER2HWTIL_S_CONTROL;
--USER2HWTI_S_EXISTS <= USER2HWTIH_S_EXISTS and USER2HWTIL_S_EXISTS;
--HWTI2USERH_M_WRITE <= HWTI2USER_M_WRITE;
--HWTI2USERL_M_WRITE <= HWTI2USER_M_WRITE;
--HWTI2USERH_M_DATA <= HWTI2USER_M_DATA(0 to 31);
--HWTI2USERL_M_DATA <= HWTI2USER_M_DATA(32 to 63);
--HWTI2USERH_M_CONTROL <= HWTI2USER_M_CONTROL;
--HWTI2USERL_M_CONTROL <= HWTI2USER_M_CONTROL;
--HWTI2USER_M_FULL <= HWTI2USERH_M_FULL or HWTI2USERL_M_FULL;
--HWTI2USER_S_READ <= FSL_S_READ;
--FSL_S_DATA <= HWTI2USER_S_DATA;
--FSL_S_CONTROL <= HWTI2USER_S_CONTROL;
--FSL_S_EXISTS <= HWTI2USER_S_EXISTS;
--USER2HWTI_M_WRITE <= FSL_M_WRITE;
--USER2HWTI_M_DATA <= FSL_M_DATA;
--USER2HWTI_M_CONTROL <= FSL_M_CONTROL;
--FSL_M_FULL <= USER2HWTI_M_FULL;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_RdCE(USER_NUM_SLAVE_CE to USER_NUM_CE-1) <= iBus2IP_RdCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
uBus2IP_WrCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_WrCE(USER_NUM_SLAVE_CE to USER_NUM_CE-1) <= iBus2IP_WrCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-3-clause | 924246d08ab90ae4c9368753166aeb62 | 0.51834 | 3.628508 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hvm_core_v1_00_a/hdl/vhdl/hvm_core.vhd | 2 | 4,127 | ----------------------------------------------------------------------------------
-- Written by Jason Agron
-- Summer '07
-- ******************************
-- Company:
-- Engineer:
--
-- Create Date: 15:25:12 12/22/2006
-- Design Name:
-- Module Name: hvm_core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISPM;
--use UNISPM.VComponents.all;
library hvm_core_v1_00_a;
use hvm_core_v1_00_a.all;
entity hvm_core is
port(
clk : in std_logic;
reset : in std_logic;
go : IN std_logic;
done : OUT std_logic;
mode : IN std_logic_vector(0 to 1);
debug_address : out std_logic_vector(0 to 31);
debug_data : out std_logic_vector(0 to 31);
BRAM_Clk_PM : out std_logic;
BRAM_EN_PM : out std_logic;
BRAM_WE_PM : out std_logic_vector(0 to 3);
BRAM_Addr_PM : out std_logic_vector(0 to 31);
BRAM_Din_PM : in std_logic_vector(0 to 31);
BRAM_Dout_PM : out std_logic_vector(0 to 31);
BRAM_Clk_SM : out std_logic;
BRAM_EN_SM : out std_logic;
BRAM_WE_SM : out std_logic_vector(0 to 3);
BRAM_Addr_SM : out std_logic_vector(0 to 31);
BRAM_Din_SM : in std_logic_vector(0 to 31);
BRAM_Dout_SM : out std_logic_vector(0 to 31)
);
end hvm_core;
architecture Behavioral of hvm_core is
COMPONENT interp
PORT(
prog_mem_dOUT0 : IN std_logic_vector(0 to 31);
state_mem_dOUT0 : IN std_logic_vector(0 to 31);
go : IN std_logic;
mode : IN std_logic_vector(0 to 1);
done : out std_logic;
clock_sig : IN std_logic;
reset_sig : IN std_logic;
prog_mem_addr0 : OUT std_logic_vector(0 to 31);
prog_mem_dIN0 : OUT std_logic_vector(0 to 31);
prog_mem_rENA0 : OUT std_logic;
prog_mem_wENA0 : OUT std_logic;
state_mem_addr0 : OUT std_logic_vector(0 to 7);
state_mem_dIN0 : OUT std_logic_vector(0 to 31);
state_mem_rENA0 : OUT std_logic;
state_mem_wENA0 : OUT std_logic
);
END COMPONENT;
SIGNAL prog_mem_dOUT0 : std_logic_vector(0 to 31);
SIGNAL state_mem_dOUT0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_addr0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_dIN0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_rENA0 : std_logic;
SIGNAL prog_mem_wENA0 : std_logic;
SIGNAL state_mem_addr0 : std_logic_vector(0 to 7);
SIGNAL state_mem_dIN0 : std_logic_vector(0 to 31);
SIGNAL state_mem_rENA0 : std_logic;
SIGNAL state_mem_wENA0 : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
uut: interp PORT MAP(
prog_mem_addr0 => prog_mem_addr0,
prog_mem_dIN0 => prog_mem_dIN0,
prog_mem_dOUT0 => prog_mem_dOUT0,
prog_mem_rENA0 => prog_mem_rENA0,
prog_mem_wENA0 => prog_mem_wENA0,
state_mem_addr0 => state_mem_addr0,
state_mem_dIN0 => state_mem_dIN0,
state_mem_dOUT0 => state_mem_dOUT0,
state_mem_rENA0 => state_mem_rENA0,
state_mem_wENA0 => state_mem_wENA0,
go => go,
done => done,
mode => mode,
clock_sig => clk,
reset_sig => reset
);
-- Old method (before done was internal to the interpreter)
-- done <= '1' when prog_mem_addr0 = x"FFFFFFFF" else '0';
-- Hook up debug interface
debug_address <= prog_mem_addr0;
debug_data <= prog_mem_dOUT0;
-- Connect up PM BRAM interface
BRAM_Clk_PM <= clk;
BRAM_EN_PM <= prog_mem_rENA0;
BRAM_WE_PM <= prog_mem_wENA0 & prog_mem_wENA0 & prog_mem_wENA0 & prog_mem_wENA0;
BRAM_Addr_PM <= prog_mem_addr0;
prog_mem_dOUT0 <= BRAM_Din_PM;
BRAM_Dout_PM <= prog_mem_dIN0;
-- Connect up SM BRAM interface
BRAM_Clk_SM <= clk;
BRAM_EN_SM <= state_mem_rENA0;
BRAM_WE_SM <= state_mem_wENA0 & state_mem_wENA0 & state_mem_wENA0 & state_mem_wENA0;
BRAM_Addr_SM <= x"00000" & "00" & state_mem_addr0 & "00"; -- Make addresses word addressable
state_mem_dOUT0 <= BRAM_Din_SM;
BRAM_Dout_SM <= state_mem_dIN0;
end Behavioral;
| bsd-3-clause | 4cbafb4355f64ecd37b199bb298f897a | 0.634359 | 2.711564 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd | 2 | 15,898 | -------------------------------------------------------------------------------
-- $Id: muxf_struct_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** license agreement with Xilinx, Inc. Xilinx hereby **
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-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: muxf_struct_f.vhd
--
-- Description: Given a vector of input bits, Iv (not necessarily a
-- power of two). and a select value, Sel, this block
-- will build the multiplexing function
--
-- O <= Iv(Sel)
--
-- using the MUXF (MUXF5, MUXF6, etc.) primitives of
-- the target FPGA family, C_FAMILY, if possible and,
-- otherwise, using inferred multiplexers.
--
-- Since MUXF primitives are targeted, it is proper
-- that the Iv signals are driven by LUTs.
--
-- A help entity, muxf_struct, which is instantiated
-- recursively, is used to facilitate the implementation.
-- (So, compiling this file will add two entities,
-- muxf_struct and muxf_struct_f, to the target library.)
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- muxf_struct_f.vhd
-- muxf_struct (entity and architecture in this file)
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
--------------------------------------------------------------------------------
-- This is a helper entity. The entity declaration for muxf_struct_f is
-- further, below.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
use proc_common_v3_00_a.family_support.all; -- supported, primitives_type
library unisim;
entity muxf_struct is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_NI_PO2E : positive; -- Num Inputs, Power-of-2 Envelope
C_FAMILY : string
);
port (
LO : out std_logic; -- Normally only one of
O : out std_logic; -- LO or O would be used.
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NI_PO2E)-1)
);
end entity muxf_struct;
library proc_common_v3_00_a;
library unisim;
use unisim.all; -- Makes unisim entities available for default binding.
--------------------------------------------------------------------------------
-- Line-length guideline purposely not followed in some places to expose parallel code structures.
--------------------------------------------------------------------------------
architecture imp of muxf_struct is
--
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
constant SIZE : natural := Iv'length;
constant PO2E : natural := C_NI_PO2E;
constant THIS_LEVEL : natural := C_START_LEVEL + clog2(PO2E);
constant K_FAMILY : families_type := str2fam(C_FAMILY);
constant S5 : boolean := supported(K_FAMILY, u_MUXF5_D) and THIS_LEVEL = 5;
constant S6 : boolean := supported(K_FAMILY, u_MUXF6_D) and THIS_LEVEL = 6;
constant S7 : boolean := supported(K_FAMILY, u_MUXF7_D) and THIS_LEVEL = 7;
constant S8 : boolean := supported(K_FAMILY, u_MUXF8_D) and THIS_LEVEL = 8;
constant INFERRED : boolean := not(S5 or S6 or S7 or S8);
--
signal s, i0, i1 : std_logic; -- If there is no i1 at a particular mux level,
-- it is left undriven and s is tied to '0'.
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF6_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF7_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF8_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Below, some generates and component instantiations are one per line
-- to show similarities and differences.
----------------------------------------------------------------------------
-- Base instance, just one or two inputs, no recursion.
----------------------------------------------------------------------------
E2_GEN : if PO2E=2 and SIZE=2 generate s <= Sel(0); i0 <= Iv(0); i1 <= Iv(1); end generate;
E1_GEN : if PO2E=2 and SIZE=1 generate s <= '0'; i0 <= Iv(0); end generate;-- No driver for i1
----------------------------------------------------------------------------
-- Use recursion to get lower-level mux structures to feed the mux at
-- this level.
----------------------------------------------------------------------------
GT2_GEN : if PO2E > 2 generate
constant NE : natural := PO2E/2; -- Next envelope.
constant BOTH : boolean := (SIZE > NE); -- Needs recursive call for
-- both the left and right sides; otherwise just a left-side
-- recursive call is needed (with C_NI_PO2E reduced by half) and Iv
-- passed down unchanged.
constant LSIZE : natural := bo2na(BOTH) * (2**(clog2(SIZE))/2)
+ bo2na(not BOTH) * SIZE;
-- 1st option above: LSIZE is next smaller power of 2
-- 2nd option above: SIZE is passed down unchanged
begin
LEFT_GEN : IF true generate
I_I0 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i0,
O => open,
Iv => Iv(0 to LSIZE-1),
Sel => Sel(1 to Sel'right)
)
;
end generate;
RIGHT_GEN : IF BOTH generate
I_I1 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => SIZE-LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i1,
O => open,
Iv => Iv(LSIZE to SIZE-1),
Sel => Sel(1 to Sel'right)
)
;
s <= Sel(0);
end generate;
LEFT_ONLY_GEN : IF not BOTH generate
s <= '0';
end generate;
end generate;
-- Instantiate the mux at this level.
--
-- Structurals
S5_GEN : if S5 generate I_F5 : component MUXF5_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S6_GEN : if S6 generate I_F6 : component MUXF6_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S7_GEN : if S7 generate I_F7 : component MUXF7_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S8_GEN : if S8 generate I_F8 : component MUXF8_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
-- Inferred
INFERRED_GEN : if INFERRED generate
signal h : std_logic;
begin
h <= i0 when s = '0' else i1 ;
LO <= h;
O <= h;
END generate;
end architecture imp;
---)
---(
--------------------------------------------------------------------------------
-- Generic descriptions
--------------------------------------------------------------------------------
-- C_START_LEVEL : natural - The size of the LUTs feeding into MUXFN network.
-- For example, for six-input LUTs,
-- C__START_LEVEL = 6 and the first level of muxes
-- are MUXF7.
-- C_NUM_INPUTS : positive - The number of inputs to be muxed.
-- C_FAMILY : string - The target FPGA family.
--------------------------------------------------------------------------------
-- Port descriptions
--------------------------------------------------------------------------------
-- O : out std_logic - Mux ouput
-- Iv : in std_logic_vector(0 to C_NUM_INPUTS-1) - Mux inputs
-- Sel: in std_logic_vector(0 to log2(C_NUM_INPUTS) - 1) - Select lines.
-- - The Iv values must be ordered such that the correct
-- - one is selected according to O <= Iv(Sel).
--------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
--
entity muxf_struct_f is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_FAMILY : string
);
port (
O : out std_logic;
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NUM_INPUTS) - 1)
);
end muxf_struct_f;
architecture imp of muxf_struct_f is
begin
MUXF_STRUCT_I : entity proc_common_v3_00_a.muxf_struct
generic map (
C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => C_NUM_INPUTS,
C_NI_PO2E => 2**clog2(C_NUM_INPUTS),
C_FAMILY => C_FAMILY
)
port map (
LO => open,
O => O,
Iv => Iv,
Sel => Sel
);
end imp;
---)
| bsd-3-clause | 420ff8fc111d71eace426447e0a0bf22 | 0.441565 | 4.574964 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd | 2 | 12,734 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| bsd-3-clause | af463f20ec9f72dd89b9d8a84a72945b | 0.414402 | 5.560699 | false | false | false | false |
jevinskie/aes-over-pcie | source/state_filter_out_p.vhd | 1 | 1,761 | -- File name: state_filter_out_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel state_filter_out
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_filter_out_p is
port (
current_state : in state_type;
sub_bytes_out : in state_type;
shift_rows_out : in state_type;
mix_columns_out : in state_type;
add_round_key_out : in state_type;
load_out : in byte;
subblock : in subblock_type;
i : in g_index;
next_state : out state_type
);
end entity state_filter_out_p;
architecture mux of state_filter_out_p is
begin
process(current_state, sub_bytes_out, shift_rows_out,
mix_columns_out, add_round_key_out, load_out, subblock, i)
begin
next_state <= current_state;
case subblock is
when identity =>
-- already selected
when sub_bytes =>
next_state <= sub_bytes_out;
when shift_rows =>
next_state <= shift_rows_out;
when mix_columns =>
next_state <= mix_columns_out;
when add_round_key =>
next_state <= add_round_key_out;
when load_pt =>
for x in index loop
for y in index loop
if (x + y * 4 = i) then
next_state(x, y) <= load_out;
end if;
end loop;
end loop;
when store_ct =>
-- already selected
when others =>
-- already selected
end case;
end process;
end architecture mux;
| bsd-3-clause | b28709ec66b39181d42ab95e561862ee | 0.531516 | 3.762821 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd | 2 | 18,833 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause | 8f0a94332cb939f3c5d009a3b031cda1 | 0.411034 | 3.644862 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/ethtx_task/ethtx_task.vhd | 1 | 5,282 | ---------------------------------------------------------------------------------------------------
--
-- Title : ethtx_task
-- Design : eth_new
-- Author : lihf
-- Company : wireless
--
---------------------------------------------------------------------------------------------------
--
-- File : ethtx_task.vhd
-- Generated : Tue Aug 29 10:23:40 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ethtx_task} architecture {arch_ethtx_task}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethtx_task is
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end ethtx_task;
--}} End of automatically maintained section
architecture arch_ethtx_task of ethtx_task is
component fifo_block
generic(
DWIDTH : INTEGER;
BLOCK_AWIDTH : INTEGER;
FIFO_AWIDTH : INTEGER;
RAM_TYPE : STRING
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component fifo2zcpsm
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_rd_block : out std_logic;
fifo_raddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_rdata : in std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_raddr : std_logic_vector(TASKFIFO_BLOCK_AWIDTH - 1 downto 0);
signal fifo_rdata : std_logic_vector(TASKFIFO_DWIDTH - 1 downto 0);
signal fifo_rd_block : std_logic;
begin
u_task_fifo : fifo_block
generic map(
DWIDTH => TASKFIFO_DWIDTH,
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
FIFO_AWIDTH => TASKFIFO_AWIDTH,
RAM_TYPE => TASKFIFO_RAM_TYPE
)
port map(
clk => TxFIFO_W_Clk,
reset => reset,
clr => TxFIFO_Clr,
wr_block => TxFIFO_W_Block,
wr_clk => TxFIFO_W_Clk,
wren => TxFIFO_WE,
waddr => TxFIFO_WAddr,
wdata => TxFIFO_WData,
rd_block => fifo_rd_block,
rd_clk => zcpsm_clk,
raddr => fifo_raddr,
rdata => fifo_rdata,
empty => fifo_empty,
full => fifo_full
);
u_zcpsm_task : fifo2zcpsm
generic map(
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
DWIDTH => TASKFIFO_DWIDTH
)
port map(
clk => TxFIFO_W_Clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
fifo_rd_block => fifo_rd_block,
fifo_raddr => fifo_raddr,
fifo_rdata => fifo_rdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
TxFIFO_Full <= fifo_full;
TxFIFO_Empty <= fifo_empty;
-- enter your statements here --
end arch_ethtx_task;
| gpl-2.0 | e5a7716e6f9a79578a6a9e522b9e34f4 | 0.527452 | 3.042627 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_slave_attach_burst.vhd | 2 | 60,028 | -------------------------------------------------------------------------------
-- $Id: xbic_slave_attach_burst.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_slave_attach_burst.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_slave_attach_burst.vhd
-- Version: v1_00_a
-- Description: Custom PLB slave attachment supporting only PLB single
-- beat transfers.
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- xbic_slave_attach_burst.vhd
-- |
-- |- xbic_addr_be_support
-- |- xbic_addr_decode
-- |- xbic_be_reset_gen.vhd
-- |- xbic_addr_reg_cntr_brst_flex.vhd
-- |-- xbic_flex_addr_cntr.vhd
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET Feb-9-07
-- ~~~~~~
-- -- Custom Slave Attachment version for the XPS BRAM IF Cntlr
-- -- Bypassed input address and qualifiers registering to remove
-- one clock of latency during address phase.
-- -- Optimized for PLBV46 Performance op mode.
-- ^^^^^^
--
-- DET 5/1/2007 Update for Jm
-- ~~~~~~
-- - Corrected a bug that caused a spurious Sl_wrBTerm to be generated if
-- Fixed Length Burst Write of 2 data beats was on the PLB but not
-- addressed to the XPS BRAM IF Cntlr addresss space.
-- ^^^^^^
--
-- DET 5/16/2007 Jm
-- ~~~~~~
-- - Revamped qualifier validation and address decoding to improve Fmax
-- in Spartan devices.
-- ^^^^^^
--
-- DET 6/8/2007 jm.10
-- ~~~~~~
-- - Zeroed out the MSBit of the Sl_rdwdaddr(0:3) bus since 16 word
-- cachelines are not supported.
-- ^^^^^^
--
-- DET 6/13/2007 Jm.10
-- ~~~~~~
-- - More Fmax optimizations.
-- - Had to remove indeterminate burst screening from request validation
-- to meet 99MHz in Spartan
-- ^^^^^^
--
-- DET 6/25/2007 Jm.11
-- ~~~~~~
-- - Added Sl_rearbitrate_i to clear condition of sig_force_wrbterm flop
-- im each of the 32-bit, 64-bit, and 128-bit generates.
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a library reference.
-- - Updated this core's library reference to v1_00_b.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_type"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
library xps_bram_if_cntlr_v1_00_b;
use xps_bram_if_cntlr_v1_00_b.xbic_addr_be_support;
use xps_bram_if_cntlr_v1_00_b.xbic_addr_decode;
use xps_bram_if_cntlr_v1_00_b.xbic_be_reset_gen;
Use xps_bram_if_cntlr_v1_00_b.xbic_addr_cntr; -- new for timing debug
Use xps_bram_if_cntlr_v1_00_b.xbic_dbeat_control;
use xps_bram_if_cntlr_v1_00_b.xbic_data_steer_mirror;
-------------------------------------------------------------------------------
entity xbic_slave_attach_burst is
generic (
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_type :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF" -- IP user0 high address
);
C_SPLB_NUM_MASTERS : integer := 4;
C_SPLB_MID_WIDTH : integer := 2;
C_SPLB_P2P : integer Range 0 to 1 := 0;
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : Integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_SMALLEST_MASTER : Integer := 32;
C_CACHLINE_ADDR_MODE : Integer range 0 to 1 := 0;
C_FAMILY : string := "virtex4"
);
port(
--System signals
Bus_Rst : in std_logic;
Bus_Clk : in std_logic;
-- PLB Bus signals
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector
(0 to C_SPLB_MID_WIDTH - 1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector
(0 to (C_SPLB_DWIDTH/8)-1);
PLB_Msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Controls to the IP/IPIF modules
Bus2Bram_CS : out std_logic;
Bus2Bram_WrReq : out std_logic;
Bus2Bram_RdReq : out std_logic;
Bus2Bram_Addr : out std_logic_vector (0 to C_SPLB_AWIDTH-1);
Bus2Bram_BE : out std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH/8-1);
Bus2Bram_WrData : out std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH-1);
-- Inputs from the BRAM interface logic
Bram2Bus_RdData : in std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH-1);
Bram2Bus_WrAck : in std_logic;
Bram2Bus_RdAck : in std_logic
);
end entity xbic_slave_attach_burst;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture implementation of xbic_slave_attach_burst is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- Functions Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: encode_slave_size
--
-- Function Description:
-- This function encodes the Slave Native Data Width into
-- a 2-bit field for PLB_Ssize output.
--
-------------------------------------------------------------------
function encode_slave_size(native_dwidth : integer)
return std_logic_vector is
variable temp_size : std_logic_vector(0 to 1);
begin
case native_dwidth is
when 64 =>
temp_size := "01"; -- 64 bits wide
when 128 =>
temp_size := "10"; -- 128 bits wide
when others =>
temp_size := "00"; -- 32 bits wide
end case;
Return(temp_size);
end function encode_slave_size;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Fix the Slave Size response to the PLB DBus width
-- note "00" = 32 bits wide
-- "01" = 64 bits wide
-- "10" = 128 bits wide
constant SLAVE_SIZE : std_logic_vector(0 to 1) :=
encode_slave_size(C_SPLB_NATIVE_DWIDTH);
Constant STEER_ADDR_SIZE : integer := 6;
-------------------------------------------------------------------------------
-- Signal and type Declarations
-------------------------------------------------------------------------------
-- Intermediate Slave Replyut signals (to PLB)
signal sl_addrack_i : std_logic;
signal sl_wait_i : std_logic;
signal sl_rearbitrate_i : std_logic;
signal sl_wrdack_i : std_logic;
signal sl_wrcomp_i : std_logic;
signal sl_wrbterm_i : std_logic;
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
signal sl_rdwdaddr_i : std_logic_vector(0 to 3);
signal sl_rddack_i : std_logic;
signal sl_rdcomp_i : std_logic;
signal sl_rdbterm_i : std_logic;
signal sl_mbusy_i : std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
signal bus2ip_cs_i : std_logic;
signal bus2ip_wrreq_i : std_logic;
signal bus2ip_rdreq_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_be_i : std_logic_vector(0 to (C_SPLB_NATIVE_DWIDTH/8)-1);
signal bus2ip_data_i : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rddata_i : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal valid_plb_type : boolean := False;
signal valid_plb_size : Boolean := False;
signal single_transfer : std_logic;
signal cacheln_transfer : std_logic;
signal burst_transfer : std_logic;
signal indeterminate_burst : std_logic;
signal sig_valid_request : std_logic;
signal sig_good_request : std_logic;
signal sig_internal_be : std_logic_vector(0 to (C_SPLB_NATIVE_DWIDTH/8)-1);
signal sig_combined_abus : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal sig_steer_addr : std_logic_vector(0 to STEER_ADDR_SIZE-1);
signal sig_steer_addr_reg : std_logic_vector(0 to STEER_ADDR_SIZE-1);
signal sig_addr_decode_hit : std_logic;
signal sig_clr_addrack : std_logic;
signal sig_sl_busy : std_logic;
signal sig_clear_sl_busy : std_logic;
signal sig_set_sl_busy : std_logic;
Signal sig_clr_rearbitrate : std_logic;
signal rearb_condition : std_logic;
signal not_rearb_condition : std_logic;
signal wait_condition : std_logic;
Signal sig_clr_wait : std_logic;
signal sig_do_cmd : std_logic;
signal sig_do_cmd_reg : std_logic;
signal sig_clr_qualifiers : std_logic;
signal sig_mst_id : std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
signal sig_mst_id_int : integer range 0 to C_SPLB_NUM_MASTERS-1 := 0;
signal sig_rd_dreg : std_logic_vector(0 to C_SPLB_DWIDTH-1);
signal sig_rd_data_mirror_steer : std_logic_vector(0 to C_SPLB_DWIDTH-1);
signal sig_rd_data_128 : std_logic_vector(0 to 127);
Signal sig_wr_req : std_logic;
Signal sig_ld_wr_dreg : std_logic;
signal sig_wr_dreg : std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
Signal sig_wr_req_reg : std_logic;
Signal sig_rd_req_reg : std_logic;
signal sig_clr_rdack : std_logic;
signal sig_plb_done : std_logic;
signal sig_xfer_done : std_logic;
signal sig_xfer_done_dly1 : std_logic;
signal sig_xfer_almost_done : std_logic;
signal sig_ld_addr_cntr : std_logic;
signal sig_combined_dack : std_logic;
-- Signal sig_be_mask : std_logic_vector(0 to
-- (C_SPLB_NATIVE_DWIDTH/32) - 1);
Signal sig_internal_wrdack : std_logic;
Signal sig_internal_rddack : std_logic;
signal sig_clear_rdack_erly1 : std_logic;
Signal sig_internal_rddack_early1 : std_logic;
signal sig_clear_rdack_erly2 : std_logic;
Signal sig_internal_rddack_early2 : std_logic;
signal sig_rdcomp_erly : std_logic;
signal sig_clr_rdcomp : std_logic;
signal sig_clear_wrack : std_logic;
signal sig_clear_rdack : std_logic;
signal doing_flburst_reg : std_logic;
signal doing_single_reg : std_logic;
signal doing_cacheln_reg : std_logic;
signal sig_force_wrbterm : std_logic;
signal sig_init_db_cntr : std_logic;
signal sig_clr_wrreq : std_logic;
signal sig_clear_wrack_dly1 : std_logic;
--signal sig_cmd_done : std_logic;
signal sig_clr_rdbterm : std_logic;
signal sig_set_rdbterm : std_logic;
signal sig_cline_spec_1dbeat_case : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
------------------------------------------------------------------
-- Misc. Logic Assignments
------------------------------------------------------------------
-- PLB Output port connections
Sl_addrAck <= sl_addrack_i ;
Sl_wait <= sl_wait_i ;
Sl_rearbitrate <= sl_rearbitrate_i ;
Sl_wrDAck <= sl_wrdack_i ;
Sl_wrComp <= sl_wrcomp_i ;
Sl_wrBTerm <= sl_wrbterm_i ;
Sl_rdDBus <= sl_rddbus_i ;
Sl_rdWdAddr <= sl_rdwdaddr_i ;
Sl_rdDAck <= sl_rddack_i ;
Sl_rdComp <= sl_rdcomp_i ;
Sl_rdBTerm <= sl_rdbterm_i ;
Sl_MBusy <= sl_mbusy_i ;
Sl_MRdErr <= (others => '0') ;
Sl_MWrErr <= (others => '0') ;
Sl_SSize <= SLAVE_SIZE
when (sig_set_sl_busy = '1')
Else "00";
sl_rddbus_i <= sig_rd_dreg;
sl_wrcomp_i <= sig_xfer_done and
sig_wr_req_reg;
sl_wrbterm_i <= (sig_force_wrbterm and
sig_set_sl_busy) or
(doing_flburst_reg and
sig_wr_req_reg and
sig_xfer_almost_done);
-- Backend output signals
Bus2Bram_CS <= bus2ip_cs_i ;
Bus2Bram_WrReq <= bus2ip_wrreq_i ;
Bus2Bram_RdReq <= bus2ip_rdreq_i ;
Bus2Bram_Addr <= bus2ip_addr_i ;
Bus2Bram_BE <= bus2ip_be_i ;
Bus2Bram_WrData <= bus2ip_data_i ;
-- Backend input signals
ip2bus_wrack_i <= Bram2Bus_WrAck ;
ip2bus_rdack_i <= Bram2Bus_RdAck ;
ip2bus_rddata_i <= Bram2Bus_RdData ;
bus2ip_data_i <= sig_wr_dreg;
bus2ip_rdreq_i <= sig_rd_req_reg;
-- Fmax mod to remove address decode from validation path
-- --sig_do_cmd <= (sig_addr_decode_hit and
-- Fmax Mod to simplify implimentation
-- sig_do_cmd <= (sig_good_request and
-- not(sig_sl_busy)) or
-- --(sig_addr_decode_hit and
-- (sig_good_request and
-- sig_clear_sl_busy);
-- Fmax Mod to simplify implimentation
-- Maybe this is better for implementation tools and Fmax ?
sig_do_cmd <= sig_good_request and sig_clear_sl_busy
When sig_sl_busy = '1'
Else sig_good_request;
sig_mst_id_int <= CONV_INTEGER(sig_mst_id);
sig_clr_qualifiers <= sig_clear_sl_busy and
not(sig_do_cmd);
sig_combined_dack <= bus2ip_wrreq_i or
sig_internal_rddack_early2;
-- Rearbitrate if
-- - another address hit occurs
-- - and the slave attach is busy
-- - and the current command is not nearing completion
--rearb_condition <= sig_addr_decode_hit and
rearb_condition <= sig_good_request and
sig_sl_busy and
not(sig_clear_sl_busy or
sig_xfer_almost_done or
sig_xfer_done);
not_rearb_condition <= not(rearb_condition or
sl_rearbitrate_i);
-- Rearbitrate FLOP
sig_clr_rearbitrate <= Bus_Rst or
sl_rearbitrate_i;
I_FLOP_REARB : FDRE
port map(
Q => sl_rearbitrate_i ,
C => Bus_clk ,
CE => rearb_condition ,
D => '1' ,
R => sig_clr_rearbitrate
);
-- Wait FLOP
--GAB --wait_condition <= sig_addr_decode_hit
--GAB wait_condition <= sig_good_request
--GAB and sig_sl_busy and
--GAB not(sig_clear_sl_busy);
--GAB
--GAB sig_clr_wait <= Bus_Rst or
--GAB sig_set_sl_busy or
--GAB sl_rearbitrate_i;
--GAB
--GAB I_FLOP_WAIT : FDRE
--GAB port map(
--GAB Q => sl_wait_i ,
--GAB C => Bus_clk ,
--GAB CE => wait_condition ,
--GAB D => '1' ,
--GAB R => sig_clr_wait
--GAB );
--GAB TEMP
sl_wait_i <= '0';
-- Address Acknowledge Flops (incorporates register duplication)
sig_clr_addrack <= Bus_Rst or
sig_set_sl_busy or
(sig_sl_busy and
not(sig_clear_sl_busy));
I_FLOP_ADDRACK : FDRE
port map(
Q => sl_addrack_i ,
C => Bus_clk ,
CE => sig_do_cmd ,
--D => '1' ,
D => not_rearb_condition,
R => sig_clr_addrack
);
I_FLOP_SET_SLBUSY : FDRE
port map(
Q => sig_set_sl_busy,
C => Bus_clk ,
CE => sig_do_cmd ,
--D => '1' ,
D => not_rearb_condition,
R => sig_clr_addrack
);
sig_plb_done <= (sig_xfer_done and
sig_internal_wrdack) or
(sig_xfer_done and
sig_internal_rddack_early1);
I_FLOP_CLR_SL_BUSY : FDRE
port map(
Q => sig_clear_sl_busy,
C => Bus_clk ,
CE => sig_plb_done ,
D => '1' ,
R => sig_clear_sl_busy
);
------------------------------------------------------------
-- Instance: I_ADDR_BE_SUPRT
--
-- Description:
-- This instantiates the address and be support module.
--
------------------------------------------------------------
I_ADDR_BE_SUPRT : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_be_support
generic map (
C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
-- Inputs from PLB
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus ,
PLB_BE => PLB_BE ,
PLB_Msize => PLB_Msize,
-- Outputs to Internal logic
Internal_ABus => sig_combined_abus,
Internal_BE => sig_internal_be
);
----------------------------------------------------------------
-- PLB Size Validation
-- This combinatorial process validates the PLB request
-- attribute PLB_Size that is supported by this slave.
--
-- Unsupported transfers are:
-- Indeterminate length bursts
-- Fixed length Bursts of byte width
-- Fixed length bursts of half word width
-- Cacheline 16
----------------------------------------------------------------
VALIDATE_SIZE : process (PLB_Size)
begin
case PLB_Size is
-- single data beat transfer
when "0000" => -- one to eight bytes
valid_plb_size <= true;
single_transfer <= '1';
cacheln_transfer <= '0';
burst_transfer <= '0';
-- cacheline transfer
when "0001" | -- 4 word cache-line
"0010" => -- 8 word cache-line
valid_plb_size <= true;
single_transfer <= '0';
cacheln_transfer <= '1';
burst_transfer <= '0';
-- burst transfer (fixed length)
when "1010" | -- word burst transfer
"1011" | -- double word burst transfer
"1100" => -- quad word burst transfer
valid_plb_size <= true;
single_transfer <= '0';
cacheln_transfer <= '0';
burst_transfer <= '1';
when others =>
valid_plb_size <= false;
single_transfer <= '0';
cacheln_transfer <= '0';
burst_transfer <= '0';
end case;
end process VALIDATE_SIZE;
-------------------------------------------------------------------------------
-- PLB Size Validation
-- This combinatorial process validates the PLB request attribute PLB_type
-- that is supported by this slave.
-------------------------------------------------------------------------------
VALIDATE_type : process (PLB_type)
begin
if(PLB_type="000")then
valid_plb_type <= true;
else
valid_plb_type <= false;
end if;
end process VALIDATE_type;
-------------------------------------------------------------------------------
-- Indeterminate Burst
-- This slave attachment does NOT support indeterminate burst. Cycles which
-- are determined to be indeterminate will not be responded to by this slave.
-- Note that PLBV46 simplificatons require that only BE(0 to 3) be monitored
-- because fixed length burst data beat counts cannot exceed 16.
-------------------------------------------------------------------------------
VALIDATE_BURST : process (--burst_transfer,
PLB_BE,
PLB_Size)
--sig_internal_be)
begin
--if (burst_transfer = '1' and
if (PLB_Size(0) = '1' and
--sig_internal_be(0 to 3) = "0000") then -- indetirminate burst
PLB_BE(0 to 3) = "0000") then -- indetirminate burst
indeterminate_burst <= '1';
else
indeterminate_burst <= '0';
end if;
end process VALIDATE_BURST;
-------------------------------------------------------------------------------
-- Access Validation
-- This combinatorial process validates the PLB request attributes that are
-- supported by this slave.
-------------------------------------------------------------------------------
VALIDATE_REQUEST : process (PLB_PAvalid,
valid_plb_size,
valid_plb_type) --,
--indeterminate_burst)
begin
-- temp DET if (PLB_PAvalid = '1') and -- Address Request
-- temp DET (valid_plb_size) and -- a valid plb_size
-- temp DET (valid_plb_type) and -- a valid plb type
-- temp DET (indeterminate_burst = '0') then -- and a memory xfer
-- temp DET
-- temp DET sig_valid_request <= '1';
-- temp DET
-- temp DET else
-- temp DET
-- temp DET sig_valid_request <= '0';
-- temp DET
-- temp DET end if;
if (PLB_PAvalid = '1' and -- Address Request
valid_plb_size and -- a valid plb_size
valid_plb_type) then -- a valid plb type
sig_valid_request <= '1';
else
sig_valid_request <= '0';
end if;
end process VALIDATE_REQUEST;
------------------------------------------------------------
-- If Generate
--
-- Label: P2P_MODE_ENABLED
--
-- If Generate Description:
-- P2P Mode enabled so this IfGen removes the Address
-- Decoding function.
--
--
------------------------------------------------------------
P2P_MODE_ENABLED : if (C_SPLB_P2P = 1) generate
begin
sig_good_request <= sig_valid_request and
not(indeterminate_burst);
-- Address Decoder Removed in P2P mode
--sig_addr_decode_hit <= sig_valid_request;
end generate P2P_MODE_ENABLED;
------------------------------------------------------------
-- If Generate
--
-- Label: SHARED_MODE_ENABLED
--
-- If Generate Description:
-- Shared bus mode so include Address Decoder.
--
--
------------------------------------------------------------
SHARED_MODE_ENABLED : if (C_SPLB_P2P = 0) generate
begin
sig_good_request <= sig_addr_decode_hit and
sig_valid_request and
not(indeterminate_burst);
-------------------------------------------------------------------
-- Address Decoder Component Instance
-- This component decodes the specified base address pair and
-- outputs the decode hit indication.
-------------------------------------------------------------------
I_ADDR_DECODER : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_decode
generic map(
C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_FAMILY => C_FAMILY
)
port map(
-- PLB Interface signals
Address_In => sig_combined_abus,
--Address_Valid => sig_valid_request,
Address_Valid => PLB_PAValid,
-- Decode output signals
Addr_Match => sig_addr_decode_hit
);
end generate SHARED_MODE_ENABLED;
---------------------------------------------------------------------
-- Generate the Slave Busy
-- This process implements the FLOP that indicates the Slave is Busy
-- with a command. The output of the FLOP is used internally.
---------------------------------------------------------------------
GENERATE_SL_BUSY : process (Bus_clk)
begin
if (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus_Rst = '1' or
sig_clear_sl_busy = '1') then
sig_sl_busy <= '0';
elsif (sig_set_sl_busy = '1') Then
sig_sl_busy <= '1';
else
null; -- hold current state
end if;
end if;
end process GENERATE_SL_BUSY;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_SL_MBUSY
--
-- Process Description:
-- This process implements the flops that drive the SL_MBusy
-- to the PLB. There is one FLOP per Master.
--
-------------------------------------------------------------
DO_SL_MBUSY : process(Bus_clk)
begin
if (Bus_clk'EVENT and Bus_clk = '1') Then
for i in 0 to C_SPLB_NUM_MASTERS - 1 loop
if (Bus_Rst = '1') then
sl_mbusy_i(i) <= '0';
elsif (i=sig_mst_id_int)then
if (sig_set_sl_busy = '1') Then
sl_mbusy_i(i) <= '1'; -- set specific bit for req master
elsif (sig_clear_sl_busy = '1') Then
sl_mbusy_i(i) <= '0'; -- clear specific bit for req master
end if;
else
sl_mbusy_i(i) <= '0';
end if;
end loop;
end if;
end process DO_SL_MBUSY;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_XFER_QUALIFIERS
--
-- Process Description:
-- This process implements the register that samples and holds
-- the command qualifiers
--
-------------------------------------------------------------
REG_XFER_QUALIFIERS : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
sig_clr_qualifiers = '1') then
bus2ip_cs_i <= '0';
sig_wr_req_reg <= '0';
sig_rd_req_reg <= '0';
sig_mst_id <= (others => '0');
doing_flburst_reg <= '0';
doing_single_reg <= '0';
doing_cacheln_reg <= '0';
elsif (sig_do_cmd = '1') then
bus2ip_cs_i <= '1';
sig_wr_req_reg <= not(PLB_RNW);
sig_rd_req_reg <= PLB_RNW;
sig_mst_id <= PLB_masterID;
doing_flburst_reg <= burst_transfer;
doing_single_reg <= single_transfer;
doing_cacheln_reg <= cacheln_transfer;
else
null; -- hold state
end if;
end if;
end process REG_XFER_QUALIFIERS;
-- -------------------------------------------------------------------------------
-- -- BE Reset Generator
-- -- The following entity generates a mask for inhibiting mirrored BE's.
-- -- The BE's of smaller masters are mirrored to the upper byte lanes
-- -- so based on the master's size and the address presented, all un-needed
-- -- BE's are cleared in the address counter at qualifier load time.
-- -- Otherwise, single data beat write requests from smaller Masters can corrupt
-- -- data in wider Slaves as a result of Mirrored BEs being set.
-- -------------------------------------------------------------------------------
-- BE_RESET_I : entity xps_bram_if_cntlr_v1_00_b.xbic_be_reset_gen
-- generic map(
-- C_DWIDTH => C_SPLB_NATIVE_DWIDTH,
-- C_AWIDTH => C_SPLB_AWIDTH,
-- C_SMALLEST => C_SPLB_SMALLEST_MASTER
-- )
-- port map(
-- Addr => sig_combined_abus,
-- MSize => PLB_Msize,
--
-- Reset_BE => sig_be_mask
-- );
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DO_CMD
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_DO_CMD : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
sig_clear_sl_busy = '1') then
sig_do_cmd_reg <= '0';
else
sig_do_cmd_reg <= sig_do_cmd;
end if;
end if;
end process REG_DO_CMD;
-- Fmax Mod to reduce serial timing paths
--sig_ld_addr_cntr <= (sig_do_cmd and
-- not(sig_set_sl_busy or sig_sl_busy)) or
-- (sig_do_cmd and sig_clear_sl_busy);
-- Fmax Mod to reduce serial timing paths
sig_ld_addr_cntr <= PLB_PAValid and sig_clear_sl_busy
When (sig_sl_busy = '1')
Else (PLB_PAValid and
not(sig_set_sl_busy));
-- -- Address Counter Clr
-- sig_cmd_done <= (sig_xfer_done_dly1 and
-- bus2ip_wrreq_i) or
-- -- (sig_xfer_almost_done and
-- -- sig_internal_wrdack) or
-- (sig_xfer_done and
-- sig_internal_rddack_early1);
------------------------------------------------------------
-- Instance: I_ADDR_CNTR
--
-- Description:
-- This instance incorporates the Address counter that is needed
-- during Burst and Cacheline transfers
--
------------------------------------------------------------
I_ADDR_CNTR : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_cntr
generic map (
C_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_CACHLINE_ADDR_MODE => C_CACHLINE_ADDR_MODE,
C_ADDR_CNTR_WIDTH => C_SPLB_AWIDTH ,
C_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_PLB_AWIDTH => C_SPLB_AWIDTH
)
port map (
-- Clock and Reset
Bus_Rst => Bus_Rst, -- : In std_logic;
Bus_clk => Bus_Clk, -- : In std_logic;
-- Inputs from Slave Attachment
Mstr_Size_in => PLB_MSize ,
PLB_Size_in => PLB_Size ,
PLB_RNW_in => PLB_RNW ,
Bus_Addr_in => sig_combined_abus ,
Addr_Load => sig_ld_addr_cntr ,
Addr_Cnt_en => sig_combined_dack ,
Qualifiers_Load => sig_ld_addr_cntr ,
BE_in => sig_internal_be ,
--Reset_BE => sig_be_mask ,
-- BE Outputs
BE_out => bus2ip_be_i ,
-- IPIF & IP address bus source (AMUX output)
Address_Out => bus2ip_addr_i
);
-- ------------------------------------------------------------
-- -- Instance: I_ADDR_CNTR
-- --
-- -- Description:
-- -- This instance incorporates the Address counter that is needed
-- -- during Burst and Cacheline transfers
-- --
-- ------------------------------------------------------------
-- I_ADDR_CNTR : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_reg_cntr_brst_flex
-- generic map (
-- C_CACHLINE_ADDR_MODE => C_CACHLINE_ADDR_MODE, -- : Integer range 0 to 1 := 0;
-- --C_SPLB_P2P => C_SPLB_P2P , -- : integer range 0 to 1 := 0;
-- C_SPLB_P2P => 1 , -- set to 1 to reduce address load latency
-- C_NUM_ADDR_BITS => C_SPLB_AWIDTH , -- : Integer := 32; -- bits
-- C_PLB_DWIDTH => C_SPLB_NATIVE_DWIDTH -- : Integer := 64 -- bits
-- )
-- port map (
-- -- Clock and Reset
-- Bus_reset => Bus_Rst, -- : In std_logic;
-- Bus_clk => Bus_Clk, -- : In std_logic;
--
--
-- -- Inputs from Slave Attachment
-- Single => single_transfer , -- : In std_logic;
-- Cacheln => cacheln_transfer , -- : In std_logic;
-- Burst => burst_transfer , -- : In std_logic;
-- S_H_Qualifiers => sig_ld_addr_cntr , -- : In std_logic;
-- Xfer_done => sig_cmd_done , -- : In std_logic;
-- Addr_Load => sig_ld_addr_cntr , -- : In std_logic;
-- Addr_Cnt_en => sig_combined_dack , -- : In std_logic;
-- Addr_Cnt_Size => PLB_Size , -- : In Std_logic_vector(0 to 3);
-- Addr_Cnt_Size_Erly => PLB_Size , -- : in std_logic_vector(0 to 3);
-- Mstr_SSize => PLB_MSize , -- : in std_logic_vector(0 to 1);
-- Address_In => sig_combined_abus , -- : in std_logic_vector(0 to C_NUM_ADDR_BITS-1);
-- BE_in => sig_internal_be , -- : In Std_logic_vector(0 to (C_PLB_DWIDTH/8)-1);
-- Reset_BE => sig_be_mask , -- : in std_logic_vector(0 to (C_PLB_DWIDTH/32) - 1);
--
-- -- BE Outputs
-- BE_out => bus2ip_be_i , -- : Out Std_logic_vector(0 to (C_PLB_DWIDTH/8)-1);
--
-- -- IPIF & IP address bus source (AMUX output)
-- Address_Out => bus2ip_addr_i -- : out std_logic_vector(0 to C_NUM_ADDR_BITS-1)
--
-- );
------------------------------------------------------------
-- Data beat controller logic
-- Fmax Mod to reduce serial timing paths
-- DET sig_init_db_cntr <= sig_do_cmd and
-- DET not(sig_set_sl_busy);
-- Fmax Mod to reduce serial timing paths
sig_init_db_cntr <= PLB_PAValid and sig_clear_sl_busy
When (sig_sl_busy = '1')
Else (PLB_PAValid and
not(sig_set_sl_busy));
------------------------------------------------------------
-- Instance: I_DBEAT_CONTROL
--
-- Description:
-- This HDL instantiates the data beat controller that
-- calculates the data acknowledges for the given request.
-- It outputs a done and almost done control flag that is
-- used to terminate Singles, Cachelines, and Fixed Length
-- Bursts at the appropriate timing needed for PLB protcol.
------------------------------------------------------------
I_DBEAT_CONTROL : entity xps_bram_if_cntlr_v1_00_b.xbic_dbeat_control
generic map (
-- Generics
C_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
-- Input ports
Bus_Rst => Bus_Rst ,
Bus_clk => Bus_Clk ,
-- Start Control
Req_Init => sig_init_db_cntr ,
-- Qualifiers
Doing_Single => single_transfer ,
Doing_Cacheline => cacheln_transfer ,
Doing_FLBurst => burst_transfer ,
RNW_In => PLB_RNW ,
--BE_In => sig_internal_be(0 to 3),
BE_In => PLB_BE(0 to 3) ,
Size_In => PLB_Size ,
MSize_In => PLB_Msize ,
-- Count Enables
Wr_DAck => sig_internal_wrdack,
Rd_DAck => sig_internal_rddack_early1,
-- Special Case Output signals
Cline_Spec_1DBeat_Case => sig_cline_spec_1dbeat_case,
-- Done State output signals
AlmostDone => sig_xfer_almost_done,
Done => sig_xfer_done
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_XFER_DONE
--
-- Process Description:
-- This process registers the Xfer done Flag to delay it by
-- one Bus Clk period.
--
-------------------------------------------------------------
REG_XFER_DONE : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_xfer_done_dly1 <= '0';
else
sig_xfer_done_dly1 <= sig_xfer_done;
end if;
end if;
end process REG_XFER_DONE;
------------------------------------------------------------
-- Write Acknowledge FLOP (WrAck is Same as Address Acknowledge signal)
-- Requires register duplication
sig_wr_req <= not(PLB_RNW) and
not_rearb_condition;
sig_clear_wrack <= Bus_Rst or
(sig_xfer_done and
sig_internal_wrdack);
sig_clr_wrreq <= Bus_Rst or
sig_clear_wrack_dly1;
-- Generate Wrack to the PLB
I_FLOP_WRACK_2BUS : FDRE
port map(
Q => sl_wrdack_i ,
C => Bus_clk ,
CE => sig_do_cmd ,
D => sig_wr_req ,
R => sig_clear_wrack
);
-- register duplication for internal Wrdack use
I_FLOP_WRACK : FDRE
port map(
Q => sig_internal_wrdack ,
C => Bus_clk ,
CE => sig_do_cmd ,
D => sig_wr_req ,
R => sig_clear_wrack
);
-- -- register duplication for internal Wrdack use
-- I_FLOP_CLR_WRREQ : FDRE
-- port map(
-- Q => sig_clear_wrack_dly1 ,
-- C => Bus_clk ,
-- CE => sig_do_cmd ,
-- D => sig_wr_req ,
-- R => sig_clear_wrack
-- );
-- Generate the Write Enable to the BRAM
I_FLOP_WREN : FDRE
port map(
Q => bus2ip_wrreq_i ,
C => Bus_clk ,
CE => '1' ,
D => sig_internal_wrdack,
R => Bus_Rst
);
-- Read Acknowledge FLOPS
sig_clear_rdack_erly1 <= Bus_Rst or
(sig_xfer_done and
sig_internal_rddack_early1);
I_FLOP_RDACK_2BUS : FDRE
port map(
Q => sl_rddack_i ,
C => Bus_clk ,
CE => sig_rd_req_reg ,
D => sig_internal_rddack_early1 ,
R => Bus_Rst
);
I_FLOP_RDACK_EARLY1 : FDRE
port map(
Q => sig_internal_rddack_early1,
C => Bus_clk ,
CE => sig_set_sl_busy ,
D => PLB_RNW ,
R => sig_clear_rdack_erly1
);
sig_clear_rdack_erly2 <= Bus_Rst or
(sig_xfer_almost_done and
sig_internal_rddack_early2 and
not(sig_set_sl_busy));
I_FLOP_RDACK_EARLY2 : FDRE
port map(
Q => sig_internal_rddack_early2,
C => Bus_clk ,
CE => sig_do_cmd ,
D => PLB_RNW ,
R => sig_clear_rdack_erly2
);
sig_rdcomp_erly <= ((doing_single_reg or
sig_cline_spec_1dbeat_case) and
sig_internal_rddack_early2) or
(sig_xfer_almost_done and
sig_internal_rddack_early1);
sig_clr_rdcomp <= sig_clear_rdack_erly1 or
sl_rdcomp_i;
-- Read Complete Flop
I_FLOP_RDCOMP : FDRE
port map(
Q => sl_rdcomp_i ,
C => Bus_clk ,
CE => sig_rd_req_reg ,
D => sig_rdcomp_erly,
--R => sig_clear_rdack_erly1
R => sig_clr_rdcomp
);
-- Read burst terminate FLOP
sig_set_rdbterm <= doing_flburst_reg and
sig_rd_req_reg and
sig_xfer_almost_done and
sig_internal_rddack_early1;
sig_clr_rdbterm <= Bus_Rst or
not(doing_flburst_reg) or
sl_rdbterm_i;
-- Read BTERM Flop
I_FLOP_RDBTERM : FDRE
port map(
Q => sl_rdbterm_i ,
C => Bus_clk ,
CE => sig_set_rdbterm ,
D => '1',
R => sig_clear_rdack_erly1
);
------------------------------------------------------------
-- If Generate
--
-- Label: SLAVE_32_SPECIAL
--
-- If Generate Description:
-- This IfGen implements the special condition case for a
-- Fixed length Burst write of 2 data beats and a Slave width
-- of 32 bits.
--
------------------------------------------------------------
SLAVE_32_SPECIAL : if (C_SPLB_NATIVE_DWIDTH = 32) generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SPECIAL_WRBTERM_32
--
-- Process Description:
-- Special Write Burst Termination check for Slave 32
-- Because of the optimized Write data acknowledge response
-- during the Sl_AddrAck asertion, the Write Burst case of
-- length 2 must be detected early so that the Sl_wrBTerm can
-- be asserted in conjunction with the first Sl_wrDAck assertion.
--
-- Note:
-- If the requested transfer width is wider than the
-- Native Slave width, then Burst Length Expansion is required
-- and Burst Terminate is not asserted immediately.
-------------------------------------------------------------
SPECIAL_WRBTERM_32 : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(sig_force_wrbterm = '1' and
sig_internal_wrdack = '1') or
sl_rearbitrate_i = '1') then
sig_force_wrbterm <= '0';
--elsif (sig_addr_decode_hit = '1' and
elsif (sig_good_request = '1' and
PLB_RNW = '0' and
burst_transfer = '1' and
--sig_internal_be(0 to 3) = "0001") then
PLB_BE(0 to 3) = "0001") then
case PLB_size is
when "1010" => -- word xfer
sig_force_wrbterm <= '1';
-- when "1011" => -- double word xfer
--
-- sig_force_wrbterm <= '0';
--
-- when "1011" => -- quad word xfer
--
-- sig_force_wrbterm <= '0';
when others => -- burst length expansion case
sig_force_wrbterm <= '0';
end case;
else
null; -- hold current state
end if;
end if;
end process SPECIAL_WRBTERM_32;
end generate SLAVE_32_SPECIAL;
------------------------------------------------------------
-- If Generate
--
-- Label: SLAVE_64_SPECIAL
--
-- If Generate Description:
-- This IfGen implements the special condition case for a
-- Fixed length Burst write of 2 data beats and a Slave width
-- of 64 bits.
--
------------------------------------------------------------
SLAVE_64_SPECIAL : if (C_SPLB_NATIVE_DWIDTH = 64) generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SPECIAL_WRBTERM_64
--
-- Process Description:
-- Special Write Burst Termination check for Slave 64
-- Because of the optimized Write data acknowledge response
-- during the Sl_AddrAck asertion, the Write Burst case of
-- length 2 must be detected early so that the Sl_wrBTerm can
-- be asserted in conjunction with the first Sl_wrDAck assertion.
--
-- Note:
-- If the requested transfer width is wider than the
-- Native Slave width, then Burst Length Expansion is required
-- and Burst Terminate is not asserted immediately.
-------------------------------------------------------------
SPECIAL_WRBTERM_64 : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(sig_force_wrbterm = '1' and
sig_internal_wrdack = '1') or
sl_rearbitrate_i = '1') then
sig_force_wrbterm <= '0';
--elsif (sig_addr_decode_hit = '1' and
elsif (sig_good_request = '1' and
PLB_RNW = '0' and
burst_transfer = '1' and
--sig_internal_be(0 to 3) = "0001") then
PLB_BE(0 to 3) = "0001") then
case PLB_size is
when "1010" => -- word xfer
sig_force_wrbterm <= '1';
when "1011" => -- double word xfer
sig_force_wrbterm <= '1';
-- when "1011" => -- quad word xfer
--
-- sig_force_wrbterm <= '0';
when others => -- burst length expansion case
sig_force_wrbterm <= '0';
end case;
else
null; -- hold current state
end if;
end if;
end process SPECIAL_WRBTERM_64;
end generate SLAVE_64_SPECIAL;
------------------------------------------------------------
-- If Generate
--
-- Label: SLAVE_128_SPECIAL
--
-- If Generate Description:
-- This IfGen implements the special condition case for a
-- Fixed length Burst write of 2 data beats and a Slave width
-- of 128 bits.
--
------------------------------------------------------------
SLAVE_128_SPECIAL : if (C_SPLB_NATIVE_DWIDTH = 128) generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SPECIAL_WRBTERM_128
--
-- Process Description:
-- Special Write Burst Termination check for Slave 128
-- Because of the optimized Write data acknowledge response
-- during the Sl_AddrAck asertion, the Write Burst case of
-- length 2 must be detected early so that the Sl_wrBTerm can
-- be asserted in conjunction with the first Sl_wrDAck assertion.
--
-- Note:
-- Since the Slave is 128 bits wide, burst length expansion
-- will never occur so the WrBTerm must be asserted immediately.
-------------------------------------------------------------
SPECIAL_WRBTERM_128 : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(sig_force_wrbterm = '1' and
sig_internal_wrdack = '1') or
sl_rearbitrate_i = '1') then
sig_force_wrbterm <= '0';
elsif (sig_good_request = '1' and
PLB_RNW = '0' and
burst_transfer = '1' and
--sig_internal_be(0 to 3) = "0001") then
PLB_BE(0 to 3) = "0001") then
sig_force_wrbterm <= '1';
else
null; -- hold current state
end if;
end if;
end process SPECIAL_WRBTERM_128;
end generate SLAVE_128_SPECIAL;
-------------------------------------------------------------
-- Write Data Bus logic
--
--
-------------------------------------------------------------
sig_ld_wr_dreg <= sig_internal_wrdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_WR_DREG
--
-- Process Description:
-- This process implements the Write Data Register.
--
-------------------------------------------------------------
DO_WR_DREG : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
sig_wr_req_reg = '0') then
sig_wr_dreg <= (others => '0');
elsif (sig_ld_wr_dreg = '1') then
sig_wr_dreg <= PLB_wrDBus(0 to C_SPLB_NATIVE_DWIDTH-1);
else
null; -- hold current state
end if;
end if;
end process DO_WR_DREG;
-------------------------------------------------------------
-- Read Data Bus logic
--
--
-------------------------------------------------------------
-- Rip the Read Data Bus Steering address from the address
-- counter output
sig_steer_addr <= bus2ip_addr_i(C_SPLB_AWIDTH -
STEER_ADDR_SIZE to
C_SPLB_AWIDTH-1);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STEER_ADDR
--
-- Process Description:
-- This process registers the read data steer address to
-- delay it by 1 clock. THis aligns the address with the
-- corresponding data value out of the BRAM.
--
-------------------------------------------------------------
REG_STEER_ADDR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_steer_addr_reg <= (others => '0');
elsif (sig_internal_rddack_early2 = '1') then
sig_steer_addr_reg <= sig_steer_addr;
else
null; -- hold current state
end if;
end if;
end process REG_STEER_ADDR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDWDADDR
--
-- Process Description:
-- This process registers the needed address bits from the
-- registered Steer Address to geneate the Sl_rdwdAdr output
-- that is required for Cacheline Read operations.
--
-------------------------------------------------------------
REG_RDWDADDR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
doing_cacheln_reg = '0' or
sig_internal_rddack_early1 = '0') then
sl_rdwdaddr_i <= (others => '0');
else
-- DET sl_rdwdaddr_i <=
-- DET sig_steer_addr_reg(STEER_ADDR_SIZE-6 to
-- DET STEER_ADDR_SIZE-3);
-- DET Zero MSBit since Cacheline 16 is not supported
sl_rdwdaddr_i(1 to 3) <=
sig_steer_addr_reg(STEER_ADDR_SIZE-5 to
STEER_ADDR_SIZE-3);
end if;
end if;
end process REG_RDWDADDR;
------------------------------------------------------------
-- Instance: I_MIRROR_STEER
--
-- Description:
-- This instantiates a parameterizable Mirror ands Steering
-- support module for the Read Data. This is needed when
-- a wide Slave is providing Read data to a narrow Master.
--
------------------------------------------------------------
I_MIRROR_STEER : entity xps_bram_if_cntlr_v1_00_b.xbic_data_steer_mirror
generic map (
C_STEER_ADDR_WIDTH => STEER_ADDR_SIZE ,
C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
C_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER
)
port map (
Steer_Addr_In => sig_steer_addr_reg ,
Data_In => ip2bus_rddata_i ,
Data_Out => sig_rd_data_mirror_steer
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_DATA_REG
--
-- Process Description:
-- This process implements the Read Data Register.
-- Mirroring and Steeering is assumed to be done on the
-- input data to the register.
-------------------------------------------------------------
RD_DATA_REG : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_rd_dreg <= (others => '0');
elsif (sig_internal_rddack_early1 = '1') then
sig_rd_dreg <= sig_rd_data_mirror_steer;
else
sig_rd_dreg <= (others => '0');
end if;
end if;
end process RD_DATA_REG;
end implementation;
| bsd-3-clause | cb8c631f1ad3c5ce89bf10cd80e4f122 | 0.45049 | 4.193364 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/gpmc_wishbone_wrapper.vhd | 2 | 7,987 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
-- ----------------------------------------------------------------------------
entity gpmc_wishbone_wrapper is
-- ----------------------------------------------------------------------------
generic(sync : boolean := true; burst : boolean := false );
port
(
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of gpmc_wishbone_wrapper is
-- ----------------------------------------------------------------------------
signal write, writen, writen_sync_0 : std_logic;
signal read, readn, readn_sync_0 : std_logic;
signal cs, csn, csn_sync_0 : std_logic ;
signal writedata, writedata_sync_0,iob_writedata, writedata_bridge,iob_readdata, readdata_bridge : std_logic_vector(15 downto 0);
signal address, address_sync_0, address_bridge : std_logic_vector(15 downto 0);
signal burst_counter : std_logic_vector(16 downto 0);
signal wbm_readdata_bridge : std_logic_vector(15 downto 0);
signal csn_bridge,wen_bridge, oen_bridge : std_logic;
signal gpmc_clk_old, gpmc_clk_re : std_logic;
signal bus_control_logic_side, bus_control_bus_side : std_logic ;
signal is_read, is_write, iob_dq_hiz : std_logic ;
signal debounce_counter : std_logic_vector(1 downto 0);
attribute IOB: string;
attribute IOB of csn_bridge: signal is "true";
attribute IOB of wen_bridge: signal is "true";
attribute IOB of oen_bridge : signal is "true";
attribute IOB of iob_readdata: signal is "true";
--attribute IOB of address_bridge : signal is "true" ;
begin
gen_async : if sync = false generate
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
address <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if gpmc_advn = '0' then
address <= gpmc_ad;
end if;
end if;
end process;
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
cs <= '0';
read <= '0';
writedata <= (others => '0');
elsif(rising_edge(gls_clk)) then
cs <= (not gpmc_csn) and (gpmc_advn) ;--and (gpmc_wen XOR gpmc_oen);
write <= (not gpmc_wen);
read <= (not gpmc_oen);
if gpmc_advn = '1' and gpmc_csn ='0' and gpmc_wen='0' then
writedata <= gpmc_ad;
end if;
end if;
end process;
gpmc_ad <= wbm_readdata when (gpmc_csn = '0' and gpmc_oen = '0') else
(others => 'Z');
wbm_address <= address;
wbm_writedata <= writedata;
wbm_strobe <= cs and (write xor read);
wbm_write <= write;
wbm_cycle <= cs and (write xor read);
end generate ;
gen_syn : if sync = true generate
gen_burst : if burst = true generate
process(gpmc_clk, gls_reset)
begin
if(gls_reset='1') then
address_bridge <= (others => '0');
elsif(falling_edge(gpmc_clk)) then
if gpmc_advn = '0' then
address_bridge <= iob_writedata;
elsif readn = '0' and burst_counter(16) = '0' then
address_bridge <= address_bridge + 1;
end if;
end if;
end process;
end generate;
process(gpmc_clk, gls_reset)
begin
if(gls_reset='1') then
burst_counter <= (others => '0');
elsif(falling_edge(gpmc_clk)) then
if gpmc_csn = '1' then
burst_counter <= '0' & X"0001";
elsif readn = '0' and burst_counter(16) = '0' then
burst_counter <= burst_counter(15 downto 0) & '0'; -- burst access should be a maximum of 16 accesses
end if;
end if;
end process;
gen_no_burst : if burst = false generate
process(gpmc_clk, gls_reset)
begin
if(gls_reset='1') then
address_bridge <= (others => '0');
elsif(falling_edge(gpmc_clk)) then
if gpmc_advn = '0' then
address_bridge <= iob_writedata;
end if;
end if;
end process;
end generate;
process(gpmc_clk, gls_reset)
begin
if(gls_reset='1') then
csn_bridge <= '1';
wen_bridge <= '1';
oen_bridge <= '1';
iob_readdata <= (others => '0');
writedata_bridge <= (others => '0');
elsif(falling_edge(gpmc_clk)) then
csn_bridge <= gpmc_csn;
wen_bridge <= gpmc_wen;
oen_bridge <= gpmc_oen;
iob_readdata <= readdata_bridge;
writedata_bridge <= iob_writedata;
end if;
end process;
process(gpmc_clk, gls_reset)
begin
if(gls_reset='1') then
iob_dq_hiz <= '1' ;
elsif(falling_edge(gpmc_clk)) then
iob_dq_hiz <= gpmc_oen;
end if;
end process;
readdata_bridge <= wbm_readdata;
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
csn <= '1';
writen <= '1';
readn <= '1';
csn_sync_0 <= '1';
writen_sync_0 <= '1';
readn_sync_0 <= '1';
writedata <= (others => '0');
writedata_sync_0 <= (others => '0');
address <= (others => '0');
address_sync_0 <= (others => '0');
--readdata_bridge <= x"0000";
elsif(rising_edge(gls_clk)) then
-- Dual flop synchronizer stage 1
csn_sync_0 <= csn_bridge;
writen_sync_0 <= wen_bridge;
readn_sync_0 <= oen_bridge;
writedata_sync_0 <= writedata_bridge;
address_sync_0 <= address_bridge;
-- Dual flop synchronizer stage 2
csn <= csn_sync_0;
writen <= writen_sync_0;
readn <= readn_sync_0;
writedata <= writedata_sync_0;
address <= address_sync_0;
-- csn <= csn_bridge;
-- writen <= wen_bridge;
-- readn <= oen_bridge;
-- writedata <= writedata_bridge;
-- address <= address_bridge;
-- wbm_readdata does not go through the dual flop synchronize as its goes the other direction
--if wbm_ack = '1' then
--readdata_bridge <= wbm_readdata;
--else
-- readdata_bridge <= x"0000";
--end if;
end if ;
end process;
iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "SLOW")
port map ( O => iob_writedata(i), IO => gpmc_ad(i), I => iob_readdata(i), T => iob_dq_hiz);
end generate;
wbm_address <= address;
wbm_writedata <= writedata;
wbm_strobe <= (not csn) and ((not writen) or (not readn)) ;
wbm_write <= (not writen) and (not csn) ;
wbm_cycle <= (not csn) and ((not writen) or (not readn)) ;
end generate;
end architecture RTL;
| lgpl-3.0 | e0a6c9d372a34c606e661fc536c41431 | 0.585201 | 3.29905 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/sixteen_bit_reg.vhd | 1 | 1,353 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:19:23 11/11/2015
-- Design Name:
-- Module Name: sixteen_bit_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sixteen_bit_reg is
port( s_clk: in std_logic;
s_rst: in std_logic;
s_ld: in std_logic;
s_reg_in: in std_logic_vector(15 downto 0);
s_reg_out: out std_logic_vector(15 downto 0)
);
end sixteen_bit_reg;
architecture Behavioral of sixteen_bit_reg is
begin
process(s_clk, s_rst, s_ld)
begin
if s_rst = '1' then
s_reg_out<=(others=>'0');
elsif (s_clk'event and s_clk='1') and (s_ld='1') then
s_reg_out <= s_reg_in;
end if;
end process;
end Behavioral;
| unlicense | 266441c26667752905e845b5c13113dd | 0.564671 | 3.43401 | false | false | false | false |
guilhermekrz/Pipeline-Processor | HW_Src/MIPS.vhd | 1 | 16,206 | -- Clock_manual(button 0) = PIN_R22
-- CLock_27 = PIN_D12
-- Top Level Structural Model for MIPS Processor Core
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MIPS IS
PORT(
reset, clock_27,clock_manual : IN STD_LOGIC;
switch : IN STD_LOGIC_VECTOR(9 downto 0);
Branch_out, Zero_out, LessThanZeroOut, BranchLessThanZeroOut : OUT STD_LOGIC;
flush_out,flushP_out : OUT STD_LOGIC;
resetOut, clockOut : OUT STD_LOGIC;
sevenSegmentVector4Out : OUT std_logic_vector(27 downto 0));
END MIPS;
ARCHITECTURE structure OF MIPS IS
COMPONENT Ifetch
PORT(
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
PC_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
correct : OUT STD_LOGIC_VECTOR( 15 downto 0);
wrong : OUT STD_LOGIC_VECTOR( 15 downto 0);
--Branch Signals
Branch : IN STD_LOGIC;
Zero : IN STD_LOGIC;
BranchLessThanZero: IN STD_LOGIC;
LessThanZero : IN STD_LOGIC;
Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END COMPONENT;
--------------------------------------------------------
COMPONENT Idecode
PORT( read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
-----Registers output-------------------------------
registerT0 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT4 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT5 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT6 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT7 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT8 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT9 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
------------------------------------------------------
write_register_addressToMemory : OUT STD_LOGIC_VECTOR(4 downto 0);
flushP : IN STD_LOGIC;
----------------
alu_result0 : IN STD_LOGIC_vector(31 downto 0);
RegWrite0 : IN STD_LOGIC;
write_register_addressFromMemory0: IN STD_LOGIC_VECTOR(4 downto 0);
MemToReg0 : IN STD_LOGIC;
stall : OUT STD_LOGIC;
---------------
write_register_addressFromMemory: IN STD_LOGIC_VECTOR(4 downto 0);
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT control
PORT(
ALUSrc : OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
MemtoReg : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
RegDst : OUT STD_LOGIC;
--Branch Signals
Branch : OUT STD_LOGIC;
BranchLessThanZero: OUT STD_LOGIC;
--flush
flush : OUT STD_LOGIC;
flushP : IN STD_LOGIC;
Zero : IN STD_LOGIC;
LessThanZero : IN STD_LOGIC;
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT Execute
PORT( --Branch Signals
Zero : OUT STD_LOGIC;
LessThanZero : OUT STD_LOGIC;
ALU_Result : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Add_result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Read_data_2 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Sign_Extend : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
ALUOp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );
ALUSrc : IN STD_LOGIC;
flushP : IN STD_LOGIC;
PC_plus_4 : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
--------------------------------------------------------
COMPONENT dmemory
PORT( read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
alu_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite,MemToReg : IN STD_LOGIC;
Clock,reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT sevenSegment4
PORT( numberDesired4 : in std_logic_vector(15 downto 0);
sevenSegmentVector4 : out std_logic_vector(27 downto 0);
clock, reset : in std_logic);
END COMPONENT;
---------------- declare signals used to connect VHDL components---------------------
--Clock
SIGNAL clock : STD_LOGIC;
--IFE
SIGNAL PC : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--IFE to IDE
SIGNAL Instruction : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--IFE to EXE
SIGNAL PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--IDE
SIGNAL registerT0 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT3 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT4 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT5 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT6 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT7 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT8 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT9 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--IDE to EXE
SIGNAL read_data_1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Sign_extend : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--EXE to IFE
SIGNAL Add_result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Zero : STD_LOGIC;
SIGNAL LessThanZero : STD_LOGIC;
--EXE to (IDE and DMEM)
SIGNAL ALU_result : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--(IDE) to (EXE and DMEM)
SIGNAL read_data_2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--DMEM to IDE
SIGNAL read_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--CONTROL to IFE
SIGNAL Branch : STD_LOGIC;
SIGNAL BranchLessThanZero:STD_LOGIC;
--CONTROL to IDE
SIGNAL RegDst : STD_LOGIC;
SIGNAL RegWrite : STD_LOGIC;
SIGNAL MemtoReg : STD_LOGIC;
--CONTROL to EXE
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL ALUop : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
--CONTROL to DMEM
SIGNAL MemWrite : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
--sevenSegment4
SIGNAL sevenSegmentVector4:STD_LOGIC_VECTOR( 27 DOWNTO 0 );
--Our pipe: IF / ID-EX / DMEM / WB
--Pipe between IFE and (IDE-EXE)
SIGNAL branchP : STD_LOGIC;
SIGNAL ZeroP : STD_LOGIC;
SIGNAL BranchLessThanZeroP : STD_LOGIC;
SIGNAL LessThanZeroP : STD_LOGIC;
SIGNAL Add_resultP : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL InstructionP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL PC_plus_4_outP : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--Pipe between (IDE-EXE-CONTROL) and (DMEM)
SIGNAL ALU_resultP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_data_2P : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL MemWriteP : STD_LOGIC;
SIGNAL MemReadP : STD_LOGIC;
SIGNAL MemToRegP : STD_LOGIC;
SIGNAL RegWriteP : STD_LOGIC;
SIGNAL write_register_addressP: STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address : STD_LOGIC_VECTOR(4 downto 0);
--Pipe between (DMEM) and (WB)
SIGNAL read_dataP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL RegWritePP : STD_LOGIC;
SIGNAL write_register_addressPP : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
--flush
SIGNAL flush : STD_LOGIC;
SIGNAL flushP : STD_LOGIC;
--stall
SIGNAL stall : STD_LOGIC;
--Branch Prediction Accuracy (static always not-taken)
SIGNAL correct : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL wrong : STD_LOGIC_VECTOR(15 downto 0);
--End of Our pipe: IF / ID-EX / DMEM / WB
--Number to display on the 7-segment display
SIGNAL numberDesiredToDisplay : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
process
BEGIN
WAIT UNTIL falling_edge(clock);--clock'EVENT AND clock = '0';
--if(reset='1') then
if(reset='0') then
branchP <= '0';
ZeroP <= '0';
BranchLessThanZeroP <= '0';
LessThanZeroP <= '0';
Add_resultP <= "00000000";
InstructionP <= "00000000000000000000000000000000";
PC_plus_4_outP <= "0000000000";
--------------
ALU_resultP <= "00000000000000000000000000000000";
read_data_2P <= "00000000000000000000000000000000";
MemWriteP <= '0';
MemReadP <= '0';
MemToRegP <= '0';
RegWriteP <= '0';
write_register_addressP <= "00000";
--------------
read_dataP <= "00000000000000000000000000000000";
RegWritePP <= '0';
write_register_addressPP <= "00000";
--------------
flushP <= '0';
elsif (stall='1') then
branchP <= '1';
ZeroP <= '1';
BranchLessThanZeroP <= '0';
LessThanZeroP <= '0';
Add_resultP <= PC(9 downto 2);
--InstructionP <= "00000000000000000000000000000000";
--PC_plus_4_outP <= "0000000000";
--------------------
----------------------
read_dataP <= read_data;
RegWritePP <= RegWriteP;
write_register_addressPP <= write_register_addressP;
----------------------
--------------------
ALU_resultP <= "00000000000000000000000000000000";
read_data_2P <= "00000000000000000000000000000000";
MemWriteP <= '0';
MemReadP <= '0';
MemToRegP <= '0';
RegWriteP <= '0';
write_register_addressP <= "00000";
flushP <= '0';
else
branchP <= branch;
ZeroP <= Zero;
BranchLessThanZeroP <= BranchLessThanZero;
LessThanZeroP <= LessThanZero;
Add_resultP <= Add_result;
InstructionP <= Instruction;
PC_plus_4_outP <= PC_plus_4;
--------------------
----------------------
read_dataP <= read_data;
RegWritePP <= RegWriteP;
write_register_addressPP <= write_register_addressP;
----------------------
--------------------
ALU_resultP <= ALU_result;
read_data_2P <= read_data_2;
MemWriteP <= MemWrite;
MemReadP <= MemRead;
MemToRegP <= MemToReg;
RegWriteP <= RegWrite;
write_register_addressP <= write_register_address;
flushP <= flush;
end if;
end process;
process (clock_27,clock_manual,switch,registerT0,registerT1,registerT2,registerT3,registerT4,registerT5,registerT6,registerT7,registerT8,registerT9,PC,Alu_Result,correct,wrong)
begin
if(switch(8)='1') then
clock <= clock_manual;
else
clock <= clock_27;
end if;
if(switch(9)='1') then
if(switch(7 downto 0)=X"00") then
numberDesiredToDisplay <= registerT0(15 downto 0);
elsif (switch(7 downto 0)=X"01") then
numberDesiredToDisplay <= registerT1(15 downto 0);
elsif (switch(7 downto 0)=X"02") then
numberDesiredToDisplay <= registerT2(15 downto 0);
elsif (switch(7 downto 0)=X"03") then
numberDesiredToDisplay <= registerT3(15 downto 0);
elsif (switch(7 downto 0)=X"04") then
numberDesiredToDisplay <= registerT4(15 downto 0);
elsif (switch(7 downto 0)=X"05") then
numberDesiredToDisplay <= registerT5(15 downto 0);
elsif (switch(7 downto 0)=X"06") then
numberDesiredToDisplay <= registerT6(15 downto 0);
elsif (switch(7 downto 0)=X"07") then
numberDesiredToDisplay <= registerT7(15 downto 0);
elsif (switch(7 downto 0)=X"08") then
numberDesiredToDisplay <= registerT8(15 downto 0);
elsif (switch(7 downto 0)=X"09") then
numberDesiredToDisplay <= registerT9(15 downto 0);
elsif (switch(7 downto 0)=X"50") then
numberDesiredToDisplay <= "000000" & PC;
elsif (switch(7 downto 0)=X"40") then
numberDesiredToDisplay <= Alu_Result(15 downto 0);
elsif (switch(7 downto 0)=X"20") then
numberDesiredToDisplay <= correct(15 downto 0);
elsif (switch(7 downto 0)=X"30") then
numberDesiredToDisplay <= wrong(15 downto 0);
else
numberDesiredToDisplay <= X"0000";
end if;
else
numberDesiredToDisplay <= (registerT0(7 downto 0) & registerT1(7 downto 0));
end if;
end process;
-- copy important signals to output pins for easy display in Simulator
Branch_out <= Branch;
BranchLessThanZeroOut <= BranchLessThanZero;
Zero_out <= Zero;
LessThanZeroOut <= LessThanZero;
ResetOut <= Reset;
clockOut <= clock;
sevenSegmentVector4Out <= sevenSegmentVector4;
flush_out <= flush;
flushP_out <= flushP;
-- connect the 5 MIPS components
IFE : Ifetch
PORT MAP ( Instruction => Instruction,
PC_plus_4_out => PC_plus_4,
Add_result => Add_resultP,
--Branch Signals
Branch => branchP,
Zero => ZeroP,
BranchLessThanZero=> BranchLessThanZeroP,
LessThanZero => LessThanZeroP,
correct => correct,
wrong => wrong,
PC_out => PC,
clock => clock,
reset => not reset );
ID : Idecode
PORT MAP (
read_data_1 => read_data_1,
read_data_2 => read_data_2,
Instruction => InstructionP,
read_data => read_dataP,
flushP => flushP,
RegWrite => RegWritePP,
RegDst => RegDst,
Sign_extend => Sign_extend,
registerT0 => registerT0,
registerT1 => registerT1,
registerT2 => registerT2,
registerT3 => registerT3,
registerT4 => registerT4,
registerT5 => registerT5,
registerT6 => registerT6,
registerT7 => registerT7,
registerT8 => registerT8,
registerT9 => registerT9,
write_register_addressToMemory => write_register_address,
write_register_addressFromMemory => write_register_addressPP,
------------------Forward DMEM to ID
alu_result0 => Alu_resultP,
RegWrite0 => RegWriteP,
write_register_addressFromMemory0 => write_register_addressP,
MemToReg0 => MemToRegP,
stall => stall,
------------------
clock =>clock,
reset => not reset );
CTL: control
PORT MAP ( Opcode => InstructionP( 31 DOWNTO 26 ),
RegDst => RegDst,
ALUSrc => ALUSrc,
MemToReg => MemToReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
--Branch Signals
Branch => Branch,
BranchLessThanZero=> BranchLessThanZero,
--flush
flush => flush,
flushP => flushP,
Zero => Zero,
LessThanZero => LessThanZero,
ALUop => ALUop,
clock => clock,
reset => not reset );
EXE: Execute
PORT MAP ( Read_data_1 => read_data_1,
read_data_2 => read_data_2,
Sign_extend => Sign_extend,
Function_opcode => InstructionP( 5 DOWNTO 0 ),
ALUOp => ALUop,
ALUSrc => ALUSrc,
--Branch Signals
Zero => Zero,
LessThanZero => LessThanZero,
flushP => flushP,
ALU_result => ALU_result,
Add_result => Add_result,
PC_plus_4 => PC_plus_4_outP,
clock => clock,
Reset => not reset );
MEM: dmemory
PORT MAP ( read_data => read_data,
address => ALU_resultP (7 DOWNTO 0),
alu_result => ALU_resultP,
write_data => read_data_2P,
MemRead => MemReadP,
Memwrite => MemWriteP,
MemToReg => MemToRegP,
clock => clock,
reset => not reset );
SEV4: sevenSegment4
PORT MAP (
numberDesired4 => numberDesiredToDisplay,
sevenSegmentVector4 => sevenSegmentVector4,
clock => clock,
reset => reset );
END structure;
| gpl-2.0 | d7d66a295570c2ce84d4afc2ea2eb906 | 0.583179 | 3.302629 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/dynshreg2_f.vhd | 2 | 16,198 | -------------------------------------------------------------------------------
-- $Id: dynshreg2_f.vhd,v 1.1.4.50 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg2_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg2_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version differs from dynshreg_f only in that it
-- has a work around needed to get the C_DEPTH = 1 case
-- past a target synthesis tool.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- Functionally identical but with work-around
-- as noted in the description.
--
-- ~~~~~~
-- FLO MM/DD/YYYY
-- ^^^^^^
-- History comment.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity dynshreg2_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg2_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg2_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_ONEDEEP : boolean := (C_DEPTH = 1); -- Case needing XST workaround
--
constant USE_INFERRED : boolean := not USE_ONEDEEP
and
(
( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16)
);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED and not USE_ONEDEEP;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
---(
INFERRED_ONEDEEP : if USE_ONEDEEP = true generate
signal data: std_logic_vector (0 to C_DWIDTH-1);
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din;
end if;
end if;
end process;
Dout <= data;
end generate INFERRED_ONEDEEP;
---)
end behavioral;
---)
| bsd-3-clause | b5d3bd977bde05b4e8127c961d219696 | 0.462526 | 4.584772 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/switch_fab_2.vhd | 1 | 13,266 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_2.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: switch_fab_2.vhd,v $
-- Revision 1.3 2015/06/15 16:39:54 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.2 2007/08/13 10:14:19 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.1 2004/08/13 15:16:05 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:48 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/07/27 17:06:19 mmiehling
-- multifunction added
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_2 IS
GENERIC (
registered : IN boolean );
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_2;
ARCHITECTURE switch_fab_2_arch OF switch_fab_2 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
-- TYPE sw_states IS (sw_0, sw_1);
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL sel : std_logic_vector(1 DOWNTO 0);
SIGNAL wbi_slave_stb : std_logic;
BEGIN
without_q : IF NOT registered GENERATE
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END GENERATE without_q;
---------------------------------------------------------------------
with_q : IF registered GENERATE
ack_0 <= ack_0_int;
ack_1 <= ack_1_int;
wbi_slave.stb <= wbi_slave_stb;
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_state <= sw_0;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_0_int = '1') AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSE
sw_state <= sw_0;
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_state <= sw_1;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- single
wbi_slave_stb <= wbo_1.stb;
ELSIF (wbo_slave.ack = '1' OR ack_1_int = '1') AND wbo_1.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSE
sw_state <= sw_1;
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
sw_state <= sw_0;
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN sel <= "01";
ELSIF cyc_1 = '1' THEN sel <= "10";
ELSE sel <= "00";
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN sel <= "10";
ELSIF cyc_0 = '1' THEN sel <= "01";
ELSE sel <= "00";
END IF;
WHEN OTHERS => sel <= "00";
END CASE;
END PROCESS sw_fsm_sel;
data_sw : PROCESS( clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave.dat <= (OTHERS => '0');
wbi_slave.adr <= (OTHERS => '0');
wbi_slave.sel <= (OTHERS => '0');
wbi_slave.we <= '0';
wbi_slave_cyc <= '0';
ack_0_int <= '0';
err_0 <= '0';
ack_1_int <= '0';
err_1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
wbi_slave_cyc <= sel(0) OR sel(1);
IF sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_0_int <= '1';
ELSE
ack_0_int <= '0';
END IF;
IF sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_0 <= '1';
ELSE
err_0 <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_1_int <= '1';
ELSE
ack_1_int <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_1 <= '1';
ELSE
err_1 <= '0';
END IF;
CASE sel IS
WHEN "01" => wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
WHEN OTHERS => wbi_slave.dat <= wbo_1.dat;
wbi_slave.adr <= wbo_1.adr;
wbi_slave.sel <= wbo_1.sel;
wbi_slave.we <= wbo_1.we;
wbi_slave.cti <= wbo_1.cti;
wbi_slave.tga <= wbo_1.tga;
END CASE;
END IF;
END PROCESS data_sw;
END GENERATE with_q;
END switch_fab_2_arch;
| gpl-3.0 | 672dc4ef0cd9000c6f3132786227710a | 0.420775 | 3.725358 | false | false | false | false |
QuickJack/logi-hard | test_bench/heart_beat_tb.vhd | 2 | 2,479 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:46 02/19/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/heart_beat_tb.vhd
-- Project Name: logipi_ugv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: heart_beat
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY heart_beat_tb IS
END heart_beat_tb;
ARCHITECTURE behavior OF heart_beat_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT heart_beat
generic(clk_period_ns : positive := 10;
beat_period_ns : positive := 1_000_000_000;
beat_length_ns : positive := 200_000_000);
PORT(
gls_clk : IN std_logic;
gls_reset : IN std_logic;
beat_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal beat_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: heart_beat
generic map(clk_period_ns => 10,
beat_period_ns => 100_000,
beat_length_ns => 20_000)
PORT MAP (
gls_clk => clk,
gls_reset => reset,
beat_out => beat_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 | 7f36575957e535579b06436fe6bfd2c1 | 0.594595 | 3.744713 | false | true | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_bam.vhd | 3 | 146,340 | -------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_bam.vhd
-- Version: v3.01a
-- Description: Bus Attachment Module, OPB to IPIC.
--
-- VHDL Standard: VHDL 93
-------------------------------------------------------------------------------
-- Structure: opb_bam
-- -- reset_mir
-- -- interrupt_control
-- -- rdpfifo_top
-- -- wrpfifo_top
-- -- opb_be_gen
-- -- brst_addr_cntr
-- -- brst_addr_cntr_reg
-- -- opb_flex_addr_cntr
-- -- write_buffer
-- -- srl_fifo3
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 10/22/02
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- FLO 12/09/02
-- ^^^^^^
-- Support now for posted writes and burst of posted writes under
-- OPB_seqAddr=1. (The latter not yet tested.)
-- ~~~~~~
-- FLO 03/21/03
-- ^^^^^^
-- Hooked up neglected connection of OPB_BE to opb_be_s0.
-- ~~~~~~
-- FLO 05/15/2003
-- ^^^^^^
-- Introduced signal OPB_seqAddr_eff to disable bursts when parameter
-- C_DEV_BURST_ENABLE is false.
-- ~~~~~~
--
-- FLO 05/27/2003
-- ^^^^^^
-- Use sln_xferack_s1 to enable other than '0' values to the
-- OPBOUT pipestage when this stage is present and there is
-- a single address range. This, in turn, allows the optimization
-- of passing ip2bus_data through to ip2bus_data_mx without
-- qualification by a CE Address-Range decode, saving a LUT per
-- data-bus bit for this case.
-- ~~~~~~
--
-- FLO 05/28/2003
-- ^^^^^^
-- Made a correction to the last change that was causing it to
-- drive sln_dbus during a write transaction.
-- Now the sln_dbus_s2 signals are separated from the other _s2 signals
-- for application of the reset when sln_xferack_s1 = '0' and this
-- reset is further qualified by bus2ip_rnw_s1.
-- ~~~~~~
-- FLO 09/10/2003
-- ^^^^^^
-- Fixed the mirror instantiation, which erroneously had the address tied low.
-- ~~~~~~
--
-- ALS 10/22/03
-- ^^^^^^
-- Creation of version v3_00_b to include read and write packet FIFOs.
-- Also modified code for direct entity instantiation.
-- ~~~~~~
-- ALS 11/18/03
-- ^^^^^^
-- Creation of version v3_01_a to modify generics and some ports to align
-- with the PLB IPIF. Added look-ahead address counter for read bursts and write
-- buffer for write bursts.
-- ~~~~~~~
--
-- ALS 04/09/04
-- ^^^^^^
-- Removed vectorization of IP2Bus signals
-- ^^^^^^
-- GAB 04/15/04
-- ^^^^^^
-- - Updated to use libraries proc_common_v2_00_a, wrpfifo_v1_01_b,
-- rdpfifo_v1_01_b, and interrupt_control_v1_00_a.
-- - Fixed issues with wrpfifo for pipeline model 0
-- - Fixed issues with wrpfifo and rdpfifo for cases when write buffer
-- was instantiated.
-- - Fixed issues with master aborts, delayed IP acknowledges.
-- - Fixed double clock wide wrce which caused an interrupt to be generated
-- when an interrupt was cleared.
-- - Improved utilization by allowing the tools to place the read mux
-- - Removed checks on postedwrinh when write buffer was instantiated because
-- the write buffer currently does not support this feature.
-- - Set MAX_USER_ADDR_RANGE minimum to 7 because opb_flex_addr_cntr.vhd expects
-- a minimum of 7 address bits to decode.
-- - Changed reset/mir to be posted write inhibited because of problems with
-- various pipeline models and single beat reads. CS,CE, etc. to reset_mir
-- would not occur because they where inhibited on the same clock cycle as
-- they were to be generated.
-- - Created abort detection logic for pipeline models 1,3, and 7 to allow the
-- ipif to properly recover from a master abort.
--
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- - Fixed issues with dynamic switching of IP2Bus_PostedWrInh signal
-- - Optimized slave data read mux
-- - Fixed issue with Bus2IP_Burst signal when WriteBuffer was instantiated
-- - Fixed issue with Bus2IP_AddrValid when WriteBuffer was instantiated
-- ~~~~~~~
-- GAB 08/10/04
-- ^^^^^^
-- - Modified port range for IP2RFIFO_Data and WFIFO2IP_Data to be based on
-- the C_ARD_DWIDTH_ARRAY generic and not hard coded. Fixes CR191551
-- - Added synopsys translate_off/translate_on statements to exclude assert
-- statements from the synthesis process.
-- - Added assert statement to check for match of C_ARD_DWIDTH_ARRAY element
-- and fifo WR_WIDTH_BITS setting, though the mis-match of array sizes should
-- cause the simulation to error out on load.
-- ~~~~~~~
-- GAB 07/06/05
-- ^^^^^^
-- Removed xfer_abort signal from Sln_xferack logic to help improve timing.
-- ~~~~~~~
-- GAB 08/05/05
-- ^^^^^^
-- Fixed issue with IP2Bus_Postedwrinh_s2 getting reset with OPB_Select would
-- negate. IP2Bus_Postedwrinh_s2 should only negat based on UserIP.
-- ~~~~~~~
--
-- GAB 09/21/05
-- ^^^^^^
-- Fixed long timing path issue with Sln_Retry signal and cycle aborts. Modified
-- logic to suppress sln_xferack_s1 with cycle_abort for models where out-pipe was
-- included.
-- ~~~~~~~
-- GAB 10/12/05
-- ^^^^^^
-- Incorperated rev C mods into rev A to fix slow timing path with the address
-- decode. The modification simply shifts the input pipe stage for the address
-- to after the address decode. Therefore the functionality does not change
-- nor does the latency. This fix only improves pipeline 5 and 7 (i.e. any
-- with a model with a input pipeline stage).
-- ~~~~~~~
-- GAB 5/19/06
-- ^^^^^^
-- Removed unused last_wr_xferack, last_wr_xferack_d1,
-- and last_wr_xferack_d2.
-- Added bus2ip_rnw_s1 signal to SLN_XFERACK_PROC process's sinsitivity list.
-- This fixes CR231744.
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-- -------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.ipif_pkg.all;
use opb_v20_v1_10_d.ipif_steer;
use opb_v20_v1_10_d.family.all;
use opb_v20_v1_10_d.pselect;
use opb_v20_v1_10_d.or_muxcy;
use opb_v20_v1_10_d.reset_mir;
use opb_v20_v1_10_d.brst_addr_cntr;
use opb_v20_v1_10_d.brst_addr_cntr_reg;
use opb_v20_v1_10_d.opb_be_gen;
use opb_v20_v1_10_d.interrupt_control;
use opb_v20_v1_10_d.wrpfifo_top;
use opb_v20_v1_10_d.rdpfifo_top;
entity opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0000", -- IPIF_INTR
x"0000_0000_6000_003F",
--
x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_0100", -- USER_00
x"0000_0000_6000_01FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_INTR
32, -- IPIF_INTR
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 16, -- IPIF_INTR
1, -- IPIF_RST
8 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= (
0 => (others => 0)
,1 => (others => 0)
,2 => (others => 0)
);
C_PIPELINE_MODEL : integer := 7;
-- The pipe stages are enumerated and numbered as:
-- -- ----------
-- n Pipe stage
-- -- ----------
-- 0 OPBIN
-- 1 IPIC
-- 2 OPBOUT
-- Each pipe stage is either present or absent (i.e. bypassed).
-- The pipe stage, n, is present if the (2^n)th
-- bit in C_PIPELINE_MODEL is 1.
--
C_DEV_BLK_ID : INTEGER := 1;
-- Unique block ID, assigned to the device when the system is built.
C_DEV_MIR_ENABLE : INTEGER := 0;
C_OPB_AWIDTH : INTEGER := 32;
-- width of Address Bus (in bits)
C_OPB_DWIDTH : INTEGER := 32;
-- Width of the Data Bus (in bits)
C_FAMILY : string := "virtexe";
--
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
--
-- There will be one interrupt signal for each entry in
-- C_IP_INTR_MODE_ARRAY. The leftmost entry will be the
-- mode for input port IP2Bus_Intr(0), the next entry
-- for IP2Bus_Intr(1), etc.
--
-- These modes are supported:
--
-- Mode Description
--
-- 1 Active-high interrupt condition.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port-- that is an interrupt condition
-- that is latched and cleared in the IP core and made available
-- to the system via the Interrupt Source Controller in
-- the Bus Attachment Module.
--
-- 2 Active-low interrupt condition.
-- Like 1, except that the interrupt condition is asserted low.
--
-- 3 Active-high pulse interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose single clock period of active-high
-- assertion is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 4 Active-low pulse interrupt event.
-- Like 3, except the interrupt-event pulse is active low.
--
-- 5 Positive-edge interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose low-to-high transition, synchronous
-- with the clock, is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 6 Negative-edge interrupt event.
-- Like 5, except that the interrupt event is a
-- high-to-low transition.
--
-- Other mode codes are reserved.
--
C_DEV_BURST_ENABLE : INTEGER := 0;
-- Burst Enable for IPIF Interface
C_INCLUDE_ADDR_CNTR : INTEGER := 0;
-- ALS added generic for read address counter
-- inclusion of read address look ahead counter and write address counter
C_INCLUDE_WR_BUF : INTEGER := 0
-- ALS: added generic for write buffer
);
port
(
-- OPB signals
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
-- IPIC signals (address, data, acknowledges)
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1);
Bus2IP_AddrValid : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_OPB_DWIDTH-1);
IP2Bus_Ack : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
-- IPIC signals (Read Packet FIFO)
IP2RFIFO_Data : in std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA)) - 1) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out std_logic_vector(0 to bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA))) - 1);
RFIFO2IP_WrAck : out std_logic;
-- IPIC signals (Write Packet FIFO)
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
WFIFO2IP_AlmostEmpty: out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA)) - 1);
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out std_logic_vector(0 to bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA))) - 1);
WFIFO2IP_RdAck : out std_logic;
-- interrupts
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
IP2INTC_Irpt : out std_logic;
-- Software test breakpoint signal
Freeze : in std_logic;
Bus2IP_Freeze : out std_logic;
-- clocks and reset
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic
);
end entity opb_bam;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
architecture implementation of opb_bam is
-------------------------------------------------------------------------------
-- Function and Constant Declarations
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MIR fields
--
-- 4 7 5 8 8 # bits
--
-- 0-----3 4----------10 11-----15 16-----------23 24------------31
-- +-------+-------------+---------+---------------+----------------+
-- |MAJOR | MINOR |REVISION | BLK_ID | TYPE | MIR
-- |VERSION| VERSION |(letter) | | |
-- +-------+-------------+---------+---------------+----------------+
-- 0 = a
-- 1 = b
-- etc.
--
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
--
-- v1_03_c (aka V1.3c)
----------------------------------------------------------------------------
-- constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 1;
-- constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 0;
-- constant MIR_REVISION : INTEGER := 0;
-- ALS - modified MIR_MAJOR_VERSION to 3 and MIR_MINOR_VERSION to 1
constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 3;
constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 1;
constant MIR_REVISION : INTEGER range 0 to 25 := 0;
constant MIR_TYPE : INTEGER := 1;
-- Always '1' for OPB ipif interface type
-- ToDo, stays same for bus_attach?
constant NUM_ARDS : integer := C_ARD_ID_ARRAY'length;
constant NUM_CES : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant WRBUF_DEPTH : integer := 16;
constant INCLUDE_OPBIN_PSTAGE : boolean := (C_PIPELINE_MODEL/1) mod 2 = 1;
constant INCLUDE_IPIC_PSTAGE : boolean := (C_PIPELINE_MODEL/2) mod 2 = 1;
constant INCLUDE_OPBOUT_PSTAGE : boolean := (C_PIPELINE_MODEL/4) mod 2 = 1;
constant INCLUDE_RESET_MIR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INCLUDE_INTR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant INCLUDE_ADDR_CNTR : boolean
:= (C_INCLUDE_ADDR_CNTR=1 and C_DEV_BURST_ENABLE=1)
or (C_INCLUDE_ADDR_CNTR=1 and C_INCLUDE_WR_BUF=1);
-- ALS - added boolean constants for Read and Write Packet FIFOs
constant INCLUDE_RDFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
constant INCLUDE_WRFIFO : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Set SINGLE_CE if the only attached element is a user IP with only 1 CE.
constant SINGLE_CE : boolean := C_ARD_ID_ARRAY'length = 1
and C_ARD_NUM_CE_ARRAY(0) = 1
and C_ARD_ID_ARRAY(0) /= IPIF_RST;
-- constant ZERO_SLV : std_logic_vector(0 to 199) := (others => '0');
constant VIRTEX_II : boolean := derived(C_FAMILY, virtex2);
---------------------------------------------------------------------------
-- Function bo2sl
---------------------------------------------------------------------------
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
---------------------------------------------------------------------------
-- Function num_common_high_order_addr_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of high-order address bits
-- that can be commonly decoded across all address pairs passed in as
-- the argument ara. Note: only the C_OPB_AWIDTH rightmost bits of an entry
-- in ara are considered to make up the address.
----------------------------------------------------------------------------
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_OPB_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_OPB_AWIDTH-1)
:= ara(0)( ara(0)'length-C_OPB_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
---------------------------------------------------------------------------
-- Function cs_index_or_maxint
---------------------------------------------------------------------------
function cs_index_or_maxint(C_ARD_ID_ARRAY:INTEGER_ARRAY_TYPE; ID:INTEGER)
return integer is
begin
if find_ard_id(C_ARD_ID_ARRAY, ID) then
return get_id_index(C_ARD_ID_ARRAY, ID);
else
return integer'high;
end if;
end cs_index_or_maxint;
constant RESET_MIR_CS_IDX : natural
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RST);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RESET_MIR is false.
constant INTR_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_INTR);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_INTR is false.
-- ALS - added read and write packet FIFOs indices
constant RDFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant RDFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RDFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RDPFIFO is false.
constant WRFIFO_DATA_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
constant WRFIFO_REG_CS_IDX : integer
:= cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_WRFIFO_REG);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_WRPFIFO is false.
---------------------------------------------------------------------------
-- Function ce_index_or_maxint
---------------------------------------------------------------------------
function ce_index_or_maxint(C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE; IDX: integer)
return integer is
begin
if IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, IDX);
else
return integer'high;
end if;
end ce_index_or_maxint;
constant RESET_MIR_CE_IDX : natural
:=ce_index_or_maxint(C_ARD_ID_ARRAY,
RESET_MIR_CS_IDX);
constant INTR_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
INTR_CS_IDX);
-- ALS - added constants for read and write FIFOS
constant RFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX);
constant RFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
RDFIFO_DATA_CS_IDX);
constant WFIFO_REG_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX);
constant WFIFO_DATA_CE : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
WRFIFO_DATA_CS_IDX);
---------------------------------------------------------------------------
-- Function ce_hi_avoiding_bounds_error (was intr_ce_hi_avoiding_bounds_error)
-- ALS - modified this function to be usable by the FIFO Register CEs
---------------------------------------------------------------------------
function ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE;
CS_IDX: integer
) return integer is
begin
if CS_IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, CS_IDX)
+ C_ARD_NUM_CE_ARRAY(CS_IDX) - 1;
else
return integer'high;
end if;
end ce_hi_avoiding_bounds_error;
constant INTR_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
INTR_CS_IDX
);
-- ALS - added constant for read/write FIFO register CE high
constant RFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
RDFIFO_REG_CS_IDX
);
constant WFIFO_REG_CE_HI : natural
:= ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
WRFIFO_REG_CS_IDX
);
---------------------------------------------------------------------------
-- Function number_CEs_for
---------------------------------------------------------------------------
function number_CEs_for(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end number_CEs_for;
----------------------------------------------------------------------------
-- Constant zero std_logic_vector large enough for any needed use.
----------------------------------------------------------------------------
constant ZSLV : std_logic_vector(0 to 255) := (others => '0');
---------------------------------------------------------------------------
-- Function num_decode_bits
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function returns the number of address bits that need to be
-- decoded to find a "hit" in the address range defined by
-- the idx'th pair of base_address/high_address in c_ard_addr_range_array.
-- Only the rightmost numbits are considered and the result is the
-- number of leftmost bits within this field that need to be decoded.
----------------------------------------------------------------------------
function num_decode_bits(ard_addr_range_array : SLV64_ARRAY_TYPE;
numbits : natural;
idx : natural)
return integer is
constant SZ : natural := ard_addr_range_array(0)'length;
constant ADDR_XOR : std_logic_vector(0 to numbits-1)
:= ard_addr_range_array(2*idx )(SZ-numbits to SZ-1) -- base
xor ard_addr_range_array(2*idx+1)(SZ-numbits to SZ-1); -- high
begin
for i in 0 to numbits-1 loop
if ADDR_XOR(i)='1' then return i;
end if;
end loop;
return(numbits);
end function num_decode_bits;
---------------------------------------------------------------------------
-- Function encoded_size_is_1
---------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Returns whether bit n of the encoded representation of the data size
-- for address range ar is a 1
--
-- DSIZE Encoded value
-- 8 001
-- 16 010
-- 32 011
-- 64 100
-- 128 101
-- Others not supported
--------------------------------------------------------------------------
function encoded_size_is_1(ar, n: natural) return boolean is
begin
case n is
-- high-order bit
when 0 => return C_ARD_DWIDTH_ARRAY(ar) = 64 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- middle bit
when 1 => return C_ARD_DWIDTH_ARRAY(ar) = 16 or
C_ARD_DWIDTH_ARRAY(ar) = 32;
-- low-order bit
when 2 => return C_ARD_DWIDTH_ARRAY(ar) = 8 or
C_ARD_DWIDTH_ARRAY(ar) = 32 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- default for unsupported values
when others => return false;
end case;
end encoded_size_is_1;
---------------------------------------------------------------------------
-- Function num_cs_for_bit
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Returns the number of CS signals that need to be or'ed to give
-- bit n of the encoded size.
----------------------------------------------------------------------------
function num_cs_for_bit(n: natural) return natural is
variable r: natural;
begin
r := 0;
for k in 0 to NUM_ARDS-1 loop
if encoded_size_is_1(k, n) then r := r+1; end if;
end loop;
return r;
end num_cs_for_bit;
---------------------------------------------------------------------------
-- Function eff_ip2bus_val
---------------------------------------------------------------------------
-- ALS - modified to include read and write packet fifos
function eff_ip2bus_val(i : integer;
rst : std_logic;
intr : std_logic;
wrfifo : std_logic;
rdfifo : std_logic;
user : std_logic
) return std_logic is
begin
if C_ARD_ID_ARRAY(i) = IPIF_RST then return rst;
elsif C_ARD_ID_ARRAY(i) = IPIF_INTR then return intr;
elsif C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA then return wrfifo;
elsif C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then return rdfifo;
else return user;
end if;
end eff_ip2bus_val;
---------------------------------------------------------------------------
-- ALS: added function get_max_addr_range
-- Function get_max_addr_range
-- This function parses the ARD_ADDR_RANGE_ARRAY to determine which
-- baseaddr/highaddr pair spans the greatest address range. This is then
-- used to size the burst address counter
---------------------------------------------------------------------------
function get_max_user_addr_range(bus_awidth:integer) return integer is
variable max_range : integer := 0;
variable curr_range : integer := 0;
begin
for i in 0 to C_ARD_ADDR_RANGE_ARRAY'length/2-1 loop
if C_ARD_ID_ARRAY(i) = IPIF_RST or
C_ARD_ID_ARRAY(i) = IPIF_INTR or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_WRFIFO_DATA or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_REG or
C_ARD_ID_ARRAY(i) = IPIF_RDFIFO_DATA then
max_range := max_range;
else
-- addr_bits function returns number of address bits that are equal
-- between baseaddr and highaddr, so the address range is the
-- bus width minus the address bits
curr_range := bus_awidth - num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i);
if curr_range >= max_range then
max_range := curr_range;
else
max_range := max_range;
end if;
end if;
end loop;
return max_range;
end get_max_user_addr_range;
-- opb_flex_addr_cntr requires a minimum range of 7 (or 0 to 6)
-- constant MAX_USER_ADDR_RANGE : integer := get_max_user_addr_range(C_OPB_AWIDTH); --GB
constant MAX_USER_ADDR_RANGE : integer := max2(7,get_max_user_addr_range(C_OPB_AWIDTH)); --GB
------------------------------------------------------------------------------
-- Signal declarations
------------------------------------------------------------------------------
signal bus2ip_clk_i : std_logic;
signal bus2ip_reset_i : std_logic;
signal opb_select_s0 : std_logic;
signal opb_select_s0_d1 : std_logic;
signal opb_rnw_s0 : std_logic;
signal opb_seqaddr_s0 : std_logic;
signal opb_seqaddr_s0_d1 : std_logic;
signal bus2ip_burst_s1 : std_logic;
signal bus2ip_burst_s1_d1 : std_logic;
signal opb_seqaddr_d1 : std_logic;
signal opb_abus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_dbus_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_rnw_s1 : std_logic;
signal bus2ip_be_s0 : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal bus2ip_be_s1 : std_logic_vector(0 to C_OPB_DWIDTH/8-1) := (others => '0');
signal bus2ip_cs_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit : std_logic_vector(0 to NUM_ARDS-1); -- GAB 10/12/05
signal bus2ip_cs_hit_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_enable_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_ce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_ce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_addr_s0 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addr_s1 : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal bus2ip_addrvalid_s1 : std_logic;
signal bus2ip_data_s0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal bus2ip_data_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal devicesel_s0 : std_logic;
signal devicesel : std_logic; -- GAB 10/12/05
-- ALS - added address counter signals
signal address_load : std_logic;
signal opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_opb_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal next_steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal steer_addr_cntr_out : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal opb_be_cntr_out : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal opb_be_cntr_steer : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
-- ALS - added bus2ip_rdreq and bus2ip_wrreq and signals to support their
-- generation
signal rdreq : std_logic;
signal rdreq_hold : std_logic;
signal rdreq_hold_rst : std_logic;
signal bus2ip_rdreq_s0 : std_logic;
signal bus2ip_rdreq_s1 : std_logic;
signal Bus2IP_RdReq : std_logic; --REMOVE IF THIS BECOMES A PORT
signal wrreq : std_logic;
signal wrreq_hold : std_logic;
signal wrreq_hold_rst : std_logic;
signal bus2ip_wrreq_s0 : std_logic;
signal bus2ip_wrreq_s1 : std_logic;
signal Bus2IP_WrReq : std_logic; --REMOVE IF THIS BECOMES A PORT
-- ALS added write buffer signals
signal wrbuf_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_be : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal wrbuf_burst : std_logic;
signal wrbuf_xferack : std_logic;
signal wrbuf_errack : std_logic;
signal wrbuf_retry : std_logic;
signal wrbuf_cs : std_logic_vector(0 to NUM_ARDS-1);
signal wrbuf_rnw : std_logic;
signal wrbuf_ce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_wrce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_rdce : std_logic_vector(0 to NUM_CES-1);
signal wrbuf_empty : std_logic;
signal wrbuf_addrcntr_en : std_logic;
signal wrbuf_addrcntr_rst : std_logic;
signal wrbuf_addrvalid : std_logic;
signal ipic_pstage_ce : std_logic;
signal wrdata_ack : std_logic;
signal wrbuf_addrack : std_logic;
-- ALS added transfer start and done signals
signal opb_xfer_done : std_logic;
signal opb_xfer_start : std_logic;
constant NUM_ENCODED_SIZE_BITS : natural := 3;
type OR_CSES_PER_BIT_TABLE_TYPE is array(0 to NUM_ENCODED_SIZE_BITS-1) of
std_logic_vector(0 to NUM_ARDS-1);
signal cs_to_or_for_dsize_bit : OR_CSES_PER_BIT_TABLE_TYPE;
signal encoded_dsize_s0 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal encoded_dsize_s1 : std_logic_vector(0
to NUM_ENCODED_SIZE_BITS-1);
signal ip2bus_data_mx : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal sln_dbus_s2 : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal ipic_xferack : std_logic;
signal sln_xferack_s1 : std_logic;
signal sln_xferack_s1_d1 : std_logic;
signal sln_xferack_s1_d2 : std_logic;
signal sln_xferack_s2 : std_logic;
signal sln_retry_s1 : std_logic;
signal sln_retry_s1_d1 : std_logic;
signal sln_retry_s1_d2 : std_logic;
signal sln_retry_s2 : std_logic;
signal sln_errack_s1 : std_logic;
signal sln_errack_s2 : std_logic;
signal sln_toutsup_s1 : std_logic;
signal sln_toutsup_s2 : std_logic;
signal reset2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal reset2bus_ack : std_logic;
signal reset2bus_error : std_logic;
signal reset2bus_retry : std_logic;
signal reset2bus_toutsup : std_logic;
signal reset2bus_postedwrinh : std_logic;
-- interrupt signals
signal intr2bus_data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal intr2bus_rdack : std_logic;
signal intr2bus_wrack : std_logic;
signal intr2bus_ack : std_logic;
signal intr2bus_error : std_logic;
signal intr2bus_retry : std_logic;
signal intr2bus_toutsup : std_logic;
signal intr2bus_postedwrinh : std_logic;
-- FIFO signals
signal rfifo_error : std_logic;
signal rfifo_rdack : std_logic;
signal rfifo_retry : std_logic;
signal rfifo_toutsup : std_logic;
signal rfifo_wrack : std_logic;
signal rdfifo_ack : std_logic;
signal rdfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal rdfifo2intr_deadlock : std_logic;
signal wfifo_error : std_logic;
signal wfifo_rdack : std_logic;
signal wfifo_retry : std_logic;
signal wfifo_toutsup : std_logic;
signal wfifo_wrack : std_logic;
signal wrfifo_ack : std_logic;
signal wrfifo2bus_data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal wrfifo2intr_deadlock : std_logic;
signal new_pw_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal new_pw_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_when_pw : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_wnot_pw : std_logic;
signal inh_xferack_when_pw : std_logic;
signal inh_xferack_when_burst_rd: std_logic;
signal last_xferack : std_logic;
signal last_xferack_s0 : std_logic;
signal last_xferack_d1 : std_logic;
signal last_xferack_d1_s0 : std_logic;
signal last_xferack_d2 : std_logic;
signal last_pw_xferack : std_logic;
signal last_pw_xferack_d1 : std_logic;
signal last_pw_xferack_d2 : std_logic;
-- signal last_wr_xferack : std_logic;
-- signal last_wr_xferack_d1 : std_logic;
-- signal last_wr_xferack_d2 : std_logic;
signal last_burstrd_xferack : std_logic;
signal last_burstrd_xferack_d1 : std_logic;
signal last_burstrd_xferack_d2 : std_logic;
signal OPB_seqAddr_eff : std_logic;
signal postedwr_s0 : std_logic;
signal postedwrack_s2 : std_logic;
signal cycle_abort : std_logic;
signal cycle_abort_d1 : std_logic;
signal xfer_abort : std_logic;
signal cycle_active : std_logic;
signal ip2bus_postedwrinh_s1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d1 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_postedwrinh_s2_d2 : std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
signal ip2bus_xferack : std_logic;
-------------------------------------------------------------------------------
begin
OPB_seqAddr_eff <= OPB_seqAddr and bo2sl(C_DEV_BURST_ENABLE=1);
bus2ip_clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
Bus2IP_Freeze <= Freeze;
reset2bus_postedwrinh <= '1'; --GB
intr2bus_postedwrinh <= '1';
---------------------------------------------------------------------------
-- Pipeline Stage 0
---------------------------------------------------------------------------
GEN_PSTAGE0: if INCLUDE_OPBIN_PSTAGE generate
begin
PROC_PSTAGE0 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
opb_select_s0 <= '0';
bus2ip_cs_hit_s0 <= (others => '0'); -- GAB 10/12/05
else
opb_select_s0 <= OPB_select;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
end if;
end process;
end generate;
--
GEN_BYPASS0: if not INCLUDE_OPBIN_PSTAGE generate
begin
opb_select_s0 <= OPB_select;
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
last_xferack_s0 <= last_xferack;
last_xferack_d1_s0 <= last_xferack_d1;
bus2ip_cs_hit_s0 <= bus2ip_cs_hit; -- GAB 10/12/05
end generate;
---------------------------------------------------------------------------
-- Pipeline Stage 1
---------------------------------------------------------------------------
GEN_PSTAGE1: if INCLUDE_IPIC_PSTAGE generate
begin
-- RdReq and WrReq need to be registered for this stage independent
-- of write buffer inclusion
PROC_PSTAGE1_RDWR_REQ : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= '0';
bus2ip_wrreq_s1 <= '0';
encoded_dsize_s1 <= (others => '0');
else
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
encoded_dsize_s1 <= encoded_dsize_s0;
end if;
end if;
end process PROC_PSTAGE1_RDWR_REQ;
-- Write Buffer takes place of IPIC PSTAGE for the remaining signals
-- register in this stage only if Write Buffer is not included
WRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 1 generate
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
bus2ip_be_s1 <= wrbuf_be;
bus2ip_addr_s1 <= opb_addr_cntr_out;
end generate WRBUF_IPIC_PSTAGE_GEN;
NOWRBUF_IPIC_PSTAGE_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
PROC_PSTAGE1 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
bus2ip_cs_s1 <= (others => '0');
bus2ip_ce_s1 <= (others => '0');
bus2ip_rdce_s1 <= (others => '0');
bus2ip_wrce_s1 <= (others => '0');
bus2ip_addrvalid_s1 <= '0';
else
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
end if;
end process PROC_PSTAGE1;
-- If the address counter is included, it represents the S1 register stage
-- It is just necessary to register the BEs
-- If the address counter is not included, create the register stage for both
-- the address and the BEs
ADDRCNT_IPIC_STAGE: if INCLUDE_ADDR_CNTR generate
bus2ip_addr_s1 <= opb_addr_cntr_out;
ADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process ADDRCNT_IPIC_REG_PROC;
end generate ADDRCNT_IPIC_STAGE;
NOADDRCNT_IPIC_STAGE: if not(INCLUDE_ADDR_CNTR) generate
NOADDRCNT_IPIC_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be; -- BEs output from steering logic
end if;
end process NOADDRCNT_IPIC_REG_PROC;
end generate NOADDRCNT_IPIC_STAGE;
end generate NOWRBUF_IPIC_PSTAGE_GEN;
end generate GEN_PSTAGE1;
--
GEN_BYPASS1: if not INCLUDE_IPIC_PSTAGE generate
begin
bus2ip_cs_s1 <= wrbuf_cs;
bus2ip_ce_s1 <= wrbuf_ce;
bus2ip_wrce_s1 <= wrbuf_wrce;
bus2ip_data_s1 <= wrbuf_data;
bus2ip_rnw_s1 <= wrbuf_rnw;
bus2ip_burst_s1 <= wrbuf_burst;
bus2ip_addrvalid_s1 <= wrbuf_addrvalid;
encoded_dsize_s1 <= encoded_dsize_s0;
bus2ip_rdce_s1 <= wrbuf_rdce;
bus2ip_addr_s1 <= opb_addr_cntr_out;
bus2ip_be_s1 <= wrbuf_be;
-- ALS - added bus2ip_rdreq and bus2ip_wrreq
bus2ip_rdreq_s1 <= bus2ip_rdreq_s0;
bus2ip_wrreq_s1 <= bus2ip_wrreq_s0;
end generate GEN_BYPASS1;
Bus2IP_CS <= bus2ip_cs_s1;
Bus2IP_CE <= bus2ip_ce_s1;
Bus2IP_RdCE <= bus2ip_rdce_s1;
Bus2IP_WrCE <= bus2ip_wrce_s1;
Bus2IP_Addr <= bus2ip_addr_s1;
Bus2IP_Data <= bus2ip_data_s1;
Bus2IP_BE <= bus2ip_be_s1;
Bus2IP_RNW <= bus2ip_rnw_s1;
Bus2IP_Burst <= bus2ip_burst_s1 and or_reduce(bus2ip_cs_s1);
Bus2IP_AddrValid <= bus2ip_addrvalid_s1;
-- ALS - added Bus2IP_RdReq and Bus2IP_WrReq
-- ToDo - determine if these should be ports
Bus2IP_RdReq <= bus2ip_rdreq_s1;
Bus2IP_WrReq <= bus2ip_wrreq_s1;
ip2bus_postedwrinh_s1 <= IP2Bus_PostedWrInh; --GB
---------------------------------------------------------------------------
-- Pipeline Stage 2
---------------------------------------------------------------------------
GEN_PSTAGE2: if INCLUDE_OPBOUT_PSTAGE generate
begin
PROC_PSTAGE2 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need to be reset by OPB_Select
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if OPB_Select = '0' then
sln_xferack_s2 <= '0';
sln_errack_s2 <= '0';
sln_retry_s2 <= '0';
sln_toutsup_s2 <= '0';
-- ip2bus_postedwrinh_s2 <= (others => '0'); --GB
else
sln_xferack_s2 <= sln_xferack_s1 and not cycle_abort ;
sln_retry_s2 <= sln_retry_s1 ;
sln_errack_s2 <= sln_errack_s1 ;
sln_toutsup_s2 <= sln_toutsup_s1;
-- ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end if;
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if (Reset or not (sln_xferack_s1 and bus2ip_rnw_s1)) = '1' then
sln_dbus_s2 <= (others => '0');
else
sln_dbus_s2 <= sln_dbus_s1;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end if;
end process;
end generate;
--
GEN_BYPASS2: if not INCLUDE_OPBOUT_PSTAGE generate
begin
sln_dbus_s2 <= sln_dbus_s1;
sln_xferack_s2 <= sln_xferack_s1 and OPB_Select;
sln_retry_s2 <= sln_retry_s1 and OPB_Select;
sln_errack_s2 <= sln_errack_s1 and OPB_Select;
sln_toutsup_s2 <= sln_toutsup_s1 and OPB_Select;
postedwrack_s2 <= postedwr_s0;
ip2bus_postedwrinh_s2 <= ip2bus_postedwrinh_s1; --GB
end generate;
Sln_Dbus <= sln_dbus_s2;
Sln_xferAck <= sln_xferack_s2 and OPB_Select; --GB
Sln_retry <= sln_retry_s2 and OPB_Select; --GB
-- Sln_xferAck <= sln_xferack_s2 and OPB_Select and not(xfer_abort); --GB
-- Sln_retry <= (sln_retry_s2 or cycle_abort) and OPB_Select; --GB
Sln_errAck <= sln_errack_s2 and OPB_Select;
Sln_toutSup <= sln_toutsup_s2;
-----------------------------------------------------------------------------
-- Extend burst signal by 1 clock
-----------------------------------------------------------------------------
BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
opb_seqaddr_s0_d1 <= opb_seqaddr_s0;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of devicesel_s0
-----------------------------------------------------------------------------
DEVICESEL_S0_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => K_DEV_ADDR_DECODE_WIDTH,
C_AW => C_OPB_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0, -- GAB 10/12/05
-- AValid => opb_select_s0, -- GAB 10/12/05
-- CS => devicesel_s0 -- GAB 10/12/05
A => OPB_abus, -- GAB 10/12/05
AValid => OPB_select, -- GAB 10/12/05
CS => devicesel -- GAB 10/12/05
);
------------------------------------------------------------------------------
-- Determination of clock periods on which IPIC transactions are blocked
-- from starting, either because
-- (1) an acknowledged IPIC transaction is finishing and being cleared
-- from the pipeline, or
-- (2) the posted-write pipeline is filling.
-----------------------------------------------------------------------------
DELAYS_FOR_BLK_PROC : process (OPB_Clk) is
begin
if OPB_Clk'event and OPB_Clk='1' then
sln_xferack_s1_d1 <= sln_xferack_s1;
sln_xferack_s1_d2 <= sln_xferack_s1_d1;
sln_retry_s1_d1 <= sln_retry_s1;
sln_retry_s1_d2 <= sln_retry_s1_d1;
opb_select_s0_d1 <= opb_select_s0;
new_pw_s0_d1 <= new_pw_s0;
opb_seqaddr_d1 <= OPB_seqAddr_eff;
-- last_wr_xferack_d1 <= last_wr_xferack;
-- last_wr_xferack_d2 <= last_wr_xferack_d1;
last_burstrd_xferack_d1 <= last_burstrd_xferack;
last_burstrd_xferack_d2 <= last_burstrd_xferack_d1;
bus2ip_cs_hit_s0_d1 <= bus2ip_cs_hit_s0;
ip2bus_postedwrinh_s2_d1 <= ip2bus_postedwrinh_s2;
ip2bus_postedwrinh_s2_d2 <= ip2bus_postedwrinh_s2_d1;
end if;
end process;
--ToDo, can bus2ip_clk_i be used on the above, as below?
DX_FFS_PROC : process (bus2ip_clk_i) is
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
last_xferack_d1 <= last_xferack;
last_xferack_d2 <= last_xferack_d1;
last_pw_xferack_d1 <= last_pw_xferack;
last_pw_xferack_d2 <= last_pw_xferack_d1;
end if;
end process;
-- Code below works with Write buffer included
-- inh_cs_wnot_pw <= bo2sl(
-- not (opb_rnw_s0='1' and OPB_seqAddr_s0='1')
-- -- Do not
-- and -- inhibit when a burst read
-- (
-- (sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
--
--
-- or (sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE or INCLUDE_OPBOUT_PSTAGE))
--
-- or (sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE and INCLUDE_OPBOUT_PSTAGE))
-- )
-- );
--
-- -- ABove works when burst enable, pipeline model 2, no writebuffer, doing back to back write/reads
-- -- But causes interrupts/ pfifo tests to fail
--
--
-- original code
INH_CS_NOWRBUF_GEN : if C_INCLUDE_WR_BUF = 0 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_retry_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
INH_CS_WRBUF_GEN : if C_INCLUDE_WR_BUF = 1 generate
inh_cs_wnot_pw <= bo2sl
(
-- Do not inhibit when a burst read
not (opb_rnw_s0='1' and opb_seqaddr_s0_d1='1')
and
(
(sln_xferack_s1='1' and (INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1='1' and (INCLUDE_OPBIN_PSTAGE
or INCLUDE_OPBOUT_PSTAGE))
or
(sln_xferack_s1_d2='1' and (INCLUDE_OPBIN_PSTAGE
and INCLUDE_OPBOUT_PSTAGE))
)
);
end generate;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_INH_CS_WPW_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i));
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or
(new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_NO_WRBUF;
GEN_INH_CS_WPW_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_pw_s0(i) <= ((bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or (last_xferack_d1_s0 and opb_select_s0))
and not opb_rnw_s0;
inh_cs_when_pw(i) <= bo2sl(
(new_pw_s0(i)='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or (new_pw_s0_d1(i)='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
end generate;
end generate GEN_INH_CS_WPW_WRBUF;
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
GEN_PWI_PROC_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
ip2bus_postedwrinh, bus2ip_cs_hit_s0,
opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or ( bus2ip_cs_hit_s0(i)
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => ip2bus_postedwrinh(i)
)
);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1'); --and C_DEV_BURST_ENABLE=1);--GB
end process;
end generate GEN_PWI_PROC_NO_WRBUF;
GEN_PWI_PROC_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
bus2ip_cs_hit_s0, opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or bus2ip_cs_hit_s0(i);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1' and C_DEV_BURST_ENABLE=1);
end process;
end generate GEN_PWI_PROC_WRBUF;
last_xferack <= sln_xferack_s2
and not OPB_seqAddr_eff
and not(last_xferack_d1);
last_burstrd_xferack <= sln_xferack_s2
and (not OPB_seqAddr_eff and opb_seqaddr_d1) -- falling edge of burst
and not(last_xferack_d1);
inh_xferack_when_burst_rd <= not(or_reduce(new_pw_s0)) and
( (last_burstrd_xferack and bo2sl(INCLUDE_OPBOUT_PSTAGE))
or (last_burstrd_xferack_d1 and bo2sl(INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_burstrd_xferack_d2 and bo2sl(INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
last_pw_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff and postedwrack_s2;
inh_xferack_when_pw <=
bo2sl((last_pw_xferack='1' and (INCLUDE_OPBOUT_PSTAGE))
or
(last_pw_xferack_d1='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_pw_xferack_d2='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
-----------------------------------------------------------------------------
-- ALS: added register to extend burst signal 1 clock
-----------------------------------------------------------------------------
BUS2IP_BURST_EXTEND_PROCESS: process (bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i = '1' then
bus2ip_burst_s1_d1 <= bus2ip_burst_s1;
end if;
end process BUS2IP_BURST_EXTEND_PROCESS;
-----------------------------------------------------------------------------
-- Start and end of transaction detection
-----------------------------------------------------------------------------
opb_xfer_done <= (last_xferack
or sln_retry_s2
-- detected master abort (required for some pipe models)
or (xfer_abort )
-- master abort
or (not(opb_select_s0) and (opb_select_s0_d1) ) );
-- Not being used
-- XFER_DONE_REG_I: FDR
-- port map (
-- Q => opb_xfer_done_d1, --[out]
-- C => bus2ip_clk_i, --[in]
-- D => opb_xfer_done, --[in]
-- R => bus2ip_reset_i --[in]
-- );
-- New xfer starts when any CS is asserted and on the next clock
-- after xfer done if select is still asserted, or on the rising edge
-- of select
opb_xfer_start <= (or_reduce(bus2ip_cs_hit_s0) and not xfer_abort and --GB
( (opb_select_s0 and last_xferack_d1_s0)
or (opb_select_s0 and not(opb_select_s0_d1)) ) );
------------------------------------------------------------------------------
-- ALS: added address counter and BE generator
-- Generation of address counter and BE generator
-- When the IPIC pipe stage is included, a registered counter is used. The counter
-- register acts as the IPIC pipe stage register. The CE
-- generation logic needs the next address count so that the output CEs are
-- in alignment with the address
-- When the IPIC pipe stage is not included, a direct path counter is used.
-- The next address count is the same as the address count and the output CEs
-- will align with the address.
-- Steer address counter generates the addresses on each IP2Bus Ack
-- for use in generating the byte enables
------------------------------------------------------------------------------
ADDRCNT_BE_GEN: if INCLUDE_ADDR_CNTR or C_INCLUDE_WR_BUF = 1 generate
signal byte_xfer : std_logic;
signal hw_xfer : std_logic;
signal fw_xfer : std_logic;
signal addrcntr_en : std_logic;
signal steeraddr_cnt_en : std_logic;
begin
addrcntr_en <= IP2Bus_AddrAck
and wrbuf_addrcntr_en
and bus2ip_burst_s1;
steeraddr_cnt_en <= IP2Bus_Ack and bus2ip_burst_s1;
address_load <= opb_xfer_start and wrbuf_empty;
BE_GEN_I: entity opb_v20_v1_10_d.opb_be_gen
generic map (
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_WR_BUF => C_INCLUDE_WR_BUF
)
port map (
Bus_clk => bus2ip_clk_i,
Address_in => next_steer_addr_cntr_out,
BE_in => opb_be_s0,
Load_BE => address_load,
Rst_BE => bus2ip_reset_i,
BE_out => opb_be_cntr_out,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer
);
DIRECTPATH_CNTR_GEN: if not(INCLUDE_IPIC_PSTAGE) and C_INCLUDE_WR_BUF=0 generate
-- since no IPIC pipe stage, use direct path cntr so that there is not
-- a clock delay for loading the address
signal addr_cntr_load : std_logic;
begin
addr_cntr_load <= not((or_reduce(bus2ip_cs_hit_s0))) or opb_xfer_done;
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => addrcntr_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => opb_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_opb_addr_cntr_out <= opb_addr_cntr_out;
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH )
port map (
Address_in => opb_abus_s0,
Addr_load => addr_cntr_load,
Addr_CntEn => steeraddr_cnt_en,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Address_out => steer_addr_cntr_out,
OPB_Clk => bus2ip_clk_i);
-- since directpath cntr, next count value is the same as the count value
next_steer_addr_cntr_out <= steer_addr_cntr_out;
end generate DIRECTPATH_CNTR_GEN;
REG_CNTR_GEN: if INCLUDE_IPIC_PSTAGE or C_INCLUDE_WR_BUF = 1 generate
-- since IPIC pipe stage, use registered counter. This will act as the pipe stage
-- for the address. The CEs will use the un-registered counter address so that
-- they align with the address after going through the pipe stage
BUS2IPADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => addrcntr_en,
Addr_Cnt_rst => wrbuf_addrcntr_rst,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_opb_addr_cntr_out,
Address_Out => opb_addr_cntr_out
);
STEERADDR_CNTR_I: entity opb_v20_v1_10_d.brst_addr_cntr_reg
generic map (
C_CNTR_WIDTH => MAX_USER_ADDR_RANGE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Xfer_done => opb_xfer_done,
RNW => wrbuf_rnw,
Addr_Load => address_load,
Addr_Cnt_en => steeraddr_cnt_en,
Addr_Cnt_rst => bus2ip_reset_i,
Address_In => opb_abus_s0,
Byte_xfer => byte_xfer,
Hw_xfer => hw_xfer,
Fw_xfer => fw_xfer,
Next_address_out => next_steer_addr_cntr_out,
Address_Out => steer_addr_cntr_out
);
end generate REG_CNTR_GEN;
end generate ADDRCNT_BE_GEN;
NO_ADDRCNT_BE_GEN: if not(INCLUDE_ADDR_CNTR) and C_INCLUDE_WR_BUF = 0 generate
next_opb_addr_cntr_out <= opb_abus_s0;
opb_addr_cntr_out <= opb_abus_s0;
next_steer_addr_cntr_out<= opb_abus_s0;
steer_addr_cntr_out <= opb_abus_s0;
opb_be_cntr_out <= opb_be_s0;
address_load <= '1';
end generate NO_ADDRCNT_BE_GEN;
-----------------------------------------------------------------------------
-- Generation of Write Buffer
-----------------------------------------------------------------------------
WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 1 generate
begin
wrbuf_addrack <= IP2Bus_AddrAck;
wrdata_ack <= '1' when (ipic_xferack='1' and wrbuf_rnw='0')
else '0';
WRITE_BUF: entity opb_v20_v1_10_d.write_buffer
generic map ( C_INCLUDE_OPBIN_PSTAGE => INCLUDE_OPBIN_PSTAGE,
C_INCLUDE_IPIC_PSTAGE => INCLUDE_IPIC_PSTAGE,
C_INCLUDE_OPBOUT_PSTAGE => INCLUDE_OPBOUT_PSTAGE,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_WRBUF_DEPTH => WRBUF_DEPTH,
C_NUM_CES => NUM_CES,
C_NUM_ARDS => NUM_ARDS
)
port map (
Bus_reset => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Data_in => bus2ip_data_s0,
CE => bus2ip_ce_s0,
Wr_CE => bus2ip_wrce_s0,
Rd_CE => bus2ip_rdce_s0,
RNW => opb_rnw_s0,
CS_hit => bus2ip_cs_hit_s0,
CS => bus2ip_cs_s0,
CS_enable => bus2ip_cs_enable_s0,
Burst => opb_seqaddr_s0,
Xfer_start => opb_xfer_start,
Xfer_done => opb_xfer_done,
Addr_ack => wrbuf_addrack,
Wrdata_ack => wrdata_ack,
WrBuf_data => wrbuf_data,
WrBuf_burst => wrbuf_burst,
WrBuf_xferack => wrbuf_xferack,
WrBuf_errack => wrbuf_errack,
WrBuf_retry => wrbuf_retry,
WrBuf_CS => wrbuf_cs,
WrBuf_RNW => wrbuf_rnw,
WrBuf_CE => wrbuf_ce,
WrBuf_WrCE => wrbuf_wrce,
WrBuf_RdCE => wrbuf_rdce,
WrBuf_Empty => wrbuf_empty,
WrBuf_AddrCnt_en => wrbuf_addrcntr_en,
WrBuf_AddrCntr_rst => wrbuf_addrcntr_rst,
WrBuf_AddrValid => wrbuf_addrvalid,
IPIC_Pstage_CE => ipic_pstage_ce
);
-- inclusion of write buffer requires the BEs to be registered
BE_REG_PROC : process(bus2ip_clk_i)
begin
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if bus2ip_reset_i = '1' then
wrbuf_be <= (others => '0');
else
wrbuf_be <= opb_be_cntr_steer;
end if;
end if;
end process BE_REG_PROC;
end generate WRITE_BUFFER_GEN;
NO_WRITE_BUFFER_GEN: if C_INCLUDE_WR_BUF = 0 generate
begin
wrbuf_data <= bus2ip_data_s0;
wrbuf_burst <= opb_seqaddr_s0;
wrbuf_xferack <= '0';
wrbuf_errack <= '0';
wrbuf_retry <= '0';
wrbuf_cs <= bus2ip_cs_s0;
wrbuf_rnw <= opb_rnw_s0;
wrbuf_ce <= bus2ip_ce_s0;
wrbuf_wrce <= bus2ip_wrce_s0;
wrbuf_rdce <= bus2ip_rdce_s0;
wrbuf_empty <= '1';
wrbuf_addrcntr_en <= '1';
wrbuf_addrcntr_rst <= '0';
wrbuf_addrvalid <= or_reduce(bus2ip_ce_s0);
wrbuf_be <= opb_be_cntr_steer;
ipic_pstage_ce <= '1';
end generate NO_WRITE_BUFFER_GEN;
------------------------------------------------------------------------------
-- Generation of per-address-range mechanism.
------------------------------------------------------------------------------
PER_AR_GEN: for i in 0 to NUM_ARDS-1 generate
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,i);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= log2(C_ARD_NUM_CE_ARRAY(i));
constant OFFSET : integer
:= log2(C_ARD_DWIDTH_ARRAY(i)/8);
-- OFFSET gives the number of address bits corresponding to the
-- DWIDTH of the address range, e.g. zero for bytes, 1 for
-- doublets, 2 for quadlets, 3 for octlets, etc.
begin
--------------------------------------------------------------------------
-- CS decoders
--------------------------------------------------------------------------
CS_I: entity opb_v20_v1_10_d.pselect
generic map (
C_AB => - K_DEV_ADDR_DECODE_WIDTH
+ num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_OPB_AWIDTH,
i),
C_AW => C_OPB_AWIDTH - K_DEV_ADDR_DECODE_WIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(i*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_OPB_AWIDTH
+ K_DEV_ADDR_DECODE_WIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
-- A => opb_abus_s0(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1),
-- AValid => devicesel_s0, --NEW GB
-- CS => bus2ip_cs_hit_s0(i)
A => opb_abus(K_DEV_ADDR_DECODE_WIDTH to C_OPB_AWIDTH-1), -- GAB 10/12/05
AValid => devicesel, -- GAB 10/12/05
CS => bus2ip_cs_hit(i) -- GAB 10/12/05
);
--
-- ToDo, pselect above and AND gate below can
-- be optimized later with a special pselect that
-- has outputs for both bus2ip_cs_s0 and bus2ip_cs_hit_s0.
--
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
-- bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw --GB
--
-- when C_DEV_BURST_ENABLE=0 or
--
-- (opb_seqaddr_s0 = '0'and opb_seqaddr_s0_d1 = '0') or
-- opb_rnw_s0 = '1' or
-- eff_ip2bus_val(
-- i =>i,
-- rst =>reset2bus_postedwrinh,
-- intr=>intr2bus_postedwrinh,
-- wrfifo=>'0',
-- rdfifo=>'0',
-- user=> ip2bus_postedwrinh(i)
-- --user=>ip2bus_postedwrinh
-- )='1'
-- else
-- not inh_cs_when_pw(i);
GEN_CS_ENABLE_NOWRBUF : if C_INCLUDE_WR_BUF = 0 generate --GB
bus2ip_cs_enable_s0(i) <= not(inh_cs_wnot_pw)
when opb_rnw_s0 = '1'
or eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
-- user => ip2bus_postedwrinh(i)
user => (ip2bus_postedwrinh_s2_d1(i)
and bo2sl(INCLUDE_OPBIN_PSTAGE))
or (ip2bus_postedwrinh_s2(i)
and bo2sl(not INCLUDE_OPBIN_PSTAGE))
)='1'
else not(inh_cs_when_pw(i));
end generate GEN_CS_ENABLE_NOWRBUF;
GEN_CS_ENABLE_WRBUF : if C_INCLUDE_WR_BUF = 1 generate --GB
bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw
when C_DEV_BURST_ENABLE=0
or (opb_seqaddr_s0 = '0'
and opb_seqaddr_s0_d1 = '0')
or opb_rnw_s0 = '1'
else not inh_cs_when_pw(i);
end generate GEN_CS_ENABLE_WRBUF;
bus2ip_cs_s0(i) <= bus2ip_cs_hit_s0(i) and bus2ip_cs_enable_s0(i);
-------------------------------------------------------------------------
-- Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(i) - 1 generate
begin
----------------------------------------------------------------------
-- CE decoders
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1)
:= std_logic_vector(TO_UNSIGNED(j, CE_ADDR_SIZE));
begin
CE_I : entity opb_v20_v1_10_d.pselect
generic map (
C_AB => CE_ADDR_SIZE,
C_AW => CE_ADDR_SIZE,
C_BAR => BAR
)
port map (
A => next_opb_addr_cntr_out(C_OPB_AWIDTH - OFFSET - CE_ADDR_SIZE to
C_OPB_AWIDTH - OFFSET - 1),
AValid => bus2ip_cs_s0(i),
CS => bus2ip_ce_s0(CE_INDEX_START+j)
);
end generate;
--
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
bus2ip_ce_s0(CE_INDEX_START+j) <= bus2ip_cs_s0(i);
end generate;
--
----------------------------------------------------------------------
-- RdCE decoders
----------------------------------------------------------------------
bus2ip_rdce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and opb_rnw_s0;
----------------------------------------------------------------------
-- WrCE decoders
----------------------------------------------------------------------
bus2ip_wrce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and not opb_rnw_s0;
----------------------------------------------------------------------
end generate PER_CE_GEN;
end generate PER_AR_GEN;
------------------------------------------------------------------------
-- Master Abort Detection --GB
------------------------------------------------------------------------
-- This process detects when an abort occurs from the master.
-- and is used to gate off sln_xferack and sln_retry from the bus
--
GEN_ABORTS_FOR_1_3_7 : if (INCLUDE_OPBIN_PSTAGE and not (INCLUDE_OPBOUT_PSTAGE))
or (INCLUDE_OPBIN_PSTAGE and INCLUDE_IPIC_PSTAGE) generate
ABORT_DET : process(bus2ip_clk_i)
begin
if(bus2ip_clk_i'EVENT and bus2ip_clk_i='1')then
if(Reset = '1' or last_xferack_d1 = '1'
or or_reduce(bus2ip_cs_hit_s0) = '0' or sln_retry_s2 = '1')then
cycle_active <= '0';
elsif(or_reduce(bus2ip_cs_hit_s0) = '1' and sln_retry_s2 = '0')then
cycle_active <= '1';
end if;
cycle_abort_d1 <= cycle_abort;
end if;
end process ABORT_DET;
cycle_abort <= '1' when ( cycle_active = '1'
and or_reduce(bus2ip_cs_hit_s0) = '0'
and last_xferack_d1 = '0')
else '0';
GEN_XFERABORT_FOR_1_3 : if INCLUDE_OPBIN_PSTAGE and not(INCLUDE_OPBOUT_PSTAGE) generate
xfer_abort <= cycle_abort or cycle_abort_d1;
end generate;
GEN_XFERABORT_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE) or INCLUDE_OPBOUT_PSTAGE generate
xfer_abort <= cycle_abort;
end generate;
end generate GEN_ABORTS_FOR_1_3_7;
-- Abort logic is not needed for pipeline models 0,2,4,5, and 6
GEN_NOABORTS_FOR_REST : if not(INCLUDE_OPBIN_PSTAGE)
or (not(INCLUDE_IPIC_PSTAGE) and INCLUDE_OPBOUT_PSTAGE) generate
begin
xfer_abort <= '0';
cycle_abort <= '0';
end generate GEN_NOABORTS_FOR_REST;
------------------------------------------------------------------------------
-- This process selects the set of CS signals that activate a given bit of the
-- encoded size.
------------------------------------------------------------------------------
ENCODE_SIZE_BIT_SEL_PROC : process (bus2ip_cs_s0)
type NAT_ARRAY_TYPE is array(natural range <>) of natural;
variable next_bit : NAT_ARRAY_TYPE(0 to 2);
begin
next_bit := (others => 0);
for i in 0 to NUM_ARDS-1 loop
for j in 0 to NUM_ENCODED_SIZE_BITS-1 loop
if encoded_size_is_1(i,j) then
cs_to_or_for_dsize_bit(j)(next_bit(j)) <= bus2ip_cs_s0(i);
next_bit(j) := next_bit(j)+1;
end if;
end loop;
end loop;
end process;
------------------------------------------------------------------------------
-- This generates the encoded data size as a function of the address range
-- being addressed.
------------------------------------------------------------------------------
ENCODED_SIZE_CS_OR_GEN : for i in 0 to NUM_ENCODED_SIZE_BITS-1 generate
begin
----------------------------------------------------------------------------
-- If no address range requires the bit high, then fix it low.
----------------------------------------------------------------------------
ALWAYS_LOW_GEN : if num_cs_for_bit(i) = 0 generate
encoded_dsize_s0(i) <= '0';
end generate;
----------------------------------------------------------------------------
-- If all address ranges require the bit high, then fix it high.
----------------------------------------------------------------------------
ALWAYS_HIGH_GEN: if num_cs_for_bit(i) = NUM_ARDS generate
encoded_dsize_s0(i) <= '1';
end generate;
----------------------------------------------------------------------------
-- If some address ranges require the bit high, and other address ranges
-- require it low, then OR together the CS signals for the address ranges
-- that require it high.
----------------------------------------------------------------------------
SOMETIMES_HIGH_GEN: if num_cs_for_bit(i) /= 0
and num_cs_for_bit(i) /= NUM_ARDS generate
-- instance of carry-chain OR for each bit
ENCODED_SIZE_OR : entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => num_cs_for_bit(i)
)
port map (
In_bus => cs_to_or_for_dsize_bit(i)(0 to num_cs_for_bit(i)-1),
Or_out => encoded_dsize_s0(i)
);
end generate;
end generate;
------------------------------------------------------------------------------
-- Steer write data from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the write data and BEs before the
-- write buffer
------------------------------------------------------------------------------
I_STEER_DATA : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => opb_dbus_s0,
Addr => opb_abus_s0,
BE_In => opb_be_s0,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => bus2ip_data_s0,
BE_Out => open,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Steer byte enables from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
-- this steering module is used to steer the byte enables output from
-- the address counter/be generator during reads
------------------------------------------------------------------------------
I_STEER_BE : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Addr => next_steer_addr_cntr_out,
BE_In => opb_be_cntr_out,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => open,
BE_Out => opb_be_cntr_steer,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Mirror read data to appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
------------------------------------------------------------------------------
I_MIRROR : entity opb_v20_v1_10_d.IPIF_Steer
generic map(
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Rd_Data_In => ip2bus_data_mx,
Decode_size => encoded_dsize_s1,
--Addr => bus2ip_addr_s1,
Addr => steer_addr_cntr_out,
Rd_Data_Out => sln_dbus_s1,
--
-- Wr steering tied off, see I_STEER
Wr_Data_In => ZSLV(0 to C_OPB_DWIDTH-1),
BE_In => ZSLV(0 to C_OPB_DWIDTH/8-1),
Wr_Data_Out => open,
BE_Out => open
);
-- Generate for pipeline model 0, 2, 4, 6
IP2BUS_XFERACK_0_2_GEN : if not(INCLUDE_OPBIN_PSTAGE) generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 1
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d1)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d1(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
-- Generate for pipeline model 1,3,5,and 7
IP2BUS_XFERACK_REST_GEN : if INCLUDE_OPBIN_PSTAGE generate
------------------------------------------------------------------------------
-- For inhibiting of posted writes IP2Bus_Ack needs to be gated off for 2
-- clocks during dynamic changes in the ip2bus_postedwrinh signal. During
-- reads and when the write buffer is instantiated simply pass IP2Bus_Ack
-- without gating it off.
------------------------------------------------------------------------------
-- GB
IP2BUS_XFERACK_PROC : process(bus2ip_cs_s1,IP2Bus_Ack,opb_rnw_s0,
ip2bus_postedwrinh_s2_d2)
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
r := r or (IP2Bus_Ack and bus2ip_cs_s1(i)
and
( (ip2bus_postedwrinh_s2_d2(i) and not(opb_rnw_s0))
or (opb_rnw_s0)
or (bo2sl(C_INCLUDE_WR_BUF=1))
));
end loop;
ip2bus_xferack <= r;
end process IP2BUS_XFERACK_PROC;
end generate;
------------------------------------------------------------------------------
-- Generation of sln_xferack.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
IPIC_XFERACK_PROC : process (bus2ip_cs_s1, bus2ip_cs_hit_s0,
opb_rnw_s0, ip2bus_xferack,
reset2bus_ack, intr2bus_ack,
reset2bus_postedwrinh, intr2bus_postedwrinh,
wrfifo_ack, rdfifo_ack,ip2bus_postedwrinh_s2_d2,
IP2Bus_PostedWrInh) is
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if (
-- GB - Removed check of postedwrinh when write buffer is instantiated. Write buffer
-- logic does not have postedwrinh implemented yet and this was causing a problem
-- with some of the configurations. When the write buffer is instantiated the
-- postedwrinh signal is ignored.
(bo2sl(C_INCLUDE_WR_BUF=0)
and eff_ip2bus_val(i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
wrfifo => '0',
rdfifo => '0',
user => IP2Bus_PostedWrInh(i))
)
or opb_rnw_s0
or bo2sl(C_INCLUDE_WR_BUF=1)) = '1' then
-- This is the case where transactions are reads, or writes
-- that are not posted or write buffer is included
r := r or (bus2ip_cs_s1(i)
and eff_ip2bus_val(i => i,
rst => reset2bus_ack,
intr => intr2bus_ack,
wrfifo => wrfifo_ack,
rdfifo => rdfifo_ack,
user => ip2bus_xferack --GB
));
else
-- posted writes, but no write buffer is included
r := r or bus2ip_cs_hit_s0(i);
end if;
end loop;
ipic_xferack <= r ;
end process ;
SLN_XFERACK_PROC : process (ipic_xferack, wrbuf_xferack, bus2ip_rnw_s1,
inh_xferack_when_pw , inh_xferack_when_burst_rd ) is
begin
if bus2ip_rnw_s1 = '0' then
if C_INCLUDE_WR_BUF = 1 then
sln_xferack_s1 <= wrbuf_xferack and not(inh_xferack_when_pw);
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_pw);
end if;
else
sln_xferack_s1 <= ipic_xferack and not (inh_xferack_when_burst_rd);
end if;
end process SLN_XFERACK_PROC;
------------------------------------------------------------------------------
-- Generation of sln_retry.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_RETRY_PROC : process (bus2ip_cs_s1, IP2Bus_Retry, reset2bus_retry,
intr2bus_retry,rfifo_retry, wfifo_retry,
wrbuf_retry, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_retry_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates Retry during write transfers
sln_retry_s1 <= wrbuf_retry;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_retry_help := reset2bus_retry;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_retry_help := intr2bus_retry;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_retry_help := rfifo_retry;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_retry_help := wfifo_retry;
else
ip2bus_retry_help := IP2Bus_Retry;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_retry_help);
end loop;
sln_retry_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_error.
-- ALS - modified to include read and write FIFOs
-- ALS - modified to include write buffer
------------------------------------------------------------------------------
SLN_ERRACK_PROC : process (bus2ip_cs_s1, IP2Bus_Error, reset2bus_error,
intr2bus_error, rfifo_error, wfifo_error,
wrbuf_errack, bus2ip_rnw_s1) is
variable r : std_logic;
variable ip2bus_error_help : std_logic;
begin
if C_INCLUDE_WR_BUF = 1 and bus2ip_rnw_s1 = '0' then
-- write buffer generates ErrAck during write transfers
sln_errack_s1 <= wrbuf_errack;
else
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_error_help := reset2bus_error;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_error_help := intr2bus_error;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_error_help := rfifo_error;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_error_help := wfifo_error;
else
ip2bus_error_help := IP2Bus_Error;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_error_help);
end loop;
sln_errack_s1 <= r;
end if;
end process;
------------------------------------------------------------------------------
-- Generation of sln_toutsup.
-- ALS - modified to include read and write FIFOs
------------------------------------------------------------------------------
SLN_TOUTSUP_PROC : process (bus2ip_cs_s1, IP2Bus_ToutSup, reset2bus_toutsup,
intr2bus_toutsup, rfifo_toutsup, wfifo_toutsup) is
variable r : std_logic;
variable ip2bus_toutsup_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_toutsup_help := reset2bus_toutsup;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_toutsup_help := intr2bus_toutsup;
elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX) or (i = RDFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := rfifo_toutsup;
elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX) or (i = WRFIFO_REG_CS_IDX)) then
ip2bus_toutsup_help := wfifo_toutsup;
else
ip2bus_toutsup_help := IP2Bus_ToutSup;
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_toutsup_help);
end loop;
sln_toutsup_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of ip2bus_data_mx, as a function of IP2Bus_Data
-- and bus2ip_rdce, using carry chain logic.
-- Note, internal address ranges such as RESET_MIR or Interrupt Source
-- controller are multiplexed into the appropriate "slot".
------------------------------------------------------------------------------
-- READMUX_GEN : if not SINGLE_CE generate
-- begin
-- READMUX_PROCESS: process(bus2ip_rdce_s1,
-- reset2bus_data,
-- intr2bus_data,
-- rdfifo2bus_data,
-- wrfifo2bus_data,
-- ip2bus_data)
-- begin
-- ip2bus_data_mx <= (others => '0');
-- for i in bus2ip_cs_s1'range loop
-- if bus2ip_cs_s1(i) = '1' then
-- if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
-- ip2bus_data_mx <= reset2bus_data;
-- elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
-- ip2bus_data_mx <= intr2bus_data;
-- elsif INCLUDE_RDFIFO and ((i = RDFIFO_DATA_CS_IDX)
-- or (i = RDFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= rdfifo2bus_data;
-- elsif INCLUDE_WRFIFO and ((i = WRFIFO_DATA_CS_IDX)
-- or (i = WRFIFO_REG_CS_IDX)) then
-- ip2bus_data_mx <= wrfifo2bus_data;
-- else
-- ip2bus_data_mx <= ip2bus_data;
-- end if;
-- end if;
-- end loop;
-- end process READMUX_PROCESS;
-- end generate;
READMUX_GEN : if not SINGLE_CE generate
begin
READMUX_PROCESS: process(reset2bus_data,
intr2bus_data,
rdfifo2bus_data,
wrfifo2bus_data,
ip2bus_data)
begin
for i in ip2bus_data_mx'range loop
ip2bus_data_mx(i) <= reset2bus_data(i)
or intr2bus_data(i)
or rdfifo2bus_data(i)
or wrfifo2bus_data(i)
or ip2bus_data(i);
end loop;
end process READMUX_PROCESS;
end generate;
READMUX_SINGLE_CE_GEN : if SINGLE_CE generate
begin
ip2bus_data_mx <= ip2bus_data;
end generate;
-- PER_BIT_GEN : for i in 0 to C_OPB_DWIDTH-1 generate
-- signal cry : std_logic_vector(0 to (Bus2IP_RdCE'length + 1)/2);
-- begin
-- cry(0) <= '0';
-- PER_CE_PAIR_GEN : for j in 0 to (Bus2IP_RdCE'length + 1)/2-1 generate
-- signal ip2bus_data_rmmx0 : std_logic;
-- signal ip2bus_data_rmmx1 : std_logic;
-- signal lut_out : std_logic;
-- constant nopad : boolean
-- := (j /= (Bus2IP_RdCE'length + 1)/2-1)
-- or (Bus2IP_RdCE'length mod 2 = 0);
-- begin
-- -----------------------------------------------------------------------
-- -- ToDo, the read-back mux can be optimized to exclude any data bits
-- -- that are not present in AR with DWIDTH less than C_OPB_DWIDTH...
-- -- possibly also for bits that are known to be not implemented, e.g.
-- -- a register that doesn't use all bit positions or is write-only.
-- -----------------------------------------------------------------------
-- -- LUT (last LUT may multiplex one data bit instead of two)
-- -----------------------------------------------------------------------
---- WOPAD : if nopad generate
---- signal ip2bus_data_rmmx0 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- signal ip2bus_data_rmmx1 : std_logic_vector(0 to C_OPB_DWIDTH-1);
---- begin
-- -------------------------------------------------------------------
-- -- Always include the first of two possilble mux channels thru LUT.
-- -------------------------------------------------------------------
-- ip2bus_data_rmmx0 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR -- ToDo, this is inefficient because
-- -- interrupt_control already multiplexes
-- -- the data. Optimize later.
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j >= INTR_CE_LO) and
-- (2*j <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j >= RFIFO_REG_CE_LO) and (2*j <= RFIFO_REG_CE_HI))
-- or
-- (2*j = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j >= WFIFO_REG_CE_LO) and (2*j <= WFIFO_REG_CE_HI))
-- or
-- (2*j = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j )*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- -------------------------------------------------------------------
-- -- Don't include second channel when odd number and on last LUT.
-- -------------------------------------------------------------------
-- WOPAD : if nopad generate
-- begin
-- ip2bus_data_rmmx1 <=
-- ----------------------------------------------
-- -- RESET_MIR
-- ----------------------------------------------
-- reset2bus_data(i)
-- when INCLUDE_RESET_MIR and
-- (2*j+1 = RESET_MIR_CE_IDX)
-- else
-- ----------------------------------------------
-- -- INTR
-- ----------------------------------------------
-- intr2bus_data(i)
-- when INCLUDE_INTR and
-- (2*j+1 >= INTR_CE_LO) and
-- (2*j+1 <= INTR_CE_HI)
-- else
-- ----------------------------------------------
-- -- Read FIFO
-- ----------------------------------------------
-- rdfifo2bus_data(i)
-- when INCLUDE_RDFIFO and (
-- ((2*j+1 >= RFIFO_REG_CE_LO) and (2*j+1 <= RFIFO_REG_CE_HI))
-- or
-- (2*j+1 = RFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- Write FIFO
-- ----------------------------------------------
-- wrfifo2bus_data(i)
-- when INCLUDE_WRFIFO and (
-- ((2*j+1 >= WFIFO_REG_CE_LO) and (2*j+1 <= WFIFO_REG_CE_HI))
-- or
-- (2*j+1 = WFIFO_DATA_CE) )
-- else
-- ----------------------------------------------
-- -- IP Core
-- ----------------------------------------------
-- --IP2Bus_Data((2*j+1)*C_OPB_DWIDTH + i);
-- IP2Bus_Data(i);
-- --lut_out <= not (
-- -- (ip2bus_data_rmmx0(i) and bus2ip_rdce_s1(2*j )) or
-- -- (ip2bus_data_rmmx1(i) and bus2ip_rdce_s1(2*j+1)));
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )) or
-- (ip2bus_data_rmmx1 and bus2ip_rdce_s1(2*j+1)));
-- end generate;
-- WIPAD : if not nopad generate
-- lut_out <= not (
-- (ip2bus_data_rmmx0 and bus2ip_rdce_s1(2*j )));
-- end generate;
-- -----------------------------------------------------------------------
-- -- MUXCY
-- -----------------------------------------------------------------------
-- I_MUXCY : MUXCY
-- port map (
-- O => cry(j+1),
-- CI => cry(j),
-- DI => '1',
-- S => lut_out
-- );
-- end generate;
-- ip2bus_data_mx(i) <= cry((Bus2IP_RdCE'length + 1)/2);
-- end generate;
-- end generate;
--
--
-- READMUX_SINGLE_CE_GEN : if SINGLE_CE and INCLUDE_OPBOUT_PSTAGE generate
-- begin
-- ip2bus_data_mx <= ip2bus_data;
-- end generate;
-------------------------------------------------------------------------------
-- Reset/MIR
-------------------------------------------------------------------------------
INCLUDE_RESET_MIR_GEN : if INCLUDE_RESET_MIR generate
begin
RESET_MIR_I0 : entity opb_v20_v1_10_d.reset_mir
Generic map (
C_DWIDTH => C_OPB_DWIDTH,
C_INCLUDE_SW_RST => 1,
C_INCLUDE_MIR => C_DEV_MIR_ENABLE,
C_MIR_MAJOR_VERSION => MIR_MAJOR_VERSION,
C_MIR_MINOR_VERSION => MIR_MINOR_VERSION,
C_MIR_REVISION => MIR_REVISION,
C_MIR_BLK_ID => C_DEV_BLK_ID,
C_MIR_TYPE => MIR_TYPE
)
port map (
Reset => Reset,
Bus2IP_Clk => bus2ip_clk_i,
SW_Reset_WrCE => bus2ip_wrce_s1(RESET_MIR_CE_IDX),
SW_Reset_RdCE => bus2ip_rdce_s1(RESET_MIR_CE_IDX),
Bus2IP_Data => bus2ip_data_s1,
Bus2IP_Reset => bus2ip_reset_i,
Reset2Bus_Data => reset2bus_data,
Reset2Bus_Ack => reset2bus_ack,
Reset2Bus_Error => reset2bus_error,
Reset2Bus_Retry => reset2bus_retry,
Reset2Bus_ToutSup => reset2bus_toutsup
);
end generate;
EXCLUDE_RESET_MIR_GEN : if not INCLUDE_RESET_MIR generate
begin
bus2ip_reset_i <= Reset;
reset2bus_data <= (others => '0');
reset2bus_ack <= '0';
reset2bus_error <= '0';
reset2bus_retry <= '0';
reset2bus_toutsup <= '0';
end generate;
Bus2IP_Reset <= bus2ip_reset_i;
-------------------------------------------------------------------------------
-- Interrupts
-- ALS - added interrupts from Read and Write FIFOs
-- ALS - added code to allow C_INCLUDE_DEV_ISC and C_INCLUDE_DEV_PENCODER to
-- come from dependent props array
-------------------------------------------------------------------------------
INTR_CTRLR_GEN : if INCLUDE_INTR generate
constant NUM_IPIF_IRPT_SRC : natural := 4;
constant INTR_INDEX : integer :=
get_id_index(C_ARD_ID_ARRAY, IPIF_INTR);
signal errack_reserved: std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector( 0 to NUM_IPIF_IRPT_SRC-1);
begin
errack_reserved <= Sln_errack_s2 & '0';
ipif_lvl_interrupts(0) <= '0'; -- assign to DMA2Intr_Intr(0) when DMA is added
ipif_lvl_interrupts(1) <= '0'; -- assign to DMA2Intr_Intr(1) when DMA is added
ipif_lvl_interrupts(2) <= rdfifo2intr_deadlock; -- = '0' if FIFOs not included
ipif_lvl_interrupts(3) <= wrfifo2intr_deadlock; -- = '0' if FIFOs not included
INTERRUPT_CONTROL_I : entity opb_v20_v1_10_d.interrupt_control
generic map (
C_INTERRUPT_REG_NUM => number_CEs_for(IPIF_INTR),
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(INCLUDE_DEV_PENCODER)=1,
C_INCLUDE_DEV_ISC => C_ARD_DEPENDENT_PROPS_ARRAY
(INTR_INDEX)(EXCLUDE_DEV_ISC)=0,
C_IRPT_DBUS_WIDTH => C_OPB_DWIDTH
)
port map (
Bus2IP_Clk_i => bus2ip_clk_i,
Bus2IP_Data_sa => bus2ip_data_s1,
Bus2IP_RdReq_sa => '0',
Bus2IP_Reset_i => bus2ip_reset_i,
Bus2IP_WrReq_sa => '0',
Interrupt_RdCE => bus2ip_rdce_s1(INTR_CE_LO to INTR_CE_HI),
Interrupt_WrCE => bus2ip_wrce_s1(INTR_CE_LO to INTR_CE_HI),
IPIF_Reg_Interrupts => errack_reserved,
-- ALS - modified to connect read and write FIFO interrupts
--IPIF_Lvl_Interrupts => ZERO_SLV(0 to NUM_IPIF_IRPT_SRC-1),
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error, -- These are tied low in block
Intr2Bus_Retry => intr2bus_retry, --
Intr2Bus_ToutSup => intr2bus_toutsup --
);
end generate;
REMOVE_INTERRUPT : if (not INCLUDE_INTR) generate
intr2bus_data <= (others => '0');
IP2INTC_Irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_retry <= '0';
intr2bus_toutsup <= '0';
intr2bus_wrack <= '0';
end generate REMOVE_INTERRUPT;
intr2bus_ack <= intr2bus_rdack or intr2bus_wrack;
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation if FIFOs are included
-------------------------------------------------------------------------------
NO_RDREQ_WRREQ_GEN: if not(INCLUDE_RDFIFO) and not(INCLUDE_WRFIFO) generate
bus2ip_rdreq_s0 <= '0';
bus2ip_wrreq_s0 <= '0';
end generate NO_RDREQ_WRREQ_GEN;
GEN_RDREQ_WREQ: if ((INCLUDE_RDFIFO) or (INCLUDE_WRFIFO)) generate
-- only 4 possible CS for FIFOs, size vector accordingly
signal fifo_cs : std_logic_vector(0 to 3);
signal any_fifo_cs : std_logic;
begin
-----------------------------------------------------------------------------
-- ALS - added process to generate read and write request
-- Generation of Bus2IP_RdReq and Bus2IP_WrReq stage 0 signals
-- These stage 0 signals will follow the pipeline models and generate statements
-- so that the appropriate stage 1 signal is created.
--
-- MODIFIED: 01/24/04 to be for any CS, not just FIFO CS - also
-- these signals will be qualified with ADDR
-- These signals assert for any FIFO CS. They are 1-clock pulse wide for single
-- transfers and stay asserted for burst transfers.
-----------------------------------------------------------------------------
GEN_PFIFOS_NO_WRBUF : if C_INCLUDE_WR_BUF = 0 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s0(RDFIFO_REG_CS_IDX) & bus2ip_cs_s0(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s0(WRFIFO_REG_CS_IDX) & bus2ip_cs_s0(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
GEN_PFIFOS_WITH_WRBUF : if C_INCLUDE_WR_BUF = 1 generate
BOTHFIFOS_GEN: if INCLUDE_RDFIFO and INCLUDE_WRFIFO generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX);
end generate BOTHFIFOS_GEN;
ONLY_RDFIFO_GEN: if INCLUDE_RDFIFO and not(INCLUDE_WRFIFO) generate
fifo_cs <= bus2ip_cs_s1(RDFIFO_REG_CS_IDX) & bus2ip_cs_s1(RDFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_RDFIFO_GEN;
ONLY_WRFIFO_GEN: if INCLUDE_WRFIFO and not(INCLUDE_RDFIFO) generate
fifo_cs <= bus2ip_cs_s1(WRFIFO_REG_CS_IDX) & bus2ip_cs_s1(WRFIFO_DATA_CS_IDX)
& "00";
end generate ONLY_WRFIFO_GEN;
end generate;
-- ToDo: see if LUT OR would be better here since max of 4 bits
ANYCS_OR_I: entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => 4
)
port map (
In_bus => fifo_cs,
Or_out => any_fifo_cs
);
-------------------------------------------------------------------------------
-- RDREQ_WRREQ Generation
-------------------------------------------------------------------------------
-- read request
rdreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '1' and rdreq_hold = '0'
else '0';
-- hold the value of rdreq by setting a flop when rdreq asserts
-- this is used to gate off rdreq to keep it a one-clock pulse
rdreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
RDREQ_HOLD_FF: FDRE
port map (
Q => rdreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> rdreq, --[in]
D => '1', --[in]
R => rdreq_hold_rst --[in]
);
RDREQ_PIPE0_GEN: if C_PIPELINE_MODEL=0 generate
begin
-- need to extend read req 1 clock after sequential address
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0_d1 and opb_rnw_s0);
end generate RDREQ_PIPE0_GEN;
RDREQ_PIPE_NOT0_GEN: if C_PIPELINE_MODEL /= 0 generate
-- generate bus2ip_rdreq by OR'ing the single pulse request with the burst
-- signal
bus2ip_rdreq_s0 <= rdreq or (opb_seqaddr_s0 and opb_rnw_s0);
end generate RDREQ_PIPE_NOT0_GEN;
WRREQ_GEN_FOR_PIPE_0_1 : if C_PIPELINE_MODEL = 0
or C_PIPELINE_MODEL = 1 generate
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0'
else '0';
end generate WRREQ_GEN_FOR_PIPE_0_1;
WRREQ_GEN_FOR_REST : if C_PIPELINE_MODEL /= 0
and C_PIPELINE_MODEL /= 1 generate
-- write request
wrreq <= '1'
when any_fifo_cs = '1' and opb_rnw_s0 = '0' and wrreq_hold='0'
else '0';
-- hold the value of wrreq by setting a flop when wrreq asserts
-- this is used to gate off wrreq to keep it a one-clock pulse
wrreq_hold_rst <= (not(sln_xferack_s1) and (sln_xferack_s1_d1))
or sln_retry_s1
or not(opb_select_s0);
WRREQ_HOLD_FF: FDRE
port map (
Q => wrreq_hold, --[out]
C => bus2ip_clk_i, --[in]
CE=> wrreq, --[in]
D => '1', --[in]
R => wrreq_hold_rst --[in]
);
end generate WRREQ_GEN_FOR_REST;
-- generate bus2ip_wrreq by OR'ing the single pulse request with the burst
-- signal extended by 1 clock so that the write request is valid during entire burst
-- for all pipeline models except 5
WRREQ_PIPE_NOT5_GEN: if C_PIPELINE_MODEL = 0 or
C_PIPELINE_MODEL = 1 or
C_PIPELINE_MODEL = 2 or
C_PIPELINE_MODEL = 3 or
C_PIPELINE_MODEL = 7 generate
bus2ip_wrreq_s0 <= wrreq or (not(opb_rnw_s0) and bus2ip_burst_s1);
end generate WRREQ_PIPE_NOT5_GEN;
-- for pipeline model 5, generate bus2ip_wrreq by OR'ing the single pulse request
-- with delayed version of the burst_s1 signal
WRREQ_PIPE5_GEN: if C_PIPELINE_MODEL=4 or
C_PIPELINE_MODEL=5 or
C_PIPELINE_MODEL=6 generate
begin
bus2ip_wrreq_s0 <= wrreq or (not(bus2ip_rnw_s1) and bus2ip_burst_s1_d1);
end generate WRREQ_PIPE5_GEN;
end generate GEN_RDREQ_WREQ;
-------------------------------------------------------------------------------
-- Bus2IP_RdAddrValid and Bus2IP_WrAddrValid Generation
-- These signals are a single pulse during single transactions and are extended
-- during burst transactions
--bus2ip_rdaddrvalid_s0 <= bus2ip_rdreq_s0 and wrbuf_addrvalid;
--bus2ip_wraddrvalid_s0 <= bus2ip_wrreq_s0 and wrbuf_addrvalid;
------------------------------------------------------------------------------
-- Read FIFO
------------------------------------------------------------------------------
INCLUDE_RDFIFO_GEN : if (INCLUDE_RDFIFO) generate
constant DATA_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
signal bus2ip_rdreq_rfifo: std_logic;
signal bus2ip_rdce3_rfifo: std_logic;
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for RDFIFO."
severity FAILURE;
--synopsys translate_on
----------------------------------------------------------------------------
-- For RDFIFO, trim Bus2IP_RdReq as needed per pipeline model. The RDFIFO
-- moves burst data on every cycle and requires that
-- OPB_seqAddr is low on the next-to-last cycle.
----------------------------------------------------------------------------
RDREQ_RDCE_PIPE0_GEN: if C_PIPELINE_MODEL = 0 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE0_GEN;
RDREQ_RDCE_PIPE124_GEN: if C_PIPELINE_MODEL=1 or
C_PIPELINE_MODEL=2 or
C_PIPELINE_MODEL=4 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1;
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE);
end generate RDREQ_RDCE_PIPE124_GEN;
RDREQ_RDCE_PIPE3_GEN: if C_PIPELINE_MODEL=3 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not opb_seqaddr_d1 and bus2ip_burst_s1);
end generate RDREQ_RDCE_PIPE3_GEN;
RDREQ_RDCE_PIPE56_GEN: if C_PIPELINE_MODEL = 5 or
C_PIPELINE_MODEL = 6 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and opb_seqaddr_d1);
end generate RDREQ_RDCE_PIPE56_GEN;
RDREQ_RDCE_PIPE7_GEN: if C_PIPELINE_MODEL = 7 generate
bus2ip_rdreq_rfifo <= bus2ip_rdreq_s1 and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
bus2ip_rdce3_rfifo <= bus2ip_rdce_s1(RFIFO_DATA_CE) and
not (not OPB_seqAddr_eff and (opb_seqaddr_d1 or bus2ip_burst_s1));
end generate RDREQ_RDCE_PIPE7_GEN;
I_RDFIFO: entity opb_v20_v1_10_d.rdpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_Clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_rfifo,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce3_rfifo,
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(RFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(RFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(RFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_Data => IP2RFIFO_Data,
-- Outputs to the IP
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty => open,
RFIFO2DMA_Empty => open,
RFIFO2DMA_Occupancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => rdfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => rdfifo2bus_data,
FIFO2Bus_WrAck => rfifo_wrack,
FIFO2Bus_RdAck => rfifo_rdack,
FIFO2Bus_Error => rfifo_error,
FIFO2Bus_Retry => rfifo_retry,
FIFO2Bus_ToutSup => rfifo_toutsup
);
end generate INCLUDE_RDFIFO_GEN;
REMOVE_RDFIFO_GEN : if (not INCLUDE_RDFIFO) generate
rdfifo2bus_data <= (others => '0');
rdfifo2intr_deadlock <= '0';
RFIFO2IP_AlmostFull <= '0';
RFIFO2IP_Full <= '0';
RFIFO2IP_Vacancy <= (others => '0');
RFIFO2IP_WrAck <= '0';
rfifo_error <= '0';
rfifo_rdack <= '0';
rfifo_retry <= '0';
rfifo_toutsup <= '0';
rfifo_wrack <= '0';
end generate REMOVE_RDFIFO_GEN;
rdfifo_ack <= rfifo_wrack or rfifo_rdack;
--------------------------------------------------------------------------------
-- Write FIFO
--------------------------------------------------------------------------------
INCLUDE_WRFIFO_GEN : if (INCLUDE_WRFIFO) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
begin
--synopsys translate_off
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the WRFIFO."
severity FAILURE;
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DWIDTH_ARRAY(DATA_INDEX)
report "This implementation of the OPB IPIF requires the write " &
" width to be equal to the data width specified in " &
" C_ARD_DWIDTH_ARRAY for WRFIFO."
severity FAILURE;
--synopsys translate_on
I_WRPFIFO_TOP: entity opb_v20_v1_10_d.wrpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_OPB_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => bus2ip_reset_i,
Bus_clk => bus2ip_clk_i,
Bus_RdReq => bus2ip_rdreq_s1,
Bus_WrReq => bus2ip_wrreq_s1,
Bus2FIFO_RdCE1 => bus2ip_rdce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_RdCE2 => bus2ip_rdce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_RdCE3 => bus2ip_rdce_s1(WFIFO_DATA_CE),
Bus2FIFO_WrCE1 => bus2ip_wrce_s1(WFIFO_REG_CE_LO),
Bus2FIFO_WrCE2 => bus2ip_wrce_s1(WFIFO_REG_CE_LO+1),
Bus2FIFO_WrCE3 => bus2ip_wrce_s1(WFIFO_DATA_CE),
Bus_DBus => bus2ip_data_s1,
-- Inputs from the IP
IP2WFIFO_RdReq => IP2WFIFO_RdReq,
IP2WFIFO_RdMark => IP2WFIFO_RdMark,
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore,
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease,
-- Outputs to the IP
WFIFO2IP_Data => WFIFO2IP_Data,
WFIFO2IP_RdAck => WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => WFIFO2IP_Empty,
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
-- Outputs to the IP
WFIFO2DMA_AlmostFull => open,
WFIFO2DMA_Full => open,
WFIFO2DMA_Vacancy => open,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => wrfifo2intr_deadlock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => wrfifo2bus_data,
FIFO2Bus_WrAck => wfifo_wrack,
FIFO2Bus_RdAck => wfifo_rdack,
FIFO2Bus_Error => wfifo_error,
FIFO2Bus_Retry => wfifo_retry,
FIFO2Bus_ToutSup => wfifo_toutsup
);
end generate INCLUDE_WRFIFO_GEN;
REMOVE_WRFIFO_GEN : if (not INCLUDE_WRFIFO) generate
WFIFO2IP_AlmostEmpty <= '0';
WFIFO2IP_Data <= (others => '0');
WFIFO2IP_Empty <= '0';
WFIFO2IP_Occupancy <= (others => '0');
WFIFO2IP_RdAck <= '0';
wfifo_error <= '0';
wfifo_rdack <= '0';
wfifo_retry <= '0';
wfifo_toutsup <= '0';
wfifo_wrack <= '0';
wrfifo2bus_data <= (others => '0');
wrfifo2intr_deadlock <= '0';
end generate REMOVE_WRFIFO_GEN;
wrfifo_ack <= wfifo_wrack or wfifo_rdack;
end implementation;
| bsd-3-clause | d1b57ade1462c7d1aa6e304af3ab6cb4 | 0.448244 | 4.132031 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_2.vhd | 2 | 17,268 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_2.c
-- RETURN_VALUE 31
-- reg4 = returnValue
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, &data->returnValue );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push &data->returnValue
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- if (data->returnValue == RETURN_VALUE ) retVal = SUCCESS;
-- else retVal = FAILURE;
when STATE_12 =>
-- Load the value of data->returnValue
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
if ( intrfc2thrd_value = x"0000001F" ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | be6ef0cf938d78917c23a0148f8ec46e | 0.544765 | 3.806878 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDEV2/tb_IDE_top_level.vhd | 1 | 4,579 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:38:05 12/15/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Desktop/IDEController/IDEController/tb_IDE_top_level.vhd
-- Project Name: IDEController
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IDE_top_level
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_IDE_top_level IS
END tb_IDE_top_level;
ARCHITECTURE behavior OF tb_IDE_top_level IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IDE_top_level
PORT(
W : IN std_logic;
R : IN std_logic;
Re : OUT std_logic;
CS : IN std_logic;
CPU_data : INOUT std_logic_vector(3 downto 0);
CS1FX : OUT std_logic;
CS3FX : OUT std_logic;
DA : OUT std_logic_vector(2 downto 0);
HD_data : INOUT std_logic_vector(7 downto 0);
DIOR : OUT std_logic;
DIOW : OUT std_logic;
reset : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal W : std_logic := '0';
signal R : std_logic := '0';
signal CS : std_logic := '0';
signal reset : std_logic := '0';
signal clk : std_logic := '0';
--BiDirs
signal CPU_data : std_logic_vector(3 downto 0);
signal HD_data : std_logic_vector(7 downto 0);
--Outputs
signal Re : std_logic;
signal CS1FX : std_logic;
signal CS3FX : std_logic;
signal DA : std_logic_vector(2 downto 0);
signal DIOR : std_logic;
signal DIOW : std_logic;
-- Clock period definitions
constant clk_period : time := 30 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IDE_top_level PORT MAP (
W => W,
R => R,
Re => Re,
CS => CS,
CPU_data => CPU_data,
CS1FX => CS1FX,
CS3FX => CS3FX,
DA => DA,
HD_data => HD_data,
DIOR => DIOR,
DIOW => DIOW,
reset => reset,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*6;
reset <= '1';
wait for clk_period*6;
--Setup
CS <= '0';
W <= '1';
CPU_data <= "0001";
wait for clk_period*6;
--State 0
W <= '0';
wait for clk_period*6;
CPU_data <= "0010";
wait for clk_period*6;
W <= '1';
wait for clk_period*6;
--State 1
W <= '0';
wait for clk_period*6;
CPU_data <= "0011";
wait for clk_period*6;
W <= '1';
wait for clk_period*6;
--State 2
W <= '0';
wait for clk_period*6;
CPU_data <= "ZZZZ";
wait for clk_period*6;
--State 3
R <= '1';
HD_data <= "10101110";
wait for clk_period*6;
R <= '0';
wait for clk_period*6;
--State 4
R <= '1';
wait for clk_period*6;
R <= '0';
HD_data <= "ZZZZZZZZ";
wait for clk_period*6;
--TESTING A WRITE
W <= '1';
wait for clk_period*6;
CPU_data <= "0001";
wait for clk_period*6;
--State 0
W <= '0';
wait for clk_period*6;
CPU_data <= "0010";
wait for clk_period*6;
W <= '1';
wait for clk_period*6;
--State 1
W <= '0';
wait for clk_period*6;
CPU_data <= "0011";
wait for clk_period*6;
W <= '1';
wait for clk_period*6;
--State 2
W <= '0';
wait for clk_period*6;
CPU_data <= "ZZZZ";
wait for clk_period*6;
--State 3
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 4
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
wait;
end process;
END;
| unlicense | a4eb5a0ff82be54655b1ab03d709caea | 0.55012 | 3.125597 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/ethrx_task/ethrx_task.vhd | 1 | 5,569 | ---------------------------------------------------------------------------------------------------
--
-- Title : ethrx_task
-- Design : eth_new
-- Author : dove
-- Company : google
--
---------------------------------------------------------------------------------------------------
--
-- File : ethrx_task.vhd
-- Generated : Sun Sep 3 10:52:10 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ethrx_task} architecture {arch_ethrx_task}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethrx_task is
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end ethrx_task;
--}} End of automatically maintained section
architecture arch_ethrx_task of ethrx_task is
component fifo_block
generic(
DWIDTH : INTEGER;
BLOCK_AWIDTH : INTEGER;
FIFO_AWIDTH : INTEGER;
RAM_TYPE : STRING
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component zcpsm2fifo
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_wr_block : out std_logic;
fifo_wren : out std_logic;
fifo_waddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_wdata : out std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic
);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_wren : std_logic;
signal fifo_waddr : std_logic_vector(TASKFIFO_BLOCK_AWIDTH - 1 downto 0);
signal fifo_wdata : std_logic_vector(TASKFIFO_DWIDTH - 1 downto 0);
signal fifo_db_wr_block : std_logic;
signal fifo_rxtask_wr_block : std_logic;
-- signal fifo_wr_block : std_logic;
begin
fifo_rxtask_wr_block <= fifo_db_wr_block or fifo_wr_block;
u_rx_task_fifo : fifo_block
generic map(
DWIDTH => TASKFIFO_DWIDTH,
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
FIFO_AWIDTH => TASKFIFO_AWIDTH,
RAM_TYPE => TASKFIFO_RAM_TYPE
)
port map(
clk => RxFIFO_R_Clk,
reset => reset,
clr => '0',
wr_block => fifo_rxtask_wr_block,
wr_clk => zcpsm_clk,
wren => fifo_wren,
waddr => fifo_waddr,
wdata => fifo_wdata,
rd_block => RxFIFO_R_Block,
rd_clk => RxFIFO_R_Clk,
raddr => RxFIFO_RAddr,
rdata => RxFIFO_RData,
empty => fifo_empty,
full => fifo_full
);
u_rx_zcpsm_task : zcpsm2fifo
generic map(
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
DWIDTH => TASKFIFO_DWIDTH
)
port map(
clk => RxFIFO_R_Clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
-- fifo_wr_block => open,
fifo_wr_block => fifo_db_wr_block,
fifo_wren => fifo_wren,
fifo_waddr => fifo_waddr,
fifo_wdata => fifo_wdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
RxFIFO_Empty <= fifo_empty;
RxFIFO_Full <= fifo_full;
-- enter your statements here --
end arch_ethrx_task;
| gpl-2.0 | 6405a99c7b3b4b1e1e3fa6e446329216 | 0.529 | 3.008644 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethrx.vhd | 1 | 10,801 | library ieee;
use ieee.std_logic_1164.all;
entity ethrx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 12;
FIFO_AWIDTH : natural := 2;
WR_CYCLE : natural := 3;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(15 downto 0)
);
end entity;
architecture arch_ethrx of ethrx is
component ethrx_input
generic(
HEAD_AWIDTH : NATURAL;
BUFF_AWIDTH : NATURAL);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic;
buff_wren : out std_logic;
buff_waddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_wdata : out std_logic_vector(7 downto 0));
end component;
component Rx_queue
generic(
HEAD_AWIDTH : NATURAL;
FIFO_AWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
clk : in std_logic;
reset : in std_logic;
head_wren : in std_logic;
head_waddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_wdata : in std_logic_vector(7 downto 0);
head_wr_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component blockdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
addra : in std_logic_vector((Awidth-1) downto 0);
clka : in std_logic;
addrb : in std_logic_vector((Awidth-1) downto 0);
clkb : in std_logic;
dia : in std_logic_vector((Dwidth-1) downto 0);
wea : in std_logic;
dob : out std_logic_vector((Dwidth-1) downto 0));
end component;
component zcpsm2dma
generic(
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
lastframe_flag : out std_logic;
start : out std_logic;
length : out std_logic_vector(15 downto 0);
start_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
start_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : out std_logic_vector(7 downto 0);
rstep : out std_logic_vector(7 downto 0);
busy : in std_logic);
end component;
component rx_dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((2*DWIDTH-1) downto 0));
end component;
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
signal head_wren : std_logic;
signal head_waddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wdata : std_logic_vector(7 downto 0);
signal head_wr_block : std_logic;
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(7 downto 0);
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(7 downto 0);
signal dma_length : std_logic_vector(15 downto 0);
signal dma_start_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wstep : std_logic_vector(7 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rdata : std_logic_vector(7 downto 0);
signal dma_wren : std_logic;
signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wdata : std_logic_vector(15 downto 0);
signal ram_wren_d1 : std_logic;
signal ram_wren_d2 : std_logic;
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal dma_wren_dly : std_logic;
begin
-- test <= head_wr_block;
ethrx_busy <= dma_busy;
u_input : ethrx_input
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH
)
port map(
-- test_crc => test,
clk => clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
buff_wren => buff_wren,
buff_waddr => buff_waddr,
buff_wdata => buff_wdata
);
u_db_queue : Rx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 1,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_rx_queue : Rx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_rx_buffer : blockdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 8
)
port map(
addra => buff_waddr,
clka => clk,
addrb => buff_raddr,
clkb => clk,
dia => buff_wdata,
wea => buff_wren,
dob => buff_rdata
);
u_dma : rx_dma_ctrl
generic map(
DWIDTH => 8,
-- RD_CYCLE => WR_CYCLE,
RD_CYCLE => WR_CYCLE,
RD_DELAY => 1,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => '1',
start => dma_start,
length => dma_length,
start_waddr => dma_start_waddr,
start_raddr => dma_start_raddr, -- 32룬½ØÈ¡ºó12λ×÷Ϊrx_bufferµÄµØÖ·
wstep => dma_wstep,
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren,
waddr => dma_waddr,
wdata => dma_wdata
);
u_zcpsm2dma : zcpsm2dma
generic map (
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_dma_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port,
lastframe_flag => lastframe_flag,
start => dma_start,
length => dma_length,
start_waddr => dma_start_waddr,
start_raddr => dma_start_raddr,
wstep => dma_wstep,
rstep => dma_rstep,
busy => dma_busy
);
buff_raddr <= dma_raddr(BUFF_AWIDTH - 1 downto 0);
dma_rdata <= buff_rdata;
-- p_wr: process(clk, reset)
-- begin
-- if reset = '1' then
--- ram_wren_d1 <= '0';
-- ram_wren_d2 <= '0';
-- ram_waddr <= (others => '0');
-- ram_wdata <= (others => '0');
-- elsif rising_edge(clk) then
-- ram_wren_d1 <= dma_wren;
-- ram_wren_d2 <= ram_wren_d1;
-- if dma_wren = '1' then
-- ram_waddr <= dma_waddr;
-- ram_wdata <= dma_wdata;
-- end if;
-- end if;
-- end process;
-- ram_wren <= ram_wren_d1 or ram_wren_d2;
u_wren_dly : ShiftReg
generic map(width => 1, depth => WR_CYCLE)
port map(clk => clk, ce => '1', d => v0, q => v1, s => open);
v0(0) <= dma_wren;
dma_wren_dly <= v1(0);
p_wr : process(clk, reset)
begin
if reset = '1' then
ram_wren <= '0';
ram_waddr <= (others => '0');
ram_wdata <= (others => '0');
elsif rising_edge(clk) then
if dma_wren = '1' then
ram_waddr <= dma_waddr;
ram_wdata <= dma_wdata;
end if;
if dma_wren = '1' then
ram_wren <= '1';
elsif dma_wren_dly = '1' then
ram_wren <= '0';
end if;
end if;
end process;
end arch_ethrx;
| gpl-2.0 | be7eb014f527b43ca31112d0ba9c8656 | 0.606703 | 2.661 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/onehot2encoded.vhd | 3 | 10,950 | -------------------------------------------------------------------------------
-- $Id: onehot2encoded.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- onehot2encoded.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
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-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: onehot2encoded.vhd
-- Version: v1.02e
-- Description: This file converts a one-hot bus to an encoded bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: General use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- OPB_ARB_PKG includes necessary constants and functions
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_1HOT_BUS_SIZE -- number of bits in the 1-hot bus
--
-- Definition of Ports:
-- Bus_1hot -- input 1-hot bus
-- Bus_enc -- output encoded bus
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity onehot2encoded is
generic (
C_1HOT_BUS_SIZE : integer := 8
);
port (
Bus_1hot : in std_logic_vector(0 to C_1HOT_BUS_SIZE-1);
Bus_enc : out std_logic_vector(0 to log2(C_1HOT_BUS_SIZE)-1)
);
end onehot2encoded;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of onehot2encoded is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- encoder logic requires that the 1hot bus be padded to next power of 2
constant PAD_1HOT_BUS_SIZE : integer := pad_power2(C_1HOT_BUS_SIZE);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pad_1hot_bus : std_logic_vector(0 to PAD_1HOT_BUS_SIZE-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- OR_BITS is used to determine if segments of the 1-hot bus are '1'
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Padded bus generation
-------------------------------------------------------------------------------
pad_1hot_bus(0 to C_1HOT_BUS_SIZE-1) <= Bus_1hot;
-------------------------------------------------------------------------------
-- Encoded Bus generation
-------------------------------------------------------------------------------
-- Note this logic uses the padded version of the 1hot bus to insure that
-- the calculations are on a constant which is a power of 2
ENC_BUS_GEN: for i in 0 to log2(PAD_1HOT_BUS_SIZE)-1 generate
signal temp_or : std_logic_vector(0 to 2**i) := (others => '0');
begin
OR_GENERATE: for j in 1 to 2**i generate
BUS_OR: entity opb_v20_v1_10_d.or_bits
generic map ( C_NUM_BITS => PAD_1HOT_BUS_SIZE/2**(i+1),
C_START_BIT => PAD_1HOT_BUS_SIZE/2**(i+1)
+ (j-1)*PAD_1HOT_BUS_SIZE/2**i,
C_BUS_SIZE => PAD_1HOT_BUS_SIZE
)
port map (
In_Bus => pad_1hot_bus,
Sig => temp_or(j-1),
Or_out => temp_or(j)
);
end generate OR_GENERATE;
Bus_enc(i) <= temp_or(2**i);
end generate ENC_BUS_GEN;
end implementation;
| bsd-3-clause | cea3709022c0a40d9e874cee8ac3a36e | 0.388767 | 5.420792 | false | false | false | false |
jevinskie/aes-over-pcie | source/top_top.vhd | 1 | 3,449 | -- File name: aes_top.vhd
-- Created: 2009-04-04
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES top level
use work.aes.all;
use work.pcie.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte;
rx_data_k : in std_logic;
rx_status : in std_logic_vector(2 downto 0);
rx_elec_idle : in std_logic;
phy_status : in std_logic;
rx_valid : in std_logic;
tx_detect_rx : out std_logic;
tx_elec_idle : out std_logic;
tx_comp : out std_logic;
rx_pol : out std_logic;
power_down : out std_logic_vector(1 downto 0);
tx_data : out byte;
tx_data_k : out std_logic
);
end entity top_top;
architecture structural of top_top is
signal got_key : std_logic;
signal got_pt : std_logic;
signal send_ct : std_logic;
signal aes_done : std_logic;
signal tx_data_aes : byte;
signal last_rx_data : byte;
begin
pcie_top_b : entity work.pcie_top(structural) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
rx_data_k => rx_data_k, rx_status => rx_status,
rx_elec_idle => rx_elec_idle, phy_status => phy_status,
rx_valid => rx_valid, tx_detect_rx => tx_detect_rx,
tx_elec_idle => tx_elec_idle, tx_comp => tx_comp,
rx_pol => rx_pol, power_down => power_down,
tx_data => tx_data, tx_data_k => tx_data_k,
tx_data_aes => tx_data_aes, aes_done => aes_done,
got_key => got_key, got_pt => got_pt, send_ct => send_ct
);
-- leda C_1406 off
process(clk)
begin
if rising_edge(clk) then
last_rx_data <= rx_data;
end if;
end process;
-- leda C_1406 on
aes_top_b : entity work.aes_top(structural) port map (
clk => clk, nrst => nrst, rx_data => last_rx_data,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done, tx_data => tx_data_aes
);
end architecture structural;
architecture structural_p of top_top is
signal got_key : std_logic;
signal got_pt : std_logic;
signal send_ct : std_logic;
signal aes_done : std_logic;
signal tx_data_aes : byte;
signal last_rx_data : byte;
begin
pcie_top_b : entity work.pcie_top(structural) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
rx_data_k => rx_data_k, rx_status => rx_status,
rx_elec_idle => rx_elec_idle, phy_status => phy_status,
rx_valid => rx_valid, tx_detect_rx => tx_detect_rx,
tx_elec_idle => tx_elec_idle, tx_comp => tx_comp,
rx_pol => rx_pol, power_down => power_down,
tx_data => tx_data, tx_data_k => tx_data_k,
tx_data_aes => tx_data_aes, aes_done => aes_done,
got_key => got_key, got_pt => got_pt, send_ct => send_ct
);
-- leda C_1406 off
process(clk)
begin
if rising_edge(clk) then
last_rx_data <= rx_data;
end if;
end process;
-- leda C_1406 on
aes_top_p_b : entity work.aes_top(structural_p) port map (
clk => clk, nrst => nrst, rx_data => last_rx_data,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done, tx_data => tx_data_aes
);
end architecture structural_p;
| bsd-3-clause | bc5ce85f38c3d38062bfcbdc0a7a32c6 | 0.568861 | 3.017498 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_broadcast_1.vhd | 2 | 22,391 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_broadcast_1.c
-- NUM_THREADS = 3
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * waken_num
-- reg6 = * function
-- reg7 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of waken_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- set i=0
reg1_next <= Z32;
next_state <= STATE_7;
when STATE_7 =>
case reg1 is
when x"00000000" => next_state <= STATE_8;
when x"00000001" => next_state <= STATE_8;
when x"00000002" => next_state <= STATE_8;
when others => next_state <= STATE_13;
end case;
-- hthread_create( &data->thread[i], NULL, data->function, (void *) data );
when STATE_8 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_13 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
case intrfc2thrd_value is
when x"00000003" => next_state <= STATE_16;
when others => next_state <= STATE_15;
end case;
when STATE_15 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_16 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_cond_broadcast( data->cond );
when STATE_18 =>
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_cond_broadcast
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_20 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_21;
when STATE_21 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_22;
next_state <= WAIT_STATE;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_22 =>
reg1_next <= Z32;
next_state <= STATE_23;
when STATE_23 =>
case reg1 is
when x"00000000" => next_state <= STATE_24;
when x"00000001" => next_state <= STATE_24;
when x"00000002" => next_state <= STATE_24;
when others => next_state <= STATE_28;
end case;
-- retVal = hthread_join( data->thread[i], NULL );
when STATE_24 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
when STATE_25 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_27;
when STATE_27 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
reg1_next <= reg1 + 1;
-- retVal = *( data->waken_num )
when STATE_28 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_29;
when STATE_29 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b37d2bf1d587d4a1035d8fc70e52431f | 0.552454 | 3.617286 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_dmux_blk.vhd | 3 | 3,792 | -------------------------------------------------------------------------------
-- $Id: ip2bus_dmux_blk.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- ip2bus_dmux_blk.vhd - VHD design file
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_dmux_blk.vhd
--
-- Description: VHDL design file that is a wrapper around the IPIF data
-- MUX design.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ip2bus_dmux_blk.vhd
-- ip2bus_dmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
--
-- History:
-- DET Aug 21, 2001 -- First version adapted from Visual HDL output
-- LCW Nov 8, 2004 -- updated for NCSim
--
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ip2bus_dmux;
entity ip2bus_dmux_blk is
generic (
C_DBUS_WIDTH : INTEGER := 32
);
port (
DMA2Bus_Data : in std_logic_vector(0 to C_DBUS_WIDTH - 1 );
Intr2Bus_DBus : in std_logic_vector(0 to C_DBUS_WIDTH - 1 );
IP2Bus_Data : in std_logic_vector(0 to C_DBUS_WIDTH - 1 );
IP2Bus_Data_mx : out std_logic_vector(0 to C_DBUS_WIDTH - 1 );
Reset2Bus_Data : in std_logic_vector(0 to C_DBUS_WIDTH - 1 );
RFIFO2Bus_Data : in std_logic_vector(0 to C_DBUS_WIDTH - 1 );
WFIFO2Bus_Data : in std_logic_vector(0 to C_DBUS_WIDTH - 1 )
);
end ip2bus_dmux_blk;
architecture implementation of ip2bus_dmux_blk is
begin
I_IP2BUS_DMUX: entity opb_ipif_v2_00_h.ip2bus_dmux
generic map (C_DBUS_WIDTH)
port map (
IP2Bus_Data => IP2Bus_Data(0 to C_DBUS_WIDTH - 1),
WFIFO2Bus_Data => WFIFO2Bus_Data(0 to C_DBUS_WIDTH - 1),
RFIFO2Bus_Data => RFIFO2Bus_Data(0 to C_DBUS_WIDTH - 1),
DMA2Bus_Data => DMA2Bus_Data(0 to C_DBUS_WIDTH - 1),
IRPT2Bus_Data => Intr2Bus_DBus(0 to C_DBUS_WIDTH - 1),
Reset2Bus_Data => Reset2Bus_Data(0 to C_DBUS_WIDTH - 1),
IP2Bus_Data_mx => IP2Bus_Data_mx(0 to C_DBUS_WIDTH - 1));
end implementation;
| bsd-3-clause | 33b5b66b9fac78b5b945ecde073e164d | 0.414557 | 4.139738 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_hwti_v3_00_a/hdl/vhdl/user_logic_hwti.vhd | 2 | 155,103 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread Interface
-- Version 3: Subinterfaces for memory, function call, and control
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
library opb_SynchManager_v1_00_c;
use opb_SynchManager_v1_00_c.common.all;
---------------------------------------------------------------------------
-- Address Space
---------------------------------------------------------------------------
-- Note: All addresses must be word addressable. ie the last two bits of
-- each address must be 0b00.
-- BASEADDR +
-- x0000 Thread ID Register
-- x0004 Timer Register (Read Only)
-- x0008 Status Register (Read Only)
-- x000C Command Register
-- x0010 Argument Register
-- x0014 Result Register (Read Only)
-- x0018 Debug System Register (Read Only)
-- x001C Debug User Register (Read Only)
-- x0020 Master Read Register (Read Only)
-- x0024 Master Write Register (Read Only)
-- x0028 Stack Pointer (Read Only)
-- x002C Frame Pointer (Read Only)
-- x0030 Heap Pointer (Read Only)
-- x0034 8B Dynamic Memory Table (Read Only)
-- x0038 32B Dynamic Memory Table (Read Only)
-- x003C 1024B Dynamic Memory Table (Read Only)
-- x0040 Unlimited Dynamic memory Address (Read Only)
-- x0044 Unused
-- x0048 Remote Procedure Call Mutex/Condvar Numbers
-- x004C Remote Procedure Call Argument Struct Address
-- x0050 Start of global address space
-- .....
-- x7FFC End of global address space
---------------------------------------------------------------------------
-- Port Declarations
---------------------------------------------------------------------------
-- Definition of Ports:
-- IPIC
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_CS -- Bus to IP chip select for user logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_PostedWrInh -- IP to Bus posted write inhibit
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
---------------------------------------------------------------------------
-- Hardware Thread Interface Entity
---------------------------------------------------------------------------
entity user_logic_hwti is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := x"6300_0000";
C_HIGHADDR : std_logic_vector(0 to 31) := x"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector := x"7600_0000"
);
port (
--CONTROL : in STD_LOGIC_VECTOR(35 DOWNTO 0);
OPBtimer : out std_logic_vector(0 to 31);
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Clk : in std_logic;
Bus2IP_CS : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_RdCE : in std_logic_vector(0 to 3);
Bus2IP_Reset : in std_logic;
Bus2IP_WrCE : in std_logic_vector(0 to 3);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Ack : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
IP2Bus_Error : out std_logic;
IP2Bus_PostedWrInh : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_ToutSup : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_MstBE : out std_logic_vector(0 to 3);
IP2Bus_Addr : out std_logic_vector(0 to 31);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to 31);
intrfc2thrd : out std_logic_vector(0 to 63);
thrd2intrfc : in std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic
);
end entity user_logic_hwti;
---------------------------------------------------------------------------
-- Architecture Section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwti is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
---------------------------------------------------------------------------
-- Bram declaration
---------------------------------------------------------------------------
component bram_imp_dual is
port (
clk: in std_logic;
addra: in std_logic_vector(0 to 12);
dia: in std_logic_vector(0 to 31);
doa: out std_logic_vector(0 to 31);
ena: in std_logic;
wea: in std_logic;
addrb: in std_logic_vector(0 to 12);
dib: in std_logic_vector(0 to 31);
dob: out std_logic_vector(0 to 31);
enb: in std_logic;
web: in std_logic
);
end component;
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant COUNT_BITS : integer := 8;
-- Constants for conditional variable commands
constant CONDVAR_CMD_SIGNAL : std_logic_vector(0 to 3) := "0010";
constant CONDVAR_CMD_WAIT : std_logic_vector(0 to 3) := "0100";
constant CONDVAR_CMD_BCAST : std_logic_vector(0 to 3) := "0110";
constant CONDVAR_FAILED : std_logic_vector(0 to 3) := x"E";
constant CONDVAR_SUCCESS : std_logic_vector(0 to 3) := x"A";
-- Address Mapped Register Offsets
-- Please see the address map at the top of this file for further details
constant REG_THREAD_ID : std_logic_vector(0 to 13) := b"0000_0000_0000_00";
constant REG_TIMER : std_logic_vector(0 to 13) := b"0000_0000_0000_01";
constant REG_STATUS : std_logic_vector(0 to 13) := b"0000_0000_0000_10";
constant REG_COMMAND : std_logic_vector(0 to 13) := b"0000_0000_0000_11";
constant REG_ARGUMENT : std_logic_vector(0 to 13) := b"0000_0000_0001_00";
constant REG_RESULT : std_logic_vector(0 to 13) := b"0000_0000_0001_01";
constant REG_DEBUG_SYSTEM : std_logic_vector(0 to 13) := b"0000_0000_0001_10";
constant REG_DEBUG_USER : std_logic_vector(0 to 13) := b"0000_0000_0001_11";
constant REG_MASTER_READ : std_logic_vector(0 to 13) := b"0000_0000_0010_00";
constant REG_MASTER_WRITE : std_logic_vector(0 to 13) := b"0000_0000_0010_01";
constant REG_STACKPTR : std_logic_vector(0 to 13) := b"0000_0000_0010_10";
constant REG_FRAMEPTR : std_logic_vector(0 to 13) := b"0000_0000_0010_11";
constant REG_HEAPPTR : std_logic_vector(0 to 13) := b"0000_0000_0011_00";
constant REG_8B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_01";
constant REG_32B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_10";
constant REG_1024B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_11";
constant REG_UNLIMITED_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0100_00";
constant REG_RPC_MUTEXCONVAR : std_logic_vector(0 to 13) := b"0000_0000_0100_10";
constant REG_RPC_T_ADDRESS : std_logic_vector(0 to 13) := b"0000_0000_0100_11";
-- I expect these to be derived from generics someday, based on how many instantiated BRAMS
-- The readable address space is slighly larger, this is due to the dynamic memory tables.
-- The BRAM is readable from the Dynamic Table entries up, BRAM is writable from the RPC
-- address and up. Although, it should only be the system kernel writing to the RPC regs.
constant GLOBAL_BASE_ADDR : std_logic_vector(0 to 13) := b"0000_0000_0101_00";
constant GLOBAL_BASE_ADDRREADABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_01";
constant GLOBAL_HIGH_ADDR : std_logic_vector(0 to 13) := b"0111_1111_1111_11";
-- Lower half of address range for dynamic memory allocation
constant BASE_ADDR_MALLOC_8B : std_logic_vector(0 to 15) := x"7FF8";
constant BASE_ADDR_MALLOC_32B : std_logic_vector(0 to 15) := x"7EE0";
constant BASE_ADDR_MALLOC_1024B : std_logic_vector(0 to 15) := x"7A00";
-- Note the base address of the unlimit malloc is the initial heap pointer
-- Alias to determine which register is being accessed by the system bus
alias reg_address : std_logic_vector(0 to 13) is Bus2IP_Addr(16 to 29);
-- Aliases for bus reads and writes responces
-- Set to the IP2IP_Addr duing a bus master read
constant master_read_respond_address : std_logic_vector(0 to 31) := C_BASEADDR(0 to 15) & REG_MASTER_READ & "00";
-- Set to the IP2IP_Addr duing a bus master write
constant master_write_respond_address : std_logic_vector(0 to 31) := C_BASEADDR(0 to 15) & REG_MASTER_WRITE & "00";
-- Function Constants
-- Unsupported functions are commented out
-- TODO Is there a way to put this into a seperate file that can be shared with the HWTUL?
-- Special function codes for user
constant FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7FFF reserved for user logic's state machine
-- Range 8000 to 9FFF reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
-- Ranged A000 to A0FF reserved for standard library stdlib.h calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- Ranged A100 to A1FF reserved for string.h library calls
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- Opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
-- system_status Constants
constant SYSTEM_STATUS_NOT_USED : std_logic_vector(0 to 7) := x"00";
constant SYSTEM_STATUS_USED : std_logic_vector(0 to 7) := x"01";
constant SYSTEM_STATUS_RUNNING : std_logic_vector(0 to 7) := x"02";
constant SYSTEM_STATUS_BLOCKED : std_logic_vector(0 to 7) := x"04";
constant SYSTEM_STATUS_EXITED : std_logic_vector(0 to 7) := x"08";
constant SYSTEM_STATUS_EXITED_ERROR : std_logic_vector(0 to 7) := x"20";
constant SYSTEM_STATUS_EXITED_OVERFLOW : std_logic_vector(0 to 7) := x"40";
-- system_command Constants
constant SYSTEM_COMMAND_INIT : std_logic_vector(0 to 3) := x"0";
constant SYSTEM_COMMAND_RUN : std_logic_vector(0 to 3) := x"1";
constant SYSTEM_COMMAND_RESET : std_logic_vector(0 to 3) := x"2";
constant SYSTEM_COMMAND_COLDBOOT : std_logic_vector(0 to 3) := x"4";
constant SYSTEM_COMMAND_NOTUSED : std_logic_vector(0 to 3) := x"8";
-- misc constants
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant TIMEOUT_CYCLES : natural := 4; -- clock cycles to wait before suppressing timeouts
-- Thread manager commandes
-- TODO: Thread manager commands should be replaced by an external file
constant THREAD_MANAGER_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant THREAD_MANAGER_READ_THREAD : std_logic_vector(0 to 5) := "000011";
-- bram interface signals
signal wea : std_logic := '0';
signal ena : std_logic := '0';
signal addra : std_logic_vector(0 to 12) := (others => '0');
signal dia : std_logic_vector(0 to 31) := (others => '0');
signal doa : std_logic_vector(0 to 31);
signal web : std_logic := '0';
signal enb : std_logic := '0';
signal addrb : std_logic_vector(0 to 12) := (others => '0');
signal dib : std_logic_vector(0 to 31) := (others => '0');
signal dob : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- State Machine States
---------------------------------------------------------------------------
type hwti_system_state is (
START,
IDLE,
COMMAND_RESET_INIT,
COMMAND_RESET_END_BUS_TRANSACTION_WAIT,
COMMAND_RUN_INIT,
GLOBAL_READ_WAIT,
GLOBAL_READ_RESPOND,
END_BUS_TRANSACTION,
END_BUS_TRANSACTION_WAIT);
type hwti_user_state is (
START,
NOT_USED,
RESET_MALLOC_TABLE,
NOT_USED_WAIT,
USED,
USED_WAIT,
RUNNING,
SERVICE_NEW_REQUST,
USER_FUNCTION_CALL,
USER_FUNCTION_CALL_2,
USER_FUNCTION_RETURN,
USER_FUNCTION_RETURN_2,
USER_FUNCTION_RETURN_3,
LIB_FUNCTION_MEMCPY,
LIB_FUNCTION_MEMCPY_2,
LIB_FUNCTION_MEMCPY_3,
LIB_FUNCTION_MEMCPY_4,
LIB_FUNCTION_MEMCPY_5,
LIB_FUNCTION_MEMCPY_6,
LIB_FUNCTION_FREE,
LIB_FUNCTION_FREE_1,
LIB_FUNCTION_FREE_2,
LIB_FUNCTION_FREE_3,
LIB_FUNCTION_CALLOC,
LIB_FUNCTION_CALLOC_2,
LIB_FUNCTION_CALLOC_3,
LIB_FUNCTION_CALLOC_4,
LIB_FUNCTION_CALLOC_5,
LIB_FUNCTION_MALLOC,
LIB_FUNCTION_MALLOC_8a,
LIB_FUNCTION_MALLOC_8b,
LIB_FUNCTION_MALLOC_8c,
LIB_FUNCTION_MALLOC_32a,
LIB_FUNCTION_MALLOC_32b,
LIB_FUNCTION_MALLOC_32c,
LIB_FUNCTION_MALLOC_1024a,
LIB_FUNCTION_MALLOC_1024b,
LIB_FUNCTION_MALLOC_1024c,
LIB_FUNCTION_MALLOC_UNLIMITa,
LIB_FUNCTION_MALLOC_UNLIMITb,
LIB_FUNCTION_MALLOC_UNLIMITc,
OVERFLOW,
HTHREAD_RPC,
HTHREAD_RPC_2,
HTHREAD_RPC_3,
HTHREAD_RPC_3a,
HTHREAD_RPC_4,
HTHREAD_RPC_5,
HTHREAD_RPC_6,
HTHREAD_RPC_7,
HTHREAD_RPC_7a,
HTHREAD_RPC_8,
HTHREAD_RPC_8a,
HTHREAD_RPC_9,
HTHREAD_RPC_10,
HTHREAD_RPC_11,
HTHREAD_RPC_12,
HTHREAD_RPC_13,
HTHREAD_RPC_14,
HTHREAD_RPC_15,
HTHREAD_RPC_15a,
HTHREAD_RPC_16,
HTHREAD_RPC_17,
HTHREAD_RPC_17a,
HTHREAD_RPC_18,
HTHREAD_RPC_19,
HTHREAD_RPC_19a,
HTHREAD_RPC_20,
HTHREAD_RPC_20a,
HTHREAD_RPC_21,
HTHREAD_RPC_22,
HTHREAD_RPC_23,
HTHREAD_RPC_24,
HTHREAD_ATTR_INIT,
HTHREAD_ATTR_INIT_2,
HTHREAD_ATTR_INIT_3,
HTHREAD_ATTR_INIT_4,
HTHREAD_ATTR_INIT_5,
HTHREAD_ATTR_INIT_6,
HTHREAD_ATTR_INIT_7,
HTHREAD_EQUAL,
HTHREAD_EQUAL_2,
HTHREAD_MUTEX_INIT,
HTHREAD_MUTEX_INIT_2,
HTHREAD_MUTEX_INIT_3,
HTHREAD_MUTEX_INIT_4,
HTHREAD_MUTEX_INIT_5,
HTHREAD_MUTEX_INIT_6,
HTHREAD_MUTEX_INIT_7,
HTHREAD_MUTEXATTR_INIT,
HTHREAD_MUTEXATTR_INIT_2,
HTHREAD_MUTEXATTR_INIT_3,
HTHREAD_MUTEXATTR_SETNUM,
HTHREAD_MUTEXATTR_SETNUM_2,
HTHREAD_MUTEXATTR_SETNUM_3,
HTHREAD_MUTEXATTR_GETNUM,
HTHREAD_MUTEXATTR_GETNUM_2,
HTHREAD_MUTEXATTR_GETNUM_3,
HTHREAD_MUTEXATTR_GETNUM_4,
HTHREAD_MUTEX_UNLOCK,
HTHREAD_MUTEX_UNLOCK_2,
HTHREAD_MUTEX_UNLOCK_3,
HTHREAD_MUTEX_TRYLOCK,
HTHREAD_MUTEX_TRYLOCK_2,
HTHREAD_MUTEX_TRYLOCK_3,
HTHREAD_MUTEX_LOCK,
HTHREAD_MUTEX_LOCK_2,
HTHREAD_MUTEX_LOCK_3,
HTHREAD_MUTEX_LOCK_4,
HTHREAD_MUTEX_LOCK_5,
HTHREAD_MUTEX_LOCK_6,
HTHREAD_CONDATTR_INIT,
HTHREAD_CONDATTR_INIT_2,
HTHREAD_COND_WAIT,
HTHREAD_COND_WAIT_2,
HTHREAD_COND_WAIT_3,
HTHREAD_COND_WAIT_4,
HTHREAD_COND_WAIT_5,
HTHREAD_COND_WAIT_6,
HTHREAD_COND_WAIT_7,
HTHREAD_COND_WAIT_7a,
HTHREAD_COND_WAIT_8,
HTHREAD_COND_INIT,
HTHREAD_COND_INIT_2,
HTHREAD_COND_INIT_3,
HTHREAD_COND_INIT_4,
HTHREAD_COND_INIT_5,
HTHREAD_COND_INIT_6,
HTHREAD_COND_SIGNAL,
HTHREAD_COND_SIGNAL_2,
HTHREAD_COND_SIGNAL_3,
HTHREAD_COND_BCAST,
HTHREAD_COND_BCAST_2,
HTHREAD_COND_BCAST_3,
HTHREAD_EXIT,
HTHREAD_EXIT_2,
HTHREAD_EXIT_3,
WAIT_ONE_CYCLE,
POP_READ_PARAM_COUNT,
POP_READ_PARAM,
LOCAL_LOAD_RESPOND,
LOCAL_PARTIAL_LOAD,
LOCAL_PARTIAL_LOAD_1,
GLOBAL_LOAD_RETURN,
MASTER_LOAD_INIT,
MASTER_LOAD_WAIT_FOR_ACK,
MASTER_STORE_INIT,
MASTER_STORE_WAIT_FOR_ACK);
type system_request_type is (
NOOP,
CHANGE_STATUS_TO_USED,
CHANGE_STATUS_TO_RUN,
CHANGE_STATUS_TO_EXIT,
CHANGE_STATUS_TO_EXIT_ERROR,
CHANGE_STATUS_TO_EXIT_OVERFLOW,
CHANGE_STATUS_TO_BLOCK);
signal system_state, system_state_next: hwti_system_state := START;
signal user_state, user_state_next : hwti_user_state := START;
-- Registers for the System Level API
signal system_thread_id, system_thread_id_next : std_logic_vector(0 to 7);
signal system_command, system_command_next : std_logic_vector(0 to 3);
signal system_status, system_status_next : std_logic_vector(0 to 7);
signal system_argument, system_argument_next : std_logic_vector(0 to 31);
signal system_result, system_result_next : std_logic_vector(0 to 31);
-- Registers for the User Logic Level API
signal fromUser_address : std_logic_vector(0 to 31);
signal fromUser_value : std_logic_vector(0 to 31);
signal fromUser_function : std_logic_vector(0 to 15);
signal fromUser_opcode : std_logic_vector(0 to 5);
signal fromUserReg_address, fromUserReg_address_next : std_logic_vector(0 to 31);
signal fromUserReg_value, fromUserReg_value_next : std_logic_vector(0 to 31);
signal fromUserReg_function, fromUserReg_function_next : std_logic_vector(0 to 15);
signal fromUserReg_opcode, fromUserReg_opcode_next : std_logic_vector(0 to 5);
signal toUser_value, toUser_value_next : std_logic_vector(0 to 31);
-- Local memory pointers
signal framePtr, framePtr_next : std_logic_vector(0 to 15);
signal stackPtr, stackPtr_next : std_logic_vector(0 to 15);
signal heapPtr, heapPtr_next : std_logic_vector(0 to 15);
signal paramCount, paramCount_next : std_logic_vector(0 to 7);
-- Temporary registers
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
-- Signals to help communicate with the system bus
signal data_address, data_address_next: std_logic_vector(0 to 31);
signal data_value, data_value_next: std_logic_vector(0 to 31);
-- Miscelaneous signals
signal cycle_count : std_logic_vector(0 to 7);
signal timer : std_logic_vector(0 to 31);
signal read_ce, write_ce : std_logic;
signal local_memory_access : std_logic;
signal stackHeapOverflow : std_logic;
signal system_request, system_request_next : system_request_type;
signal user_return_state, user_return_state_next : hwti_user_state;
signal bus_data_out, bus_data_out_next : std_logic_vector(0 to 31);
signal debug_system, debug_system_next : std_logic_vector(0 to 31);
signal debug_user, debug_user_next : std_logic_vector(0 to 31);
------------------------------------------------------------------------
-- Functions
------------------------------------------------------------------------
------------------------------------------------------------------------
-- thread_manager_exit_thread
-- calculates the address to read to perform a exit_thread call to TM
-- TODO: move this to a common.vhd file in TM, and include it as a library
------------------------------------------------------------------------
function thread_manager_exit_thread_address( tm_base_address : in std_logic_vector;
data_width : in natural;
thread_bits : in natural;
thread_id : in std_logic_vector ) return std_logic_vector is
variable address : std_logic_vector(0 to data_width-1);
begin
address := tm_base_address;
address( data_width-thread_bits-2 to data_width-3 ) := thread_id;
address( data_width-thread_bits-8 to data_width-thread_bits-3 ) := THREAD_MANAGER_EXIT_THREAD;
return address;
end function;
------------------------------------------------------------------------
-- bit_set()
-- Determine if any bit in the array is set, if so, return 1
------------------------------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if ( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------------------------------
-- is_local_memory()
-- Determine if the passed in address lines is a reference to local memory
---------------------------------------------------------------------------
function is_local_memory( addr_lines : in std_logic_vector(0 to 31) ) return std_logic is
begin
if (addr_lines(0 to 15) = C_BASEADDR(0 to 15)
and addr_lines(16 to 29) >= GLOBAL_BASE_ADDR
and addr_lines(16 to 29) <= GLOBAL_HIGH_ADDR) then
return '1';
end if;
return '0';
end function;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture implementation
OPBtimer <= timer;
rd <= exist;
--bram instanciation
bram : bram_imp_dual port map(Bus2IP_Clk,addra,dia,doa,ena,wea,addrb,dib,dob,enb,web);
read_ce <= bit_set(Bus2IP_RdCE);
write_ce <= bit_set(Bus2IP_WrCE);
-- The next two processes work in conjunction with each other.
-- The objective is to raise the time out suppression line, if a bus transaction
-- will take longer than 8 clock cycles.
-- The CYCLE_PROC counts the number of cycles a bus transaction takes.
-- The CYCLE_CONTROL sets the timeout supporession high if going to exceed the 8 cycle count.
CYCLE_PROC : process ( Bus2IP_Clk, Bus2IP_CS ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if ( Bus2IP_CS = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_MstBE <= (others=> '1');
IP2Bus_Retry <= '0'; -- no retry
IP2Bus_Error <= '0'; -- no error
IP2Bus_PostedWrInh <= '0'; -- inhibit posted write
if cycle_count > TIMEOUT_CYCLES then
IP2Bus_ToutSup <= '1'; -- Suppress timeouts on the bus
else
IP2Bus_ToutSup <= '0'; -- Release the timeout suppress line
end if;
end process CYCLE_CONTROL;
---------------------------------------------------------------------------
-- Register Assignments
---------------------------------------------------------------------------
HWTI_STATE_PROCESS : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
system_thread_id <= system_thread_id_next;
system_command <= system_command_next;
system_status <= system_status_next;
system_argument <= system_argument_next;
system_result <= system_result_next;
if (exist= '1') then
fromUser_address <= thrd2intrfc_address;
fromUser_value <= thrd2intrfc_value;
fromUser_function <= thrd2intrfc_function;
fromUser_opcode <= thrd2intrfc_opcode;
local_memory_access <= is_local_memory( thrd2intrfc_address );
end if;
fromUserReg_address <= fromUserReg_address_next;
fromUserReg_value <= fromUserReg_value_next;
fromUserReg_function <= fromUserReg_function_next;
fromUserReg_opcode <= fromUserReg_opcode_next;
toUser_value <= toUser_value_next;
bus_data_out <= bus_data_out_next;
IP2Bus_Data <= bus_data_out_next;
system_request <= system_request_next;
user_return_state <= user_return_state_next;
data_address <= data_address_next;
data_value <= data_value_next;
framePtr <= framePtr_next;
stackPtr <= stackPtr_next;
heapPtr <= heapPtr_next;
paramCount <= paramCount_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
debug_system <= debug_system_next;
debug_user <= debug_user_next;
if ( Bus2IP_Reset = '1'
or system_command_next = SYSTEM_COMMAND_RESET ) then
system_state <= START;
user_state <= START;
else
system_state <= system_state_next;
if ( stackHeapOverflow = '1' ) then
user_state <= OVERFLOW;
else
user_state <= user_state_next;
end if;
end if;
end if;
end process HWTI_STATE_PROCESS;
-----------------------------------------------------------------------
-- HWTI_TIMER
-- Process to count the number of clock cycles the HWT is running for.
-- Starts counting when a RUN command is issued, ends counting when
-- status changes to exit.
-----------------------------------------------------------------------
HWTI_TIMER : process (Bus2IP_Clk) is
begin
if ( Bus2IP_Clk'event and (Bus2IP_Clk = '1') ) then
case system_status is
when SYSTEM_STATUS_NOT_USED =>
timer <= Z32;
when SYSTEM_STATUS_USED =>
timer <= Z32;
when SYSTEM_STATUS_RUNNING =>
timer <= timer + x"00000001";
when SYSTEM_STATUS_BLOCKED =>
timer <= timer + x"00000001";
when others =>
--do nothing
end case;
end if;
end process HWTI_TIMER;
---------------------------------------------------------------------------
-- Stack and Heap Overflow Detection
-- Check that the stack does not grow larger than the heap
-- or the heap does not grow into the stack
---------------------------------------------------------------------------
STACK_HEAP_OVERFLOW_DETECTION : process (Bus2IP_Clk) is
begin
if ( system_status = SYSTEM_STATUS_RUNNING
and stackPtr >= heapPtr ) then
stackHeapOverflow <= '1';
else
stackHeapOverflow <= '0';
end if;
end process STACK_HEAP_OVERFLOW_DETECTION;
---------------------------------------------------------------------------
-- System Bus Controller State Machine
---------------------------------------------------------------------------
HWTI_SYSTEM_STATE_MACHINE : process (Bus2IP_Clk) is
begin
-- Default bus output signal assignments
IP2Bus_Ack <= '0'; -- pulse(010) to end bus transaction
-- default bram port A signals
addra <= (others => '0');
dia <= (others => '0');
ena <= '0';
wea <= '0';
-- Default register assignments
system_state_next <= system_state;
system_thread_id_next <= system_thread_id;
system_command_next <= system_command;
system_status_next <= system_status;
system_argument_next <= system_argument;
bus_data_out_next <= bus_data_out;
debug_system_next <= debug_system;
-- The state machine
case system_state is
when START =>
--Set initial values for important signals
system_thread_id_next <= Z32(0 to 7);
system_command_next <= SYSTEM_COMMAND_INIT;
system_status_next <= SYSTEM_STATUS_NOT_USED;
system_argument_next <= Z32;
system_state_next <= IDLE;
bus_data_out_next <= Z32;
debug_system_next <= Z32;
when IDLE =>
if ( write_ce = '1' ) then
-- System is writing something to HWT
case reg_address is
when REG_THREAD_ID =>
-- system is trying to set the thread id
-- may only be written to when status is NOT_USED
if ( system_status = SYSTEM_STATUS_NOT_USED ) then
system_thread_id_next <= Bus2IP_Data(24 to 31);
end if;
system_state_next <= END_BUS_TRANSACTION;
when REG_COMMAND =>
case Bus2IP_Data(28 to 31) is
-- Note that you can not write a system command init.
when SYSTEM_COMMAND_RUN => system_state_next <= COMMAND_RUN_INIT;
when SYSTEM_COMMAND_RESET => system_state_next <= COMMAND_RESET_INIT;
when others => system_state_next <= END_BUS_TRANSACTION; -- do nothing if unreconized command
end case;
when REG_ARGUMENT =>
case system_status is
when SYSTEM_STATUS_USED =>
--set the argument register
system_argument_next <= Bus2IP_Data;
--set the value on the stack
addra <= GLOBAL_BASE_ADDR(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
when others =>
--do nothing
end case;
system_state_next <= END_BUS_TRANSACTION;
when REG_MASTER_READ =>
-- When the controller is doing a Bus Master Read, the data
-- from the bus, when its read, will be placed here. I think,
-- actually not wholy sure why this state is needed.
bus_data_out_next <= Z32;
system_state_next <= END_BUS_TRANSACTION;
when REG_RPC_MUTEXCONVAR =>
addra <= REG_RPC_MUTEXCONVAR(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
when REG_RPC_T_ADDRESS =>
addra <= REG_RPC_T_ADDRESS(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
when others =>
if (reg_address >= GLOBAL_BASE_ADDR and reg_address <= GLOBAL_HIGH_ADDR) then
-- System is requesting to write to the shard global address space
-- internal to the HWTI
addra <= Bus2IP_Addr(17 to 29);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
else
-- User is requesting to write to a register that can't be written to
-- Do nothing and ack the bus
system_state_next <= END_BUS_TRANSACTION;
end if;
end case;
elsif ( read_ce = '1' ) then
-- System is reading something from HWT
case reg_address is
when REG_THREAD_ID =>
bus_data_out_next <= Z32(0 to 23) & system_thread_id;
system_state_next <= END_BUS_TRANSACTION;
when REG_COMMAND =>
bus_data_out_next <= Z32(0 to 27) & system_command;
system_state_next <= END_BUS_TRANSACTION;
when REG_STATUS =>
bus_data_out_next <= Z32(0 to 23) & system_status;
system_state_next <= END_BUS_TRANSACTION;
when REG_ARGUMENT =>
bus_data_out_next <= system_argument;
system_state_next <= END_BUS_TRANSACTION;
when REG_RESULT =>
bus_data_out_next <= system_result;
system_state_next <= END_BUS_TRANSACTION;
when REG_MASTER_WRITE =>
-- When the controller is doing a Bus Master Write, need to
-- provide, to the bus, the data to write.
bus_data_out_next <= data_value;
system_state_next <= END_BUS_TRANSACTION;
when REG_DEBUG_SYSTEM =>
bus_data_out_next <= debug_system;
system_state_next <= END_BUS_TRANSACTION;
when REG_DEBUG_USER =>
bus_data_out_next <= debug_user;
system_state_next <= END_BUS_TRANSACTION;
when REG_TIMER =>
bus_data_out_next <= timer;
system_state_next <= END_BUS_TRANSACTION;
when REG_FRAMEPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & framePtr;
system_state_next <= END_BUS_TRANSACTION;
when REG_STACKPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & stackPtr;
system_state_next <= END_BUS_TRANSACTION;
when REG_HEAPPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & heapPtr;
system_state_next <= END_BUS_TRANSACTION;
when others =>
-- The address space that is readable from the bus is 4 Words larger than
-- the space that is writable. This is because, the dynamic memory
-- allocation tables is readable for debug purposes.
if (reg_address >= GLOBAL_BASE_ADDRREADABLE and reg_address <= GLOBAL_HIGH_ADDR) then
--debug_system_next <= --debug_system or x"00000010";
-- System is requesting to read to the shard global address space
-- internal to the HWTI
addra <= Bus2IP_Addr(17 to 29);
ena <= '1';
system_state_next <= GLOBAL_READ_WAIT;
else
--debug_system_next <= --debug_system or x"00000020";
-- Theoritically this case shouldn't happen. But what ever, return all zeros.
bus_data_out_next <= Z32;
system_state_next <= END_BUS_TRANSACTION;
end if;
end case;
else
-- Nothing is coming in off of the bus. Check to see if the
-- controller has anything for us to do.
case system_request is
when CHANGE_STATUS_TO_USED =>
system_status_next <= SYSTEM_STATUS_USED;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_RUN =>
system_status_next <= SYSTEM_STATUS_RUNNING;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT =>
system_status_next <= SYSTEM_STATUS_EXITED;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT_ERROR =>
system_status_next <= SYSTEM_STATUS_EXITED_ERROR;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT_OVERFLOW =>
system_status_next <= SYSTEM_STATUS_EXITED_OVERFLOW;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_BLOCK =>
system_status_next <= SYSTEM_STATUS_BLOCKED;
system_command_next <= SYSTEM_COMMAND_INIT; -- CHANGE ME ... maybe
system_state_next <= IDLE;
when NOOP =>
system_state_next <= IDLE;
end case;
end if;
when COMMAND_RESET_INIT =>
-- A RESET can be issued at anytime. Although, it should
-- really only be called once a thread has exited.
-- NOTE: A reset command has to be handled carefully. If we reset
-- immediatly (ie use the regular END_BUS_TRANSACTION), we will
-- get a OPB bus error, b/c the HWTI would reset before acking the bus
IP2Bus_Ack <= '1';
system_state_next <= COMMAND_RESET_END_BUS_TRANSACTION_WAIT;
when COMMAND_RESET_END_BUS_TRANSACTION_WAIT =>
-- Wait for the bus to deassert the Rd or Wr chip enable lines
if ( read_ce='0' and write_ce='0' ) then
system_command_next <= SYSTEM_COMMAND_RESET;
system_state_next <= IDLE;
bus_data_out_next <= Z32;
else
system_state_next <= system_state;
end if;
when COMMAND_RUN_INIT =>
-- For the system to issue a RUN command, status must be USED or BLOCKED
-- BLOCKED, or IDLE
case system_status is
when SYSTEM_STATUS_USED =>
--debug_system_next <= --debug_system or x"00000001";
system_command_next <= SYSTEM_COMMAND_RUN;
when SYSTEM_STATUS_BLOCKED =>
--debug_system_next <= --debug_system or x"00000002";
system_command_next <= SYSTEM_COMMAND_RUN;
when others =>
--debug_system_next <= --debug_system or x"00000004";
system_state_next <= END_BUS_TRANSACTION;
end case;
system_state_next <= END_BUS_TRANSACTION;
when GLOBAL_READ_WAIT =>
-- wait one clock cycle per the requirements of bram
system_state_next <= GLOBAL_READ_RESPOND;
when GLOBAL_READ_RESPOND =>
-- return to the system the data it requested
bus_data_out_next <= doa;
system_state_next <= END_BUS_TRANSACTION;
when END_BUS_TRANSACTION =>
-- Put the data on the bus, and 'ack' the bus.
IP2Bus_Ack <= '1';
system_state_next <= END_BUS_TRANSACTION_WAIT;
when END_BUS_TRANSACTION_WAIT =>
-- Wait for the bus to deassert the Rd or Wr chip enable lines
if ( read_ce='0' and write_ce='0' ) then
system_state_next <= IDLE;
bus_data_out_next <= Z32;
else
system_state_next <= system_state;
end if;
end case;
end process HWTI_SYSTEM_STATE_MACHINE;
-----------------------------------------------------------------------
-- The following state machine controls the HWTI, in particular does the bus master things
-----------------------------------------------------------------------
HWTI_USER_STATE_MACHINE : process (Bus2IP_clk) is
begin
wr <= '0'; --write into FSL
-- Default register assignments for bus master signals
IP2Bus_Retry <= '0';
IP2Bus_Error <= '0';
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
IP2Bus_MstBusLock <= '0';
IP2Bus_MstBurst <= '0';
IP2Bus_Addr <= (others => '0');
IP2IP_Addr <= (others => '0');
-- Default register assignments for internal signals
user_state_next <= user_state;
system_request_next <= system_request;
system_result_next <= system_result;
user_return_state_next <= user_return_state;
data_address_next <= data_address;
data_value_next <= data_value;
debug_user_next <= debug_user;
-- Default register assignments for user interface registers
fromUserReg_address_next <= fromUserReg_address;
fromUserReg_value_next <= fromUserReg_value;
fromUserReg_opcode_next <= fromUserReg_opcode;
fromUserReg_function_next <= fromUserReg_function;
intrfc2thrd_value <= toUser_value;
intrfc2thrd_function <= FUNCTION_USER_SELECT;
intrfc2thrd_goWait <= '0';
toUser_value_next <= toUser_value;
-- Default register assignment for memory pointers
framePtr_next <= framePtr;
stackPtr_next <= stackPtr;
heapPtr_next <= heapPtr;
paramCount_next <= paramCount;
-- Temporary registers for library functions
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
-- Default assignments for bram port B
addrb <= (others => '0');
enb <= '0';
web <= '0';
dib <= (others => '0');
case user_state is
-----------------------------------------------------------------------
-- States START through USED_WAIT are used to make sure the hthread
-- system sets the thread_id and command register in the correct sequence
-----------------------------------------------------------------------
when START =>
user_state_next <= NOT_USED;
system_request_next <= NOOP;
system_result_next <= x"FFFFFFFF";
user_return_state_next <= RUNNING;
data_address_next <= Z32;
data_value_next <= Z32;
intrfc2thrd_value <= Z32;
intrfc2thrd_function <= FUNCTION_RESET;
intrfc2thrd_goWait <= '1';
wr <= '1';
toUser_value_next <= Z32;
fromUserReg_address_next <= Z32;
fromUserReg_value_next <= Z32;
fromUserReg_function_next <= FUNCTION_RESET;
fromUserReg_opcode_next <= OPCODE_NOOP;
debug_user_next <= Z32;
heapPtr_next <= x"7600"; --The initial heap ptr takes into account the pre-allocated chunks of memory for malloc
reg1_next <= Z32;
reg2_next <= Z32;
reg3_next <= Z32;
reg4_next <= Z32;
when NOT_USED =>
-- Wait for the thread id to be set by the system
case system_thread_id is
when x"00" =>
user_state_next <= NOT_USED;
--Set up the memory pointers and stack frame for use
framePtr_next <= (GLOBAL_BASE_ADDR + 4) & "00";
stackPtr_next <= (GLOBAL_BASE_ADDR + 4) & "00";
--Base addr + 1 = number of parameters in call, which for thread create is always 1
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 1);
enb <= '1';
web <= '1';
dib <= Z32(0 to 30) & '1';
paramCount_next <= x"00";
-- Stop the HWTUL's reset state
intrfc2thrd_goWait <= '0';
when others =>
user_state_next <= RESET_MALLOC_TABLE;
reg1_next <= x"00000001";
system_request_next <= CHANGE_STATUS_TO_USED;
end case;
when RESET_MALLOC_TABLE =>
-- When a thread starts, need to reset malloc table
case reg1 is
when x"00000001" =>
addrb <= REG_8B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000002";
user_state_next <= RESET_MALLOC_TABLE;
when x"00000002" =>
addrb <= REG_32B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000003";
user_state_next <= RESET_MALLOC_TABLE;
when x"00000003" =>
addrb <= REG_1024B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000004";
user_state_next <= RESET_MALLOC_TABLE;
when others =>
addrb <= REG_UNLIMITED_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= Z32;
user_state_next <= NOT_USED_WAIT;
end case;
when NOT_USED_WAIT =>
-- Wait for the system state machine to change to used status
case system_status is
when SYSTEM_STATUS_USED =>
system_request_next <= NOOP;
user_state_next <= USED;
--Continue to set up strack frame
--base addr + 2 = return address for frame ptr, which for thread create is always, by design, 0000
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 2);
enb <= '1';
web <= '1';
dib <= Z32;
when others =>
user_state_next <= NOT_USED_WAIT;
end case;
when USED =>
-- Wait for a RUN command
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= USED_WAIT;
--Continue (again) to set up the stack frame
--base addr + 3 = return state, which for thread create is always, by design 0000
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 3);
enb <= '1';
web <= '1';
dib <= Z32;
when others =>
user_state_next <= USED;
end case;
when USED_WAIT =>
-- Wait for system state machines to update status register
case system_status is
when SYSTEM_STATUS_RUNNING =>
system_request_next <= NOOP;
intrfc2thrd_function <= FUNCTION_START;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when others =>
user_state_next <= USED_WAIT;
end case;
when RUNNING =>
system_request_next <= NOOP;
--wait untill a new request from user logic arrives
if (exist='1') then
user_state_next <= SERVICE_NEW_REQUST;
else
user_state_next <= RUNNING;
end if;
-----------------------------------------------------------------------
-- Once the user_state machine reaches RUNNING, the thread has been
-- created and is expected to run. The RUNNING state waits for the
-- user thread to request an opperation. Once an opperation is
-- requested, it starts to act on it. By default, the HWTI tells the user logic
-- to do its own thing, ie FUNCTION_USER_SELECT.
-----------------------------------------------------------------------
when SERVICE_NEW_REQUST =>
fromUserReg_address_next <= fromUser_address;
fromUserReg_value_next <= fromUser_value;
fromUserReg_function_next <= fromUser_function;
fromUserReg_opcode_next <= fromUser_opcode;
-- Find out what the HWTUL is requesting, if anything
case fromUser_opcode is
--------------------------------------------------------------
-- Memory sub-interface
--------------------------------------------------------------
when OPCODE_LOAD =>
if (fromUser_address(0 to 15) = C_BASEADDR(0 to 15)) then
-- HWTUL is requesting to read an address in BRAM
addrb <= fromUser_address(17 to 29);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
-- Check for a non-word-aligned read
case fromUser_address(30 to 31) is
when "00" =>
user_return_state_next <= LOCAL_LOAD_RESPOND;
when OTHERS =>
user_return_state_next <= LOCAL_PARTIAL_LOAD;
end case;
else
-- HWTUL is requesting to read an address from global address space
data_address_next <= fromUser_address;
user_return_state_next <= GLOBAL_LOAD_RETURN;
user_state_next <= MASTER_LOAD_INIT;
end if;
when OPCODE_STORE =>
if (fromUser_address(0 to 15) = C_BASEADDR(0 to 15)) then
-- HWTUL is requestiong to write an address in BRAM
addrb <= fromUser_address(17 to 29);
dib <= fromUser_value;
web <= '1';
enb <= '1';
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
else
-- HWTUL is requestiong to write an address in global address space
data_address_next <= fromUser_address;
data_value_next <= fromUser_value;
user_state_next <= MASTER_STORE_INIT;
user_return_state_next <= GLOBAL_LOAD_RETURN;
end if;
when OPCODE_DECLARE =>
-- increment the stack ptr the number of words the UL is declaring
-- TODO: check to see that param=0. If not that means the user has called push and shouldn't be calling declare again until after a function call and return.
stackPtr_next <= '0' & (stackPtr(1 to 13) + fromUser_value(19 to 31)) & "00";
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when OPCODE_READ =>
-- read the stack, based on frame ptr offset, provided by user
addrb <= framePtr(1 to 13) + fromUser_address(19 to 31);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LOCAL_LOAD_RESPOND;
when OPCODE_WRITE =>
-- write to the stack, based on frame ptr offset, provided by user
addrb <= framePtr(1 to 13) + fromUser_address(19 to 31);
dib <= fromUser_value;
web <= '1';
enb <= '1';
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when OPCODE_ADDRESSOF =>
-- return to the user frame ptr + offset
intrfc2thrd_value <= C_BASEADDR(0 to 15)
& "00"
& (framePtr(2 to 13) + fromUser_address(20 to 31))
& "00";
toUser_value_next <= C_BASEADDR(0 to 15)
& "00"
& (framePtr(2 to 13) + fromUser_address(20 to 31))
& "00";
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
--------------------------------------------------------------
-- Function sub-interface
--------------------------------------------------------------
when OPCODE_PUSH =>
-- Place the argument where the stack pointer is now, and then increment sp
addrb <= stackPtr(1 to 13);
dib <= fromUser_value;
enb <= '1';
web <= '1';
paramCount_next <= paramCount + 1;
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when OPCODE_POP =>
-- Read the number of parameters on the stack for the current function
addrb <= framePtr(1 to 13) - 3 ;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= POP_READ_PARAM_COUNT;
when OPCODE_CALL =>
case fromUser_function is
when FUNCTION_HTHREAD_ATTR_INIT =>
-- Read the parameter the user passed in
-- Parameter should be previously allocated thread attr struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_ATTR_INIT;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_ATTR_DESTROY =>
-- Read the parameter the user passed in
-- Parameter should be previously allocated thread attr struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_ATTR_INIT;
-- Note that I'm reusing the ATTR_INIT state
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_CREATE =>
-- Need to call the RPC code
-- Set reg1 to the opcode
reg1_next <= Z32(0 to 15) & FUNCTION_HTHREAD_CREATE;
-- Read the value of the mutex and condvar numbers
addrb <= REG_RPC_MUTEXCONVAR(1 to 13);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC;
when FUNCTION_HTHREAD_JOIN =>
-- Need to call the RPC code
-- Set reg1 to the opcode
reg1_next <= Z32(0 to 15) & FUNCTION_HTHREAD_JOIN;
-- Read the value of the mutex and condvar numbers
addrb <= REG_RPC_MUTEXCONVAR(1 to 13);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC;
when FUNCTION_HTHREAD_SELF =>
-- return the thread id to the user
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_value <= Z32(0 to 23) & system_thread_id;
toUser_value_next <= Z32(0 to 23) & system_thread_id;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_YIELD =>
-- return to the user immediatly
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_EQUAL =>
--read the second paramter the user pushed
--which should be a hthread_t (which is the same as an int)
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_EQUAL;
when FUNCTION_HTHREAD_EXIT =>
system_request_next <= CHANGE_STATUS_TO_EXIT;
user_state_next <= HTHREAD_EXIT;
when FUNCTION_HTHREAD_EXIT_ERROR =>
system_request_next <= CHANGE_STATUS_TO_EXIT_ERROR;
user_state_next <= HTHREAD_EXIT;
when FUNCTION_HTHREAD_MUTEXATTR_INIT =>
-- Read the parameter the user passed in
-- Parameter should be previously allocated mutexattr struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEXATTR_INIT;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_MUTEXATTR_DESTROY =>
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- return a SUCCESS to the user
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_MUTEXATTR_SETNUM =>
-- Read the second parameter the user pushed in
-- Parameter should be mutexattr struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM;
when FUNCTION_HTHREAD_MUTEXATTR_GETNUM =>
-- Read the second parameter the user pushed in
-- Parameter should be mutexattr struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM;
when FUNCTION_HTHREAD_MUTEX_INIT =>
-- Read the second parameter the user pushed in
-- Parameter should be mutex struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEX_INIT;
when FUNCTION_HTHREAD_MUTEX_DESTROY =>
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- return a SUCCESS to the user
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_MUTEX_LOCK =>
-- Read the parameter the user passed in
-- Parameter should be previously initialized mutex struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEX_LOCK;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_MUTEX_UNLOCK =>
-- Read the parameter the user passed in
-- Parameter should be previously initialized mutex struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEX_UNLOCK;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_MUTEX_TRYLOCK =>
-- Read the parameter the user passed in
-- Parameter should be previously initialized mutex struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEX_TRYLOCK;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_CONDATTR_INIT =>
-- Read the parameter the user passed in
-- Parameter should be previously allocated condattr struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_CONDATTR_INIT;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_CONDATTR_DESTROY =>
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- return a SUCCESS to the user
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_CONDATTR_SETNUM =>
-- Read the second parameter the user pushed in
-- Parameter should be condattr struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
--Note that I am reusing the states for MUTEXATTR_GETNUM
user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM;
when FUNCTION_HTHREAD_CONDATTR_GETNUM =>
-- Read the second parameter the user pushed in
-- Parameter should be condattr struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
--Note that I am reusing the states for MUTEXATTR_GETNUM
user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM;
when FUNCTION_HTHREAD_COND_INIT =>
-- Read the second parameter the user pushed in
-- Parameter should be mutex struct address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_INIT;
when FUNCTION_HTHREAD_COND_DESTROY =>
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- return a SUCCESS to the user
intrfc2thrd_function <= fromUser_value(16 to 31);
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when FUNCTION_HTHREAD_COND_WAIT =>
-- Read the the first parameter the user passed in
-- Parameter should be previously initialized cond var struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_WAIT;
when FUNCTION_HTHREAD_COND_BROADCAST =>
-- Read the parameter the user passed in
-- Parameter should be previously initialized cond var struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_BCAST;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_COND_SIGNAL =>
-- Read the parameter the user passed in
-- Parameter should be previously initialized cond var struct's address
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_SIGNAL;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
---------------------------------------------------------
-- stdlib.h functions
---------------------------------------------------------
when FUNCTION_MALLOC =>
-- User wants to allocate memory on the heap
-- Read the parameter the user (should have) passed in
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MALLOC;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_CALLOC =>
-- User wants to allocate memory on the heap
-- Read the first parameter the user passed in
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_CALLOC;
when FUNCTION_FREE =>
-- User wants to de-allocate memory on the heap
-- Read the address of the data the user passed in
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_FREE;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
---------------------------------------------------------
-- string.h functions
---------------------------------------------------------
when FUNCTION_MEMCPY =>
-- Copy data from *dest to *src, with size n
-- read the first parameter *dest
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MEMCPY;
-- Reset number of parameters
paramCount_next <= x"00";
---------------------------------------------------------
-- User defined functions
---------------------------------------------------------
when others =>
-- first write the number of params to the stack
addrb <= stackPtr(1 to 13);
dib <= Z32(0 to 23) & paramCount;
enb <= '1';
web <= '1';
-- update the stack ptr and reset the num of params
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
paramCount_next <= x"00";
user_state_next <= USER_FUNCTION_CALL;
end case;
when OPCODE_RETURN =>
-- user is returning from an internal function
-- set the return value
intrfc2thrd_value <= fromUser_value;
toUser_value_next <= fromUser_value;
-- read the HWTUL return state
addrb <= framePtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN;
when others => -- ie noop
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end case;
-----------------------------------------------------------------------
-- LIB FUNCTION MEMCPY
-- memcpy( void *dest, const void *src, size_t n )
-- Copy memory from dest to src, with size n
-- TODO use burst transacations instead of single transactions
-----------------------------------------------------------------------
when LIB_FUNCTION_MEMCPY =>
-- reg1 is the destination pointer
reg1_next <= dob;
-- read the source pointer from the stack
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MEMCPY_2;
when LIB_FUNCTION_MEMCPY_2 =>
-- reg2 is the source pointer
reg2_next <= dob;
-- read the size n from the stack
addrb <= stackPtr(1 to 13) - 3;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MEMCPY_3;
when LIB_FUNCTION_MEMCPY_3 =>
-- reg3 is the number of bytes to copy
-- force the number of bytes to copy to be increment of 4
reg3_next <= dob(0 to 29) & "00";
-- decrement the stack pointer 3 words
stackPtr_next <= '0' & (stackPtr(1 to 13) - 3) & "00";
-- reg4 will track if the to and from address are local or global
-- specifically reg4(0) is source, reg4(1) is destination
-- a 1 means the address is local, 0 means global
if ( reg2(0 to 15) = C_BASEADDR(0 to 15) ) then
reg4_next(0) <= '1';
else
reg4_next(0) <= '0';
end if;
if ( reg1(0 to 15) = C_BASEADDR(0 to 15) ) then
reg4_next(1) <= '1';
else
reg4_next(1) <= '0';
end if;
user_state_next <= LIB_FUNCTION_MEMCPY_4;
when LIB_FUNCTION_MEMCPY_4 =>
case reg3 is
when Z32 =>
-- all data is copied, return to user
intrfc2thrd_function <= fromUserReg_value(16 to 31);
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when others =>
-- there is more to read
-- initiate read of address stored in reg2, source of data
-- Determine if the address is local
case reg4(0) is
when '1' =>
-- read from local
enb <= '1';
addrb <= reg2(17 to 29);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MEMCPY_5;
when others =>
-- read from local
data_address_next <= reg2;
user_return_state_next <= LIB_FUNCTION_MEMCPY_5;
user_state_next <= MASTER_LOAD_INIT;
end case;
end case;
--
when LIB_FUNCTION_MEMCPY_5 =>
-- initiate write of data to address stored in reg1
-- Determine if the address is local
case reg4(1) is
when '1' =>
-- write to local
enb <= '1';
web <= '1';
addrb <= reg1(17 to 29);
-- if the previous read was local pull from dob, instead of data_value
case reg4(0) is
when '1' =>
dib <= dob;
when others =>
dib <= data_value;
end case;
user_state_next <= LIB_FUNCTION_MEMCPY_6;
when others =>
-- write to global
data_address_next <= reg1;
-- if the previous read was local pull from dob, instead of data_value
case reg4(0) is
when '1' =>
data_value_next <= dob;
when others =>
data_value_next <= data_value;
end case;
user_return_state_next <= LIB_FUNCTION_MEMCPY_6;
user_state_next <= MASTER_STORE_INIT;
end case;
when LIB_FUNCTION_MEMCPY_6 =>
-- increment the pointers
reg1_next <= reg1 + 4;
reg2_next <= reg2 + 4;
-- decrement the count one word
reg3_next <= reg3 - 4;
user_state_next <= LIB_FUNCTION_MEMCPY_4;
-----------------------------------------------------------------------
-- LIB FUNCTION FREE
-- free(void * address);
-- de-allocates space on the heap, specified by passed in parameter
-----------------------------------------------------------------------
when LIB_FUNCTION_FREE =>
-- Record the address of the data to deallocate
reg1_next <= dob;
user_state_next <= LIB_FUNCTION_FREE_1;
when LIB_FUNCTION_FREE_1 =>
-- The following is a lookup table for determine which mask to use
user_state_next <= LIB_FUNCTION_FREE_2;
case reg1(16 to 31) is
when x"7FF8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"7FFFFFFF";
when x"7FF0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"BFFFFFFF";
when x"7FE8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"DFFFFFFF";
when x"7FE0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"EFFFFFFF";
when x"7FD8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"F7FFFFFF";
when x"7FD0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FBFFFFFF";
when x"7FC8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FDFFFFFF";
when x"7FC0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FEFFFFFF";
when x"7FB8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FF7FFFFF";
when x"7FB0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFBFFFFF";
when x"7FA8" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFDFFFFF";
when x"7FA0" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFEFFFFF";
when x"7F98" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFF7FFFF";
when x"7F90" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFBFFFF";
when x"7F88" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFDFFFF";
when x"7F80" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFEFFFF";
when x"7F78" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFF7FFF";
when x"7F70" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFBFFF";
when x"7F68" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFDFFF";
when x"7F60" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFEFFF";
when x"7F58" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFF7FF";
when x"7F50" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFBFF";
when x"7F48" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFDFF";
when x"7F40" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFEFF";
when x"7F38" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFF7F";
when x"7F30" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFBF";
when x"7F28" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFDF";
when x"7F20" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFEF";
when x"7F18" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFF7";
when x"7F10" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFFB";
when x"7F08" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFFD";
when x"7F00" =>
reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
reg3_next <= x"FFFFFFFE";
when x"7EE0" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"7FFFFFFF";
when x"7EC0" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"BFFFFFFF";
when x"7EA0" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"DFFFFFFF";
when x"7E80" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"EFFFFFFF";
when x"7E60" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"F7FFFFFF";
when x"7E40" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"FBFFFFFF";
when x"7E20" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"FDFFFFFF";
when x"7E00" =>
reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
reg3_next <= x"FEFFFFFF";
when x"7A00" =>
reg2_next <= Z32(0 to 15) & REG_1024B_DYNAMIC_TABLE & "00";
reg3_next <= x"7FFFFFFF";
when x"7600" =>
reg2_next <= Z32(0 to 15) & REG_1024B_DYNAMIC_TABLE & "00";
reg3_next <= x"BFFFFFFF";
when others =>
-- should be the unlimited case
-- TODO check to make sure the user is de allocating this space
-- and not some random address
reg2_next <= Z32(0 to 15) & REG_UNLIMITED_DYNAMIC_TABLE & "00";
reg3_next <= Z32;
-- deallocate the space on the heap
heapPtr_next <= x"7600";
end case;
when LIB_FUNCTION_FREE_2 =>
enb <= '1';
addrb <= reg2(17 to 29);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_FREE_3;
when LIB_FUNCTION_FREE_3 =>
-- Mark the space as deallocated
enb <= '1';
web <= '1';
addrb <= reg2(17 to 29);
dib <= dob and reg3;
-- Return to the user
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_function <= fromUserReg_value(16 to 31);
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- LIB FUNCTION CALLOC
-- malloc(size_t numBytes, size_t size);
-- Allocate space on the heap, specified by passed in parameters size*size_t
-----------------------------------------------------------------------
when LIB_FUNCTION_CALLOC =>
-- Record the first parameter in reg3
reg3_next <= dob;
-- Read the second parameter
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_CALLOC_2;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when LIB_FUNCTION_CALLOC_2 =>
reg2_next <= dob;
user_state_next <= LIB_FUNCTION_CALLOC_3;
when LIB_FUNCTION_CALLOC_3 =>
-- Step 1: Multiply reg2 and reg 3, storing result in reg1
reg4_next <= std_logic_vector(conv_signed(signed("00"®2(16 to 31)) * signed("00"®3(16 to 31)), 32));
reg1_next <= std_logic_vector(conv_signed(signed("00"®2(0 to 15)) * signed("00"®3(0 to 15)), 32));
user_state_next <= LIB_FUNCTION_CALLOC_4;
when LIB_FUNCTION_CALLOC_4 =>
-- Step 2: Multiply reg2 and reg 3, storing result in reg1
reg4_next <= std_logic_vector(conv_signed(signed("00"®2(16 to 31)) * signed("00"®3(0 to 15)), 32));
reg1_next <= reg4 + (reg1(16 to 31)&x"0000");
user_state_next <= LIB_FUNCTION_CALLOC_5;
when LIB_FUNCTION_CALLOC_5 =>
-- Step 3: Multiply reg2 and reg 3, storing result in reg1
reg1_next <= reg4(16 to 31)&x"0000" + reg1;
user_state_next <= LIB_FUNCTION_MALLOC_8a;
-----------------------------------------------------------------------
-- LIB FUNCTION MALLOC
-- malloc(size_t size);
-- Allocate space on the heap, specified by passed in parameter
-----------------------------------------------------------------------
when LIB_FUNCTION_MALLOC =>
-- Record the size of the bytes to allocate in reg 1
reg1_next <= dob;
user_state_next <= LIB_FUNCTION_MALLOC_8a;
when LIB_FUNCTION_MALLOC_8a =>
-- Test to see if we should read the 8B dynamic memory table
if ( reg1 <= x"00000008" ) then
-- size of data to allocate is less than/equal to 8B
-- Read the dynmic memory table for 8B
enb <= '1';
addrb <= REG_8B_DYNAMIC_TABLE (1 to 13);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MALLOC_8b;
else
-- size of data to allocate is greater than 8B
user_state_next <= LIB_FUNCTION_MALLOC_32a;
end if;
-- Initialize reg2, the loop iterator
reg2_next <= x"80000000";
when LIB_FUNCTION_MALLOC_8b =>
-- reg 3 is the value of the dynamic memory table
reg3_next <= dob;
-- reg 4 is the address to send back to the user once an open chunk is found
-- start with the highest possible value, then decrement as we search
reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_8B;
user_state_next <= LIB_FUNCTION_MALLOC_8c;
when LIB_FUNCTION_MALLOC_8c =>
-- iterate through memory table until we find an open chunk of memory
if ( (reg2 or reg3) /= reg3 ) then
-- we have found an open chunk of memory
-- mark this chunk of memory as allocated
enb <= '1';
web <= '1';
addrb <= REG_8B_DYNAMIC_TABLE(1 to 13);
dib <= reg2 or reg3;
-- return to the user pointer to allocated memory
intrfc2thrd_value <= reg4;
toUser_value_next <= reg4;
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_function <= fromUserReg_value(16 to 31);
user_state_next <= RUNNING;
else
-- need to keep looking
if ( reg2 = x"00000001" ) then
-- we reached the end of the 8B block table, and all spaces
-- are used, try the 32B block table
user_state_next <= LIB_FUNCTION_MALLOC_32a;
else
-- decrement the return address
reg4_next <= reg4 - 8;
-- shift the loop iterator
reg2_next <= '0' & reg2(0 to 30);
-- try again
user_state_next <= LIB_FUNCTION_MALLOC_8c;
end if;
end if;
when LIB_FUNCTION_MALLOC_32a =>
-- Test to see if we should read the 32B dynamic memory table
if ( reg1 <= x"00000020" ) then
-- size of data to allocate is less than/equal to 32B
-- Read the dynmic memory table for 32B
enb <= '1';
addrb <= REG_32B_DYNAMIC_TABLE (1 to 13);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MALLOC_32b;
else
-- size of data to allocate is greater than 32B
user_state_next <= LIB_FUNCTION_MALLOC_1024a;
end if;
when LIB_FUNCTION_MALLOC_32b =>
-- reg 3 is the value of the dynamic memory table
reg3_next <= dob;
-- reg 4 is the address to send back to the user once an open chunk is found
-- start with the highest possible value, then decrement as we search
reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_32B;
user_state_next <= LIB_FUNCTION_MALLOC_32c;
when LIB_FUNCTION_MALLOC_32c =>
-- iterate through memory table until we find an open chunk of memory
if ( (reg2 or reg3) /= reg3 ) then
-- we have found an open chunk of memory
-- mark this chunk of memory as allocated
enb <= '1';
web <= '1';
addrb <= REG_32B_DYNAMIC_TABLE(1 to 13);
dib <= reg2 or reg3;
-- return to the user pointer to allocated memory
intrfc2thrd_value <= reg4;
toUser_value_next <= reg4;
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_function <= fromUserReg_value(16 to 31);
user_state_next <= RUNNING;
else
-- need to keep looking
if ( reg2 = x"01000000" ) then
-- we reached the end of the 32B block table, and all spaces
-- are used, try the 1024B block table
user_state_next <= LIB_FUNCTION_MALLOC_1024a;
else
-- decrement the return address
reg4_next <= reg4 - 32;
-- shift the loop iterator
reg2_next <= '0' & reg2(0 to 30);
-- try again
user_state_next <= LIB_FUNCTION_MALLOC_32c;
end if;
end if;
when LIB_FUNCTION_MALLOC_1024a =>
-- Test to see if we should read the 1024B dynamic memory table
if ( reg1 <= x"00000400" ) then
-- size of data to allocate is less than/equal to 1024B
-- Read the dynmic memory table for 1024B
enb <= '1';
addrb <= REG_1024B_DYNAMIC_TABLE (1 to 13);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MALLOC_1024b;
else
-- size of data to allocate is greater than 1024B
user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITa;
end if;
when LIB_FUNCTION_MALLOC_1024b =>
-- reg 3 is the value of the dynamic memory table
reg3_next <= dob;
-- reg 4 is the address to send back to the user once an open chunk is found
-- start with the highest possible value, then decrement as we search
reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_1024B;
user_state_next <= LIB_FUNCTION_MALLOC_1024c;
when LIB_FUNCTION_MALLOC_1024c =>
-- iterate through memory table until we find an open chunk of memory
if ( (reg2 or reg3) /= reg3 ) then
-- we have found an open chunk of memory
-- mark this chunk of memory as allocated
enb <= '1';
web <= '1';
addrb <= REG_1024B_DYNAMIC_TABLE(1 to 13);
dib <= reg2 or reg3;
-- return to the user pointer to allocated memory
intrfc2thrd_value <= reg4;
toUser_value_next <= reg4;
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_function <= fromUserReg_value(16 to 31);
user_state_next <= RUNNING;
else
-- need to keep looking
if ( reg2 = x"40000000" ) then
-- we reached the end of the 1024B block table, and all spaces
-- are used, try the UNLIMIT block table
user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITa;
else
-- decrement the return address
reg4_next <= reg4 - 1024;
-- shift the loop iterator
reg2_next <= '0' & reg2(0 to 30);
-- try again
user_state_next <= LIB_FUNCTION_MALLOC_1024c;
end if;
end if;
when LIB_FUNCTION_MALLOC_UNLIMITa =>
-- Test to see if we should read the UNLIMITED dynamic memory table
if ( reg1 <= x"00007000" ) then
-- size of data to allocate is less than/equal to x3000B
-- Read the dynmic memory table for UNLIMITED
enb <= '1';
addrb <= REG_UNLIMITED_DYNAMIC_TABLE (1 to 13);
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LIB_FUNCTION_MALLOC_UNLIMITb;
else
-- size of data is too big, return NULL pointer
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end if;
when LIB_FUNCTION_MALLOC_UNLIMITb =>
if ( dob = Z32 ) then
-- decrement the heapPtr specifed number of parameters
heapPtr_next <= '0' & (heapPtr(1 to 13) - reg1(18 to 29)) & "00";
user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITc;
else
-- already allocated unlimited data, return NULL pointer
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end if;
when LIB_FUNCTION_MALLOC_UNLIMITc =>
-- Write the address to the UNLIMTIED table
enb <= '1';
web <= '1';
addrb <= REG_UNLIMITED_DYNAMIC_TABLE (1 to 13);
dib <= C_BASEADDR(0 to 15) & heapPtr;
-- Tell the user to start executing again, telling it the pointer to allocated space
intrfc2thrd_value <= C_BASEADDR(0 to 15) & heapPtr;
toUser_value_next <= C_BASEADDR(0 to 15) & heapPtr;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- USER FUNCTION RETURN
-- These states are used when the HWTUL is returning from a user
-- defined function
-----------------------------------------------------------------------
when USER_FUNCTION_RETURN =>
-- check the return state address to make sure it is not 0000,
-- if it is 0000 then this is the main thread function returning
-- and we should do a hthread_exit instead.
case dob(16 to 31) is
when x"0000" =>
-- This is the return call for the main thread function
-- Need to set up the stack and state as it would appear
-- if the user called hthread_exit directly.
enb <= '1';
web <= '1';
dib <= fromUserReg_value;
addrb <= stackPtr(1 to 13);
paramCount_next <= paramCount + 1;
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
system_request_next <= CHANGE_STATUS_TO_EXIT;
user_state_next <= HTHREAD_EXIT;
when others =>
-- This is an user defined function returning
-- set the return state of the HWTUL
reg1_next <= dob; -- store return address temp in reg1
-- read the number of parameters that were involved in this function
addrb <= framePtr(1 to 13) - 3;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN_2;
end case;
when USER_FUNCTION_RETURN_2 =>
-- set the stack pointer
-- data coming off of the BRAM is number of params from previous function
stackPtr_next <= '0' & ((framePtr(1 to 13) - 3) - dob(19 to 31)) & "00";
-- read the frame pointer return address
addrb <= framePtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN_3;
when USER_FUNCTION_RETURN_3 =>
-- set the frame pointer
framePtr_next <= dob(16 to 31);
-- tell the user to start running again.
intrfc2thrd_function <= reg1(16 to 31);
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- USER FUNCTION_CALL
-- States are used when the HWTUL calls a function it has defined
-- or indirectly for a remote procedural call
-----------------------------------------------------------------------
when USER_FUNCTION_CALL =>
-- write the frame pointer to the stack
addrb <= stackPtr(1 to 13);
dib <= C_BASEADDR(0 to 15) & framePtr;
web <= '1';
enb <= '1';
-- increment the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
user_state_next <= USER_FUNCTION_CALL_2;
when USER_FUNCTION_CALL_2 =>
-- write the return state, for the HWTUL, to the stack
addrb <= stackPtr(1 to 13);
dib <= Z32(0 to 15) & fromUserReg_value(16 to 31);
web <= '1';
enb <= '1';
-- update the stack and frame ptr
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
framePtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
-- Tell the HWTUL to run again, starting at the new function address
intrfc2thrd_function <= fromUserReg_function;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Remote Procedural Call
-- May perform any action the software rpc thread is set up to accept
-- An RPC is a function call that the HWTI can not implement directly,
-- instead it has to call a software thread to do the work for it.
-- The SW thread is called through mutex & condition variable signalling.
-- reg1 = opcode
-- reg2 = mutex and condvar numbers, held in REG_RPC_MUTEXCONVAR
-- 0 to 0 unused
-- 8 to 15 rpc_mutex, protects the rpc thread
-- 16 to 23 rpc_signal_mutex, protects the rpc condvar
-- 24 to 31 rpc_signal, condvar
-- reg3 = rpc struct address, held in REG_RPC_T_ADDRESS
-- reg4 = temp
-----------------------------------------------------------------------
when HTHREAD_RPC =>
-- Store the value of the rpc mutexconvar to reg2
reg2_next <= dob;
-- Read the value of the rpc struct address
addrb <= REG_RPC_T_ADDRESS(1 to 13);
dib <= Z32(0 to 15) & fromUserReg_value(16 to 31);
enb <= '1';
-- Set up reg4 to hold the the rpc_mutex number
reg4_next <= Z32(0 to 23) & dob(8 to 15);
user_return_state_next <= HTHREAD_RPC_2;
user_state_next <= WAIT_ONE_CYCLE;
-- hthread_mutex_lock( rpc_mutex );
when HTHREAD_RPC_2 =>
-- Store the value of rpc struct address to reg3
reg3_next <= dob;
-- Read the register, on the mutex manager, to lock rpc_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_3 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when "01" =>
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_3a;
when others =>
--The Lock is ours
user_state_next <= HTHREAD_RPC_5;
end case;
when HTHREAD_RPC_3a =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_4;
when others =>
user_state_next <= HTHREAD_RPC_3a;
end case;
when HTHREAD_RPC_4 =>
--Wait for a run command
case system_command is
when SYSTEM_COMMAND_RUN =>
user_state_next <= HTHREAD_RPC_5;
system_request_next <= CHANGE_STATUS_TO_RUN;
when others =>
user_state_next <= HTHREAD_RPC_4;
end case;
when HTHREAD_RPC_5 =>
--Wait till status is RUNNING
--NOTE: status should already be running if we got the lock in RPC_3
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_6;
system_request_next <= NOOP;
-- Set up reg4 to hold the the rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_5;
end case;
-- hthread_mutex_lock( rpc_signal_mutex );
when HTHREAD_RPC_6 =>
-- Read the register, on the mutex manager, to lock rpc_signal_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_7;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_7 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when "01" =>
user_state_next <= HTHREAD_RPC_7a;
system_request_next <= CHANGE_STATUS_TO_BLOCK;
when others =>
--The Lock is ours
user_state_next <= HTHREAD_RPC_9;
end case;
when HTHREAD_RPC_7a =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_8;
when others =>
user_state_next <= HTHREAD_RPC_7a;
end case;
when HTHREAD_RPC_8 =>
--Wait for a run command
case system_command is
when SYSTEM_COMMAND_RUN =>
user_state_next <= HTHREAD_RPC_8a;
system_request_next <= CHANGE_STATUS_TO_RUN;
when others =>
user_state_next <= HTHREAD_RPC_8;
end case;
when HTHREAD_RPC_8a =>
--Wait till status is RUNNING
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_9;
system_request_next <= NOOP;
when others =>
user_state_next <= HTHREAD_RPC_8a;
end case;
--rpc->opcode = opcode
when HTHREAD_RPC_9 =>
--When we get to this point, the lock on rpc_mutex and rpc_signal_mutex is now ours
--Write the value of the opcode to the struct
data_address_next <= reg3;
data_value_next <= reg1;
user_return_state_next <= HTHREAD_RPC_10;
user_state_next <= MASTER_STORE_INIT;
--Set up reg4, for the next sequence of events. Namely set it to 8, which is the
--offset, from the base address of the rpc argument struct, to place the first parameter
reg4_next <= x"00000008";
--for( i=0; i<5; i++ ) rpc->args[i] = args[i]
when HTHREAD_RPC_10 =>
case paramCount is
when x"00" =>
-- have transfered all of the parameters to the rpc struct
-- Set up reg4 to hold the the rpc_signal number
reg4_next <= Z32(0 to 23) & reg2(24 to 31);
user_state_next <= HTHREAD_RPC_12;
when others =>
-- have one or more parameters than need to be transfered
-- read the parameter from the stack
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC_11;
-- decrement the stackPtr
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
end case;
when HTHREAD_RPC_11 =>
-- store the parameter to the rpc struct
data_address_next <= reg3(0 to 23) & (reg3(24 to 31) + reg4(24 to 31));
data_value_next <= dob;
user_return_state_next <= HTHREAD_RPC_10;
user_state_next <= MASTER_STORE_INIT;
-- increment reg4 by one word, ie 4 bytes
reg4_next <= reg4 + 4;
-- decrment paramCount
paramCount_next <= paramCount - 1;
when HTHREAD_RPC_12 =>
-- hthread_cond_signal( rpc_signal );
-- Read the register, on the cond var manager, to signal the next thread
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_SIGNAL & --bits(12 to 15) signal command
"00000000" & --bits(16 to 23) thread id
reg4(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_RPC_13;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_13 =>
--Check the return status, repeat if attempt failed
if ( data_value(28 to 31) = CONDVAR_FAILED ) then
--repeat step 2
user_state_next <= HTHREAD_RPC_12;
else
--The cond var, rpc_signal, is signaled
-- Set up reg4 to hold condvar rpc_signal number
reg4_next <= Z32(0 to 23) & reg2(24 to 31);
user_state_next <= HTHREAD_RPC_14;
end if;
when HTHREAD_RPC_14 =>
-- hthread_cond_wait( rpc_signal, rpc_signal_mutex)
-- First step in waiting is to signal the wait
-- Call to wait for cond variable signal
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_WAIT & --bits(12 to 15) broadcast command
system_thread_id & --bits(16 to 23) thread id
reg4(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_RPC_15;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_15 =>
-- Check return value, repeat if nessessary
case data_value(28 to 31) is
when CONDVAR_FAILED =>
--repeat previous step
user_state_next <= HTHREAD_RPC_14;
when others =>
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_15a;
end case;
when HTHREAD_RPC_15a =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_16;
--Set up reg4 to hold mutex rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_15a;
end case;
when HTHREAD_RPC_16 =>
-- Second step in waiting is to release the mutex, this is the signal to the
-- rest of the system that it is safe to issue hthread_signal or hthread_broadcast
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_17;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_17 =>
--Wait for a run command, which is the signal that the rpc is done
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_RPC_17a;
when others =>
user_state_next <= HTHREAD_RPC_17;
end case;
when HTHREAD_RPC_17a =>
--Wait till status is RUNNING
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_18;
system_request_next <= NOOP;
--Set up reg4 to hold mutex rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_17a;
end case;
when HTHREAD_RPC_18 =>
-- Last step in waiting is to relock the rpc_signal_mutex
-- Read the register, on the mutex manager, to lock rpc_signal_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_19;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_19 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when "01" =>
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_19a;
when others =>
--The Lock is ours
user_state_next <= HTHREAD_RPC_21;
end case;
when HTHREAD_RPC_19a =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_20;
when others =>
user_state_next <= HTHREAD_RPC_19a;
end case;
when HTHREAD_RPC_20 =>
--Wait for a run command, which is the signal that the lock is ours
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_RPC_20a;
when others =>
user_state_next <= HTHREAD_RPC_20;
end case;
when HTHREAD_RPC_20a =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_RUNNING =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_21;
when others =>
user_state_next <= HTHREAD_RPC_20a;
end case;
when HTHREAD_RPC_21 =>
--read the result from the rpc struct
data_address_next <= reg3 + 4;
user_return_state_next <= HTHREAD_RPC_22;
user_state_next <= MASTER_LOAD_INIT;
--set up reg4 to hold the rpc_signal_mutex
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
--change status to RUNNING
system_request_next <= CHANGE_STATUS_TO_RUN;
when HTHREAD_RPC_22 =>
--store the result in reg1
reg1_next <= data_value;
-- hthread_mutex_unlock( rpc_signal_mutex );
-- Read the register, on the mutex manager, to unlock the specified mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_23;
user_state_next <= MASTER_LOAD_INIT;
--set up reg4 to hold the rpc_mutex
reg4_next <= Z32(0 to 23) & reg2(8 to 15);
when HTHREAD_RPC_23 =>
-- hthread_mutex_unlock( rpc_mutex );
-- Read the register, on the mutex manager, to unlock the specified mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_24;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_24 =>
system_request_next <= NOOP;
-- Return the results to the user
intrfc2thrd_value <= reg1;
toUser_value_next <= reg1;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_ATTR_INIT
-- Hint hthread_attr_init( hthread_attr_t * attr )
-- Hint hthread_attr_destroy( hthread_attr_t * attr )
-- sets the attributes, of the passed in pointer to a thread attribute
-- to their default values. Both the init and destroy functions
-- work the same
-- Always returns an SUCCESS
-- reg1 will hold address of attr
-----------------------------------------------------------------------
when HTHREAD_ATTR_INIT =>
reg1_next <= dob;
--write a Hfalse, a 0, to attr->detached
data_address_next <= dob;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_ATTR_INIT_2;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_2 =>
--write a Hfalse, a 0, to attr->hardware
data_address_next <= reg1 + 4;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_ATTR_INIT_3;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_3 =>
--write a 0, to attr->hardware_addr
data_address_next <= reg1 + 8;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_ATTR_INIT_4;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_4 =>
--write a HT_DEFAULT_STACK_SIZE, 16 * 1024,, to attr->stack_size
data_address_next <= reg1 + 12;
data_value_next <= x"00004000";
user_return_state_next <= HTHREAD_ATTR_INIT_5;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_5 =>
--write a NULL, a 0, to attr->stack_addr
data_address_next <= reg1 + 16;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_ATTR_INIT_6;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_6 =>
--write a 64 priority, to attr->sched_param
data_address_next <= reg1 + 20;
data_value_next <= x"00000020";
user_return_state_next <= HTHREAD_ATTR_INIT_7;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_ATTR_INIT_7 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_EQUAL
-- Hint hthread_equal( hthread_t t1, hthread_2 t2 )
-- tests to see if t1 is equal to t2
-- return values are 1 if t1 == t2, else 0
-- reg1 will hold t1
-----------------------------------------------------------------------
when HTHREAD_EQUAL =>
reg1_next <= dob;
-- Read the value of t2
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_EQUAL_2;
-- Reset the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- Reset number of parameters
paramCount_next <= x"00";
when HTHREAD_EQUAL_2 =>
--Check to see if the two thread ids are equal
if ( dob(24 to 31) = reg1(24 to 31) ) then
intrfc2thrd_value <= Z32(0 to 30) & '1';
toUser_value_next <= Z32(0 to 30) & '1';
else
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
end if;
-- Tell the HWTUL to run again, starting at the new function address
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_CONDATTR_INIT
-- hthread_condattr_init( condattr_t * )
-- Initializes the condattr struct to default values
-----------------------------------------------------------------------
when HTHREAD_CONDATTR_INIT =>
reg1_next <= dob;
-- Write a 0, the default condvar number, to the condattr_t.num
data_address_next <= dob;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_CONDATTR_INIT_2;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_CONDATTR_INIT_2 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_COND_INIT
-- hthread_cond_init( cond_t *, hthread_condattr_t*)
-- Creates a condition variable based on either the default attributes,
-- if condattr_t is NULL, or on condattr_t.
-----------------------------------------------------------------------
when HTHREAD_COND_INIT =>
-- Store the address of the condvar in reg1;
reg1_next <= dob;
-- Read the address, that the use passed in, of condattr_t
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_INIT_2;
-- Reset the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- Reset number of parameters
paramCount_next <= x"00";
when HTHREAD_COND_INIT_2 =>
-- Store the address of condattr in reg2;
reg2_next <= dob;
-- Determine if the attributes are NULL or not
case dob is
when Z32 =>
-- Create a condition variable with default attributes
reg3_next <= Z32; --condvar number 0
user_state_next <= HTHREAD_COND_INIT_5;
when OTHERS =>
user_state_next <= HTHREAD_COND_INIT_3;
end case;
when HTHREAD_COND_INIT_3 =>
-- Read the value of the attr's num
data_address_next <= reg2;
user_return_state_next <= HTHREAD_COND_INIT_4;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_INIT_4 =>
-- Store the value of attr's num in reg3
reg3_next <= data_value;
user_state_next <= HTHREAD_COND_INIT_5;
when HTHREAD_COND_INIT_5 =>
-- Write the condvar's num
data_address_next <= reg1;
data_value_next <= reg3;
user_return_state_next <= HTHREAD_COND_INIT_6;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_COND_INIT_6 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_WAIT
-- hthread_cond_broadcast( hthread_cond_t *cond, hthread_mutex_t *mutex )
-- Unlocks *mutex, waits for a signal from *cond, relocks *mutex
-----------------------------------------------------------------------
when HTHREAD_COND_WAIT =>
-- reg1 will hold address of condition variable
reg1_next <= dob;
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_COND_WAIT_2;
-- Reset number of parameters
paramCount_next <= x"00";
-- decrement the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
when HTHREAD_COND_WAIT_2 =>
-- reg2 will hold address of mutex
reg2_next <= dob;
-- Initiate read of the cond var number
data_address_next <= reg1;
user_return_state_next <= HTHREAD_COND_WAIT_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_WAIT_3 =>
-- reg3 will hold cond var number
reg3_next <= data_value;
-- Initiate read of the mutex number
data_address_next <= reg2;
user_return_state_next <= HTHREAD_COND_WAIT_4;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_WAIT_4 =>
-- reg4 will hold mutex number
reg4_next <= data_value;
-- Call to wait for cond variable signal
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_WAIT & --bits(12 to 15) broadcast command
system_thread_id & --bits(16 to 23) thread id
reg3(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_COND_WAIT_5;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_WAIT_5 =>
-- Check return value, if successful unlock the mutex
if ( data_value(28 to 31) = CONDVAR_FAILED ) then
--repeat previous step
user_state_next <= HTHREAD_COND_WAIT_4;
else
user_state_next <= HTHREAD_COND_WAIT_6;
-- Change status to BLOCKED while waiting on condvar
system_request_next <= CHANGE_STATUS_TO_BLOCK;
end if;
when HTHREAD_COND_WAIT_6 =>
-- Wait till status changes to blocked
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_COND_WAIT_7;
when others =>
user_state_next <= HTHREAD_COND_WAIT_6;
end case;
when HTHREAD_COND_WAIT_7 =>
-- Call to unlock the mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_COND_WAIT_7a;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_WAIT_7a =>
--Wait for a run command, which is the signal another thread sent to us
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_COND_WAIT_8;
when others =>
user_state_next <= HTHREAD_COND_WAIT_7a;
end case;
when HTHREAD_COND_WAIT_8=>
--Wait for the system state machine to update the status
case system_status is
when SYSTEM_STATUS_RUNNING =>
--We've been signaled to continue, before returning, relock the mutex
--Note that I'm tranfering control to the mutex lock state machine
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
data_value(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_MUTEX_LOCK_3;
user_state_next <= MASTER_LOAD_INIT;
when others =>
user_state_next <= HTHREAD_COND_WAIT_8;
end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_BCAST
-- hthread_cond_broadcast( hthread_cond_t *cond )
-- Broadcasts, via the condition varable manager, all
-- threads waiting on cond
-----------------------------------------------------------------------
when HTHREAD_COND_BCAST =>
data_address_next <= dob;
-- Read the value of the cond var number
user_return_state_next <= HTHREAD_COND_BCAST_2;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_BCAST_2 =>
-- Store the cond variable in reg1
reg1_next <= data_value;
-- Read the register, on the cond var manager, to signal the next thread
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_BCAST & --bits(12 to 15) broadcast command
"00000000" & --bits(16 to 23) thread id
data_value(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_COND_BCAST_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_BCAST_3 =>
--Check the return status, repeat of attempt failed
if ( data_value(28 to 31) = CONDVAR_FAILED ) then
--restore value of the data value register
data_value_next <= reg1;
--repeat step 2
user_state_next <= HTHREAD_COND_BCAST_2;
else
--The cond var is signaled, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end if;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_SIGNAL
-- hthread_cond_signal( hthread_cond_t *cond )
-- Signals, via the condition varable manager, the highest priority
-- thread waiting on cond
-----------------------------------------------------------------------
when HTHREAD_COND_SIGNAL =>
data_address_next <= dob;
-- Read the value of the cond var number
user_return_state_next <= HTHREAD_COND_SIGNAL_2;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_SIGNAL_2 =>
-- Store the cond variable in reg1
reg1_next <= data_value;
-- Read the register, on the cond var manager, to signal the next thread
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_SIGNAL & --bits(12 to 15) signal command
"00000000" & --bits(16 to 23) thread id
data_value(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_COND_SIGNAL_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_COND_SIGNAL_3 =>
--Check the return status, repeat of attempt failed
if ( data_value(28 to 31) = CONDVAR_FAILED ) then
--restore value of the data value register
data_value_next <= reg1;
--repeat step 2
user_state_next <= HTHREAD_COND_SIGNAL_2;
else
--The cond var is signaled, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end if;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_SETNUM and HTHREAD_CONDATTR_SETNUM
-- hthread_mutexattr_getnum( mutexattr_t *, int num)
-- hthread_condattr_setnum( condattr_t *, int num)
-- Sets the value of mutexattr number to num
-- or sets the value of condattr number to num
-- Reusing these states work, because in both the case for the mutexattr
-- and the condattr struct, the first element in the struct is the
-- mutex/condvariable number.
-----------------------------------------------------------------------
when HTHREAD_MUTEXATTR_SETNUM =>
-- store the value of the address of mutexattr_t in reg1
reg1_next <= dob;
-- Read the second parameter the user pushed, the new value of the mutex number
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM_2;
-- Reset the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- Reset number of parameters
paramCount_next <= x"00";
when HTHREAD_MUTEXATTR_SETNUM_2 =>
-- Store the dob (value of num) to mutexattr
data_value_next <= dob;
data_address_next <= reg1;
user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM_3;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEXATTR_SETNUM_3 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_GETNUM and HTHREAD_CONDATTR_GETNUM
-- hthread_mutexattr_getnum( mutexattr_t *, int* num)
-- hthread_condattr_getnum( condattr_t *, int* num)
-- Gets the value of *num to the value of the mutexattr number
-- or gets the value of condattr number to num
-- Reusing these states work, because in both the case for the mutexattr
-- and the condattr struct, the first element in the struct is the
-- mutex/condvariable number.
-----------------------------------------------------------------------
when HTHREAD_MUTEXATTR_GETNUM =>
-- store the value of the address of mutexattr_t in reg1
reg1_next <= dob;
-- Read the second parameter the user pushed, address to store the mutex number to
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_2;
-- Reset the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- Reset number of parameters
paramCount_next <= x"00";
when HTHREAD_MUTEXATTR_GETNUM_2 =>
-- store the value of the address of num in reg2
reg2_next <= dob;
-- Load the value of the mutex number
data_address_next <= reg1;
user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEXATTR_GETNUM_3 =>
-- Store the value we just read, to the num passed by the user
data_value_next <= data_value;
data_address_next <= reg2;
user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_4;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEXATTR_GETNUM_4 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_INIT
-- hthread_mutexattr_init( mutexattr_t * )
-- Initializes the mutexattr struct to default values
-----------------------------------------------------------------------
when HTHREAD_MUTEXATTR_INIT =>
reg1_next <= dob;
-- Write a 0, the default mutex number, to the mutexattr_t.num
data_address_next <= dob;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_MUTEXATTR_INIT_2;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEXATTR_INIT_2 =>
-- Write a HTHREAD_MUTEX_DEFAULT, the default mutex type, to the mutexattr_t.type
data_address_next <= reg1 + 4;
data_value_next <= Z32;
user_return_state_next <= HTHREAD_MUTEXATTR_INIT_3;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEXATTR_INIT_3 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEX_INIT
-- hthread_mutex_init( mutex_t *, hthread_mutexattr_t*)
-- Creates a mutex based on either the default attributes, if mutexattr_t
-- is NULL, or on mutexattr_t.
-----------------------------------------------------------------------
when HTHREAD_MUTEX_INIT =>
-- Store the address of the mutex in reg1;
reg1_next <= dob;
-- Read the address, that the use passed in, of mutexattr_t
addrb <= stackPtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_MUTEX_INIT_2;
-- Reset the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- Reset number of parameters
paramCount_next <= x"00";
when HTHREAD_MUTEX_INIT_2 =>
-- Store the address of mutexattr in reg2;
reg2_next <= dob;
-- Determine if the attributes are NULL or not
case dob is
when Z32 =>
-- Create a mutex with default attributes
reg3_next <= Z32; --mutex number 0
reg4_next <= Z32; --HTHREAD_MUTEX_DEFAULT
data_value_next <= Z32; --to conserve a state, i'm cheating and setting
-- data_value here. reg4 gets overwriten in MUTEX_INIT_5
user_state_next <= HTHREAD_MUTEX_INIT_5;
when OTHERS =>
user_state_next <= HTHREAD_MUTEX_INIT_3;
end case;
when HTHREAD_MUTEX_INIT_3 =>
-- Read the value of the attr's num
data_address_next <= reg2;
user_return_state_next <= HTHREAD_MUTEX_INIT_4;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_INIT_4 =>
-- Store the value of attr's num in reg3
reg3_next <= data_value;
-- Read the value of the attr's type
data_address_next <= reg2 + 4;
user_return_state_next <= HTHREAD_MUTEX_INIT_5;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_INIT_5 =>
-- Store the value of the attr's type in reg4
reg4_next <= data_value;
-- Write the mutex's num
data_address_next <= reg1;
data_value_next <= reg3;
user_return_state_next <= HTHREAD_MUTEX_INIT_6;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEX_INIT_6 =>
-- Write the mutex's type
data_address_next <= reg1 + 4;
data_value_next <= reg4;
user_return_state_next <= HTHREAD_MUTEX_INIT_7;
user_state_next <= MASTER_STORE_INIT;
when HTHREAD_MUTEX_INIT_7 =>
-- Return a SUCCESS to the user;
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEX_UNLOCK
-- hthread_mutex_unlock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
when HTHREAD_MUTEX_UNLOCK =>
data_address_next <= dob;
-- Read the value of the mutex number
user_return_state_next <= HTHREAD_MUTEX_UNLOCK_2;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_UNLOCK_2 =>
-- Read the register, on the mutex manager, to unlock the specified mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
data_value(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_MUTEX_UNLOCK_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_UNLOCK_3 =>
--The Lock is released, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_MUTEX_TRYLOCK
-- hthread_mutex_trylock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
when HTHREAD_MUTEX_TRYLOCK =>
data_address_next <= dob;
-- Read the value of the mutex number
user_return_state_next <= HTHREAD_MUTEX_TRYLOCK_2;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_TRYLOCK_2 =>
-- Read the register, on the mutex manager, to lock the specified mutex
data_address_next <= synch_trylockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
data_value(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_MUTEX_TRYLOCK_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_TRYLOCK_3 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when "01" =>
--Did not get the LOCK,
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when others =>
--The Lock is ours, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_MUTEX_LOCK
-- hthread_mutex_lock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
when HTHREAD_MUTEX_LOCK =>
data_address_next <= dob;
-- Read the value of the mutex number
user_return_state_next <= HTHREAD_MUTEX_LOCK_2;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_LOCK_2 =>
-- Read the register, on the mutex manager, to lock the specified mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
data_value(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_MUTEX_LOCK_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_MUTEX_LOCK_3 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when "01" =>
--Change status to block, then wait for a RUN command
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_MUTEX_LOCK_4;
when others =>
--The Lock is ours, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end case;
when HTHREAD_MUTEX_LOCK_4 =>
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_MUTEX_LOCK_5;
when others =>
user_state_next <= HTHREAD_MUTEX_LOCK_4;
end case;
when HTHREAD_MUTEX_LOCK_5 =>
--Wait for a run command
case system_command is
when SYSTEM_COMMAND_RUN =>
--TODO check to see if the lock is ours, or if this was a random RUN command
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_MUTEX_LOCK_6;
when others =>
user_state_next <= HTHREAD_MUTEX_LOCK_5;
end case;
when HTHREAD_MUTEX_LOCK_6 =>
case system_status is
when SYSTEM_STATUS_RUNNING =>
system_request_next <= NOOP;
--The lock is now ours, return a SUCCESS to the user
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
when others =>
user_state_next <= HTHREAD_MUTEX_LOCK_6;
end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_EXIT, EXIT_ERROR, OVERFLOW
-- Calls the exit_thread API on the thread manager. Once the thread
-- manager returns, wait until the HWTI receives a RESET signal.
-----------------------------------------------------------------------
when HTHREAD_EXIT =>
-- Initiate the call to the thread manager
data_address_next <= thread_manager_exit_thread_address( C_THREAD_MANAGER_BADDR, C_OPB_AWIDTH, THREAD_BITS, system_thread_id );
user_return_state_next <= HTHREAD_EXIT_2;
user_state_next <= MASTER_LOAD_INIT;
-- Simotaneously, read the parameter that the user pushed to the stack
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
when OVERFLOW =>
-- Stack and heap overflow was detected
data_address_next <= thread_manager_exit_thread_address( C_THREAD_MANAGER_BADDR, C_OPB_AWIDTH, THREAD_BITS, system_thread_id );
system_request_next <= CHANGE_STATUS_TO_EXIT_OVERFLOW;
user_return_state_next <= HTHREAD_EXIT_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_EXIT_2 =>
-- Read the argument
system_result_next <= dob;
-- Decrement the stack for good measure
paramCount_next <= x"00";
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
user_state_next <= HTHREAD_EXIT_3;
when HTHREAD_EXIT_3 =>
case system_status is
when SYSTEM_STATUS_EXITED =>
system_request_next <= NOOP;
when SYSTEM_STATUS_EXITED_ERROR =>
system_request_next <= NOOP;
when SYSTEM_STATUS_EXITED_OVERFLOW =>
system_request_next <= NOOP;
when others =>
-- do nothing
end case;
user_state_next <= HTHREAD_EXIT_3;
-----------------------------------------------------------------------
-- Read the function call parameter from the stack, and return value
-- to user.
-----------------------------------------------------------------------
when POP_READ_PARAM_COUNT =>
-- Learn the number of parameters in the function call
-- Make sure the user is not trying to exceed this number
-- Start the read for the parameter
if ( dob(24 to 31) > fromUserReg_value(24 to 31) ) then
-- pop parameter is within known parameter count
addrb <= ( framePtr(1 to 13) - fromUserReg_value(19 to 31) ) - 4 ;
dib <= fromUser_value;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= POP_READ_PARAM;
else
-- pop parameter is outside known parameter count
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
end if;
when POP_READ_PARAM =>
-- return the value, and control, to the user thread
intrfc2thrd_value <= dob;
toUser_value_next <= dob;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Helper function to wait one clock cycle. Returns to state
-- specified in return_state
-----------------------------------------------------------------------
when WAIT_ONE_CYCLE =>
-- Wait one clock cycle
user_state_next <= user_return_state;
-----------------------------------------------------------------------
-- If the user is requesting a read that is not word-aligned, need
-- to do two reads, and return a concatenation of both.
-----------------------------------------------------------------------
when LOCAL_PARTIAL_LOAD =>
reg1_next <= dob;
addrb <= fromUserReg_address(17 to 29) + 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LOCAL_PARTIAL_LOAD_1;
when LOCAL_PARTIAL_LOAD_1 =>
case fromUserReg_address(30 to 31) is
when "01" =>
intrfc2thrd_value <= reg1(8 to 31) & dob(0 to 7);
toUser_value_next <= reg1(8 to 31) & dob(0 to 7);
when "10" =>
intrfc2thrd_value <= reg1(16 to 31) & dob(0 to 15);
toUser_value_next <= reg1(16 to 31) & dob(0 to 15);
when OTHERS =>
intrfc2thrd_value <= reg1(24 to 31) & dob(0 to 23);
toUser_value_next <= reg1(24 to 31) & dob(0 to 23);
end case;
intrfc2thrd_goWait <= '1';
wr <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Perform the remaning steps to read from BRAM. Since we are trying
-- to make the operation as fast as possible, it has its own special
-- states. And yes, I get to use this for both LOCAL_LOAD and
-- LOCAL_READ.
-----------------------------------------------------------------------
when LOCAL_LOAD_RESPOND =>
-- Return the data from BRAM and tell HWTUL to GO
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_value <= dob;
toUser_value_next <= dob;
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- After the Read helper returns, this state is called, to return the
-- HWTUL to a running state. Also note that this state is being used
-- as the return state for GLOBAL_STORE. why? because I can.
-----------------------------------------------------------------------
when GLOBAL_LOAD_RETURN =>
intrfc2thrd_goWait <= '1';
wr <= '1';
intrfc2thrd_value <= data_value;
toUser_value_next <= data_value;
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Read/load helper states
-- Performs a bus master read to data_address
-- After completion, returns to state user_return_state, data is in
-- data_value;
-----------------------------------------------------------------------
when MASTER_LOAD_INIT =>
-- Initiate read opperation
IP2Bus_Addr <= data_address;
IP2Bus_MstRdReq <= '1';
IP2IP_Addr <= master_read_respond_address;
user_state_next <= MASTER_LOAD_WAIT_FOR_ACK;
when MASTER_LOAD_WAIT_FOR_ACK =>
-- Persist with read operation until ACKed
if ( Bus2IP_MstLastAck = '1'
or Bus2IP_MstError = '1'
or Bus2IP_MstTimeOut = '1' ) then
IP2Bus_Addr <= (others=>'0');
IP2Bus_MstRdReq <= '0';
IP2IP_Addr <= (others=>'0');
data_value_next <= Bus2IP_Data;
--TODO catch an error and set a status to indicate error
user_state_next <= user_return_state;
else --ABA commented these
IP2Bus_Addr <= data_address;
IP2Bus_MstRdReq <= '1';
IP2IP_Addr <= master_read_respond_address;
user_state_next <= MASTER_LOAD_WAIT_FOR_ACK;
end if;
---------------------------------------------------------
-- Write/store helper states
-- Perform a bus master write to data_address with data_value
---------------------------------------------------------
when MASTER_STORE_INIT =>
-- Initiate write opperation
-- Note that the data_value gets set in the RUNNING state
IP2Bus_Addr <= data_address;
IP2Bus_MstWrReq <= '1';
IP2IP_Addr <= master_write_respond_address;
user_state_next <= MASTER_STORE_WAIT_FOR_ACK;
when MASTER_STORE_WAIT_FOR_ACK =>
-- Persist with write opperation until ACKed by bus
if ( Bus2IP_MstLastAck = '1'
or Bus2IP_MstError = '1'
or Bus2IP_MstTimeOut = '1') then
IP2Bus_Addr <= (others=>'0');
IP2Bus_MstWrReq <= '0';
IP2IP_Addr <= (others=>'0');
user_state_next <= user_return_state;
else
IP2Bus_Addr <= data_address;
IP2Bus_MstWrReq <= '1';
IP2IP_Addr <= master_write_respond_address;
user_state_next <= MASTER_STORE_WAIT_FOR_ACK;
end if;
end case;
end process HWTI_USER_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 87821ac44f9a89cf6938037ebc45870a | 0.532117 | 4.096643 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/error.vhd | 1 | 9,514 | --------------------------------------------------------------------------------
-- Title : Error Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : error.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- errors on RxModule, TxModule or hard IP core are collected here and passed
-- to Wishbone modules through a FIFO
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- * error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity error is
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_tag_id : in std_logic_vector(7 downto 0);
rx_ecrc_err : in std_logic;
rx_type_fmt_err : in std_logic_vector(1 downto 0);
-- Tx Module
tx_compl_abort : in std_logic;
tx_timeout : in std_logic;
-- Interrupt
wb_num_err : in std_logic;
-- Wishbone
error_ecrc_err : out std_logic;
error_timeout : out std_logic;
error_tag_id : out std_logic_vector(7 downto 0);
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- IP Core
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic
);
end entity error;
-- ****************************************************************************
architecture error_arch of error is
-- internal signals -----------------------------------------------------------
signal err_fifo_clr : std_logic;
signal err_fifo_wr_enable : std_logic;
signal err_fifo_in : std_logic_vector(15 downto 0);
-- uncomment next line when increasing FIFO depth
-- signal err_fifo_full : std_logic;
signal err_fifo_rd_enable : std_logic;
signal err_fifo_out : std_logic_vector(15 downto 0);
signal err_fifo_empty : std_logic;
signal get_value : std_logic;
signal wb_num_err_q : std_logic;
signal wb_num_err_qq : std_logic;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal ip_error_in : std_logic_vector(14 downto 0);
signal ip_error_last : std_logic_vector(14 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
err_fifo_comp : dcfifo
generic map (
intended_device_family => "Cyclone IV GX",
lpm_numwords => 4,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 2,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4)
port map (
aclr => err_fifo_clr,
wrclk => clk,
wrreq => err_fifo_wr_enable,
data => err_fifo_in,
wrempty => open,
wrfull => open,
rdclk => wb_clk,
rdreq => err_fifo_rd_enable,
q => err_fifo_out,
rdempty => err_fifo_empty,
rdfull => open);
-------------------------------------------------------------------------------
fifo_wr : process(clk, rst)
begin
if(rst = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
err_fifo_clr <= '1';
ip_error_last <= (others => '0');
elsif(clk'event and clk = '1') then
err_fifo_clr <= '0';
-- store errors if new error occred
if(ip_error_last /= ip_error_in) then
err_fifo_wr_enable <= '1';
err_fifo_in <= '0' & ip_error_in;
ip_error_last <= ip_error_in;
end if;
-- reset signals
if(err_fifo_wr_enable = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
end if;
end if;
end process fifo_wr;
-------------------------------------------------------------------------------
fifo_rd : process(wb_clk, wb_rst)
begin
if(wb_rst = '1') then
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
error_msi_num <= '0';
err_fifo_rd_enable <= '0';
get_value <= '0';
wb_num_err_q <= '0';
wb_num_err_qq <= '0';
elsif(wb_clk'event and wb_clk = '1') then
-- sample wb_num_err because this is synchronous to clk
wb_num_err_q <= wb_num_err;
wb_num_err_qq <= wb_num_err_q;
-- read values as soon as they appear
if(err_fifo_empty = '0') then
err_fifo_rd_enable <= '1';
end if;
-- reset enable an start analysis of value read from FIFO
if(err_fifo_rd_enable = '1') then
err_fifo_rd_enable <= '0';
get_value <= '1';
end if;
-- propagate error signals to outer environment
if(get_value = '1') then
get_value <= '0';
error_timeout <= err_fifo_out(14);
error_r2c0 <= err_fifo_out(13);
error_rpl <= err_fifo_out(12);
error_cor_ext_rpl <= err_fifo_out(11);
error_cor_ext_rcv <= err_fifo_out(10 downto 9);
error_ecrc_err <= err_fifo_out(8);
error_tag_id <= err_fifo_out(7 downto 0);
else
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
end if;
-- propagate error signals to outer environment
error_msi_num <= wb_num_err_qq;
end if;
end process fifo_rd;
-------------------------------------------------------------------------------
-- capture occuring errors
ip_error_in(14) <= '1' when tx_timeout = '1' else '0';
ip_error_in(13) <= '1' when r2c_err0 = '1' else '0';
ip_error_in(12) <= '1' when derr_rpl = '1' else '0';
ip_error_in(11) <= '1' when derr_cor_ext_rpl = '1' else '0';
ip_error_in(10 downto 9) <= derr_cor_ext_rcv when derr_cor_ext_rcv /= "00" else "00";
ip_error_in(8) <= '1' when rx_ecrc_err = '1' else '0';
ip_error_in(7 downto 0) <= rx_tag_id when rx_ecrc_err = '1' else (others => '0');
cpl_err(6) <= '0';
cpl_err(5) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "01" else
'0';
cpl_err(4) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "10" else
'0';
cpl_err(3) <= '0';
cpl_err(2) <= '0' when rst = '1' else
'1' when tx_compl_abort = '1' else
'0';
cpl_err(1 downto 0) <= (others => '0');
cpl_pending <= '0';
-------------------------------------------------------------------------------
end architecture error_arch;
| gpl-3.0 | 5bdb971621e332758ae80f6c08d86b04 | 0.446395 | 3.767921 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_sim.vhd | 3 | 136,585 | -------------------------------------------------------------------------------
-- $Id: dma_sg_sim.vhd,v 1.8 2003/11/04 20:11:34 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg sim architecture (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_sim.vhd
--
-- Description: See file dma_sg.vhd for a description of this function.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg_sim.vhd
-- |
-- |- dma_sg.vhd
-- |
-- |- dma_sg_pkg.vhd
-- |
-- |- dma_sg_cmp.vhd
-- |
-- |- ctrl_reg.vhd
-- |
-- |- ld_arith_reg.vhd
-- |
-- |- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- FLO 07/17/02
-- ^^^^^^
-- Workaround for XST F.23 bug that affects dma_sg,
-- e.g. "XGR_tmp <= dma_cs(cco)"
-- ~~~~~~
--
-- FLO 10/22/02
-- ^^^^^^
-- Put a generate statement around the clock divider so that it
-- is included only if there is a packet channel with interrupt
-- coalescing enabled.
-- ~~~~~~
--
-- FLO 01/10/03
-- ^^^^^^
-- Removed earlier XST workaround restriction that status fifo
-- entries for packet channels had to be on either channel 0 or 1.
--
-- FLO 01/30/03
-- ^^^^^^
-- Added constant DMA_DWIDTH = 32, then made values that depend on the
-- fact that DMASG is a 32-bit device to depend on this constant. Most
-- of these were previously depending on C_OPB_DWIDTH. But, we want to
-- be able to have C_OPB_DWIDTH be 64 bits so that DMA data transfers
-- and bursts work on 64-bit buses such as the PLB.
--
-- Added constant BPBT_BITS and eliminated some places where BPST was
-- assumed to be 4 and BPBT was assumed to be 32.
-- ~~~~~~
--
-- FLO 01/31/03
-- ^^^^^^
-- Changed the Generation of DMA2Bus_MstBE so that it handles both
-- 32-bit (DMA_DWIDTH) master operations that it performs relative
-- to its own registers and DMA operations at the full Bus width, i.e.,
-- the width given by C_OPB_AWIDTH.
--
-- Added assertions to check the validity of some of the assumptions
-- upon which the implementation depends.
-- ~~~~~~
--
-- FLO 02/01/03
-- ^^^^^^
-- Fixed generation of dma2bus_addr_sg and dma2ip_addr_sg, which were using
-- BPST_BITS as a way of getting a constant 2. This constant is 2 only if
-- C_OPB_DWIDTH is 32, so the problem appeared with the first attempt
-- to use C_OPB_DWIDTH=64.
-- ~~~~~~
--
-- FLO 02/02/03
-- ^^^^^^
-- Correction to generation of DMA2Bus_MstBE.
-- More corrections of BPST_BITS being used where 2 should have been used.
-- ~~~~~~
--
-- FLO 02/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 03/11/03
-- ^^^^^^
-- Changed constant DMA_TO_OPB_DWIDTH_FACTOR_BITS from type positive to natural.
-- This was needed to have the C_OPB_DWIDTH = 32 case elaborate properly
-- since the value of this constant is zero for this case.
-- ~~~~~~
--
-- FLO 05/13/2003
-- ^^^^^^
-- Added instance of module burst_size_calc. This instance calculates the
-- size for the next bus transaction based on the maximum transfers
-- per burst, the Length remaining (and for Rx channels, the PLength
-- remaining). This instance is in place but is not hooked up and used, yet.
-- ~~~~~~
--
-- FLO 05/14/2003
-- ^^^^^^
-- The burst_size_calc instance is now integrated.
-- This version does bursts of size 16 and does remainders as bursts
-- of size 1 to 15.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- The HW_SW_COMPATIBILITY component "letter" is rev'ed from a to b.
-- The new C_DMA_SHORT_BURST_REMAINDER generic is passed to
-- instance of burst_size_calc.
-- TPB now comes from a generic (C_DMA_BURST_SIZE).
-- Changed to the non-ripple-counter version of the packet-wait timebase
-- divider.
-- ~~~~~~
-- FLO 09/03/2003
-- ^^^^^^
-- Fixed a bug whereby if PWB=1, PWBR interrupts were generated even
-- when UPC=0. Problem was that the ld_arith_reg that was used to
-- implement the pw_timer has OP overriding LOAD. The fix was to
-- switch to ld_arith_reg2, which allows the override order to be
-- reversed.
-- ~~~~~~
-- FLO 11/04/2003
-- ^^^^^^
-- - Addressed a slow signal propagation through dma2bus_mstnum by
-- inserting a pipestage and adding state MSTNUM_PIPE that matches
-- the pipe delay for the state machine.
-- - Also, removed some comments now considered obsolete or of marginal value.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--Possible enhancements
-- (11) Error conditions that could be detected in a "debug" mode.
-- (a) SGS=1 but not at end of Tx packet.
-- (b) SGS=1 but not enough buffer space to finish current Rx packet.
-- (c) Underflow or overflow of UPC.
-- (d) Exactly one of SLOCAL, DLOCAL set.
-- (e) Status value becomes available from the IP but there
-- is not a corresponding address saved in the SRAddr FIFO to
-- which to write it.
-- (25) Handle the case where a Bus2IP_MstError or Bus2IP_MstTimeout
-- is the response to a master operation (SG not yet covered).
-- (27) Check that UPC, PCT, PWB are excluded when channel is not
-- type 2 or 3 or interrupt coalescing is disabled for the channel.
library ieee;
use ieee.numeric_std.all;
-- VisualHDL gives compile errors when using the explicitly named
-- use clauses, below.
--use ieee.numeric_std.UNSIGNED;
--use ieee.numeric_std.TO_UNSIGNED
--use ieee.numeric_std.TO_INTEGER;
--use ieee.numeric_std."=";
--use ieee.numeric_std."+";
--use ieee.numeric_std."-";
--use ieee.numeric_std."<";
--use ieee.numeric_std.RESIZE;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.dma_sg_cmp.all;
use ipif_common_v1_00_d.dma_sg_pkg.ceil_log2;
use ipif_common_v1_00_d.dma_sg_pkg.r_RSTMIR;
use ipif_common_v1_00_d.dma_sg_pkg.r_DMACR;
use ipif_common_v1_00_d.dma_sg_pkg.r_SA;
use ipif_common_v1_00_d.dma_sg_pkg.r_DA;
use ipif_common_v1_00_d.dma_sg_pkg.r_LENGTH;
use ipif_common_v1_00_d.dma_sg_pkg.r_DMASR;
use ipif_common_v1_00_d.dma_sg_pkg.r_BDA;
use ipif_common_v1_00_d.dma_sg_pkg.r_SWCR;
use ipif_common_v1_00_d.dma_sg_pkg.r_UPC;
use ipif_common_v1_00_d.dma_sg_pkg.r_PCT;
use ipif_common_v1_00_d.dma_sg_pkg.r_PWB;
use ipif_common_v1_00_d.dma_sg_pkg.r_ISR;
use ipif_common_v1_00_d.dma_sg_pkg.r_IER;
use ipif_common_v1_00_d.dma_sg_pkg.r_PLENGTH;
use ipif_common_v1_00_d.dma_sg_pkg.b_BSY;
use ipif_common_v1_00_d.dma_sg_pkg.b_SINC;
use ipif_common_v1_00_d.dma_sg_pkg.b_DINC;
use ipif_common_v1_00_d.dma_sg_pkg.b_SLOCAL;
use ipif_common_v1_00_d.dma_sg_pkg.b_DLOCAL;
use ipif_common_v1_00_d.dma_sg_pkg.b_SGS;
use ipif_common_v1_00_d.dma_sg_pkg.b_L_dmacr;
use ipif_common_v1_00_d.dma_sg_pkg.b_SGE;
use ipif_common_v1_00_d.dma_sg_pkg.b_DD;
use ipif_common_v1_00_d.dma_sg_pkg.b_DE;
use ipif_common_v1_00_d.dma_sg_pkg.b_PD;
use ipif_common_v1_00_d.dma_sg_pkg.b_PCTR;
use ipif_common_v1_00_d.dma_sg_pkg.b_PWBR;
use ipif_common_v1_00_d.dma_sg_pkg.b_SGDA;
use ipif_common_v1_00_d.dma_sg_pkg.b_SGEND;
use ipif_common_v1_00_d.dma_sg_pkg.bo2sl;
use ipif_common_v1_00_d.dma_sg_pkg.Div_Stages;
use ipif_common_v1_00_d.dma_sg_pkg.UPCB;
use ipif_common_v1_00_d.dma_sg_pkg.PWBB;
library proc_common_v1_00_b;
architecture sim of dma_sg is
constant RESET_ACTIVE : std_logic := '1';
constant C_M : natural := C_IPIF_ABUS_WIDTH - 2;
-- Bus2IP_Addr and DMA2IP_Addr are word addresses;
-- the low-order two bits of the byte address
-- are not included.
-- ToDo, eventually, this should probably change so that
-- they are byte addresses.
constant MAJOR_VERSION : natural := 1;
constant MINOR_VERSION : natural := 1;
constant HW_SW_COMPATIBILITY_REVISION : natural := 1;
constant LAST_CHAN : natural := C_DMA_CHAN_TYPE'length - 1;
constant NUM_CHANS : natural := LAST_CHAN+1;
constant NUM_CHAN_BITS : natural := ceil_log2(NUM_CHANS);
-- There are NUM_CHANS channels, numbered 0 .. LAST_CHAN.
constant RPB : natural := 4; -- Register-pitch bits = the number of bits
-- needed to encode the word addresses
-- of all registers (and reserved register
-- addresses) for a channel. The number
-- of registers and reserved addresses
-- per channel is 2^RPB, so the
-- word address of a register on one channel
-- is separated from the word address of
-- of the same register on the next higher
-- channel by 2^RPB.
constant BPST : natural := C_OPB_DWIDTH / 8;
-- Bytes per single transfer on the bus.
constant BPST_BITS : natural := ceil_log2(BPST);
-- Number of bits needed to encode
-- the range 0 to BPST-1.
constant BPBT : natural := BPST * TPB;
-- Bytes per burst transfer on the bus.
constant BPBT_BITS : natural := ceil_log2(BPBT);
constant RIPPLE_PW_DIVIDER : boolean := false;
constant DMA_DWIDTH : natural := 32; -- DMASG is a 32-bit device.
-- Registers
type DMACR_t
is array (natural range <>) of std_logic_vector(b_SINC to
b_L_dmacr);
signal tmp_C_DMA_BASEADDR : std_logic_vector(0 to 63);
-- XST workaround
signal DMACR : DMACR_t(0 to LAST_CHAN);
type UNSIGNED_t
is array (natural range <>) of UNSIGNED(0 to DMA_DWIDTH-1);
signal SA : UNSIGNED_t(0 to LAST_CHAN);
signal DA : UNSIGNED_t(0 to LAST_CHAN);
signal LENGTH : UNSIGNED_t(0 to LAST_CHAN);
signal BDA : UNSIGNED_t(0 to LAST_CHAN);
-- XGR_E33 type SWCR_t
-- XGR_E33 is array (natural range <>) of std_logic_vector(b_SGE to b_SGE);
-- XGR_E33 signal SWCR : SWCR_t(0 to LAST_CHAN);
signal SWCR : std_logic_vector(0 to LAST_CHAN);
type UPC_t
is array (natural range <>) of UNSIGNED(DMA_DWIDTH-UPCB to
DMA_DWIDTH-1);
signal UPC : UPC_t(0 to LAST_CHAN);
signal PCT : UPC_t(0 to LAST_CHAN);
type PWB_t
is array (natural range <>) of UNSIGNED(DMA_DWIDTH-PWBB to
DMA_DWIDTH-1);
signal PWB : PWB_t(0 to LAST_CHAN); -- Packet Wait Bound
signal pw_timer : PWB_t(0 to LAST_CHAN); -- Timer used in generating
-- PWBR interrupt.
signal PLENGTH : UNSIGNED_t(0 to LAST_CHAN);
signal LENGTH_cco : UNSIGNED(0 to DMA_DWIDTH-1);
signal PLENGTH_cco : UNSIGNED(0 to DMA_DWIDTH-1);
signal rx_cco : std_logic;
-- Per-channel reset
signal reset : std_logic_vector (0 to LAST_CHAN);
signal prog_reset : std_logic_vector (0 to LAST_CHAN);
-- Enables
signal chan_num : natural; -- The channel addressed by Bus2IP_Addr.
signal chan_sel : std_logic_vector (0 to LAST_CHAN);
-- Decode of chan_num to one-hot.
signal cco : natural range 0 to LAST_CHAN;
-- The channel currently operating.
signal cco_onehot : std_logic_vector (0 to LAST_CHAN);
-- cco decoded to onehot.
signal RSTMIR_sel : std_logic;
signal DMACR_sel : std_logic;
signal SA_sel : std_logic;
signal DA_sel : std_logic;
signal LENGTH_sel : std_logic;
signal dmasr_sel : std_logic;
signal BDA_sel : std_logic;
signal SWCR_sel : std_logic;
signal UPC_sel : std_logic;
signal PCT_sel : std_logic;
signal PWB_sel : std_logic;
signal ISR_sel : std_logic;
signal IER_sel : std_logic;
signal PLENGTH_sel : std_logic;
-- Read back register muxing
signal ver_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal dcr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal sa_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal da_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal lnt_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal dsr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal bda_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal sge_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal upc_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal pct_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal pwb_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal isr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal ier_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal ple_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal adj : UNSIGNED(0 to BPST_BITS); -- Amt to add or subtr when updating
-- LENGTH and PLENGTH.
signal LENGTH_ge_2BPST: std_logic; -- Used in calculating adj.
signal PLENGTH_ge_2BPST: std_logic; -- Used in calculating adj.
signal LENGTH_ge_BPBT : std_logic; -- Used for deciding burst transaction.
signal PLENGTH_ge_BPBT : std_logic; -- Used for deciding burst transaction.
--ToDo. dec_LENGTH, inc_SA and inc_DA can be combined into a common signal.
signal dec_LENGTH : std_logic;
signal inc_SA : std_logic;
signal inc_DA : std_logic;
signal dec_PLENGTH : std_logic;
signal inc_PLENGTH : std_logic;
signal clr_PLENGTH : std_logic;
--Register bits and bit fields
signal SINC : std_logic_vector(0 to LAST_CHAN);
signal DINC : std_logic_vector(0 to LAST_CHAN);
signal SLOCAL : std_logic_vector(0 to LAST_CHAN);
signal DLOCAL : std_logic_vector(0 to LAST_CHAN);
signal SGS : std_logic_vector(0 to LAST_CHAN);
signal L_tx : std_logic_vector(0 to LAST_CHAN);
signal dma_active : std_logic_vector(0 to LAST_CHAN);
signal DBE : std_logic_vector(0 to LAST_CHAN);
signal DBT : std_logic_vector(0 to LAST_CHAN);
signal L_rx : std_logic_vector(0 to LAST_CHAN);
signal L : std_logic_vector(0 to LAST_CHAN);
signal SGE : std_logic_vector(0 to LAST_CHAN);
signal DD : std_logic_vector(0 to LAST_CHAN);
signal DE : std_logic_vector(0 to LAST_CHAN);
signal PD : std_logic_vector(0 to LAST_CHAN);
signal SGDA : std_logic_vector(0 to LAST_CHAN);
signal SGEND : std_logic_vector(0 to LAST_CHAN);
signal PCTR : std_logic_vector(0 to LAST_CHAN);
signal PWBR : std_logic_vector(0 to LAST_CHAN);
signal EDD : std_logic_vector(0 to LAST_CHAN);
signal EDE : std_logic_vector(0 to LAST_CHAN);
signal EPD : std_logic_vector(0 to LAST_CHAN);
signal ESGDA : std_logic_vector(0 to LAST_CHAN);
signal ESGEND : std_logic_vector(0 to LAST_CHAN);
signal EPCTR : std_logic_vector(0 to LAST_CHAN);
signal EPWBR : std_logic_vector(0 to LAST_CHAN);
-- Other signals.
signal sgGo : std_logic_vector(0 to LAST_CHAN);
-- SG is enabled and not at end.
signal dma2bus_wrack_i : std_logic;
signal dma2bus_rdack_i : std_logic;
-- is_idle: The DMA state machine is waiting to start processing the next
-- BD or to start a simple DMA operation.
signal is_idle : std_logic_vector(0 to LAST_CHAN);
-- sg_active: SG has been enabled
-- and started and has not yet reached the point where it is stopped
-- or disabled and has cleanly finished the work that it started
-- while active. Cleanly finishing its work includes, for SG packet
-- Rx and SG packet Tx channels, that all packets that were started
-- have finished and their status is recorded.
signal sg_active : std_logic_vector(0 to LAST_CHAN);
signal sg_active_d1 : std_logic_vector(0 to LAST_CHAN);
signal dma_completing : std_logic;
signal dma_starting : std_logic;
signal set_DBE, set_DBT, set_L_rx : std_logic;
signal rx, tx : std_logic_vector(0 to LAST_CHAN);
-- rx(i) iff channel i is for Rx; tx(i) iff channel i is for Tx
signal dest_is_a_fifo : std_logic; -- The DMA destination for cco is a fifo.
signal dma_sel : std_logic; -- Master transaction is for dma i/o.
signal dma_sel_d1: std_logic;
signal sg_sel : std_logic; -- Master transaction is for sg BD i/o.
signal pl_sel : std_logic; -- Master transaction is for PLENGTH i/o.
signal sr_sel : std_logic;
signal dma2bus_addr_dma : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal dma2ip_addr_dma : std_logic_vector(0 to C_M-1);
signal dma2bus_mstwrreq_dma : std_logic;
signal dma2bus_mstrdreq_dma : std_logic;
signal dma2bus_mstnum_dma : std_logic_vector(DMA2Bus_MstNum'range);
signal dma2bus_mstnum_dma_p1: std_logic_vector(DMA2Bus_MstNum'range);
signal burst_cond_dma : std_logic; -- The condition on which the decision
-- to burst is based.
signal dma2bus_addr_sg : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal dma2ip_addr_sg : std_logic_vector(0 to C_M-1);
signal dma2bus_mstwrreq_sg : std_logic;
signal dma2bus_mstrdreq_sg : std_logic;
signal dma2bus_mstwrreq_sr : std_logic;
signal dma2bus_mstwrreq_pl : std_logic;
signal first : std_logic_vector(0 to LAST_CHAN);
-- Channel cco is on its first
-- DMA operation of a packet.
signal update_first : std_logic; -- Update first for the cco.
signal no_bda_link : std_logic_vector(0 to LAST_CHAN);
-- The BDA for the corresponding channel has been written while
-- not sg_active and an operation under the next sg_active tenure has not
-- started.
signal load_length : std_logic_vector(0 to LAST_CHAN);
signal load_bda : std_logic_vector(0 to LAST_CHAN);
signal wr_SRAddrFIFO : std_logic_vector(0 to LAST_CHAN);
signal rd_SRAddrFIFO : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_full : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_nonempty : std_logic_vector(0 to LAST_CHAN);
type SRAddrFIFO_out_t
is array (natural range <>) of std_logic_vector(
0 to
C_OPB_AWIDTH-1
);
signal SRAddrFIFO_out : SRAddrFIFO_out_t(0 to LAST_CHAN);
type sg_offset_t
is array (natural range <>) of UNSIGNED(0 to RPB-1);
signal sg_offset : sg_offset_t(0 to LAST_CHAN);
signal reset_sg_offset : std_logic;
signal inc_sg_offset : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_cco_hasroom : std_logic;
signal DMA2Intr_Intr_i : std_logic_vector(0 to LAST_CHAN);
signal pw_enable_pulse : std_logic;
-- An enable pulse of one Bus2IP_Clk period at the frequency
-- of required PWB update.
signal pwb_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal pw_timer_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal upc_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal pwb_loaded : std_logic_vector(0 to LAST_CHAN);
-- Bitwise "or" of an UNSIGNED value.
-- Todo Replace calls by instances of or_muxcy?
function or_UNSIGNED(s: UNSIGNED) return std_logic is
variable ss : UNSIGNED(0 to s'length-1) := s;
variable result: std_logic := '0';
begin
for i in s'left to s'right loop
result := result or s(i);
end loop;
return result;
end or_UNSIGNED;
-- Find the leftmost bit over the LENGTH registers of all channels.
function min_length_left(nv: INTEGER_ARRAY_TYPE) return natural is
variable largest_width : natural := 0;
begin
for i in 0 to LAST_CHAN loop
if nv(i) > largest_width then largest_width := nv(i); end if;
end loop;
return DMA_DWIDTH - largest_width;
end min_length_left;
-- LENGTHS_LEFT gives the minimum left index over all channels.
-- It corresponds to the widest LENGTH register required.
constant LENGTHS_LEFT : natural := min_length_left(C_DMA_LENGTH_WIDTH);
constant LENGTHS_WIDTH : natural := DMA_DWIDTH-LENGTHS_LEFT;
function zero_vector(n: natural) return UNSIGNED is
variable result : UNSIGNED(0 to n-1) := (others => '0');
begin
return result;
end zero_vector;
function clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE: INTEGER_ARRAY_TYPE)
return boolean is
begin
for i in C_DMA_CHAN_TYPE'range loop
if (C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3)
and C_INTR_COALESCE(i) = 1 then
return true;
end if;
end loop;
return false;
end clock_divider_needed;
function to_string(n: natural) return STRING is
variable s : string(20 downto 1);
variable j : natural := 1;
variable m : natural := n;
type decimal_digit_to_char is array (natural range 0 to 9) of character;
constant tab : decimal_digit_to_char :=
('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
begin
loop
s(j) := tab(m mod 10);
m := m / 10;
exit when m = 0;
j := j+1;
end loop;
return s(j downto 1);
end to_string;
function is_power_of_2(n: positive) return boolean is
begin
if n = 1 then return true;
elsif n mod 2 = 1 then return false;
else return is_power_of_2(n/2);
end if;
end is_power_of_2;
begin --( architecture
----------------------------------------------------------------------------
-- Checks on parameters and interface signals.
----------------------------------------------------------------------------
assert Bus2IP_Data'length = DMA_DWIDTH
report "Bus2IP_Data is a vector of size " &
to_string(Bus2IP_Data'length) &
", which is not equal, as required, to " &
to_string(DMA_DWIDTH) & "."
severity failure;
assert is_power_of_2(C_OPB_DWIDTH)
report "C_OPB_DWIDTH is " &
to_string(C_OPB_DWIDTH) &
", which is not a power of two, as required."
severity failure;
assert is_power_of_2(DMA_DWIDTH)
report "DMA_DWIDTH is " &
to_string(DMA_DWIDTH) &
", which is not a power of two, as required."
severity failure;
assert is_power_of_2(TPB)
report "TPB is " &
to_string(TPB) &
", which is not a power of two, as required."
severity failure;
assert C_OPB_DWIDTH >= DMA_DWIDTH
report "C_OPB_DWIDTH with value " &
to_string(C_OPB_DWIDTH) &
" is not greater than or equal to DMA_DWIDTH with value " &
to_string(DMA_DWIDTH) &
", as required."
severity failure;
----------------------------------------------------------------------------
-- Verify that TPB (Transfers Per Burst) is consistent with the width of
-- DMA2Bus_MstNum.
----------------------------------------------------------------------------
assert ceil_log2(TPB) <= DMA2Bus_MstNum'length
report "In file opb_ipif_sim.vhd the width of DMA2Bus_MstNum of " &
to_string(DMA2Bus_MstNum'length) &
" is to small for the DMA burst size of " &
to_string(TPB) &
" ."
severity failure;
tmp_C_DMA_BASEADDR <= C_DMA_BASEADDR; -- ToDo, XST workaround
--ToDo, handle byte enable signals (probably return error on non BE=1111)
-- Assignment of register bits and bit fields
SINC_GENERATE: for i in 0 to LAST_CHAN generate
SINC(i) <= DMACR(i)(0);
end generate;
DINC_GENERATE: for i in 0 to LAST_CHAN generate
DINC(i) <= DMACR(i)(1);
end generate;
SLOCAL_GENERATE: for i in 0 to LAST_CHAN generate
SLOCAL(i) <= DMACR(i)(2);
end generate;
DLOCAL_GENERATE: for i in 0 to LAST_CHAN generate
DLOCAL(i) <= DMACR(i)(3);
end generate;
SGS_GENERATE: for i in 0 to LAST_CHAN generate
SGS(i) <= '1' when C_DMA_CHAN_TYPE(i) = 0 else
DMACR(i)(4);
end generate;
SGE_GENERATE: for i in 0 to LAST_CHAN generate
SGE(i) <= '0' when C_DMA_CHAN_TYPE(i) = 0 else
SWCR(i);
end generate;
SGGO_GENERATE: for i in 0 to LAST_CHAN generate
sgGo(i) <= (not SGS(i) and SGE(i))
or -- If pkt SG, then get to a packet boundary.
( not first(i)
and bo2sl( C_DMA_CHAN_TYPE(i) = 2
or C_DMA_CHAN_TYPE(i) = 3
)
);
end generate;
L_TX_GEN: for i in 0 to LAST_CHAN generate
L_tx(i) <= '0' when (C_DMA_CHAN_TYPE(i) /= 2) else DMACR(i)(b_L_dmacr);
end generate;
--- Address decoding
-- channel selects
chan_num <= TO_INTEGER(UNSIGNED(Bus2IP_Addr( C_M-RPB-NUM_CHAN_BITS
to C_M-RPB-1 )));
CHAN_SELECTION: process (chan_num)
begin
for i in 0 to LAST_CHAN loop
chan_sel(i) <= bo2sl(chan_num = i);
end loop;
end process;
CCO_ONEHOT_PROCESS: process (cco)
begin
for i in 0 to LAST_CHAN loop
cco_onehot(i) <= bo2sl(cco = i);
end loop;
end process;
RX_GEN: for i in 0 to LAST_CHAN generate
rx(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 3) and (sgGo(i) or sg_active(i));
-- A sg rx packet channel can be used for simple DMA when it is not
-- operating under SG.
end generate;
dest_is_a_fifo <= bo2sl( C_DMA_CHAN_TYPE(cco) = 2
and sg_active(cco) = '1');
TX_GEN: for i in 0 to LAST_CHAN generate
tx(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 2) and (sgGo(i) or sg_active(i));
-- A sg tx packet channel can be used for simple DMA when it is not
-- operating under SG.
end generate;
-- register selects
RSTMIR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_RSTMIR, RPB)));
DMACR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DMACR, RPB)));
SA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_SA, RPB)));
DA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DA, RPB)));
LENGTH_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_LENGTH, RPB)));
DMASR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DMASR, RPB)));
BDA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_BDA, RPB)));
SWCR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_SWCR, RPB)));
UPC_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_UPC, RPB)));
PCT_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PCT, RPB)));
PWB_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PWB, RPB)));
ISR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_ISR, RPB)));
IER_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_IER, RPB)));
PLENGTH_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PLENGTH, RPB)));
--= end, Address decoding
--- Various logic
----------------------------------------------------------------------------
-- These statements calculate adj.
-- Either LENGTH or PLENGTH is the evaluated value, depending on whether the
-- channel is rx. If the evaluated value is >= BPST, adj is BPST, which
-- means that the low-order two bits may need to be masked. Otherwise,
-- adj is the two low-order bits of the evaluated value.
----------------------------------------------------------------------------
LENGTH_ge_BPBT<= or_UNSIGNED( LENGTH_cco(LENGTHS_LEFT to
DMA_DWIDTH - BPBT_BITS - 1));
PLENGTH_ge_BPBT<= or_UNSIGNED(PLENGTH_cco(LENGTHS_LEFT to
DMA_DWIDTH - BPBT_BITS - 1));
LENGTH_ge_2BPST <= LENGTH_ge_BPBT or
or_UNSIGNED( LENGTH_cco(DMA_DWIDTH - BPBT_BITS to
DMA_DWIDTH - BPST_BITS - 2));
PLENGTH_ge_2BPST <= PLENGTH_ge_BPBT or
or_UNSIGNED(PLENGTH_cco(DMA_DWIDTH - BPBT_BITS to
DMA_DWIDTH - BPST_BITS - 2));
----------------------------------------------------------------------------
-- The next process maintains the global adj value with
-- respect to the cco.
-- Notes:
-- (1) Whenever adj is to be used to update channel n, cco=n must hold
-- for both the previous and current cycles.
-- (2) adj is sourced from FFs to reduce path time.
-- (3) When dec_length is true, we are looking ahead by
-- an extra BPST, which is the reason for the >= 2*BPST check
-- instead of a >= BPST check.
-- (4) It is required that BPST be a power of 2.
----------------------------------------------------------------------------
ADJ_PROCESS: process (Bus2IP_Clk)
variable len : UNSIGNED(0 to LENGTH_cco'length-1);
variable len_ge_2BPST : std_logic;
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if rx(cco)='0' then
len := LENGTH_cco;
len_ge_2BPST := LENGTH_ge_2BPST;
else
len := PLENGTH_cco;
len_ge_2BPST := PLENGTH_ge_2BPST;
end if;
adj(0) <= len_ge_2BPST
or (not dec_length and len( DMA_DWIDTH
- BPST_BITS
- 1)
);
for i in 1 to BPST_BITS LOOP
-- The following expression zeroes non high-order adj bits
-- when the next transfer will be BPST, otherwise
-- adj becomes what is left to transfer, i.e. the corresponding
-- adj bit is taken from the corresponding len bit.
adj(i) <= not( len_ge_2BPST
or (not dec_length and len( DMA_DWIDTH
- BPST_BITS
- 1)
)
)
and len(DMA_DWIDTH - BPST_BITS + i - 1);
end loop;
end if;
end process;
DMA2Bus_Error <= '0';
DMA2Bus_Retry <= '0';
Bus2IP_DMA_Ack <= '0';
DMA2Bus_ToutSup <= '0';
DMA2INTR_GENERATE: for i in 0 to LAST_CHAN generate
DMA2Intr_Intr_i(i) <= (DD(i) and EDD(i))
or (DE(i) and EDE(i))
or (PD(i) and EPD(i))
or (PCTR(i) and EPCTR(i))
or (PWBR(i) and EPWBR(i))
or (SGDA(i) and ESGDA(i))
or (SGEND(i) and ESGEND(i));
DMA2Intr_Intr(i) <= DMA2Intr_Intr_i(i);
end generate;
L_GEN: for i in 0 to LAST_CHAN generate
L(i) <= ( (tx(i) and L_tx(i))
or (rx(i) and L_rx(i))
);
end generate;
FIRST_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if reset(i) = '1' then
first(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 2 or
C_DMA_CHAN_TYPE(i) = 3);
elsif update_first = '1' and cco = i then
first(i) <= L(i);
end if;
end loop;
end if;
end process;
SG_OFFSET_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if (reset(i) or (reset_sg_offset and cco_onehot(i))) = '1' then
sg_offset(i) <= (others => '0');
elsif inc_sg_offset(i) = '1' then
sg_offset(i) <= sg_offset(i) + 1;
end if;
end loop;
end if;
end process;
SRAddrFIFO_cco_hasroom <= '1' when (C_DMA_CHAN_TYPE(cco) = 2 or
C_DMA_CHAN_TYPE(cco) = 3)
and SRAddrFIFO_full(cco) = '0'
else '0';
--= end, Various logic
--- Clock divider.
INCLUDE_CLOCK_DIVIDER: if clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE) generate
constant num_stages : natural
:= Div_Stages(base_period => C_CLK_PERIOD_PS,
target_period=> C_PACKET_WAIT_UNIT_NS
* 1000
);
begin
--------------------------------------------------------------------------
-- This option implements the packet-wait timebase divider using a
-- Q-to-Clk ripple counter.
--------------------------------------------------------------------------
GEN_RIPPLE_PW_DIVIDER: if RIPPLE_PW_DIVIDER generate
signal divby2to : std_logic_vector(0 to num_stages);
signal ripout, ripout_d1, ripout_d2, ripout_d3 : std_logic;
begin
divby2to(0) <= Bus2IP_Clk;
ripout <= divby2to(num_stages);
------------------------------------------------------------------------
-- Clock division via a ripple counter.
------------------------------------------------------------------------
DIVIDE_CLK: for i in 1 to num_stages generate
DIV_FF: process(divby2to(i-1), Bus2IP_Reset)
begin
if Bus2IP_Reset = RESET_ACTIVE then
divby2to(i) <= '0';
else
if divby2to(i-1)'event and divby2to(i-1) = '1' then
divby2to(i) <= not divby2to(i);
end if;
end if;
end process;
end generate;
------------------------------------------------------------------------
-- This process syncronizes the output of the ripple counter into
-- the Bus2IP_Clk domain and sets up edge detection.
------------------------------------------------------------------------
SYNC_AND_ENABLE: process(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
ripout_d1 <= '0';
ripout_d2 <= '0';
ripout_d3 <= '0';
else
ripout_d1 <= divby2to(num_stages);
ripout_d2 <= ripout_d1;
ripout_d3 <= ripout_d2;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Edge detection gives a one-pulse signal in the Bus2IP_Clk domain.
------------------------------------------------------------------------
pw_enable_pulse <= not ripout_d2 and ripout_d3;
end generate GEN_RIPPLE_PW_DIVIDER;
--------------------------------------------------------------------------
-- This option implements the packet-wait timebase divider using a
-- synchronous counter.
--------------------------------------------------------------------------
GEN_SYNC_PW_DIVIDER: if not RIPPLE_PW_DIVIDER generate
constant ZERO_NUM_STAGES : std_logic_vector(0 to num_stages-1)
:= (others => '0');
signal sdivby2to : std_logic_vector(num_stages downto 1);
signal sdivby2to_num_stages_d1 : std_logic;
begin
SYNC_PW_DIVIDER : PROCESS(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
sdivby2to <= (others => '0');
else
sdivby2to <= std_logic_vector(UNSIGNED(sdivby2to) + 1);
end if;
end if;
end process;
OUPUT_D1: process(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
sdivby2to_num_stages_d1 <= '0';
else
sdivby2to_num_stages_d1 <= sdivby2to(num_stages);
end if;
end if;
end process;
pw_enable_pulse <= not sdivby2to(num_stages)
and sdivby2to_num_stages_d1;
end generate GEN_SYNC_PW_DIVIDER;
end generate INCLUDE_CLOCK_DIVIDER;
EXCLUDE_CLOCK_DIVIDER: if not clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE) generate
pw_enable_pulse <= '0';
end generate EXCLUDE_CLOCK_DIVIDER;
--= end, Clock divider.
--- Register implementations
---------------------------------------------------------------------
-- These processes generate the DMA2Bus_WrAck.
---------------------------------------------------------------------
DMA2BUS_WRACK_I_PROCESS: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = RESET_ACTIVE) then
dma2bus_wrack_i <= '0';
--ToDo The last conjunct probably not needed.
elsif ((DMA_WrCE and Bus2IP_WrReq)='1' and dma2bus_wrack_i='0') then
dma2bus_wrack_i <= '1';
else
dma2bus_wrack_i <= '0';
end if;
end if;
end process;
DMA2Bus_WrAck <= dma2bus_wrack_i;
---------------------------------------------------------------------
-- These processes implement the channel reset "register".
---------------------------------------------------------------------
PERP_CHANNEL_RESET_GEN: for i in 0 to LAST_CHAN generate
prog_reset(i) <=
bo2sl( (chan_sel(i) and RSTMIR_sel and dma2bus_wrack_i) = '1'
and (Bus2IP_Data(DMA_DWIDTH-4 to
DMA_DWIDTH-1)) = "1010"
);
reset(i) <= bo2sl(Bus2IP_Reset = RESET_ACTIVE)
or prog_reset(i);
end generate;
---------------------------------------------------------------------
-- This process implements a DMACR register for each channel.
---------------------------------------------------------------------
-- DMACR_REG_PROCESS: process (Bus2IP_Clk)
-- begin
-- for i in 0 to LAST_CHAN loop
-- if Bus2IP_Clk'event and Bus2IP_Clk='1' then
-- if (reset(i) = RESET_ACTIVE) then
-- DMACR(i)(0 to 6) <= "1001000";
-- elsif (chan_sel(i) and DMACR_sel and dma2bus_wrack_i) = '1' then
-- DMACR(i)(0 to 6) <= Bus2IP_Data(0 to 6);
-- end if;
-- end if;
-- end loop;
-- end process;
DMACR_GENERATE: for i in 0 to LAST_CHAN generate
I_DMACR: ctrl_reg_0_to_6
-- I_DMACR: entity ctrl_reg(sim)
generic map ("1001100")
port map (
clk => Bus2IP_Clk,
rst => reset(i),
chan_sel => chan_sel(i),
reg_sel => DMACR_sel,
wr_ce => dma2bus_wrack_i,
d => Bus2IP_Data(b_SINC to b_L_dmacr),
q => DMACR(i)(b_SINC to b_L_dmacr)
);
end generate;
SWCR_GENERATE: for i in 0 to LAST_CHAN generate
I_SWCR: ctrl_reg_0_to_0
generic map ("0")
port map (
clk => Bus2IP_Clk,
rst => reset(i),
chan_sel => chan_sel(i),
reg_sel => SWCR_sel,
wr_ce => dma2bus_wrack_i,
-- XGR_E33 d => Bus2IP_Data(b_SGE to b_SGE),
-- XGR_E33 q => SWCR(i)(b_SGE to b_SGE)
d => Bus2IP_Data(b_SGE),
q => SWCR(i)
);
end generate;
--r ---------------------------------------------------------------------
--r -- This process implements a SA register for each channel.
--r ---------------------------------------------------------------------
--r SA_REG_PROCESS: process (Bus2IP_Clk)
--r begin
--r for i in 0 to LAST_CHAN loop
--r if Bus2IP_Clk'event and Bus2IP_Clk='1' then
--r if (reset(i) = RESET_ACTIVE) then
--r SA(i) <= (others => '0');
--r elsif (cco_onehot(i) and SINC(i) and inc_SA) = '1' then
--r SA(i) <= SA(i) + BPST;
--r elsif (chan_sel(i) and SA_sel and dma2bus_wrack_i) = '1' then
--r SA(i) <= UNSIGNED(Bus2IP_Data);
--r end if;
--r end if;
--r end loop;
--r end process;
---------------------------------------------------------------------
-- The below implements a SA for each channel.
---------------------------------------------------------------------
SA_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(SA(i)'range);
begin
--
RST_EF <= reset(i);
LOAD_EF <= (chan_sel(i) and SA_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and SINC(i) and inc_SA);
--
I_SA : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => true,
C_REG_WIDTH => SA(i)'length,
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => SA(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => BPST_BITS
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(SA(i)'range),
LD => Bus2IP_Data(0 to DMA_DWIDTH-1),
AD => "1",
LOAD => LOAD_EF,
OP => OP_EF
);
--
SA(i)(SA(i)'range) <=
UNSIGNED(qslv(SA(i)'range));
end generate;
end generate;
---------------------------------------------------------------------
-- The below implements a DA for each channel.
---------------------------------------------------------------------
DA_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(DA(i)'range);
begin
--
RST_EF <= reset(i);
LOAD_EF <= (chan_sel(i) and DA_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and DINC(i) and inc_DA);
--
I_DA : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => true,
C_REG_WIDTH => DA(i)'length,
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => DA(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => BPST_BITS
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DA(i)'range),
LD => Bus2IP_Data(0 to DMA_DWIDTH-1),
AD => "1",
LOAD => LOAD_EF,
OP => OP_EF
);
--
DA(i)(DA(i)'range) <=
UNSIGNED(qslv(DA(i)'range));
end generate;
end generate;
LOAD_LENGTH_GENERATE: for i in 0 to LAST_CHAN generate
load_length(i) <= chan_sel(i) and LENGTH_sel and dma2bus_wrack_i;
end generate;
LOAD_BDA_GENERATE: for i in 0 to LAST_CHAN generate
load_bda(i) <= chan_sel(i) and BDA_sel and dma2bus_wrack_i;
end generate;
---------------------------------------------------------------------
-- The below implements a LENGTH register of the correct size for
-- each channel.
---------------------------------------------------------------------
LENGTH_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(0 to DMA_DWIDTH-1);
begin
--
RST_EF <= reset(i) or ((cco_onehot(i) and clr_PLENGTH));
LOAD_EF <= (chan_sel(i) and LENGTH_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and dec_LENGTH);
--
I_LENGTH : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_LD_OFFSET => 0,
C_AD_WIDTH => adj'length,
C_AD_OFFSET => 0
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
LD => Bus2IP_Data(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
AD => std_logic_vector(adj),
LOAD => LOAD_EF,
OP => OP_EF
);
--
LENGTH(i)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1) <=
unsigned(qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1));
LENGTH(i)(0 to DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i)-1) <=
(others => '0');
end generate;
end generate;
---------------------------------------------------------------------
-- The below implements a PLENGTH register of the correct size for
-- each channel that requires one.
---------------------------------------------------------------------
PLENGTH_REG_GEN: for i in 0 to LAST_CHAN generate
T0or1_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 generate
PLENGTH(i) <= (others => '0');
end generate;
T2_GEN: if C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3 generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(0 to DMA_DWIDTH-1);
begin
--
RST_EF <= reset(i) or ((cco_onehot(i) and clr_PLENGTH));
LOAD_EF <= (chan_sel(i) and PLENGTH_sel and dma2bus_wrack_i);
OP_ADD_GEN: if C_DMA_CHAN_TYPE(i) = 2 generate
OP_EF <= (cco_onehot(i) and inc_PLENGTH);
end generate;
OP_SUB_GEN: if C_DMA_CHAN_TYPE(i) = 3 generate
OP_EF <= (cco_onehot(i) and dec_PLENGTH);
end generate;
--
I_PLENGTH : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => C_DMA_CHAN_TYPE(i) = 2,
C_REG_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_LD_OFFSET => 0,
C_AD_WIDTH => adj'length,
C_AD_OFFSET => 0
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
LD => Bus2IP_Data(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
AD => std_logic_vector(adj),
LOAD => LOAD_EF,
OP => OP_EF
);
--
PLENGTH(i)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1) <=
unsigned(qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1));
PLENGTH(i)(0 to DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i)-1)
<= (others => '0');
end generate;
end generate;
---------------------------------------------------------------------
-- dma_active bit (set when LENGTH loaded, cleared by dma state machine).
---------------------------------------------------------------------
DMA_ACTIVE_BIT_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
dma_active(i) <= '0';
elsif load_length(i) = '1' then
dma_active(i) <= '1';
elsif dma_completing = '1' and cco = i then
dma_active(i) <= '0';
end if;
end if;
end loop;
end process;
---------------------------------------------------------------------
-- This process implements a DMASR register for each channel.
-- (note: DMA_BSY and SG_BSY implemented separately.)
---------------------------------------------------------------------
DMASR_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DBE(i) <= '0';
DBT(i) <= '0';
L_rx(i) <= '0';
elsif cco = i then
if dma_starting = '1' then
DBE(i) <= '0';
DBT(i) <= '0';
L_rx(i) <= '0';
elsif set_DBE = '1' then
DBE(i) <= '1';
elsif set_DBT = '1' then
DBT(i) <= '1';
elsif set_L_rx= '1' then
L_rx(i) <= '1';
end if;
end if;
end if;
end loop;
end process;
---------------------------------------------------------------------
-- This process implements a BDA register for each channel that
-- supports scatter/gather.
---------------------------------------------------------------------
BDA_REG_PROCESS: process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
for i in 0 to LAST_CHAN loop
if C_DMA_CHAN_TYPE(i) = 1
or C_DMA_CHAN_TYPE(i) = 2
or C_DMA_CHAN_TYPE(i) = 3 then
if (reset(i) = RESET_ACTIVE) then
BDA(i) <= ( others => '0');
no_bda_link(i) <= '0';
elsif load_bda(i) = '1' then
BDA(i) <= UNSIGNED(Bus2IP_Data);
no_bda_link(i) <= not sg_active(i);
elsif (cco_onehot(i) and sg_active(i) and not is_idle(i)) = '1' then
no_bda_link(i) <= '0';
end if;
else
no_bda_link(i) <= '0';
end if;
end loop;
end if;
end process;
----------------------------------------------------------------------------
-- The processes below implement the ISR interrupt bits for each channel.
----------------------------------------------------------------------------
DD_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DD(i) <= '0';
elsif dma_completing = '1' and cco_onehot(i) = '1' then
DD(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
DD(i) <= DD(i) xor Bus2IP_Data(b_DD); -- Tog on wr.
end if;
end if;
end loop;
end process;
DE_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DE(i) <= '0';
elsif (set_DBE or set_DBT) = '1' and cco_onehot(i) = '1' then
DE(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
DE(i) <= DE(i) xor Bus2IP_Data(b_DE); -- Tog on wr.
end if;
end if;
end loop;
end process;
PD_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PD(i) <= '0';
elsif rd_SRAddrFIFO(i) = '1' then
PD(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PD(i) <= PD(i) xor Bus2IP_Data(b_PD); -- Tog on wr.
end if;
end if;
end loop;
end process;
PCTR_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PCTR(i) <= '0';
elsif (UPC(i) >= PCT(i)) and (PCT(i) /= 0) then
PCTR(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PCTR(i) <= PCTR(i) xor Bus2IP_Data(b_PCTR); -- Tog on wr.
end if;
end if;
end loop;
end process;
PWBR_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PWBR(i) <= '0';
elsif C_DMA_CHAN_TYPE(i) > 1 and
C_INTR_COALESCE(i) = 1 and
(pw_timer_eq_0(i)) = '1' then
PWBR(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PWBR(i) <= PWBR(i) xor Bus2IP_Data(b_PWBR); -- Tog on wr.
end if;
end if;
end loop;
end process;
SGDA_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
SGDA(i) <= '0';
elsif (not sg_active(i) and sg_active_d1(i) and not SGE(i)) = '1'
then
SGDA(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
SGDA(i) <= SGDA(i) xor Bus2IP_Data(b_SGDA); -- Tog on wr.
end if;
end if;
end loop;
end process;
SGDEND_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
SGEND(i) <= '0';
elsif (not sg_active(i) and sg_active_d1(i) and SGS(i)) = '1' then
SGEND(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
SGEND(i) <= SGEND(i) xor Bus2IP_Data(b_SGEND); -- Tog on wr.
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the IER for each channel.
----------------------------------------------------------------------------
IER_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
EDD(i) <= '0';
EDE(i) <= '0';
EPD(i) <= '0';
EPCTR(i) <= '0';
EPWBR(i) <= '0';
ESGDA(i) <= '0';
ESGEND(i) <= '0';
elsif (chan_sel(i) and IER_sel and dma2bus_wrack_i) = '1' then
EDD(i) <= Bus2IP_Data(b_DD);
EDE(i) <= Bus2IP_Data(b_DE);
EPD(i) <= Bus2IP_Data(b_PD);
EPCTR(i) <= Bus2IP_Data(b_PCTR);
EPWBR(i) <= Bus2IP_Data(b_PWBR);
ESGDA(i) <= Bus2IP_Data(b_SGDA);
ESGEND(i) <= Bus2IP_Data(b_SGEND);
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the UPC register for each channel.
----------------------------------------------------------------------------
UPC_REG_PROCESS: process (Bus2IP_Clk)
variable add1 : UNSIGNED(DMA_DWIDTH-UPCB to DMA_DWIDTH-1);
variable sub1 : natural;
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
add1 := (others => rd_SRAddrFIFO(i)); -- zero or minus 1
if (chan_sel(i) and UPC_sel and dma2bus_wrack_i and
Bus2IP_Data(DMA_DWIDTH-1)) = '1' then
sub1 := 1;
else sub1 := 0;
end if;
if (reset(i) = RESET_ACTIVE) then
UPC(i) <= (others => '0');
else
UPC(i) <= (UPC(i) - add1) - sub1;
-- This will increment if rd_SRAddrFIFO(i), decrement if
-- writing a one in LSB, stay unchanged if both or neither.
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the PCT register for each channel.
----------------------------------------------------------------------------
PCT_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PCT(i) <= (others => '0');
elsif (chan_sel(i) and PCT_sel and dma2bus_wrack_i) = '1' then
PCT(i) <= UNSIGNED(Bus2IP_Data(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1)
);
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the PWB register for each channel.
----------------------------------------------------------------------------
PWB_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
pwb_loaded(i) <= '0';
if (reset(i) = RESET_ACTIVE) then
PWB(i) <= (others => '0');
elsif (chan_sel(i) and PWB_sel and dma2bus_wrack_i) = '1' then
PWB(i) <= UNSIGNED(Bus2IP_Data(DMA_DWIDTH - PWBB to
DMA_DWIDTH - 1)
);
pwb_loaded(i) <= '1';
end if;
end if;
end loop;
end process;
PWB_EQ_0_GEN: for i in 0 to LAST_CHAN generate
pwb_eq_0(i) <= not or_UNSIGNED(PWB(i));
pw_timer_eq_0(i) <= not or_UNSIGNED(pw_timer(i));
upc_eq_0(i) <= not or_UNSIGNED(UPC(i));
end generate;
---------------------------------------------------------------------
-- The below implements a pw_timer register of each channel
-- that requires one.
---------------------------------------------------------------------
-- XGR issue on generic context
LENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0)) &
LENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0) to
DMA_DWIDTH-1);
PLENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0)) &
PLENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0) to
DMA_DWIDTH-1);
-- XGR
PW_TIMER_REG_GEN: for i in 0 to LAST_CHAN generate
T0or1_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 generate
pw_timer(i) <= (others => '0');
end generate;
T2or3_GEN: if C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3 generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OPxx, LOADxx_n, RSTxx : std_logic;
signal qslv : std_logic_vector(pw_timer(i)'range);
constant ALL_ONES : std_logic_vector(0 to pw_timer(i)'length-1)
:= (others => '1');
begin
--
RSTxx <= reset(i) or pwb_eq_0(i);
LOADxx_n <= not ( upc_eq_0(i)
or DMA2Intr_Intr_i(i)
or pw_timer_eq_0(i)
or pwb_loaded(i)
);
OPxx <= pw_enable_pulse;
--
i_pw_timer : component ld_arith_reg2
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => pw_timer(i)'length,
C_RESET_VALUE => ALL_ONES,
C_LD_WIDTH => pw_timer(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0,
C_LOAD_OVERRIDES => true
)
port map (
CK => Bus2IP_Clk,
RST => RSTxx,
Q => qslv(pw_timer(i)'range),
LD => std_logic_vector(PWB(i)),
AD => "1",
LOAD_n => LOADxx_n,
OP => OPxx
);
--
pw_timer(i) <= unsigned(qslv(pw_timer(i)'range));
end generate;
end generate;
--= end, Register implementations
--- Some register values selected by cco.
-- XGR LENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco)) &
-- XGR LENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco) to
-- XGR DMA_DWIDTH-1);
-- XGR PLENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco)) &
-- XGR PLENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco) to
-- XGR DMA_DWIDTH-1);
--= end, Some register values selected by cco.
---( Register readback
---------------------------------------------------------------------
-- This process enables the selected register onto DMA2Bus_Data
-- on slave reads.
---------------------------------------------------------------------
READ_REGISTER_PROCESS:process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
DMA2Bus_Data(0) <=
(ver_i(0) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(0) and DMA_RdCE and DMACR_sel) or
( sa_i(0) and DMA_RdCE and SA_sel) or
( da_i(0) and DMA_RdCE and DA_sel) or
(lnt_i(0) and DMA_RdCE and LENGTH_sel) or
(dsr_i(0) and DMA_RdCE and DMASR_sel) or
(bda_i(0) and DMA_RdCE and BDA_sel) or
(sge_i(0) and DMA_RdCE and SWCR_sel) or
-- (upc_i(0) and DMA_RdCE and UPC_sel) or
-- (pct_i(0) and DMA_RdCE and PCT_sel) or
-- (pwb_i(0) and DMA_RdCE and PWB_sel) or
-- (isr_i(0) and DMA_RdCE and ISR_sel) or
-- (ier_i(0) and DMA_RdCE and IER_sel) or
(ple_i(0) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(1) <=
(ver_i(1) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(1) and DMA_RdCE and DMACR_sel) or
( sa_i(1) and DMA_RdCE and SA_sel) or
( da_i(1) and DMA_RdCE and DA_sel) or
(lnt_i(1) and DMA_RdCE and LENGTH_sel) or
(dsr_i(1) and DMA_RdCE and DMASR_sel) or
(bda_i(1) and DMA_RdCE and BDA_sel) or
-- (sge_i(1) and DMA_RdCE and SWCR_sel) or
-- (upc_i(1) and DMA_RdCE and UPC_sel) or
-- (pct_i(1) and DMA_RdCE and PCT_sel) or
-- (pwb_i(1) and DMA_RdCE and PWB_sel) or
-- (isr_i(1) and DMA_RdCE and ISR_sel) or
-- (ier_i(1) and DMA_RdCE and IER_sel) or
(ple_i(1) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(2) <=
(ver_i(2) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(2) and DMA_RdCE and DMACR_sel) or
( sa_i(2) and DMA_RdCE and SA_sel) or
( da_i(2) and DMA_RdCE and DA_sel) or
(lnt_i(2) and DMA_RdCE and LENGTH_sel) or
(dsr_i(2) and DMA_RdCE and DMASR_sel) or
(bda_i(2) and DMA_RdCE and BDA_sel) or
-- (sge_i(2) and DMA_RdCE and SWCR_sel) or
-- (upc_i(2) and DMA_RdCE and UPC_sel) or
-- (pct_i(2) and DMA_RdCE and PCT_sel) or
-- (pwb_i(2) and DMA_RdCE and PWB_sel) or
-- (isr_i(2) and DMA_RdCE and ISR_sel) or
-- (ier_i(2) and DMA_RdCE and IER_sel) or
(ple_i(2) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(3) <=
(ver_i(3) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(3) and DMA_RdCE and DMACR_sel) or
( sa_i(3) and DMA_RdCE and SA_sel) or
( da_i(3) and DMA_RdCE and DA_sel) or
(lnt_i(3) and DMA_RdCE and LENGTH_sel) or
(dsr_i(3) and DMA_RdCE and DMASR_sel) or
(bda_i(3) and DMA_RdCE and BDA_sel) or
-- (sge_i(3) and DMA_RdCE and SWCR_sel) or
-- (upc_i(3) and DMA_RdCE and UPC_sel) or
-- (pct_i(3) and DMA_RdCE and PCT_sel) or
-- (pwb_i(3) and DMA_RdCE and PWB_sel) or
-- (isr_i(3) and DMA_RdCE and ISR_sel) or
-- (ier_i(3) and DMA_RdCE and IER_sel) or
(ple_i(3) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(4) <=
(ver_i(4) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(4) and DMA_RdCE and DMACR_sel) or
( sa_i(4) and DMA_RdCE and SA_sel) or
( da_i(4) and DMA_RdCE and DA_sel) or
(lnt_i(4) and DMA_RdCE and LENGTH_sel) or
(dsr_i(4) and DMA_RdCE and DMASR_sel) or
(bda_i(4) and DMA_RdCE and BDA_sel) or
-- (sge_i(4) and DMA_RdCE and SWCR_sel) or
-- (upc_i(4) and DMA_RdCE and UPC_sel) or
-- (pct_i(4) and DMA_RdCE and PCT_sel) or
-- (pwb_i(4) and DMA_RdCE and PWB_sel) or
-- (isr_i(4) and DMA_RdCE and ISR_sel) or
-- (ier_i(4) and DMA_RdCE and IER_sel) or
(ple_i(4) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(5) <=
(ver_i(5) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(5) and DMA_RdCE and DMACR_sel) or
( sa_i(5) and DMA_RdCE and SA_sel) or
( da_i(5) and DMA_RdCE and DA_sel) or
(lnt_i(5) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(5) and DMA_RdCE and DMASR_sel) or
(bda_i(5) and DMA_RdCE and BDA_sel) or
-- (sge_i(5) and DMA_RdCE and SWCR_sel) or
-- (upc_i(5) and DMA_RdCE and UPC_sel) or
-- (pct_i(5) and DMA_RdCE and PCT_sel) or
-- (pwb_i(5) and DMA_RdCE and PWB_sel) or
-- (isr_i(5) and DMA_RdCE and ISR_sel) or
-- (ier_i(5) and DMA_RdCE and IER_sel) or
(ple_i(5) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(6) <=
(ver_i(6) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(6) and DMA_RdCE and DMACR_sel) or
( sa_i(6) and DMA_RdCE and SA_sel) or
( da_i(6) and DMA_RdCE and DA_sel) or
(lnt_i(6) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(6) and DMA_RdCE and DMASR_sel) or
(bda_i(6) and DMA_RdCE and BDA_sel) or
-- (sge_i(6) and DMA_RdCE and SWCR_sel) or
-- (upc_i(6) and DMA_RdCE and UPC_sel) or
-- (pct_i(6) and DMA_RdCE and PCT_sel) or
-- (pwb_i(6) and DMA_RdCE and PWB_sel) or
-- (isr_i(6) and DMA_RdCE and ISR_sel) or
-- (ier_i(6) and DMA_RdCE and IER_sel) or
(ple_i(6) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(7) <=
(ver_i(7) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(7) and DMA_RdCE and DMACR_sel) or
( sa_i(7) and DMA_RdCE and SA_sel) or
( da_i(7) and DMA_RdCE and DA_sel) or
(lnt_i(7) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(7) and DMA_RdCE and DMASR_sel) or
(bda_i(7) and DMA_RdCE and BDA_sel) or
-- (sge_i(7) and DMA_RdCE and SWCR_sel) or
-- (upc_i(7) and DMA_RdCE and UPC_sel) or
-- (pct_i(7) and DMA_RdCE and PCT_sel) or
-- (pwb_i(7) and DMA_RdCE and PWB_sel) or
-- (isr_i(7) and DMA_RdCE and ISR_sel) or
-- (ier_i(7) and DMA_RdCE and IER_sel) or
(ple_i(7) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(8) <=
(ver_i(8) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(8) and DMA_RdCE and DMACR_sel) or
( sa_i(8) and DMA_RdCE and SA_sel) or
( da_i(8) and DMA_RdCE and DA_sel) or
(lnt_i(8) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(8) and DMA_RdCE and DMASR_sel) or
(bda_i(8) and DMA_RdCE and BDA_sel) or
-- (sge_i(8) and DMA_RdCE and SWCR_sel) or
-- (upc_i(8) and DMA_RdCE and UPC_sel) or
-- (pct_i(8) and DMA_RdCE and PCT_sel) or
-- (pwb_i(8) and DMA_RdCE and PWB_sel) or
-- (isr_i(8) and DMA_RdCE and ISR_sel) or
-- (ier_i(8) and DMA_RdCE and IER_sel) or
(ple_i(8) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(9) <=
(ver_i(9) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(9) and DMA_RdCE and DMACR_sel) or
( sa_i(9) and DMA_RdCE and SA_sel) or
( da_i(9) and DMA_RdCE and DA_sel) or
(lnt_i(9) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(9) and DMA_RdCE and DMASR_sel) or
(bda_i(9) and DMA_RdCE and BDA_sel) or
-- (sge_i(9) and DMA_RdCE and SWCR_sel) or
-- (upc_i(9) and DMA_RdCE and UPC_sel) or
-- (pct_i(9) and DMA_RdCE and PCT_sel) or
-- (pwb_i(9) and DMA_RdCE and PWB_sel) or
-- (isr_i(9) and DMA_RdCE and ISR_sel) or
-- (ier_i(9) and DMA_RdCE and IER_sel) or
(ple_i(9) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(10) <=
(ver_i(10) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(10) and DMA_RdCE and DMACR_sel) or
( sa_i(10) and DMA_RdCE and SA_sel) or
( da_i(10) and DMA_RdCE and DA_sel) or
(lnt_i(10) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(10) and DMA_RdCE and DMASR_sel) or
(bda_i(10) and DMA_RdCE and BDA_sel) or
-- (sge_i(10) and DMA_RdCE and SWCR_sel) or
-- (upc_i(10) and DMA_RdCE and UPC_sel) or
-- (pct_i(10) and DMA_RdCE and PCT_sel) or
-- (pwb_i(10) and DMA_RdCE and PWB_sel) or
-- (isr_i(10) and DMA_RdCE and ISR_sel) or
-- (ier_i(10) and DMA_RdCE and IER_sel) or
(ple_i(10) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(11) <=
(ver_i(11) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(11) and DMA_RdCE and DMACR_sel) or
( sa_i(11) and DMA_RdCE and SA_sel) or
( da_i(11) and DMA_RdCE and DA_sel) or
(lnt_i(11) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(11) and DMA_RdCE and DMASR_sel) or
(bda_i(11) and DMA_RdCE and BDA_sel) or
-- (sge_i(11) and DMA_RdCE and SWCR_sel) or
-- (upc_i(11) and DMA_RdCE and UPC_sel) or
-- (pct_i(11) and DMA_RdCE and PCT_sel) or
-- (pwb_i(11) and DMA_RdCE and PWB_sel) or
-- (isr_i(11) and DMA_RdCE and ISR_sel) or
-- (ier_i(11) and DMA_RdCE and IER_sel) or
(ple_i(11) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(12) <=
(ver_i(12) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(12) and DMA_RdCE and DMACR_sel) or
( sa_i(12) and DMA_RdCE and SA_sel) or
( da_i(12) and DMA_RdCE and DA_sel) or
(lnt_i(12) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(12) and DMA_RdCE and DMASR_sel) or
(bda_i(12) and DMA_RdCE and BDA_sel) or
-- (sge_i(12) and DMA_RdCE and SWCR_sel) or
-- (upc_i(12) and DMA_RdCE and UPC_sel) or
-- (pct_i(12) and DMA_RdCE and PCT_sel) or
-- (pwb_i(12) and DMA_RdCE and PWB_sel) or
-- (isr_i(12) and DMA_RdCE and ISR_sel) or
-- (ier_i(12) and DMA_RdCE and IER_sel) or
(ple_i(12) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(13) <=
(ver_i(13) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(13) and DMA_RdCE and DMACR_sel) or
( sa_i(13) and DMA_RdCE and SA_sel) or
( da_i(13) and DMA_RdCE and DA_sel) or
(lnt_i(13) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(13) and DMA_RdCE and DMASR_sel) or
(bda_i(13) and DMA_RdCE and BDA_sel) or
-- (sge_i(13) and DMA_RdCE and SWCR_sel) or
-- (upc_i(13) and DMA_RdCE and UPC_sel) or
-- (pct_i(13) and DMA_RdCE and PCT_sel) or
-- (pwb_i(13) and DMA_RdCE and PWB_sel) or
-- (isr_i(13) and DMA_RdCE and ISR_sel) or
-- (ier_i(13) and DMA_RdCE and IER_sel) or
(ple_i(13) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(14) <=
(ver_i(14) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(14) and DMA_RdCE and DMACR_sel) or
( sa_i(14) and DMA_RdCE and SA_sel) or
( da_i(14) and DMA_RdCE and DA_sel) or
(lnt_i(14) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(14) and DMA_RdCE and DMASR_sel) or
(bda_i(14) and DMA_RdCE and BDA_sel) or
-- (sge_i(14) and DMA_RdCE and SWCR_sel) or
-- (upc_i(14) and DMA_RdCE and UPC_sel) or
-- (pct_i(14) and DMA_RdCE and PCT_sel) or
-- (pwb_i(14) and DMA_RdCE and PWB_sel) or
-- (isr_i(14) and DMA_RdCE and ISR_sel) or
-- (ier_i(14) and DMA_RdCE and IER_sel) or
(ple_i(14) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(15) <=
(ver_i(15) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(15) and DMA_RdCE and DMACR_sel) or
( sa_i(15) and DMA_RdCE and SA_sel) or
( da_i(15) and DMA_RdCE and DA_sel) or
(lnt_i(15) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(15) and DMA_RdCE and DMASR_sel) or
(bda_i(15) and DMA_RdCE and BDA_sel) or
-- (sge_i(15) and DMA_RdCE and SWCR_sel) or
-- (upc_i(15) and DMA_RdCE and UPC_sel) or
-- (pct_i(15) and DMA_RdCE and PCT_sel) or
-- (pwb_i(15) and DMA_RdCE and PWB_sel) or
-- (isr_i(15) and DMA_RdCE and ISR_sel) or
-- (ier_i(15) and DMA_RdCE and IER_sel) or
(ple_i(15) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(16) <=
(ver_i(16) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(16) and DMA_RdCE and DMACR_sel) or
( sa_i(16) and DMA_RdCE and SA_sel) or
( da_i(16) and DMA_RdCE and DA_sel) or
(lnt_i(16) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(16) and DMA_RdCE and DMASR_sel) or
(bda_i(16) and DMA_RdCE and BDA_sel) or
-- (sge_i(16) and DMA_RdCE and SWCR_sel) or
-- (upc_i(16) and DMA_RdCE and UPC_sel) or
-- (pct_i(16) and DMA_RdCE and PCT_sel) or
-- (pwb_i(16) and DMA_RdCE and PWB_sel) or
-- (isr_i(16) and DMA_RdCE and ISR_sel) or
-- (ier_i(16) and DMA_RdCE and IER_sel) or
(ple_i(16) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(17) <=
(ver_i(17) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(17) and DMA_RdCE and DMACR_sel) or
( sa_i(17) and DMA_RdCE and SA_sel) or
( da_i(17) and DMA_RdCE and DA_sel) or
(lnt_i(17) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(17) and DMA_RdCE and DMASR_sel) or
(bda_i(17) and DMA_RdCE and BDA_sel) or
-- (sge_i(17) and DMA_RdCE and SWCR_sel) or
-- (upc_i(17) and DMA_RdCE and UPC_sel) or
-- (pct_i(17) and DMA_RdCE and PCT_sel) or
-- (pwb_i(17) and DMA_RdCE and PWB_sel) or
-- (isr_i(17) and DMA_RdCE and ISR_sel) or
-- (ier_i(17) and DMA_RdCE and IER_sel) or
(ple_i(17) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(18) <=
(ver_i(18) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(18) and DMA_RdCE and DMACR_sel) or
( sa_i(18) and DMA_RdCE and SA_sel) or
( da_i(18) and DMA_RdCE and DA_sel) or
(lnt_i(18) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(18) and DMA_RdCE and DMASR_sel) or
(bda_i(18) and DMA_RdCE and BDA_sel) or
-- (sge_i(18) and DMA_RdCE and SWCR_sel) or
-- (upc_i(18) and DMA_RdCE and UPC_sel) or
-- (pct_i(18) and DMA_RdCE and PCT_sel) or
-- (pwb_i(18) and DMA_RdCE and PWB_sel) or
-- (isr_i(18) and DMA_RdCE and ISR_sel) or
-- (ier_i(18) and DMA_RdCE and IER_sel) or
(ple_i(18) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(19) <=
(ver_i(19) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(19) and DMA_RdCE and DMACR_sel) or
( sa_i(19) and DMA_RdCE and SA_sel) or
( da_i(19) and DMA_RdCE and DA_sel) or
(lnt_i(19) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(19) and DMA_RdCE and DMASR_sel) or
(bda_i(19) and DMA_RdCE and BDA_sel) or
-- (sge_i(19) and DMA_RdCE and SWCR_sel) or
-- (upc_i(19) and DMA_RdCE and UPC_sel) or
-- (pct_i(19) and DMA_RdCE and PCT_sel) or
-- (pwb_i(19) and DMA_RdCE and PWB_sel) or
-- (isr_i(19) and DMA_RdCE and ISR_sel) or
-- (ier_i(19) and DMA_RdCE and IER_sel) or
(ple_i(19) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(20) <=
(ver_i(20) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(20) and DMA_RdCE and DMACR_sel) or
( sa_i(20) and DMA_RdCE and SA_sel) or
( da_i(20) and DMA_RdCE and DA_sel) or
(lnt_i(20) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(20) and DMA_RdCE and DMASR_sel) or
(bda_i(20) and DMA_RdCE and BDA_sel) or
-- (sge_i(20) and DMA_RdCE and SWCR_sel) or
-- (upc_i(20) and DMA_RdCE and UPC_sel) or
-- (pct_i(20) and DMA_RdCE and PCT_sel) or
-- (pwb_i(20) and DMA_RdCE and PWB_sel) or
-- (isr_i(20) and DMA_RdCE and ISR_sel) or
-- (ier_i(20) and DMA_RdCE and IER_sel) or
(ple_i(20) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(21) <=
(ver_i(21) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(21) and DMA_RdCE and DMACR_sel) or
( sa_i(21) and DMA_RdCE and SA_sel) or
( da_i(21) and DMA_RdCE and DA_sel) or
(lnt_i(21) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(21) and DMA_RdCE and DMASR_sel) or
(bda_i(21) and DMA_RdCE and BDA_sel) or
-- (sge_i(21) and DMA_RdCE and SWCR_sel) or
-- (upc_i(21) and DMA_RdCE and UPC_sel) or
-- (pct_i(21) and DMA_RdCE and PCT_sel) or
-- (pwb_i(21) and DMA_RdCE and PWB_sel) or
-- (isr_i(21) and DMA_RdCE and ISR_sel) or
-- (ier_i(21) and DMA_RdCE and IER_sel) or
(ple_i(21) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(22) <=
(ver_i(22) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(22) and DMA_RdCE and DMACR_sel) or
( sa_i(22) and DMA_RdCE and SA_sel) or
( da_i(22) and DMA_RdCE and DA_sel) or
(lnt_i(22) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(22) and DMA_RdCE and DMASR_sel) or
(bda_i(22) and DMA_RdCE and BDA_sel) or
-- (sge_i(22) and DMA_RdCE and SWCR_sel) or
(upc_i(22) and DMA_RdCE and UPC_sel) or
(pct_i(22) and DMA_RdCE and PCT_sel) or
(pwb_i(22) and DMA_RdCE and PWB_sel) or
-- (isr_i(22) and DMA_RdCE and ISR_sel) or
-- (ier_i(22) and DMA_RdCE and IER_sel) or
(ple_i(22) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(23) <=
(ver_i(23) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(23) and DMA_RdCE and DMACR_sel) or
( sa_i(23) and DMA_RdCE and SA_sel) or
( da_i(23) and DMA_RdCE and DA_sel) or
(lnt_i(23) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(23) and DMA_RdCE and DMASR_sel) or
(bda_i(23) and DMA_RdCE and BDA_sel) or
-- (sge_i(23) and DMA_RdCE and SWCR_sel) or
(upc_i(23) and DMA_RdCE and UPC_sel) or
(pct_i(23) and DMA_RdCE and PCT_sel) or
(pwb_i(23) and DMA_RdCE and PWB_sel) or
-- (isr_i(23) and DMA_RdCE and ISR_sel) or
-- (ier_i(23) and DMA_RdCE and IER_sel) or
(ple_i(23) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(24) <=
(ver_i(24) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(24) and DMA_RdCE and DMACR_sel) or
( sa_i(24) and DMA_RdCE and SA_sel) or
( da_i(24) and DMA_RdCE and DA_sel) or
(lnt_i(24) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(24) and DMA_RdCE and DMASR_sel) or
(bda_i(24) and DMA_RdCE and BDA_sel) or
-- (sge_i(24) and DMA_RdCE and SWCR_sel) or
(upc_i(24) and DMA_RdCE and UPC_sel) or
(pct_i(24) and DMA_RdCE and PCT_sel) or
(pwb_i(24) and DMA_RdCE and PWB_sel) or
(isr_i(24) and DMA_RdCE and ISR_sel) or
(ier_i(24) and DMA_RdCE and IER_sel) or
(ple_i(24) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(25) <=
(ver_i(25) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(25) and DMA_RdCE and DMACR_sel) or
( sa_i(25) and DMA_RdCE and SA_sel) or
( da_i(25) and DMA_RdCE and DA_sel) or
(lnt_i(25) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(25) and DMA_RdCE and DMASR_sel) or
(bda_i(25) and DMA_RdCE and BDA_sel) or
-- (sge_i(25) and DMA_RdCE and SWCR_sel) or
(upc_i(25) and DMA_RdCE and UPC_sel) or
(pct_i(25) and DMA_RdCE and PCT_sel) or
(pwb_i(25) and DMA_RdCE and PWB_sel) or
(isr_i(25) and DMA_RdCE and ISR_sel) or
(ier_i(25) and DMA_RdCE and IER_sel) or
(ple_i(25) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(26) <=
(ver_i(26) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(26) and DMA_RdCE and DMACR_sel) or
( sa_i(26) and DMA_RdCE and SA_sel) or
( da_i(26) and DMA_RdCE and DA_sel) or
(lnt_i(26) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(26) and DMA_RdCE and DMASR_sel) or
(bda_i(26) and DMA_RdCE and BDA_sel) or
-- (sge_i(26) and DMA_RdCE and SWCR_sel) or
(upc_i(26) and DMA_RdCE and UPC_sel) or
(pct_i(26) and DMA_RdCE and PCT_sel) or
(pwb_i(26) and DMA_RdCE and PWB_sel) or
(isr_i(26) and DMA_RdCE and ISR_sel) or
(ier_i(26) and DMA_RdCE and IER_sel) or
(ple_i(26) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(27) <=
(ver_i(27) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(27) and DMA_RdCE and DMACR_sel) or
( sa_i(27) and DMA_RdCE and SA_sel) or
( da_i(27) and DMA_RdCE and DA_sel) or
(lnt_i(27) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(27) and DMA_RdCE and DMASR_sel) or
(bda_i(27) and DMA_RdCE and BDA_sel) or
-- (sge_i(27) and DMA_RdCE and SWCR_sel) or
(upc_i(27) and DMA_RdCE and UPC_sel) or
(pct_i(27) and DMA_RdCE and PCT_sel) or
(pwb_i(27) and DMA_RdCE and PWB_sel) or
(isr_i(27) and DMA_RdCE and ISR_sel) or
(ier_i(27) and DMA_RdCE and IER_sel) or
(ple_i(27) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(28) <=
(ver_i(28) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(28) and DMA_RdCE and DMACR_sel) or
( sa_i(28) and DMA_RdCE and SA_sel) or
( da_i(28) and DMA_RdCE and DA_sel) or
(lnt_i(28) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(28) and DMA_RdCE and DMASR_sel) or
(bda_i(28) and DMA_RdCE and BDA_sel) or
-- (sge_i(28) and DMA_RdCE and SWCR_sel) or
(upc_i(28) and DMA_RdCE and UPC_sel) or
(pct_i(28) and DMA_RdCE and PCT_sel) or
(pwb_i(28) and DMA_RdCE and PWB_sel) or
(isr_i(28) and DMA_RdCE and ISR_sel) or
(ier_i(28) and DMA_RdCE and IER_sel) or
(ple_i(28) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(29) <=
(ver_i(29) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(29) and DMA_RdCE and DMACR_sel) or
( sa_i(29) and DMA_RdCE and SA_sel) or
( da_i(29) and DMA_RdCE and DA_sel) or
(lnt_i(29) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(29) and DMA_RdCE and DMASR_sel) or
(bda_i(29) and DMA_RdCE and BDA_sel) or
-- (sge_i(29) and DMA_RdCE and SWCR_sel) or
(upc_i(29) and DMA_RdCE and UPC_sel) or
(pct_i(29) and DMA_RdCE and PCT_sel) or
(pwb_i(29) and DMA_RdCE and PWB_sel) or
(isr_i(29) and DMA_RdCE and ISR_sel) or
(ier_i(29) and DMA_RdCE and IER_sel) or
(ple_i(29) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(30) <=
(ver_i(30) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(30) and DMA_RdCE and DMACR_sel) or
( sa_i(30) and DMA_RdCE and SA_sel) or
( da_i(30) and DMA_RdCE and DA_sel) or
(lnt_i(30) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(30) and DMA_RdCE and DMASR_sel) or
(bda_i(30) and DMA_RdCE and BDA_sel) or
-- (sge_i(30) and DMA_RdCE and SWCR_sel) or
(upc_i(30) and DMA_RdCE and UPC_sel) or
(pct_i(30) and DMA_RdCE and PCT_sel) or
(pwb_i(30) and DMA_RdCE and PWB_sel) or
(isr_i(30) and DMA_RdCE and ISR_sel) or
(ier_i(30) and DMA_RdCE and IER_sel) or
(ple_i(30) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(31) <=
(ver_i(31) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(31) and DMA_RdCE and DMACR_sel) or
( sa_i(31) and DMA_RdCE and SA_sel) or
( da_i(31) and DMA_RdCE and DA_sel) or
(lnt_i(31) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(31) and DMA_RdCE and DMASR_sel) or
(bda_i(31) and DMA_RdCE and BDA_sel) or
-- (sge_i(31) and DMA_RdCE and SWCR_sel) or
(upc_i(31) and DMA_RdCE and UPC_sel) or
(pct_i(31) and DMA_RdCE and PCT_sel) or
(pwb_i(31) and DMA_RdCE and PWB_sel) or
(isr_i(31) and DMA_RdCE and ISR_sel) or
(ier_i(31) and DMA_RdCE and IER_sel) or
(ple_i(31) and DMA_RdCE and PLENGTH_sel);
end if;
end process;
-- Module Identification Register 0 - 31 used
ver_i <= std_logic_vector(TO_UNSIGNED(MAJOR_VERSION , 4)) &
std_logic_vector(TO_UNSIGNED(MINOR_VERSION , 7)) &
std_logic_vector(TO_UNSIGNED(HW_SW_COMPATIBILITY_REVISION, 5)) &
std_logic_vector(TO_UNSIGNED(C_DEV_BLK_ID, 8)) &
std_logic_vector(TO_UNSIGNED(C_DMA_CHAN_TYPE(chan_num)+4, 8));
-- DMA Control Register 0 - 7 used
dcr_i <= DMACR(chan_num) & "0000000000000000000000000";
-- Source Address 0 - 31 used
sa_i <= std_logic_vector(SA(chan_num));
-- Destination Address 0 - 31 used
da_i <= std_logic_vector(DA(chan_num));
-- DMA Length 0 - 31 used
-- lnt_i <= std_logic_vector(RESIZE(LENGTH(chan_num)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
-- DMA_DWIDTH-1),DMA_DWIDTH));
lnt_i <= std_logic_vector(RESIZE(LENGTH(chan_num)(LENGTHS_LEFT to
DMA_DWIDTH-1),DMA_DWIDTH));
-- DMA Status Register 0 - 3 used
dsr_i <= dma_active(chan_num) & DBE(chan_num) & DBT(chan_num) & L(chan_num)
& sg_active(chan_num) & "000000000000000000000000000";
-- Buffer Descriptor Address 0 - 31 used
bda_i <= std_logic_vector(BDA(chan_num));
-- Software Control Register 0 - 0 used
sge_i <= SGE(chan_num) & "0000000000000000000000000000000";
-- Unserviced Packet Count 22 - 31 used
upc_i <= std_logic_vector(RESIZE(UPC(chan_num)(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1),32));
-- Packet Count Threshold 22 - 31 used
pct_i <= std_logic_vector(RESIZE(PCT(chan_num)(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1),DMA_DWIDTH));
-- Packet Wait Bound 22 - 31 used
pwb_i <= std_logic_vector(RESIZE(PWB(chan_num)(DMA_DWIDTH - PWBB to
DMA_DWIDTH - 1),DMA_DWIDTH));
-- Interrupt Status Register 24 - 31 used
isr_i <= "0000000000000000000000000" & SGEND(chan_num) & SGDA(chan_num)
& PWBR(chan_num) & PCTR(chan_num) & PD(chan_num)
& DE(chan_num) & DD(chan_num);
-- Interrupt Enable Register 24 - 31 used
ier_i <= "0000000000000000000000000" & ESGEND(chan_num) & ESGDA(chan_num)
& EPWBR(chan_num) & EPCTR(chan_num) & EPD(chan_num)
& EDE(chan_num) & EDD(chan_num);
-- ple_i <= std_logic_vector(RESIZE(PLENGTH(chan_num)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
-- DMA_DWIDTH-1),DMA_DWIDTH));
ple_i <= std_logic_vector(RESIZE(PLENGTH(chan_num)(LENGTHS_LEFT to
DMA_DWIDTH-1),DMA_DWIDTH));
--p DMA2Bus_Data <= --p
--p std_logic_vector(TO_UNSIGNED(MAJOR_VERSION , 4)) & --p
--p std_logic_vector(TO_UNSIGNED(MINOR_VERSION , 7)) & --p
--p std_logic_vector(TO_UNSIGNED(HW_SW_COMPATIBILITY_REVISION, 5)) & --p
--p std_logic_vector(TO_UNSIGNED(C_DEV_BLK_ID, 8)) & --p
--p std_logic_vector(TO_UNSIGNED(C_DMA_CHAN_TYPE(chan_num)+4, 8)) --p
--p when (RSTMIR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p DMACR(chan_num) --p
--p & "0000000000000000000000000" when ( DMACR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(SA(chan_num)) when ( SA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(DA(chan_num)) when ( DA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p LENGTH(chan_num)( --p
--p DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
--p DMA_DWIDTH-1), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when (LENGTH_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p dma_active(chan_num) -- DMA_BSY --p
--p & DBE(chan_num) --p
--p & DBT(chan_num) --p
--p & L(chan_num) --p
--p & sg_active(chan_num) -- SG_BSY --p
--p & "000000000000000000000000000" when ( DMASR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(BDA(chan_num)) when ( BDA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p SGE(chan_num) & --p
--p "0000000000000000000000000000000" when ( SWCR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p UPC(chan_num)( --p
--p DMA_DWIDTH - UPCB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p 32 --p
--p ) --p
--p ) when ( UPC_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PCT(chan_num)( --p
--p DMA_DWIDTH - UPCB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when ( PCT_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PWB(chan_num)( --p
--p DMA_DWIDTH - PWBB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when ( PWB_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "0000000000000000000000000" --p
--p & SGEND(chan_num) & SGDA(chan_num) --p
--p & PWBR(chan_num) & PCTR(chan_num) --p
--p & PD(chan_num) --p
--p & DE(chan_num) & DD(chan_num) when ( ISR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "0000000000000000000000000" --p
--p & ESGEND(chan_num) & ESGDA(chan_num) --p
--p & EPWBR(chan_num) & EPCTR(chan_num) --p
--p & EPD(chan_num) --p
--p & EDE(chan_num) & EDD(chan_num) --p
--p when ( IER_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PLENGTH(chan_num)( --p
--p DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
--p DMA_DWIDTH-1), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when (PLENGTH_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "00000000000000000000000000000000"; --p
DMA2BUS_RDACK_I_PROCESS: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = RESET_ACTIVE) then
dma2bus_rdack_i <= '0';
else
dma2bus_rdack_i <= DMA_RdCE and Bus2IP_RdReq and not dma2bus_rdack_i;
end if;
end if;
end process;
DMA2Bus_RdAck <= dma2bus_rdack_i;
---) end, Register readback
rx_cco <= rx(cco);
----------------------------------------------------------------------------
-- The below calculates the size of burst to use for the next DMA transfer
-- on the channel currently operating (cco).
----------------------------------------------------------------------------
BURST_SIZE_CALC_I0 : burst_size_calc
generic map (
C_LENGTH_WIDTH => LENGTHS_WIDTH,
C_MSTNUM_WIDTH => C_MA2SA_NUM_WIDTH,
C_DMA_BURST_SIZE => TPB,
C_BYTES_PER_SINGLE_TRANSFER => BPST,
C_DMA_SHORT_BURST_REMAINDER => C_DMA_SHORT_BURST_REMAINDER
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
LENGTH_cco => std_logic_vector(LENGTH_cco(LENGTHS_LEFT to DMA_DWIDTH-1)),
PLENGTH_cco => std_logic_vector(PLENGTH_cco(LENGTHS_LEFT to DMA_DWIDTH-1)),
Rx_cco => rx_cco,
MstNum => dma2bus_mstnum_dma_p1
);
DMA2BUS_MSTNUM_DMA_PROC : process(Bus2ip_Clk) is
begin
if Bus2ip_Clk'event and Bus2ip_Clk = '1' then
dma2bus_mstnum_dma <= dma2bus_mstnum_dma_p1;
end if;
end process;
---( Master arbitration and concentration.
MASTER_CONCENTRATION: block
begin
DMA2Bus_MstBusLock <= '0'; -- Bus-lock capability not used.
REG_MQ_PROCESS : process (Bus2IP_Clk) is
variable dma_sg_sr_pl : std_logic_vector(0 to 3);
variable Debug_TEMP : std_logic_vector(0 to C_OPB_AWIDTH-1);
variable dma2bus_addr_var : std_logic_vector(DMA2Bus_Addr'range);
constant DMA_TO_OPB_DWIDTH_FACTOR : positive
:= C_OPB_DWIDTH / DMA_DWIDTH;
constant DMA_TO_OPB_DWIDTH_FACTOR_BITS : natural
:= ceil_log2(DMA_TO_OPB_DWIDTH_FACTOR);
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
dma_sg_sr_pl := dma_sel & sg_sel & sr_sel & pl_sel;
if Bus2IP_MstLastAck = '1' then
dma2bus_addr_var := (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstWrReq <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
--ToDo, include DMA2Bus_MstBE here or, alternatively,
--consider if taking out all but WrReq and RdReq
--would be adantageous.
else
--ToDo. May want to use encoded select (regular mux) here.
case dma_sg_sr_pl is
when "1000" =>
dma2bus_addr_var := dma2bus_addr_dma;
DMA2IP_Addr <= dma2ip_addr_dma;
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_dma;
DMA2Bus_MstRdReq <= dma2bus_mstrdreq_dma;
-- These sampled because they may
if dma_sel_d1 = '0' then -- change during the transaction.
DMA2Bus_MstBurst <= or_UNSIGNED(UNSIGNED(dma2bus_mstnum_dma(
0 to dma2bus_mstnum_dma'length-2
))); --True iff dma2bus_mstnum_dma > 1
DMA2Bus_MstNum <= dma2bus_mstnum_dma;
end if;
DMA2Bus_MstLoc2Loc <= '0';
when "0100" =>
dma2bus_addr_var := dma2bus_addr_sg;
DMA2IP_Addr <= dma2ip_addr_sg;
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_sg;
DMA2Bus_MstRdReq <= dma2bus_mstrdreq_sg;
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= std_logic_vector(TO_UNSIGNED( 1, DMA2Bus_MstNum'length));
DMA2Bus_MstLoc2Loc <= '0';
when "0010" =>
dma2bus_addr_var := std_logic_vector(SRAddrFIFO_out(cco));
Debug_TEMP := C_STAT_FIFO_ADDR(cco)(
C_STAT_FIFO_ADDR(0)'length-C_OPB_AWIDTH
to
C_STAT_FIFO_ADDR(0)'length-1
);
DMA2IP_Addr <= Debug_TEMP (C_OPB_AWIDTH - 2 - C_M to
C_OPB_AWIDTH - 2 - 1);
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_sr;
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '0';
when "0001" =>
dma2bus_addr_var := C_LEN_FIFO_ADDR(cco)(
C_LEN_FIFO_ADDR(0)'length-C_OPB_AWIDTH to
C_LEN_FIFO_ADDR(0)'length-1
);
DMA2IP_Addr <= tmp_C_DMA_BASEADDR(
tmp_C_DMA_BASEADDR'length - C_M
- 2
to tmp_C_DMA_BASEADDR'length - NUM_CHAN_BITS
- RPB
- 2
- 1
)
& std_logic_vector(TO_UNSIGNED(cco, NUM_CHAN_BITS))
& std_logic_vector(TO_UNSIGNED(r_PLENGTH, RPB));
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_pl;
DMA2Bus_MstRdReq <= not dma2bus_mstwrreq_pl;
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '1';
when others =>
dma2bus_addr_var := (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstWrReq <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '0';
end case;
------------------------------------------------------------------
-- If DMA_WIDTH = C_OPB_DWIDTH or this master transaction is to
-- move DMA data, then enable all byte lanes...
------------------------------------------------------------------
DMA2Bus_MstBE <= (others => '1');
------------------------------------------------------------------
-- ... otherwise, enable only the 4 byte lanes
-- implied by the address.
------------------------------------------------------------------
if DMA_TO_OPB_DWIDTH_FACTOR > 1 and dma_sel = '0' then
for i in 0 to DMA_TO_OPB_DWIDTH_FACTOR-1 loop
if UNSIGNED(dma2bus_addr_var(
C_OPB_AWIDTH - 2 - DMA_TO_OPB_DWIDTH_FACTOR_BITS to
C_OPB_AWIDTH - 2 - 1 -- ToDo, perhaps make the 4 and
) -- 2 constants here dependent
-- on DMA_DWIDTH
) /= i
then
DMA2Bus_MstBE(4*i to 4*(i+1)-1) <= "0000";
end if;
end loop;
end if;
--
end if;
DMA2Bus_Addr <= dma2bus_addr_var;
end if; -- Bus2IP_Clk'event and Bus2IP_Clk = '1'
end process;
end block;
---) end, Master arbitration and concentration.
--- SRAddrFIFO for each rx pkt or tx pkt channel.
SRAddrFIFO_GEN: for i in 0 to LAST_CHAN generate
SRAddrFIFO_GEN: if C_DMA_CHAN_TYPE(i) = 2 or
C_DMA_CHAN_TYPE(i) = 3 generate
I_SRL_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => DMA_DWIDTH, -- ToDo, C_OPB_AWIDTH /= DMA_DWIDTH
-- would need some attention in places
-- where a data value becomes an address.
C_DEPTH => 16
)
port map (
Clk => Bus2IP_Clk,
Reset => reset(i),
FIFO_Write => wr_SRAddrFIFO(i),
Data_In => dma2bus_addr_sg,
FIFO_Read => rd_SRAddrFIFO(i),
Data_Out => SRAddrFIFO_out(i),
FIFO_Full => SRAddrFIFO_full(i),
Data_Exists => SRAddrFIFO_nonempty(i),
Addr => open
);
end generate;
-- Tie off outputs for non-existent instances.
SRAddrFIFO_TIEOFF_GEN: if C_DMA_CHAN_TYPE(i) = 0 or
C_DMA_CHAN_TYPE(i) = 1 generate
SRAddrFIFO_out(i) <= (others => '0');
SRAddrFIFO_full(i) <= '0';
SRAddrFIFO_nonempty(i) <= '0';
end generate;
end generate;
--= end, SRAddrFIFO for each rx pkt or tx pkt channel.
---( DMA state machine.
DMA_SM: block
type dma_state is (
IDLE,
DONECHK, -- Done check. Test for end of DMA operation.
XACTION, -- Perform a bus transaction.
GET_BDA,
HANDLE_SRA, -- If required, save the address of where SR will go.
GET_DMACR,
GET_SA,
GET_DA,
GET_LENGTH,
GET_PLENGTH,
PUT_LENGTH, -- Write the completion LENGTH.
PUT_DMASR, -- Write the DMA completion status.
LQCHK,
PUT_PLENGTH,
HALT,
A_WRITE_SR,
B_WRITE_SR,
C_WRITE_SR,
MSTNUM_PIPE -- Delay allowing dma2bus_mstnum_dma to get
-- through a pipe stage.
);
type dma_state_array is array(0 to LAST_CHAN) of dma_state;
signal dma_cs : dma_state_array;
signal dma_ns : dma_state;
signal block_chan_muxing : std_logic;
signal dma_sel_ns : std_logic;
signal sg_sel_ns : std_logic;
signal pl_sel_ns : std_logic;
signal sr_sel_ns : std_logic;
signal mstr_op_done : std_logic;
signal mstr_op_done_ns : std_logic;
signal wr_cond, rd_cond : std_logic; -- direction of the mem xfer
-- XGR wa F.23 bug
signal XGR_tmp : dma_state;
begin
-- XGR wa F.23 bug
XGR_tmp <= dma_cs(cco);
DMA_SM_COM_PROCESS: process(
dma_cs, dma_active, LENGTH_cco, PLENGTH_cco,
cco, rx, tx, WFIFO2DMA_Vacancy,
Bus2IP_MstWrAck, Bus2IP_MstRdAck, Mstr_sel_ma,
Bus2IP_MstError, Bus2IP_MstTimeOut, Bus2IP_MstLastAck,
dest_is_a_fifo,
first, no_bda_link, sg_active, sgGo, L_tx,
IP2DMA_TxLength_Full, IP2DMA_RxLength_Empty,
IP2DMA_TxStatus_Empty, SRAddrFIFO_nonempty,
XGR_tmp, -- XGR wa F.23 bug
SRAddrFIFO_cco_hasroom, dma_completing, dma2bus_mstnum_dma
)
variable incdec : std_logic;
variable rx_pkt_complete : std_logic;
begin
-- Default assignments for dma_ns and state machine outputs.
dma_starting <= '0';
dma_completing <= '0';
block_chan_muxing <= '0';
set_L_rx <= '0';
set_DBE <= '0';
set_DBT <= '0';
inc_SA <= '0';
inc_DA <= '0';
dec_LENGTH <= '0';
inc_PLENGTH <= '0';
dec_PLENGTH <= '0';
clr_PLENGTH <= '0';
dma_sel_ns <= '0';
sg_sel_ns <= '0';
pl_sel_ns <= '0';
sr_sel_ns <= '0';
reset_sg_offset <= '0';
inc_sg_offset <= (others => '0');
dma2bus_mstwrreq_sg <= '0';
dma2bus_mstwrreq_sr <= '0';
dma2bus_mstwrreq_pl <= '0';
mstr_op_done_ns <= '0';
update_first <= '0';
wr_SRAddrFIFO <= (others => '0');
rd_SRAddrFIFO <= (others => '0');
is_idle <= (others => '0');
rx_pkt_complete := bo2sl(rx(cco)='1' and (PLENGTH_cco=0));
-- Next state and output logic.
--case dma_cs(cco) is
case XGR_tmp is
when IDLE =>
is_idle(cco) <= '1';
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1'
or (rx_pkt_complete and SRAddrFIFO_nonempty(cco)) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= A_WRITE_SR;
else
if sgGo(cco) = '1' then
if (not rx(cco) or not IP2DMA_RxLength_Empty
or not first(cco)
) = '1' then
if (not no_bda_link(cco)) = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_BDA;
elsif (rx(cco) and first(cco)) = '1' then
pl_sel_ns <= '1';
block_chan_muxing <= '1';
reset_sg_offset <= '1';
dma_ns <= GET_PLENGTH;
else
block_chan_muxing <= '1'; -- Optional.
reset_sg_offset <= '1';
dma_ns <= HANDLE_SRA;
end if;
else
dma_ns <= IDLE;
end if;
else
if dma_active(cco) = '1' then -- Simple DMA.
dma_starting <= '1';
-- dma_ns <= DONECHK; --ToDo, rmv
dma_ns <= MSTNUM_PIPE;
else
dma_ns <= IDLE;
end if;
end if;
end if;
when GET_BDA =>
-- This implementation assumes that the Bus2IP_MstLastAck
-- is concurrent with or follows the IP2Bus_WrAck that actually
-- writes the PLENGTH register. (An earlier implementation
-- assumed the opposite order--allowing the MasterAttachment/
-- SlaveAttachment to do a posted write. When that
-- implementation actually experienced the opposite during
-- operation, then state GET_BDA's successor state,
-- GET_PLENGTH, would respond to the Bus2IP_MstLastAck
-- that corresponds to state GET_BDA!)
-- State GET_LENGTH has similar considerations.
if Bus2IP_MstLastAck = '1' then
if (rx(cco) and first(cco)) = '1' then
pl_sel_ns <= '1';
block_chan_muxing <= '1';
reset_sg_offset <= '1';
dma_ns <= GET_PLENGTH;
else
block_chan_muxing <= '1'; -- Optional.
reset_sg_offset <= '1';
dma_ns <= HANDLE_SRA;
end if;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_BDA;
end if;
when GET_PLENGTH =>
if Bus2IP_MstLastAck = '1' then
block_chan_muxing <= '1'; -- Optional.
dma_ns <= HANDLE_SRA;
else
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= GET_PLENGTH;
end if;
when HANDLE_SRA =>
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= C_WRITE_SR;
elsif ((rx(cco) or tx(cco)) and first(cco)) = '1' then
--ToDo. Does first(cco) imply (rx(cco) or tx(cco))? If so,
-- (rx(cco) or tx(cco)) could be removed here.
if (SRAddrFIFO_cco_hasroom = '1') then
wr_SRAddrFIFO(cco) <= '1';
inc_sg_offset(cco) <= '1';
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_DMACR;
else
dma_ns <= HANDLE_SRA;
end if;
else
inc_sg_offset(cco) <= '1';
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_DMACR;
end if;
when GET_DMACR =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_SA;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_DMACR;
end if;
when GET_SA =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_DA;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_SA;
end if;
when GET_DA =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_LENGTH;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_DA;
end if;
when GET_LENGTH =>
if Bus2IP_MstLastAck = '1' then
-- See the comment of state GET_ BDA for considerations
-- that also apply to this state. The load of the LENGTH
-- register needs be complete before proceeding to the
-- next state. (A "MstLastAck" indication ahead of the
-- completion of a posted write will not work. An earlier
-- version had such posted write behavior. In that version,
-- this state was not exited until the LENGTH register
-- actually loaded; signal load_length(cco) was used.)
dma_starting <= '1';
-- dma_ns <= DONECHK; --ToDo, rmv
dma_ns <= MSTNUM_PIPE;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_LENGTH;
end if;
when MSTNUM_PIPE =>
block_chan_muxing <= '1';
dma_ns <= DONECHK;
when DONECHK =>
dma_completing <= bo2sl(LENGTH_cco = 0) or rx_pkt_complete;
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= B_WRITE_SR;
elsif dma_completing = '1' then
set_L_rx <= rx_pkt_complete;
if sg_active(cco) = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= PUT_LENGTH;
else
dma_ns <= IDLE;
end if;
elsif
-- We go to do a bus transaction when we are not at the normal
-- end of a DMA operation and there is not a condition
-- that keeps us from proceeding.
-- The condition that could keep us from proceeding is that
-- we are writing to a FIFO and it doesn't have vacancy
-- to (1) accomodate a single transfer in the case there isn't
-- enough left to do a burst or, otherwise, to (2) accomodate
-- a burst.
( dma_completing = '0'
and not ( (dest_is_a_fifo = '1')
and ( TO_INTEGER(UNSIGNED(dma2bus_mstnum_dma))
> TO_INTEGER(UNSIGNED(WFIFO2DMA_Vacancy))
)
)
) then
dma_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= XACTION;
else
-- dma_ns <= DONECHK; --ToDo, rmv
dma_ns <= MSTNUM_PIPE;
end if;
when XACTION =>
incdec :=
(Bus2IP_MstWrAck or Bus2IP_MstRdAck) and Mstr_sel_ma;
inc_SA <= incdec;
inc_DA <= incdec;
dec_LENGTH <= incdec;
inc_PLENGTH <= incdec and tx(cco);
dec_PLENGTH <= incdec and rx(cco);
if (Bus2IP_MstError or Bus2IP_MstTimeOut) = '1' then
set_DBE <= Bus2IP_MstError;
set_DBT <= Bus2IP_MstTimeOut;
dma_completing <= '1';
if sg_active(cco) = '1' then
dma_ns <= HALT;
else
dma_ns <= IDLE;
end if;
elsif (Bus2IP_MstLastAck) = '1' then
--block_chan_muxing <= '1'; -- Optional, no blocking for
-- find-grain switching
-- between channels.
-- dma_ns <= DONECHK; --ToDo, rmv
dma_ns <= MSTNUM_PIPE;
else
dma_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= XACTION;
end if;
when PUT_LENGTH =>
dma2bus_mstwrreq_sg <= '1';
if Bus2IP_MstLastAck = '1' then
block_chan_muxing <= '1';
sg_sel_ns <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= PUT_DMASR;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= PUT_LENGTH;
end if;
when PUT_DMASR =>
dma2bus_mstwrreq_sg <= '1';
if Bus2IP_MstLastAck = '1' then
inc_sg_offset(cco) <= '1';
dma_ns <= LQCHK;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= PUT_DMASR;
end if;
when LQCHK =>
update_first <= '1';
if (not tx(cco) or not L_tx(cco)) = '1' then
dma_ns <= IDLE;
elsif (not IP2DMA_TXLength_Full) = '1' then
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= PUT_PLENGTH;
else
dma_ns <= LQCHK;
end if;
when PUT_PLENGTH =>
dma2bus_mstwrreq_pl <= '1';
if Bus2IP_MstLastAck = '1' then
clr_PLENGTH <= '1';
dma_ns <= IDLE;
else
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= PUT_PLENGTH;
end if;
when HALT =>
dma_ns <= HALT;
when A_WRITE_SR =>
is_idle(cco) <= '1';
--ToDo. Perhaps can eliminate this sig and drive dma2bus_mstwrreq to '1' when sr_sel
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
dma_ns <= IDLE;
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= A_WRITE_SR;
end if;
when B_WRITE_SR =>
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
block_chan_muxing <= '1';
dma_ns <= DONECHK; -- DONECHK okay here as long as
-- chan_muxing is blocked leaving this state.
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= B_WRITE_SR;
end if;
when C_WRITE_SR =>
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
block_chan_muxing <= '1';
dma_ns <= HANDLE_SRA;
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= C_WRITE_SR;
end if;
end case;
end process;
DMA_SM_DMA_CS_REG_PROCESS: process(Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if reset(i) = '1' then
dma_cs(i) <= IDLE;
elsif cco = i then
dma_cs(i) <= dma_ns;
end if;
end if;
end loop;
end process;
DMA_SM_OTHER_REG_PROCESS: process(Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset='1' then
dma_sel <= '0';
sg_sel <= '0';
pl_sel <= '0';
sr_sel <= '0';
mstr_op_done <= '0';
cco <= 0;
else
dma_sel <= dma_sel_ns;
sg_sel <= sg_sel_ns;
pl_sel <= pl_sel_ns;
sr_sel <= sr_sel_ns;
mstr_op_done <= mstr_op_done_ns;
if block_chan_muxing = '0' then
if cco = LAST_CHAN then
cco <= 0;
else
cco <= cco+1;
end if;
end if;
end if;
end if;
end process;
DMA_SEL_D1_PROC: process(Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset='1' then
dma_sel_d1 <= '1';
else
dma_sel_d1 <= dma_sel;
end if;
end if;
end process;
wr_cond <= SLOCAL(cco) and not DLOCAL(cco);
rd_cond <= DLOCAL(cco) and not SLOCAL(cco);
dma2bus_addr_dma <= std_logic_vector(SA(cco)) when rd_cond = '1' else
std_logic_vector(DA(cco));
dma2ip_addr_dma <= std_logic_vector(DA(cco)(DMA_DWIDTH-2-C_M to
DMA_DWIDTH-2-1))
when rd_cond = '1'
else
std_logic_vector(SA(cco)(DMA_DWIDTH-2-C_M to
DMA_DWIDTH-2-1));
dma2bus_mstwrreq_dma <= wr_cond;
dma2bus_mstrdreq_dma <= rd_cond;
-- burst_cond_dma <= bo2sl(C_DMA_ALLOW_BURST) and
-- ( (rx(cco) and PLENGTH_ge_BPBT and LENGTH_ge_BPBT)
-- or (not rx(cco) and LENGTH_ge_BPBT)
-- );
-- Note for burst_cond_dma: We pass up the opportunity to include
-- in a burst a last word that has padding and whose padding would
-- bring the total to exactly BPBT. This allows a simpler test.
-- For example, with BPBT = 32, we use a "length" >= 32 test, and
-- we are passing up optimization of the 29, 30 and 31 cases
-- in order to have a simpler test.
SG_ACTIVE_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if reset(i) = '1' then
sg_active(i) <= '0';
sg_active_d1(i) <= '0';
else
sg_active_d1(i) <= sg_active(i);
if (SGE(i) and not SGS(i)) = '1' then
sg_active(i) <= '1';
elsif is_idle(i) = '1'
and ( ( C_DMA_CHAN_TYPE(i) /=2
and C_DMA_CHAN_TYPE(i) /=3
)
or ( SRAddrFIFO_nonempty(i) = '0'
and first(i) = '1'
)
) then
sg_active(i) <= '0';
end if;
end if;
end loop;
end if;
end process;
end block;
---) end, DMA state machine.
--- SG MQ bundle.
SG_SM: block
begin
dma2bus_addr_sg <= std_logic_vector(
BDA(cco)(0 to BDA(cco)'length - 2 - 1)
+ sg_offset(cco)
) & "00";
dma2ip_addr_sg <= tmp_C_DMA_BASEADDR(
tmp_C_DMA_BASEADDR'length - 2
- C_M
to tmp_C_DMA_BASEADDR'length - 2
- NUM_CHAN_BITS
- RPB
- 1
)
& std_logic_vector(TO_UNSIGNED(cco, NUM_CHAN_BITS))
& std_logic_vector(sg_offset(cco));
dma2bus_mstrdreq_sg <= not dma2bus_mstwrreq_sg;
end block;
--= end, SG MQ bundle.
end sim; --)
| bsd-3-clause | 6402e19f2c2f09769ff4cb6cb65a57ea | 0.442486 | 3.821735 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/dma_sg_pkg.vhd | 2 | 6,149 | -------------------------------------------------------------------------------
-- $Id: dma_sg_pkg.vhd,v 1.2 2003/02/26 00:12:08 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg_pkg.vhd - package
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_pkg.vhd
--
-- Description: This package contains types, constants and functions that
-- support the DMA/Scatter Gather IP block (entity dma_sg).
--
-------------------------------------------------------------------------------
-- Structure: No dependencies.
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 04/24/01 -- First version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dma_sg_pkg is
--ToDo, remove these two types
type NATURAL_VECTOR is array (natural range <>) of natural;
type BOOLEAN_VECTOR is array (natural range <>) of boolean;
constant UPCB : natural := 10; -- The number of bits implemented in UPC.
constant PWBB : natural := 10; -- The number of bits implemented in PWB.
-- Word offsets of registers from the channel register base addr.
constant r_RSTMIR : natural := 0;
constant r_DMACR : natural := 1;
constant r_SA : natural := 2;
constant r_DA : natural := 3;
constant r_LENGTH : natural := 4;
constant r_DMASR : natural := 5;
constant r_BDA : natural := 6;
constant r_SWCR : natural := 7;
constant r_UPC : natural := 8;
constant r_PCT : natural := 9;
constant r_PWB : natural :=10;
constant r_ISR : natural :=11;
constant r_IER : natural :=12;
constant r_PLENGTH : natural :=15;
-- Word offsets of fields in the Buffer Descriptor.
constant bd_SR : natural := 0;
constant bd_DMACR : natural := 1;
constant bd_SA : natural := 2;
constant bd_DA : natural := 3;
constant bd_LENGTH : natural := 4;
constant bd_DMASR : natural := 5;
constant bd_BDA : natural := 6;
-- Bit numbers.
constant b_BSY : natural := 0;
constant b_SINC : natural := 0;
constant b_DINC : natural := 1;
constant b_SLOCAL : natural := 2;
constant b_DLOCAL : natural := 3;
constant b_SGS : natural := 4;
constant b_L_dmacr: natural := 6;
constant b_L_dmasr: natural := 3;
constant b_SGE : natural := 0;
constant b_DD : natural :=31;
constant b_DE : natural :=30;
constant b_PD : natural :=29;
constant b_PCTR : natural :=28;
constant b_PWBR : natural :=27;
constant b_SGDA : natural :=26;
constant b_SGEND : natural :=25;
-- Conversion of a boolean scalar to a std_logic scalar.
function bo2sl(b: boolean) return std_logic;
-- Returns the base 2 logarithm of n, rounded up, if non-integral,
-- to the next integer.
function ceil_log2(n : natural) return natural;
-- Returns the the value, i, for which (2**i)*base_period
-- is closest to target_period.
function Div_Stages(base_period, target_period: natural) return natural;
end;
package body dma_sg_pkg is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
function ceil_log2(n : natural) return natural is
variable m : natural := 0;
variable nn : natural := n;
variable some_non_even : boolean := false;
begin
while nn /= 1 loop
m := m+1;
some_non_even := some_non_even or (nn rem 2)/=0;
nn := nn / 2;
end loop;
if some_non_even then m := m+1; end if;
return m;
end ceil_log2;
function Div_Stages(base_period, target_period: natural) return natural is
variable i: natural;
variable t: natural;
begin
assert base_period <= target_period
report "Div_Stages: base_period is not <= target_period, as required."
severity failure;
i := 0; t := base_period;
while t <= target_period loop
i := i + 1;
t := 2*t; -- t = (2**i)*base_period
end loop;
-- Pick either i or i-1 as the number of stages to give a power-or-2
-- division of 1/base_period that gives the value closest to
-- 1/target_period.
if t - target_period < target_period - t/2 then
return i;
else
return i-1;
end if;
end Div_Stages;
end;
| bsd-3-clause | 5add5c6f7ac6bf2fc7bb84df8c2ed337 | 0.477639 | 4.261261 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/ipif_pkg.vhd | 3 | 43,475 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.6 2003/10/22 16:00:27 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
--constant EXCLUDE_DEV_ISC : integer := 0;
-- -- 1 specifies that only the global interrupt
-- -- enable is present in the device interrupt source
-- -- controller and that the only source of interrupts
-- -- in the device is the IP interrupt source controller.
-- -- 0 specifies that the full device interrupt
-- -- source controller structure will be included.
--constant INCLUDE_DEV_PENCODER : integer := 1;
---- -- 1 will include the Device IID in the device interrupt
---- -- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
end package body ipif_pkg;
| bsd-3-clause | 55266a6ac5112707ff2fea239142b7b4 | 0.492421 | 4.878254 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_hwti_v3_00_a/hdl/vhdl/opb_hwti.vhd | 2 | 37,802 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- opb_hwti.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: opb_hwti.vhd
-- Version: 2.00.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Mon Aug 15 10:20:24 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
library fsl_v20_v2_11_c;
use fsl_v20_v2_11_c.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
-- M_ABus -- Master address bus
-- M_BE -- Master byte enables
-- M_busLock -- Master buslock
-- M_request -- Master bus request
-- M_RNW -- Master read, not write
-- M_select -- Master select
-- M_seqAddr -- Master sequential address
-- OPB_errAck -- OPB error acknowledge
-- OPB_MGrant -- OPB bus grant
-- OPB_retry -- OPB bus cycle retry
-- OPB_timeout -- OPB timeout error
-- OPB_xferAck -- OPB transfer acknowledge
------------------------------------------------------------------------------
entity opb_hwti is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector(0 to 31) := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7600_0000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"6300_0000";
C_HIGHADDR : std_logic_vector := X"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
OPBintrfc2thrd_value : out std_logic_vector(0 to 31);
OPBintrfc2thrd_function : out std_logic_vector(0 to 15);
OPBintrfc2thrd_goWait : out std_logic;
OPBthrd2intrfc_address : out std_logic_vector(0 to 31);
OPBthrd2intrfc_value : out std_logic_vector(0 to 31);
OPBthrd2intrfc_function : out std_logic_vector(0 to 15);
OPBthrd2intrfc_opcode : out std_logic_vector(0 to 5);
OPBM_ABus : out std_logic_vector(0 to 31);
OPBM_request :out std_logic;
OPBM_MGrant : out std_logic;
OPBM_xferAck : out std_logic;
OPBM_select : out std_logic ;
OPBtimer : out std_logic_vector(0 to 31);
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
FSL2_S_Read : out std_logic;
FSL2_S_Data : in std_logic_vector(0 to 31);
FSL2_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_hwti;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of opb_hwti is
component user_logic_hwti is
generic (
C_BASEADDR : std_logic_vector := X"6300_0000";
C_HIGHADDR : std_logic_vector := X"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector(0 to 31) := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7600_0000"
);
port
(
OPBtimer : out std_logic_vector(0 to 31);
--CONTROL : in STD_LOGIC_VECTOR(35 DOWNTO 0);
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Clk : in std_logic;
Bus2IP_CS : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_RdCE : in std_logic_vector(0 to 3);
Bus2IP_Reset : in std_logic;
Bus2IP_WrCE : in std_logic_vector(0 to 3);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Ack : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
IP2Bus_Error : out std_logic;
IP2Bus_PostedWrInh : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_ToutSup : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to 31);
IP2Bus_MstBE : out std_logic_vector(0 to 3);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to 31);
intrfc2thrd : out std_logic_vector(0 to 63);
thrd2intrfc : in std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic
);
end component user_logic_hwti;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_MASTER : integer := USER_10;
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_MASTER -- user logic master space (ip master model registers)
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR;
-- constant MASTER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant MASTER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & MASTER_BASEADDR, -- user logic master space base address
ZERO_ADDR_PAD & MASTER_HIGHADDR -- user logic master space high address
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic master space data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_MASTER_CE : integer := 4;
constant USER_NUM_CE : integer := USER_NUM_MASTER_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_MASTER_CE) -- number of chip enables for user logic master space (one per register)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic master space dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify number of chip selects for user logic slave/master spaces.
constant USER_NUM_CS : integer := 1;
constant USER_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_MASTER);
-- specify index for user logic slave/master spaces chip enable.
constant USER_MASTER_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_MASTER));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2Bus_PostedWrInh : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal iBus2IP_RNW : std_logic;
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_CS-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
-- HWTI to HWTUL interconnect
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal internal_M_ABus : std_logic_vector(0 to 31);
signal internal_M_request : std_logic;
signal internal_M_select : std_logic;
signal internal_M_RNW : std_logic;
begin
OPBM_ABus <= internal_M_ABus ;
OPBM_request <= internal_M_request;
OPBM_select <= internal_M_RNW;
OPBM_MGrant <= OPB_MGrant;
OPBM_xferAck <= OPB_xferAck;
M_RNW <= internal_M_RNW;
M_ABus <= internal_M_ABus ;
M_request <= internal_M_request;
M_select <= internal_M_select;
OPBintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
OPBintrfc2thrd_function <= intrfc2thrd (32 to 47);
OPBintrfc2thrd_goWait <= intrfc2thrd (48) ;
OPBthrd2intrfc_address <= thrd2intrfc (32 to 63);
OPBthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
OPBthrd2intrfc_function <= thrd2intrfc (64 to 79);
OPBthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
--=======================================================
thrd2intrfc <= FSL0_S_Data & FSL1_S_Data &FSL2_S_Data;
FSL0_M_Data <= intrfc2thrd(0 to 31);
FSL1_M_Data <= intrfc2thrd(32 to 63);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full ;
exist <= FSL0_S_Exists and FSL1_S_Exists and FSL2_S_Exists;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL2_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => internal_M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => internal_M_request,
Mn_busLock => M_busLock,
Mn_select => internal_M_select,
Mn_RNW => internal_M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_HWTI_I : user_logic_hwti
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_THREAD_MANAGER_BADDR => C_THREAD_MANAGER_BADDR,
C_MUTEX_MANAGER_BADDR => C_MUTEX_MANAGER_BADDR,
C_CONVAR_MANAGER_BADDR => C_CONVAR_MANAGER_BADDR
)
port map
(
OPBtimer => OPBtimer,
--CONTROL => CONTROL ,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS(0),
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh,
IP2Bus_Ack => iIP2Bus_Ack,
-- IP2Bus_RdAck => iIP2Bus_RdAck,
-- IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_CS <= iBus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_CS-1);
uBus2IP_RdCE(0 to USER_NUM_MASTER_CE-1) <= iBus2IP_RdCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
uBus2IP_WrCE(0 to USER_NUM_MASTER_CE-1) <= iBus2IP_WrCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
iIP2Bus_RdAck <= iIP2Bus_Ack and iBus2IP_RNW;
iIP2Bus_WrAck <= iIP2Bus_Ack and (not iBus2IP_RNW);
end IMP;
| bsd-3-clause | c71b1e14ba7b7cf66c1ed2c962c214b5 | 0.511507 | 4.071736 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/common/disdram.vhd | 1 | 1,166 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
entity disdram is
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end disdram;
architecture arch_disdram of disdram is
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
(Dwidth-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_ramstyle of mem : signal is "select_ram";
begin
wr: process( clk )
begin
if rising_edge(clk) then
if WE = '1' then
mem(conv_integer(A)) <= D;
end if;
end if;
end process wr;
DPO <= mem(conv_integer(DPRA));
rd : process(clk)
begin
if rising_edge(clk) then
QDPO <= mem(conv_integer(DPRA));
end if;
end process;
end arch_disdram;
| gpl-2.0 | cd63343e0a0c1c0fc0267e7d9a5170a1 | 0.645798 | 2.857843 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd | 2 | 13,746 |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
| bsd-3-clause | 72702ed8bd32c7ce5d267e6eef43baa8 | 0.410592 | 5.189128 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/mutex_store.vhd | 11 | 7,532 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity mutex_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
miaddr : in std_logic_vector(0 to C_MWIDTH-1);
miena : in std_logic;
miwea : in std_logic;
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
mikind : in std_logic_vector(0 to 1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mokind : out std_logic_vector(0 to 1);
mocount : out std_logic_vector(0 to C_CWIDTH-1)
);
end mutex_store;
architecture behavioral of mutex_store is
-- Calculate the number of mutexes to use
constant MUTEXES : integer := pow2( C_MWIDTH );
-- Constant for the last position to be reset
constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1');
-- Calculate the beginning and ending bit positions for data
constant OWN_SRT : integer := 0;
constant OWN_END : integer := OWN_SRT + C_TWIDTH-1;
constant NXT_SRT : integer := OWN_END+1;
constant NXT_END : integer := NXT_SRT + C_TWIDTH-1;
constant LST_SRT : integer := NXT_END+1;
constant LST_END : integer := LST_SRT + C_TWIDTH-1;
constant KND_SRT : integer := LST_END+1;
constant KND_END : integer := KND_SRT + 1;
constant CNT_SRT : integer := KND_END + 1;
constant CNT_END : integer := CNT_SRT + C_CWIDTH-1;
-- Declare a storage area for the mutex data
type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Declare signals for the mutex storage area
signal store : mstore;
signal mena : std_logic;
signal mwea : std_logic;
signal maddr : std_logic_vector(0 to C_MWIDTH-1);
signal minput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rena : std_logic;
signal rwea : std_logic;
signal rst_cs : rststate;
signal raddr : std_logic_vector(0 to C_MWIDTH-1);
signal raddrn : std_logic_vector(0 to C_MWIDTH-1);
signal rowner : std_logic_vector(0 to C_TWIDTH-1);
signal rnext : std_logic_vector(0 to C_TWIDTH-1);
signal rlast : std_logic_vector(0 to C_TWIDTH-1);
signal rkind : std_logic_vector(0 to 1);
signal rcount : std_logic_vector(0 to C_CWIDTH-1);
begin
moowner <= moutput(OWN_SRT to OWN_END);
monext <= moutput(NXT_SRT to NXT_END);
molast <= moutput(LST_SRT to LST_END);
mokind <= moutput(KND_SRT to KND_END);
mocount <= moutput(CNT_SRT to CNT_END);
mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount,
miena,miwea,miaddr,miowner,milast,mikind,micount) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
mena <= rena;
mwea <= rwea;
maddr <= raddr;
minput <= rowner & rnext & rlast & rkind & rcount;
else
mena <= miena;
mwea <= miwea;
maddr <= miaddr;
minput <= miowner & minext & milast & mikind & micount;
end if;
end if;
end process mutex_mux;
mutex_reset_controller : process(clk,rst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process mutex_reset_controller;
mutex_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rowner <= (others => '0');
rnext <= (others => '0');
rlast <= (others => '0');
rkind <= (others => '0');
rcount <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process mutex_reset_logic;
mutex_store_controller : process (clk) is
begin
if( rising_edge(clk) ) then
if( mena = '1' ) then
if( mwea = '1' ) then
store( conv_integer(maddr) ) <= minput;
end if;
moutput <= store( conv_integer(maddr) );
end if;
end if;
end process mutex_store_controller;
end behavioral;
| bsd-3-clause | 18f1576d38df125f699ca3cf017d83b1 | 0.561073 | 3.898551 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_mailbox.vhd | 1 | 8,063 | --------------------------------------------------------------------------------
-- Title : VME-Mailbox Control
-- Project : A15b
--------------------------------------------------------------------------------
-- File : vme_mailbox.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 08/04/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- In order to send messages on the VMEbus without using the slow interrupt
-- daisy chain, the Mailbox feature can be used. By writing and/or reading one
-- of the Mailbox Data Registers from VME-side, a local CPU interrupt can be
-- generated (signaled via mailbox_irq to WBB).
-- Due to the location of the data registers in the local SRAM (0x FF800..
-- 0x FF80c), normal A24/A32 accesses can be used in contrast to the slow daisy
-- chain mechanism.
-- Four independent 32 bit Mailbox Data Registers are supported, which can be
-- configured to cause an interrupt request upon read or write or both.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- top_a15
-- vme_ctrl
-- vme_mailbox
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_mailbox.vhd,v $
-- Revision 1.2 2012/11/12 08:13:06 MMiehling
-- bugfix mailbox: now evaluation of addresses only when access is active
--
-- Revision 1.1 2012/03/29 10:14:37 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:28:52 MMiehling
-- wrong decoding of mailbox address => spurious interrupts
--
-- Revision 1.1 2005/10/28 17:51:01 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:29:22 mmiehling
-- improved timing and area
--
-- Revision 1.3 2003/12/01 10:03:09 MMiehling
-- adopted to changed vme_adr timing
--
-- Revision 1.2 2003/06/13 10:06:14 MMiehling
-- corrected address mapping
--
-- Revision 1.1 2003/04/22 11:07:26 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_mailbox IS
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- slave access address type (sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64)
wbm_adr_o : IN std_logic_vector(19 DOWNTO 2); -- mensb master adress lines
wbm_we_o : IN std_logic; -- mensb master read/write
mensb_mstr_req : IN std_logic; -- mensb master request
ram_acc : IN std_logic; -- external ram access
mail_irq : OUT std_logic_vector(7 DOWNTO 0) -- mailbox interrupt requests (flags)
);
END vme_mailbox;
ARCHITECTURE vme_mailbox_arch OF vme_mailbox IS
CONSTANT mail_0_adr : std_logic_vector(3 DOWNTO 2):="00"; -- 0x800
CONSTANT mail_1_adr : std_logic_vector(3 DOWNTO 2):="01"; -- 0x804
CONSTANT mail_2_adr : std_logic_vector(3 DOWNTO 2):="10"; -- 0x808
CONSTANT mail_3_adr : std_logic_vector(3 DOWNTO 2):="11"; -- 0x80c
CONSTANT mail_offset_adr : std_logic_vector(19 DOWNTO 4):=x"ff80"; -- 0xFF800
-- mailbox is accessible from:
-- PCI: SRAM-offset + 0xFF800
-- A24/A32: 0xFF800
-- A16: 0x800
SIGNAL equal : std_logic_vector(5 DOWNTO 0);
SIGNAL mail_hit : std_logic_vector(3 DOWNTO 0);
SIGNAL a24_a32_mode : std_logic;
SIGNAL a16_mode : std_logic;
BEGIN
equal(5) <= '1' WHEN wbm_adr_o(19 DOWNTO 12) = mail_offset_adr(19 DOWNTO 12) ELSE '0'; -- offset is needed for A24 access
equal(4) <= '1' WHEN wbm_adr_o(11 DOWNTO 4) = mail_offset_adr(11 DOWNTO 4) ELSE '0'; -- offset is not needed for A16 access
equal(3) <= '1' WHEN wbm_adr_o(3 DOWNTO 2) = mail_3_adr ELSE '0';
equal(2) <= '1' WHEN wbm_adr_o(3 DOWNTO 2) = mail_2_adr ELSE '0';
equal(1) <= '1' WHEN wbm_adr_o(3 DOWNTO 2) = mail_1_adr ELSE '0';
equal(0) <= '1' WHEN wbm_adr_o(3 DOWNTO 2) = mail_0_adr ELSE '0';
a24_a32_mode <= sl_acc(3) OR sl_acc(2);
a16_mode <= sl_acc(4);
mail : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mail_irq <= (OTHERS => '0');
mail_hit <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF mensb_mstr_req = '1' AND ram_acc = '1' THEN
IF a24_a32_mode = '1' AND equal(3) = '1' AND equal(4) = '1' AND equal(5) = '1' THEN -- A24 or A32
mail_hit(3) <= '1';
ELSIF a16_mode = '1' AND equal(3) = '1' AND equal(4) = '1' THEN -- A16
mail_hit(3) <= '1';
ELSE
mail_hit(3) <= '0';
END IF;
IF a24_a32_mode = '1' AND equal(2) = '1' AND equal(4) = '1' AND equal(5) = '1' THEN -- A24 or A32
mail_hit(2) <= '1';
ELSIF a16_mode = '1' AND equal(2) = '1' AND equal(4) = '1' THEN -- A16
mail_hit(2) <= '1';
ELSE
mail_hit(2) <= '0';
END IF;
IF a24_a32_mode = '1' AND equal(1) = '1' AND equal(4) = '1' AND equal(5) = '1' THEN -- A24 or A32
mail_hit(1) <= '1';
ELSIF a16_mode = '1' AND equal(1) = '1' AND equal(4) = '1' THEN -- A16
mail_hit(1) <= '1';
ELSE
mail_hit(1) <= '0';
END IF;
IF a24_a32_mode = '1' AND equal(0) = '1' AND equal(4) = '1' AND equal(5) = '1' THEN -- A24 or A32
mail_hit(0) <= '1';
ELSIF a16_mode = '1' AND equal(0) = '1' AND equal(4) = '1' THEN -- A16
mail_hit(0) <= '1';
ELSE
mail_hit(0) <= '0';
END IF;
ELSE
mail_hit <= (OTHERS => '0');
END IF;
IF mensb_mstr_req = '1' AND ram_acc = '1' THEN
IF mail_hit(0) = '1' THEN
mail_irq(0) <= NOT wbm_we_o;
mail_irq(1) <= wbm_we_o;
ELSE
mail_irq(0) <= '0';
mail_irq(1) <= '0';
END IF;
IF mail_hit(1) = '1' THEN
mail_irq(2) <= NOT wbm_we_o;
mail_irq(3) <= wbm_we_o;
ELSE
mail_irq(2) <= '0';
mail_irq(3) <= '0';
END IF;
IF mail_hit(2) = '1' THEN
mail_irq(4) <= NOT wbm_we_o;
mail_irq(5) <= wbm_we_o;
ELSE
mail_irq(4) <= '0';
mail_irq(5) <= '0';
END IF;
IF mail_hit(3) = '1' THEN
mail_irq(6) <= NOT wbm_we_o;
mail_irq(7) <= wbm_we_o;
ELSE
mail_irq(6) <= '0';
mail_irq(7) <= '0';
END IF;
ELSE
mail_irq <= (OTHERS => '0');
END IF;
END IF;
END PROCESS mail;
END vme_mailbox_arch;
| gpl-3.0 | 2588d3cd1c960fe2b9f9b9dbcaa171ca | 0.495845 | 3.505652 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_init_1.vhd | 2 | 15,324 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = mutex->num
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 3adf0f1ea6b47a7dcde9396a3193861e | 0.538567 | 3.841564 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd | 4 | 18,741 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v3_00_a for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| bsd-3-clause | 10686a24f06b6541ef91392b993ad0cd | 0.466837 | 4.641159 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/exit_1.vhd | 2 | 21,281 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: exit_stress_1.c
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * function
-- reg4 = thread
-- reg5 = i
-- reg6 = joinReturn
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
reg5_next <= Z32;
next_state <= STATE_6;
when STATE_6 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_7;
else
next_state <= STATE_13;
end if;
when STATE_7 =>
next_state <= STATE_8;
-- createReturn == hthread_create( &(data->threads[i]), NULL, data->function, NULL );
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &( data->threads[i] )
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- increment i
reg5_next <= reg5 + x"00000001";
-- END OF FOR LOOP
-- int joinValue
when STATE_13 =>
-- declare 4B on stack to hold joinValue
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- get the address of joinValue
thrd2intrfc_opcode <= OPCODE_ADDRESS;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_15 =>
reg6_next <= intrfc2thrd_address;
reg5_next <= Z32;
next_state <= STATE_16;
when STATE_16 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_17;
else
next_state <= STATE_25;
end if;
-- hthread_join( data->thread[i], &joinValue );
when STATE_17 =>
-- read the value of data->thread[i]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
reg4_next <= intrfc2thrd_value;
-- push &joinValue
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- push thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- if ( joinValue == data->thread[i] )
-- *(data->numberOfTestsCompleted) += 1;
when STATE_21 =>
--read the value of joinValue
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
if ( intrfc2thrd_value = reg4 ) then
next_state <= STATE_23;
else
next_state <= STATE_16;
end if;
reg5_next <= reg5 + x"00000001";
when STATE_23 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_25 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 1549a352ece2de4e8427173da5771546 | 0.549363 | 3.685022 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux_blk.vhd | 3 | 5,669 | -------------------------------------------------------------------------------
-- $Id: ip2bus_srmux_blk.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux_blk.vhd - VHD design file
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux_blk.vhd
--
-- Description: VHDL design file that is a wrapper around the IPIF status
-- reply MUX design.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ip2bus_srmux_blk.vhd
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
--
-- History:
-- DET Aug 21, 2001 -- First version adapted from Visual HDL output
-- LCW Nov 8, 2004 -- updated for NCSim
--
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ip2bus_srmux;
entity ip2bus_srmux_blk is
port (
DMA2Bus_Error : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_ToutSup : in std_logic;
DMA2Bus_WrAck : in std_logic;
Intr2Bus_Error : in std_logic;
Intr2Bus_RdAck : in std_logic;
Intr2Bus_Retry : in std_logic;
Intr2Bus_ToutSup : in std_logic;
Intr2Bus_WrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_ToutSup_mx : out std_logic;
IP2Bus_WrAck : in std_logic;
IP2Bus_WrAck_mx : out std_logic;
RFIFO_Error : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_ToutSup : in std_logic;
RFIFO_WrAck : in std_logic;
Rst2Bus_Error : in std_logic;
Rst2Bus_RdAck : in std_logic;
Rst2Bus_Retry : in std_logic;
Rst2Bus_ToutSup : in std_logic;
Rst2Bus_WrAck : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_ToutSup : in std_logic;
WFIFO_WrAck : in std_logic
);
end ip2bus_srmux_blk;
architecture implementation of ip2bus_srmux_blk is
begin
I_IP2BUS_SRMUX: entity opb_ipif_v2_00_h.ip2bus_srmux
port map (
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_ToutSup => IP2Bus_ToutSup,
WFIFO_WrAck => WFIFO_WrAck,
WFIFO_RdAck => WFIFO_RdAck,
WFIFO_Retry => WFIFO_Retry,
WFIFO_Error => WFIFO_Error,
WFIFO_ToutSup => WFIFO_ToutSup,
RFIFO_WrAck => RFIFO_WrAck,
RFIFO_RdAck => RFIFO_RdAck,
RFIFO_Retry => RFIFO_Retry,
RFIFO_Error => RFIFO_Error,
RFIFO_ToutSup => RFIFO_ToutSup,
DMA2Bus_WrAck => DMA2Bus_WrAck,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
IRPT_WrAck => Intr2Bus_WrAck,
IRPT_RdAck => Intr2Bus_RdAck,
IRPT_Retry => Intr2Bus_Retry,
IRPT_Error => Intr2Bus_Error,
IRPT_ToutSup => Intr2Bus_ToutSup,
RESET_WrAck => Rst2Bus_WrAck,
RESET_RdAck => Rst2Bus_RdAck,
RESET_Retry => Rst2Bus_Retry,
RESET_Error => Rst2Bus_Error,
RESET_ToutSup => Rst2Bus_ToutSup,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx);
end implementation;
| bsd-3-clause | 96170c75fedf0e85af730ba552512c46 | 0.452461 | 4.104996 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_dgen.vhd | 1 | 4,693 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF FiFo512Core32W32R_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 4831e47d7fb374db15c5e9b0d59a9894 | 0.588749 | 4.063203 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/pcie_msi.vhd | 1 | 15,284 | --------------------------------------------------------------------------------
-- Title : Interrupt request logic for processing MSI
-- Project :
--------------------------------------------------------------------------------
-- File : pcie_msi.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/02/12
--------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
--
-- Interrupt request handler for processing legacy and MSI on
-- PCIe Altera.
-- Each interrupt request signal of the toplevel should be
-- connected to the irq_req vector. The generic WIDTH controls
-- the max size, which should be identical or less than the
-- setting in the PCIe core.
-- If wb_int_num_allowed is smaller than the WIDTH of the irq_req
-- vector, legacy interrupts are selected. This is also when
-- the SW does not enable the MSI capability (wb_int_num_allowed=0).
-- Else if wb_int_num_allowed greater or equal the WIDTH of the
-- irq_req vector, MSI is selected.
-- MSI:
-- The handler triggers the PCIe core interface each time if a
-- rising edge was detected on either bit of the irq_req vector
-- (interrupt request got active). This will trigger the PCIe
-- to send a MSI packet to the CPU, with a vector number equal to
-- the bit number of the irq_req vector. Only the rising edge will
-- trigger the MSI.
-- legacy Interrupts:
-- If one of the bit of irq_req gets active, the PCIe core will be
-- triggered to send a INTA_asserted message. If another bit gets
-- active, no further messages will be sent. If all bit return to
-- inactive (irq_req = 0), a INTA_deassert message will be sent.
--
-- SuR: added wb interrupt number wrap according to maximum
-- number of enabled MSI vectors; corrected state machine
-- behavior
--------------------------------------------------------------------------------
-- Hierarchy:
-- ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- * pcie_msi-
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pcie_msi is
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : out std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end pcie_msi;
architecture pcie_msi_arch of pcie_msi is
-- +---------------------------------------------------------------------------
-- | constants
-- +---------------------------------------------------------------------------
constant ZERO_5B : std_logic_vector(4 downto 0) := (others => '0');
constant ZERO_6B : std_logic_vector(5 downto 0) := (others => '0');
constant ZERO_32B : std_logic_vector(31 downto 0) := (others => '0');
-- +---------------------------------------------------------------------------
-- | internal signals
-- +---------------------------------------------------------------------------
type msi_states is (IDLE, REQUEST_MSI, REQUEST_INTA, WAIT_ON_DEASSERT_INTA, DEASSERT_INTA, WAITONEND);
signal msi_state : msi_states;
signal irq_req_q : std_logic_vector(WIDTH -1 downto 0);
signal irq_req_qq : std_logic_vector(WIDTH -1 downto 0);
signal irq_req_qqq : std_logic_vector(WIDTH -1 downto 0);
signal irq : std_logic_vector(31 downto 0);
signal clr_irq : std_logic_vector(WIDTH -1 downto 0);
signal wb_num : std_logic_vector(4 downto 0);
signal irq_type : std_logic; -- when 1: msi is selected
signal wb_num_q : std_logic_vector(4 downto 0);
signal wb_num_conv_q : std_logic_vector(4 downto 0);
signal wb_num_conv : std_logic_vector(4 downto 0);
signal int_max_msi_nbr : std_logic_vector(4 downto 0);
begin
wb_pwr_enable_o <= '0';
irq_type <= '1' when to_integer(unsigned(wb_int_num_allowed_i)) > 0 else '0';
------------------------------
-- calculate int_max_msi_nbr
------------------------------
int_max_msi_nbr <= (others => '0') when wb_int_num_allowed_i = ZERO_6B else
(others => '1') when wb_int_num_allowed_i = "100000" else
std_logic_vector(to_unsigned(to_integer(unsigned(wb_int_num_allowed_i)),5));
------------------------------------
-- provide fixed irq vector number
-- for every irq request
------------------------------------
wb_num <= "00000" when irq(0) = '1' else
"00001" when irq(1) = '1' else
"00010" when irq(2) = '1' else
"00011" when irq(3) = '1' else
"00100" when irq(4) = '1' else
"00101" when irq(5) = '1' else
"00110" when irq(6) = '1' else
"00111" when irq(7) = '1' else
"01000" when irq(8) = '1' else
"01001" when irq(9) = '1' else
"01010" when irq(10) = '1' else
"01011" when irq(11) = '1' else
"01100" when irq(12) = '1' else
"01101" when irq(13) = '1' else
"01110" when irq(14) = '1' else
"01111" when irq(15) = '1' else
"10000" when irq(16) = '1' else
"10001" when irq(17) = '1' else
"10010" when irq(18) = '1' else
"10011" when irq(19) = '1' else
"10100" WHEN irq(20) = '1' ELSE
"10101" WHEN irq(21) = '1' ELSE
"10110" WHEN irq(22) = '1' ELSE
"10111" WHEN irq(23) = '1' ELSE
"11000" WHEN irq(24) = '1' ELSE
"11001" WHEN irq(25) = '1' ELSE
"11010" WHEN irq(26) = '1' ELSE
"11011" WHEN irq(27) = '1' ELSE
"11100" WHEN irq(28) = '1' ELSE
"11101" WHEN irq(29) = '1' ELSE
"11110" WHEN irq(30) = '1' ELSE
"11111" WHEN irq(31) = '1' ELSE
"00000";
-- set vector number to interrupt pin number
wb_int_num_o <= wb_num_conv_q;
-------------------------------------------
-- if less MSI vectors are assigned than
-- were requested wrap the vector numbers
-------------------------------------------
wb_num_conv <= (others => '0') when (wb_int_num_allowed_i = ZERO_6B or
irq = ZERO_32B or wb_num = ZERO_5B) else
std_logic_vector(unsigned(wb_num) mod unsigned(int_max_msi_nbr));
process (clk_i, rst_i)
begin
if rst_i = '1' then
wb_int_o <= '0';
wb_num_q <= (others => '0');
irq_req_q <= (others => '0');
irq_req_qq <= (others => '0');
irq_req_qqq <= (others => '0');
irq <= (others => '0');
clr_irq <= (others => '0');
msi_state <= IDLE;
wb_num_conv_q <= (others => '0');
elsif clk_i'event and clk_i = '1' then
irq_req_q <= irq_req_i;
irq_req_qq <= irq_req_q;
irq_req_qqq <= irq_req_qq;
for i in 0 to WIDTH-1 loop
if irq_req_qq(i) = '1' and irq_req_qqq(i) = '0' then
irq(i) <= '1';
elsif clr_irq(i) = '1' then
irq(i) <= '0';
end if;
end loop;
if WIDTH < 32 then
irq(31 downto WIDTH) <= (others => '0');
end if;
case msi_state is
-- wait until interrupt request is pending
when IDLE =>
if irq /= 0 and irq_type = '1' then -- send msi
wb_num_q <= wb_num; -- store number of interrupt at start of processing in order
-- not to get confused if another irq gets active
wb_num_conv_q <= wb_num_conv; -- set vector number to interrupt pin number
wb_int_o <= '1'; -- indicate interrupt request to pcie core
clr_irq <= (others => '0');
msi_state <= REQUEST_MSI;
elsif irq /= 0 and irq_type = '0' then -- send legacy
wb_num_q <= wb_num; -- store number of interrupt at start of processing in order
-- not to get confused if another irq gets active
wb_num_conv_q <= (others => '0'); -- unused for inta
wb_int_o <= '1'; -- indicate interrupt request to pcie core
clr_irq <= (others => '0');
msi_state <= REQUEST_INTA;
else
wb_num_q <= (others => '0');
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
end if;
-- wait until interrupt request was processed by pcie
when REQUEST_MSI =>
if wb_int_ack_i = '1' then
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '0'; -- clear interrupt request
clr_irq <= (others => '0');
clr_irq(conv_integer(wb_num_q)) <= '1'; -- clear processed interrupt request
msi_state <= WAITONEND;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= REQUEST_MSI;
end if;
-------------------------------------
-- wait until inta message was sent
-------------------------------------
when REQUEST_INTA =>
if wb_int_ack_i = '1' then
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= WAIT_ON_DEASSERT_INTA;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= REQUEST_INTA;
end if;
----------------------------------
-- send deassert inta message if
-- processed irq is deasserted
----------------------------------
when WAIT_ON_DEASSERT_INTA =>
if irq_req_qq(to_integer(unsigned(wb_num_q))) = '0' then
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0'); -- unused for inta
wb_int_o <= '0'; -- indicate interrupt deassert to pcie core
clr_irq <= (others => '0');
clr_irq(to_integer(unsigned(wb_num_q))) <= '1'; -- clear processed interrupt request
msi_state <= DEASSERT_INTA;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= WAIT_ON_DEASSERT_INTA;
end if;
-----------------------------
-- wait until deassert inta
-- message was sent
-----------------------------
when DEASSERT_INTA =>
if wb_int_ack_i = '1' then -- deassertion was sent
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '0'; -- clear interrupt request
--clr_irq(to_integer(unsigned(wb_num_q))) <= '1'; -- clear processed interrupt request
clr_irq <= (others => '0');
msi_state <= WAITONEND;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= DEASSERT_INTA;
end if;
-- wait until handshake has ended in order to be prepared for next interrupt
when WAITONEND =>
if wb_int_ack_i = '0' then -- handshake has ended
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
else
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= WAITONEND;
end if;
-- coverage_off
when others =>
wb_num_q <= (others => '0');
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
-- coverage_on
end case;
end if;
end process;
end pcie_msi_arch;
| gpl-3.0 | 263e5fb4ec0c8999eb895dbae57d8010 | 0.424692 | 4.170259 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/wbmon.vhd | 1 | 23,976 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.8 $
--
-- $Log: wbmon.vhd,v $
-- Revision 1.8 2015/06/15 16:40:04 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.7 2010/03/01 09:28:34 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.6 2008/10/27 08:42:22 skrieger
-- R: The wrong address is displayed during an access (lower than 32 bit) to a not 32-bit-alligned address. Example: 8-bit access to address 0x00000001
-- is displayed as 8-bit access to address 0x00000000 but with the same data.
-- M: Changed data output that a 32-bit-alligned address will be output but with the correct data and with the corresponding select-lines.
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
);
END wbmon;
ARCHITECTURE wbmon_arch OF wbmon IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT bitaccess : IN natural;
CONSTANT val : in std_logic_vector--(7 DOWNTO 0)
) RETURN string is
VARIABLE reglen : natural := 1;
VARIABLE result_str : string(1 to (bitaccess / 4));
VARIABLE slv : std_logic_vector(bitaccess-1 DOWNTO 0);-- := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
slv := val;
IF bitaccess = 8 THEN
reglen := 1;
ELSIF bitaccess = 16 THEN
reglen := 3;
ELSIF bitaccess = 32 THEN
reglen := 7;
ELSIF bitaccess = 64 THEN
reglen := 15;
ELSE
END IF;
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(reglen + 1 - i) := '0';
WHEN "0001" => result_str(reglen + 1 - i) := '1';
WHEN "0010" => result_str(reglen + 1 - i) := '2';
WHEN "0011" => result_str(reglen + 1 - i) := '3';
WHEN "0100" => result_str(reglen + 1 - i) := '4';
WHEN "0101" => result_str(reglen + 1 - i) := '5';
WHEN "0110" => result_str(reglen + 1 - i) := '6';
WHEN "0111" => result_str(reglen + 1 - i) := '7';
WHEN "1000" => result_str(reglen + 1 - i) := '8';
WHEN "1001" => result_str(reglen + 1 - i) := '9';
WHEN "1010" => result_str(reglen + 1 - i) := 'A';
WHEN "1011" => result_str(reglen + 1 - i) := 'B';
WHEN "1100" => result_str(reglen + 1 - i) := 'C';
WHEN "1101" => result_str(reglen + 1 - i) := 'D';
WHEN "1110" => result_str(reglen + 1 - i) := 'E';
WHEN "1111" => result_str(reglen + 1 - i) := 'F';
WHEN others => result_str(reglen + 1 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION data_out (sel : std_logic_vector(3 downto 0); dat : std_logic_vector(31 downto 0)) RETURN string IS
variable byte0 : string(1 to 2);
variable byte1 : string(1 to 2);
variable byte2 : string(1 to 2);
variable byte3 : string(1 to 2);
BEGIN
if sel(0) = '1' then
byte0 := to_hstring(8,dat( 7 downto 0));
else
byte0 := "XX";
end if;
if sel(1) = '1' then
byte1 := to_hstring(8,dat(15 downto 8));
else
byte1 := "XX";
end if;
if sel(2) = '1' then
byte2 := to_hstring(8,dat(23 downto 16));
else
byte2 := "XX";
end if;
if sel(3) = '1' then
byte3 := to_hstring(8,dat(31 downto 24));
else
byte3 := "XX";
end if;
return (byte3 & byte2 & "_" & byte1 & byte0);
end data_out;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 4);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 8);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(31 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (3 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(31 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 4;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,"Master Data Out changed during burst cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_b)&")", x"02", enable , ERROR, sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 4;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb = '1' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon_arch; | gpl-3.0 | 68e7db6525a79f367deb8e9ddf59e6c2 | 0.479563 | 3.756227 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/direct_path_cntr_ai.vhd | 3 | 11,437 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr_ai.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr_ai.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr_ai.vhd
--
-- Description: Direct-path counter with arbitrary increment.
--
-- This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n = '1' (load
-- disabled) Dout increments by Delta each time Cnt_en is
-- true at the positive edge of Clk.
--
-- The implementation has a one-LUT delay from Din to Dout
-- (via the XORCY) in direct pass-through mode and the same
-- delay plus carry-chain propogation in count mode. There
-- is an additional LUT delay (added to the Din to Dout
-- delay) from the Load_n input or from the clock edge that
-- puts the counter into count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr_ai.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 12/02/2003 -- First version derived from
-- direct_path_cntr.vhd
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr_ai is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic;
Delta : in std_logic_vector(0 to C_WIDTH-1)
);
end direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
architecture imp of direct_path_cntr_ai is
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
signal sel_cntr_and_Load_n : std_logic; -- AND of sel_cntr and Load_n
signal mdelta : std_logic_vector(0 to Delta'length-1); -- "My delta"
-- Delta, adjusted to assure ascending range referenced from zero.
begin
mdelta <= Delta;
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
sel_cntr_and_Load_n <= sel_cntr and Load_n;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation and MUXCY carry handling.
------------------------------------------------------------------------
DELTA_LUT_GEN: if j >= C_WIDTH-mdelta'length generate
signal gen_cry: std_logic;
begin
lut_out(j) <= q_i(j) xor mdelta(mdelta'length + j - C_WIDTH)
when (sel_cntr_and_Load_n)='1'
else
Din(j);
I_MULT_AND : MULT_AND
port map (
LO => gen_cry,
I1 => sel_cntr_and_Load_n,
I0 => q_i(j)
);
MUXCY_i1: MUXCY
port map (
DI => gen_cry,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
--
NON_DELTA_LUT_GEN : if j < C_WIDTH-mdelta'length generate
begin
lut_out(j) <= q_i(j) when (sel_cntr_and_Load_n)='1' else Din(j);
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| bsd-3-clause | 0737c48fa1d60c9a0406a55697367569 | 0.432981 | 4.910691 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd | 2 | 13,366 | -------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
| bsd-3-clause | 3425d0e3e56c1b81cf7bc64c352b4e5f | 0.413587 | 4.458306 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/write_tb.vhd | 1 | 3,742 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:36:53 11/11/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE3_final/write_tb.vhd
-- Project Name: IDE3_final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: write_circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY write_tb IS
END write_tb;
ARCHITECTURE behavior OF write_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT write_circuit
PORT(
wr_clk : IN std_logic;
wr_reset : IN std_logic;
wr_pa : IN std_logic;
wr_cs : IN std_logic;
wr_cpu_wr : IN std_logic;
wr_data_in : IN std_logic_vector(3 downto 0);
address : OUT std_logic_vector(4 downto 0);
wr_data_out : OUT std_logic_vector(15 downto 0);
wr_ready : OUT std_logic;
IOW : OUT std_logic
);
END COMPONENT;
--Inputs
signal wr_clk : std_logic := '0';
signal wr_reset : std_logic := '0';
signal wr_pa : std_logic := '0';
signal wr_cs : std_logic := '0';
signal wr_cpu_wr : std_logic := '0';
signal wr_data_in : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal address : std_logic_vector(4 downto 0);
signal wr_data_out : std_logic_vector(15 downto 0);
signal wr_ready : std_logic;
signal IOW : std_logic;
-- Clock period definitions
constant wr_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: write_circuit PORT MAP (
wr_clk => wr_clk,
wr_reset => wr_reset,
wr_pa => wr_pa,
wr_cs => wr_cs,
wr_cpu_wr => wr_cpu_wr,
wr_data_in => wr_data_in,
address => address,
wr_data_out => wr_data_out,
wr_ready => wr_ready,
IOW => IOW
);
-- Clock process definitions
wr_clk_process :process
begin
wr_clk <= '0';
wait for wr_clk_period/2;
wr_clk <= '1';
wait for wr_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for wr_clk_period*2;
-- hold reset state for 100 ns.
wait for 10 ns;
wr_reset <= '1';
wait for 10 ns;
wr_reset <= '0';
wait for 10 ns;
wr_pa <= '1';
wr_cs <= '1';
wait for 10 ns;
wr_cpu_wr <= '1';
wait until wr_ready = '1';
wr_data_in <= "0001";
wait for 5 ns;
wr_cpu_wr <= '0';
wait for 10 ns;
wr_cpu_wr <= '1';
wait until wr_ready = '1';
wr_data_in <= "0010";
wait for 10 ns;
wr_cpu_wr <= '0';
wait for 10 ns;
wr_cpu_wr <= '1';
wait until wr_ready = '1';
wr_data_in <= "0011";
wait for 10 ns;
wr_cpu_wr <= '0';
wait for 10 ns;
wr_cpu_wr <= '1';
wait until wr_ready = '1';
wr_data_in <= "0100";
wait for 10 ns;
wr_cpu_wr <= '0';
-- wait for 10 ns;
--wait for wr_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| unlicense | a91f01955f7f35df370266906076ec99 | 0.562533 | 3.237024 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_slv.vhd | 1 | 3,293 | --------------------------------------------------------------------------------
-- Title : Slave of DMA controller
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_slv.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module handles accesses to the dma registers and to the
-- buffer descriptor registers from pci-side.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_fifo
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_dma_slv.vhd,v $
-- Revision 1.1 2012/03/29 10:14:40 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/18 14:02:29 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:29 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/15 09:28:53 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma_slv IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
slv_req : OUT std_logic;
slv_ack : IN std_logic
);
END vme_dma_slv;
ARCHITECTURE vme_dma_slv_arch OF vme_dma_slv IS
SIGNAL slv_ack_reg : std_logic;
BEGIN
-- request for access to registers (only write, for read not needed)
slv_req <= '1' WHEN stb_i = '1' AND we_i = '1' AND cyc_i = '1' ELSE '0';
ack_o <= '1' WHEN stb_i = '1' AND cyc_i = '1' AND (slv_ack = '1' OR slv_ack_reg = '1') ELSE '0';
ack : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv_ack_reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF stb_i = '1' AND we_i = '0' AND cyc_i = '1' THEN
slv_ack_reg <= '1';
ELSE
slv_ack_reg <= '0';
END IF;
END IF;
END PROCESS ack;
END vme_dma_slv_arch;
| gpl-3.0 | 2f6c8cb0e513430398b4d214830900c8 | 0.480413 | 4.040491 | false | false | false | false |
iocoder/graduation | hardware/vga/clkgen_sim.vhd | 1 | 1,140 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkgen is
Port (CLK : in STD_LOGIC;
CLK_56MHz : out STD_LOGIC;
CLK_50MHz : out STD_LOGIC;
CLK_28MHz : out STD_LOGIC;
CLK_25MHz : out STD_LOGIC);
end clkgen;
architecture Behavioral of clkgen is
signal oCLK_56MHz : STD_LOGIC := '0';
signal oCLK_50MHz : STD_LOGIC := '0';
signal oCLK_28MHz : STD_LOGIC := '0';
signal oCLK_25MHz : STD_LOGIC := '0';
begin
-- generate 50MHz clock
oCLK_50MHz <= CLK;
-- generate 25MHz clock
process(oCLK_50MHz)
begin
if (oCLK_50MHz = '1' and oCLK_50MHz'event ) then
oCLK_25MHz <= NOT oCLK_25MHz;
end if;
end process;
-- generate 56MHz clock
oCLK_56MHz <= oCLK_50MHz; -- just for simulation
-- generate 28MHz clock
process(oCLK_56MHz)
begin
if (oCLK_56MHz = '1' and oCLK_56MHz'event ) then
oCLK_28MHz <= NOT oCLK_28MHz;
end if;
end process;
-- connect generated clock frequencies to outputs
CLK_56MHz <= oCLK_56MHz;
CLK_50MHz <= oCLK_50MHz;
CLK_28MHz <= oCLK_28MHz;
CLK_25MHz <= oCLK_25MHz;
end Behavioral;
| gpl-3.0 | 024c6fe302c7464e5478f0f9ca37e478 | 0.659649 | 2.992126 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/generic_dcfifo_mixedw.vhd | 1 | 4,053 | --------------------------------------------------------------------------------
-- Title : Generic Altera Fifo
-- Project : PCIe-to-VME bridge
--------------------------------------------------------------------------------
-- File : generic_dcfifo_mixedw.vhd
-- Author : Grzegorz Daniluk
-- Email : [email protected]
-- Organization: CERN
-- Created : 17/05/2017
--------------------------------------------------------------------------------
-- Description :
-- Generic, parametrized mixed width fifo based on Altera dcfifo.
--------------------------------------------------------------------------------
-- Copyright (c) 2017, CERN
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity generic_dcfifo_mixedw is
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end generic_dcfifo_mixedw;
architecture syn of generic_dcfifo_mixedw is
begin
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map(
intended_device_family => g_device_family,
lpm_numwords => g_fifo_depth, -- value assigned must comply with this equation
-- 2^(LPM_WIDTHU -1) < LPM_NUMWORDS <= 2^(LPM_WIDTHU)
lpm_showahead => g_showahead, -- off: normal mode, on: show ahead mode
lpm_type => "dcfifo_mixed_widths", -- DON'T CHANGE / FIFO type
lpm_width => g_data_width, -- width for _data_ port
lpm_widthu => g_data_widthu, -- size of write usedw
lpm_width_r => g_q_width, -- width for _q_ port
lpm_widthu_r => g_q_widthu, -- size of read usedw
overflow_checking => "ON", -- DON'T CHANGE / protection circuit for overflow checking
rdsync_delaypipe => 4, -- nbr of read synchronization stages, internally reduced by 2 => 2 stages
read_aclr_synch => "OFF",
underflow_checking => "ON", -- DON'T CHANGE / protection circuit for underflow checking
use_eab => "ON", -- off: FIFO implemented in logic, on: FIFO implemented using RAM blocks
write_aclr_synch => "OFF",
wrsync_delaypipe => 4 -- nbr of write synchronization stages, internally reduced by 2 => 2 stages
)
port map (
aclr => aclr,
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => q,
rdempty => rdempty,
wrfull => wrfull,
wrusedw => wrusedw);
end syn;
| gpl-3.0 | 54f7e61269b20280abe0246e69c5f91f | 0.529731 | 4.243979 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_trylock_2.vhd | 2 | 16,356 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_trylock_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_trylock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_TRYLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- if( _mutex_owner( mutex->num ) == hthread_self() )
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg1_next <= intrfc2thrd_value;
-- Call hthread_self();
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
if ( intrfc2thrd_value = reg1 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= STATE_8;
-- hthread_mutex_unlock( mutex );
when STATE_8 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
when STATE_10 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ce4224bbe767f24d899e8030335c0a9d | 0.544815 | 3.794896 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_destroy_2.vhd | 2 | 16,193 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mtuex= (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_mutex_destroy( mutex );
when STATE_4 =>
-- Push the argument to hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_mutex_init( mutex, NULL );
when STATE_6 =>
-- Push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
next_state <= WAIT_STATE;
when STATE_9 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | bdc3b9757f0f82c8d9436bbff2a6004d | 0.544495 | 3.796717 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_clk_trans_wb2wb.vhd | 1 | 10,207 | ---------------------------------------------------------------
-- Title : Adaption from clk a to clk b
-- Project : A15
---------------------------------------------------------------
-- File : z126_01_clk_trans_wb2wb.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
-- This Module transforms the request and acknoledge signals to
-- connect to a a MHz internal bus. Also the data must be
-- transformed in order to fit into the a MHz clk domain.
---------------------------------------------------------------
-- Hierarchy:
--
-- sys_unit
-- z126_01_clk_trans_wb2wb
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_clk_trans_wb2wb.vhd,v $
-- Revision 1.1 2014/03/03 17:49:39 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_clk_trans_wb2wb IS
GENERIC (
NBR_OF_CYC : integer range 1 TO 100 := 1;
NBR_OF_TGA : integer range 1 TO 100 := 6
);
PORT (
rstn : IN std_logic;
-- a MHz domain
clk_a : IN std_logic;
cyc_a : IN std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_a : IN std_logic; -- request signal from a MHz side
ack_a : OUT std_logic; -- adopted acknoledge signal to b MHz
err_a : OUT std_logic;
we_a : IN std_logic; -- '1' = write, '0' = read
tga_a : IN std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_a : IN std_logic_vector(2 DOWNTO 0); -- transfer type
bte_a : IN std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_a : IN std_logic_vector(31 DOWNTO 0); -- adr from a MHz side
sel_a : IN std_logic_vector(3 DOWNTO 0); -- byte enables from a MHz side
dat_i_a : IN std_logic_vector(31 DOWNTO 0); -- data from a MHz side
dat_o_a : OUT std_logic_vector(31 DOWNTO 0); -- data from b MHz side to a MHz side
-- b MHz domain
clk_b : IN std_logic;
cyc_b : OUT std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_b : OUT std_logic; -- request signal adopted to b MHz
ack_b : IN std_logic; -- acknoledge signal from internal bus
err_b : IN std_logic;
we_b : OUT std_logic; -- '1' = write, '0' = read
tga_b : OUT std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_b : OUT std_logic_vector(2 DOWNTO 0); -- transfer type
bte_b : OUT std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_b : OUT std_logic_vector(31 DOWNTO 0); -- adr from b MHz side
sel_b : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for b MHz side
dat_i_b : IN std_logic_vector(31 DOWNTO 0); -- data from b MHz side
dat_o_b : OUT std_logic_vector(31 DOWNTO 0) -- data from a MHz side to b MHz side
);
END z126_01_clk_trans_wb2wb;
ARCHITECTURE z126_01_clk_trans_wb2wb_arch OF z126_01_clk_trans_wb2wb IS
COMPONENT z126_01_fifo_d1
GENERIC (
width : IN integer
);
PORT (
rstn : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END COMPONENT;
TYPE ct_states IS (idle, waitstate, acknoledge);
SIGNAL ct_state : ct_states;
CONSTANT WR_FIFO_WIDTH : integer:= 69 + NBR_OF_CYC + NBR_OF_TGA; -- cyc + dat + adr + sel + we = 32+32+4+1 = 69
CONSTANT RD_FIFO_WIDTH : integer:= 32; -- dat = 32
SIGNAL ff1_rd : std_logic;
SIGNAL ff1_wr : std_logic;
SIGNAL ff1_full_a : std_logic;
SIGNAL ff1_full_b : std_logic;
SIGNAL ff2_rd : std_logic;
SIGNAL ff2_wr : std_logic;
SIGNAL ff2_full_b : std_logic;
SIGNAL stb_b_int : std_logic;
SIGNAL ff1_dat_a : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ff1_dat_b : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ack_a_int : std_logic;
BEGIN
ack_a <= ack_a_int;
stb_b <= stb_b_int;
err_a <= '0'; -- errors will not reported: error-access will never end!
ff1_dat_a <= tga_a & cyc_a & dat_i_a & adr_a & sel_a & we_a;
tga_b <= ff1_dat_b(68+NBR_OF_CYC+NBR_OF_TGA DOWNTO 69+NBR_OF_CYC);
cyc_b <= ff1_dat_b(68+NBR_OF_CYC DOWNTO 69) WHEN stb_b_int = '1' ELSE (OTHERS => '0');
dat_o_b <= ff1_dat_b(68 DOWNTO 37);
adr_b <= ff1_dat_b(36 DOWNTO 5);
sel_b <= ff1_dat_b(4 DOWNTO 1);
we_b <= ff1_dat_b(0);
cti_b <= (OTHERS => '0');
bte_b <= (OTHERS => '0');
ff1 : z126_01_fifo_d1
GENERIC MAP (
width => WR_FIFO_WIDTH )
PORT MAP (
rstn => rstn,
clk_a => clk_a,
wr_a => ff1_wr,
data_a => ff1_dat_a,
full_a => ff1_full_a,
clk_b => clk_b,
rd_b => ff1_rd,
data_b => ff1_dat_b,
full_b => ff1_full_b
);
ff2 : z126_01_fifo_d1
GENERIC MAP (
width => RD_FIFO_WIDTH )
PORT MAP (
rstn => rstn,
clk_a => clk_b,
wr_a => ff2_wr,
data_a => dat_i_b,
clk_b => clk_a,
rd_b => ff2_rd,
data_b => dat_o_a,
full_b => ff2_full_b
);
ff1_wr <= '1' WHEN (ct_state = idle AND stb_a = '1' AND cyc_a(0) = '1' AND ff1_full_a = '0') ELSE '0';
ff2_rd <= '1' WHEN ff2_full_b = '1' ELSE '0'; -- read data from ff when available
proca : PROCESS (clk_a, rstn)
BEGIN
IF rstn = '0' THEN
ack_a_int <= '0';
ct_state <= idle;
ELSIF clk_a'EVENT AND clk_a = '1' THEN
CASE ct_state IS
WHEN idle =>
IF (ff1_wr = '1' AND we_a = '1') THEN -- write
ct_state <= acknoledge;
ack_a_int <= '1';
ELSIF (ff1_wr = '1' AND we_a = '0') THEN -- read
ct_state <= waitstate;
ack_a_int <= '0';
ELSE
ct_state <= idle;
ack_a_int <= '0';
END IF;
WHEN waitstate =>
IF ff2_full_b = '1' THEN
ct_state <= acknoledge;
ack_a_int <= '1';
ELSE
ct_state <= waitstate;
ack_a_int <= '0';
END IF;
WHEN acknoledge =>
ack_a_int <= '0';
ct_state <= idle;
WHEN OTHERS =>
ct_state <= idle;
ack_a_int <= '0';
END CASE;
END IF;
END PROCESS proca;
------------------------------------------------------------------
-- side b: stb_b is not dependent on we_a
------------------------------------------------------------------
-- for read and write equal:
ff1_rd <= '1' WHEN ((ack_b = '0' AND err_b = '0') AND ff1_full_b = '1' AND stb_b_int = '0') OR -- first data phase
((ack_b = '1' OR err_b = '1') AND ff1_full_b = '1' AND stb_b_int = '1') -- within a burst (not the last)
ELSE '0';
ff2_wr <= '1' WHEN stb_b_int = '1' AND (ack_b = '1' OR err_b = '1') AND ff1_dat_b(0) = '0' ELSE '0'; -- store read-data
-- ack_b stb_b ff1_full stb_b(+1)
-- x 0 1 1
-- x 1 1 1
-- x 0 0 0
-- 1 1 0 0
-- 0 1 0 1
procb : PROCESS (clk_b, rstn)
BEGIN
IF rstn = '0' THEN
stb_b_int <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
IF ff1_full_b = '1' THEN
IF stb_b_int = '0' THEN
stb_b_int <= '1'; -- start next data phase
ELSE
-- end of current data phase, start of next
stb_b_int <= '1'; -- or no end of current data phase
END IF;
ELSE
IF stb_b_int = '0' THEN -- no current access and no next access
stb_b_int <= '0';
ELSE
IF ack_b = '1' OR err_b = '1' THEN -- end of current data phase, no next
stb_b_int <= '0';
ELSE
stb_b_int <= '1'; -- no end of current data phase
END IF;
END IF;
END IF;
END IF;
END PROCESS procb;
END z126_01_clk_trans_wb2wb_arch;
| gpl-3.0 | 290373da765b2644cd54e8cf05d2493d | 0.45557 | 3.537955 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/family.vhd | 2 | 23,056 | -- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/proc_common/proc_common_v3_00_a/hdl/src/vhdl/family.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
| bsd-3-clause | 2e7d5eb81167206ef64c80d084c55bac | 0.548621 | 4.689992 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_system.vhd | 3 | 32,733 | -------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_M_ABus : std_logic_vector(0 to 31);
signal plb_bus_M_BE : std_logic_vector(0 to 15);
signal plb_bus_M_MSize : std_logic_vector(0 to 1);
signal plb_bus_M_RNW : std_logic_vector(0 to 0);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_M_UABus : std_logic_vector(0 to 31);
signal plb_bus_M_abort : std_logic_vector(0 to 0);
signal plb_bus_M_busLock : std_logic_vector(0 to 0);
signal plb_bus_M_lockErr : std_logic_vector(0 to 0);
signal plb_bus_M_priority : std_logic_vector(0 to 1);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 0);
signal plb_bus_M_request : std_logic_vector(0 to 0);
signal plb_bus_M_size : std_logic_vector(0 to 3);
signal plb_bus_M_type : std_logic_vector(0 to 2);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 0);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 0);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 0);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 0);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_SPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 1);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 255);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 0),
Sl_MRdErr => plb_bus_Sl_MRdErr(0 to 0),
Sl_MWrErr => plb_bus_Sl_MWrErr(0 to 0),
Sl_MIRQ => plb_bus_Sl_MIRQ(0 to 0)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request(0 to 0),
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock(0 to 0),
M_RNW => plb_bus_M_RNW(0 to 0),
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMIRQ => net_gnd1(0 to 0),
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => plb_bus_SPLB_Rst,
MPLB_Rst => open,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW(0 to 0),
M_abort => plb_bus_M_abort(0 to 0),
M_busLock => plb_bus_M_busLock(0 to 0),
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr(0 to 0),
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst(0 to 0),
M_request => plb_bus_M_request(0 to 0),
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst(0 to 0),
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ(0 to 0),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0 to 0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0 to 0),
PLB_MBusy => plb_bus_PLB_MBusy(0 to 0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0 to 0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0 to 0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0 to 0),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0 to 0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0 to 0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0 to 0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0 to 0),
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr(0 to 0),
PLB_SMWrErr => plb_bus_PLB_SMWrErr(0 to 0),
PLB_SMBusy => plb_bus_PLB_SMBusy(0 to 0),
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
SPLB_Clk => sys_clk,
SPLB_Rst => plb_bus_SPLB_Rst(1),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(1),
PLB_wrPrim => plb_bus_PLB_wrPrim(1),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_MSize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_TAttribute => plb_bus_PLB_TAttribute,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(128 to 255),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_MBusy => plb_bus_Sl_MBusy(1 to 1),
Sl_MWrErr => plb_bus_Sl_MWrErr(1 to 1),
Sl_MRdErr => plb_bus_Sl_MRdErr(1 to 1),
Sl_MIRQ => plb_bus_Sl_MIRQ(1 to 1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
| bsd-3-clause | 262802c736087d4d3bec39916680e4a7 | 0.60746 | 3.02887 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_be_gen.vhd | 3 | 14,517 | -------------------------------------------------------------------------------
-- $Id: opb_be_gen.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_be_gen.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_be_gen.vhd
--
-- Description: This counter provides the byte enables during
-- burst operations. It advances based on IP2Bus_addrAck.
-------------------------------------------------------------------------------
-- Structure:
--
--
-- opb_be_gen.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
--
-- ALS 12/24/03
-- ^^^^^^
-- Adapted from brst_addr_be_cntr.vhd
-- ~~~~~~~
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- ~~~~~~~
-- ALS 04/27/04
-- ^^^^^^
-- Fixed equations for byte_xfer_i, hw_xfer_i, and fw_xfer_i to equal the
-- bus decodes when Load_BE=1 and the sample and hold bus decodes when
-- Load_BE=0
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.log2;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity opb_be_gen is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_INCLUDE_WR_BUF : integer := 1
);
port (
-- Inputs
Bus_clk : in std_logic;
Address_in : in std_logic_vector(0 to C_OPB_AWIDTH-1);
BE_in : in std_logic_vector(0 to (C_OPB_DWIDTH/8)-1);
Load_BE : in std_logic;
Rst_BE : in std_logic;
-- BE Outputs
BE_out : out std_logic_vector(0 to (C_OPB_DWIDTH/8)-1);
-- Xfer size outputs
Byte_xfer : out std_logic;
Hw_xfer : out std_logic;
Fw_xfer : out std_logic
);
end opb_be_gen;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
architecture implementation of opb_be_gen is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal be_out_i : std_logic_vector(0 to (C_OPB_DWIDTH/8)-1);
signal byte_xfer_d : std_logic;
signal hw_xfer_d : std_logic;
signal fw_xfer_d : std_logic;
signal byte_xfer_i : std_logic;
signal hw_xfer_i : std_logic;
signal fw_xfer_i : std_logic;
signal s_h_byte_xfer : std_logic;
signal s_h_hw_xfer : std_logic;
signal s_h_fw_xfer : std_logic;
signal s_h_reset : std_logic;
signal addr_in : std_logic_vector(30 to 31);
signal be0_lutsel : std_logic;
signal be1_lutsel : std_logic;
signal be2_lutsel : std_logic;
signal be3_lutsel : std_logic;
-------------------------------------------------------------------------------
begin
-- Output assignments
BE_out <= be_out_i;
-----------------------------------------------------------------------
-- Determine the transfer size
-- NOTE: this logic is specific to a 32-bit wide OPB bus and has not
-- been written for the generalized case
-- (1-lut per signal)
byte_xfer_d <= '1'
when BE_in = "0001" or
BE_in = "0010" or
BE_in = "0100" or
BE_in = "1000"
else '0';
hw_xfer_d <= '1'
when BE_in = "0011" or
BE_in = "1100"
else '0';
fw_xfer_d <= '1'
when BE_in = "1111"
else '0';
-------------------------------------------------------------------------------
-- When write buffer is included in design, need to sample and hold the
-- xfer size until the write buffer has emptied. This will keep the correct byte
-- enabled asserted until write transaction has completed
s_h_reset <= Rst_BE and not(Load_BE);
XFER_ADDR_REG_GEN: if C_INCLUDE_WR_BUF = 1 generate
BYTE_XFER_REG : FDRE
port map(
Q => s_h_byte_xfer,
C => Bus_clk,
CE => Load_BE,
D => byte_xfer_d,
R => s_h_reset
);
HW_XFER_REG : FDRE
port map(
Q => s_h_hw_xfer,
C => Bus_clk,
CE => Load_BE,
D => hw_xfer_d,
R => s_h_reset
);
FW_XFER_REG : FDRE
port map(
Q => s_h_fw_xfer,
C => Bus_clk,
CE => Load_BE,
D => fw_xfer_d,
R => s_h_reset
);
-- extend the xfer size indicators
byte_xfer_i <= (byte_xfer_d and Load_BE) or (s_h_byte_xfer and not(Load_BE));
hw_xfer_i <= (hw_xfer_d and Load_BE) or (s_h_hw_xfer and not(Load_BE));
fw_xfer_i <= (fw_xfer_d and Load_BE) or (s_h_fw_xfer and not (Load_BE));
Byte_xfer <= s_h_byte_xfer;
Hw_xfer <= s_h_hw_xfer;
Fw_xfer <= s_h_fw_xfer;
end generate XFER_ADDR_REG_GEN;
NOXFERADDR_REG_GEN: if C_INCLUDE_WR_BUF = 0 generate
byte_xfer_i <= byte_xfer_d;
hw_xfer_i <= hw_xfer_d;
fw_xfer_i <= fw_xfer_d;
Byte_xfer <= byte_xfer_i;
Hw_xfer <= hw_xfer_i;
Fw_xfer <= fw_xfer_i;
end generate NOXFERADDR_REG_GEN;
------------------------------------------------------------------------------
-- Determine BE based on the xfer size and the LSBs of the current address
-- BE_OUT will be "0000" if illegal input BE combinations
addr_in(30 to 31) <= Address_in(30 to 31);
-- generate BE0 using luts and muxcy
-- equivalent logic:
-- BE0 <= '1' when
-- ( byte_xfer = '1' and addr_in(30 to 31) = "00" ) or
-- ( hw_xfer = '1' and addr_in(30 to 31) = "00") or
-- ( fw_xfer = '1')
-- else '0';
be0_lutsel <= '0' when
( byte_xfer_i = '1' and addr_in(30 to 31) = "00" ) or
( hw_xfer_i = '1' and addr_in(30 to 31) = "00")
else '1';
BE0_MUXCY_I : MUXCY
port map (
O => be_out_i(0),
CI => fw_xfer_i,
DI => '1',
S => be0_lutsel
);
-- generate BE1 using luts and muxcy
-- equivalent logic:
-- BE1 <= '1' when
-- ( byte_xfer_i = '1' and addr_in(30 to 31) = "01" ) or
-- ( hw_xfer_i = '1' and addr_in(30 to 31) = "00") or
-- ( fw_xfer_i = '1')
-- else '0';
be1_lutsel <= '0' when
( byte_xfer_i = '1' and addr_in(30 to 31) = "01" ) or
( hw_xfer_i = '1' and addr_in(30 to 31) = "00")
else '1';
BE1_MUXCY_I : MUXCY
port map (
O => be_out_i(1),
CI => fw_xfer_i,
DI => '1',
S => be1_lutsel
);
-- generate BE2 using luts and muxcy
-- equivalent logic:
-- BE2 <= '1' when
-- ( byte_xfer_i = '1' and addr_in(30 to 31) = "10" ) or
-- ( hw_xfer_i = '1' and addr_in(30 to 31) = "10") or
-- ( fw_xfer_i = '1')
-- else '0';
be2_lutsel <= '0' when
( byte_xfer_i = '1' and addr_in(30 to 31) = "10" ) or
( hw_xfer_i = '1' and addr_in(30 to 31) = "10")
else '1';
BE2_MUXCY_I : MUXCY
port map (
O => be_out_i(2),
CI => fw_xfer_i,
DI => '1',
S => be2_lutsel
);
-- generate BE3 using luts and muxcy
-- equivalent logic:
-- BE3 <= '1' when
-- ( byte_xfer_i = '1' and addr_in(30 to 31) = "11" ) or
-- ( hw_xfer_i = '1' and addr_in(30 to 31) = "10") or
-- ( fw_xfer_i = '1')
-- else '0';
be3_lutsel <= '0' when
( byte_xfer_i = '1' and addr_in(30 to 31) = "11" ) or
( hw_xfer_i = '1' and addr_in(30 to 31) = "10")
else '1';
BE3_MUXCY_I : MUXCY
port map (
O => be_out_i(3),
CI => fw_xfer_i,
DI => '1',
S => be3_lutsel
);
end implementation;
| bsd-3-clause | 1fc314a0fae71b2d349a423504985edb | 0.403114 | 4.253443 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_stringMatch.vhd | 2 | 44,666 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic String Match
-- Thread implements a string matching routine
-- Passed in argument is a pointer to following struct
-- struct threadArgument {
-- hthread_mutex_t * mutex;
-- int * packetIndex;
-- int * foundStringIndex;
-- int * foundStrings;
-- int sPrimaryCount;
-- int sSecondaryCount;
-- char * T;
-- };
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_START,
READ_STRUCT_1,
READ_STRUCT_2,
READ_STRUCT_4,
READ_STRUCT_5,
READ_STRUCT_6,
READ_STRUCT_7,
READ_STRUCT_8,
READ_STRUCT_9,
ALLOCATE_MEMORY_1,
ALLOCATE_MEMORY_2,
ALLOCATE_MEMORY_3,
ALLOCATE_MEMORY_4,
ALLOCATE_MEMORY_5,
INDEX_MUTEXLOCK_1,
INDEX_MUTEXLOCK_2,
INDEX_INCREMENT_1,
INDEX_INCREMENT_2,
INDEX_MUTEXUNLOCK_1,
INDEX_MUTEXUNLOCK_2,
INDEX_CHECK_1,
INDEX_CHECK_2,
COPY_T_1,
COPY_T_2,
COPY_T_3,
COPY_T_4,
CHAR_MATCH_LOOP_1,
CHAR_MATCH_LOOP_2,
CHAR_MATCH_LOOP_3,
--CHAR_MATCH_LOOP_4,
--CHAR_MATCH_LOOP_5,
CHAR_MATCH_LOOP_6,
CHAR_MATCH_LOOP_7,
CHAR_MATCH_LOOP_8,
CHAR_MATCH_LOOP_9,
CHAR_MATCH_LOOP_10,
CHAR_MATCH_LOOP_11,
CHAR_MATCH_LOOP_12,
CHAR_MATCH_LOOP_13,
CHAR_MATCH_LOOP_14,
EXIT_THREAD_1,
SEARCH_1,
SEARCH_2,
SEARCH_3,
SEARCH_4,
SEARCH_5,
SEARCH_6,
SEARCH_6a,
SEARCH_7,
SEARCH_8,
MATCH_1,
MATCH_2,
MATCH_3,
MATCH_3a,
MATCH_3b,
MATCH_4,
MATCH_5,
MATCH_6,
MATCH_7,
MATCH_8,
MATCH_9,
MATCH_10,
MATCH_11,
MATCH_12,
MATCH_13,
MATCH_14,
MATCH_15,
MATCH_16,
MATCH_17,
MATCH_18,
MATCH_19,
MATCH_20,
MATCH_21,
MATCH_22,
REPORT_STRING_1,
REPORT_STRING_2,
REPORT_STRING_3,
REPORT_STRING_4,
REPORT_STRING_5,
REPORT_STRING_6,
REPORT_STRING_7,
REPORT_STRING_8,
REPORT_STRING_9,
REPORT_STRING_10,
REPORT_STRING_11,
REPORT_STRING_12,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant C_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant C_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant C_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant C_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant C_ALLOCATE_MEMORY_3 : std_logic_vector(0 to 15) := x"0103";
constant C_ALLOCATE_MEMORY_5 : std_logic_vector(0 to 15) := x"0105";
constant C_INDEX_INCREMENT_1 : std_logic_vector(0 to 15) := x"0201";
constant C_INDEX_CHECK_2 : std_logic_vector(0 to 15) := x"0302";
constant C_INDEX_MUTEXUNLOCK_1 : std_logic_vector(0 to 15) := x"0801";
constant C_CHAR_MATCH_LOOP_11 : std_logic_vector(0 to 15) := x"0411";
constant C_CHAR_MATCH_LOOP_14 : std_logic_vector(0 to 15) := x"0414";
constant C_MATCH_1 : std_logic_vector(0 to 15) := x"0501";
constant C_MATCH_12 : std_logic_vector(0 to 15) := x"0512";
constant C_MATCH_15 : std_logic_vector(0 to 15) := x"0515";
constant C_MATCH_18 : std_logic_vector(0 to 15) := x"0518";
constant C_REPORT_STRING_1 : std_logic_vector(0 to 15) := x"0701";
constant C_REPORT_STRING_5 : std_logic_vector(0 to 15) := x"0705";
constant C_REPORT_STRING_11 : std_logic_vector(0 to 15) := x"0711";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant C_PACKET_LENGTH : std_logic_vector(0 to 31) := x"00000400";
constant C_NUMBER_PACKETS : std_logic_vector(0 to 7) := x"64";
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal mutexPtr, mutexPtr_next : std_logic_vector(0 to 31);
signal packetIndexPtr, packetIndexPtr_next : std_logic_vector(0 to 31);
signal foundStringIndexPtr, foundStringIndexPtr_next : std_logic_vector(0 to 31);
signal foundStringsPtr, foundStringsPtr_next : std_logic_vector(0 to 31);
signal sPrimaryCount, sPrimaryCount_next : std_logic_vector(0 to 11);
signal sPrimaryPtr, sPrimaryPtr_next : std_logic_vector(0 to 31);
signal TPtr, TPtr_next : std_logic_vector(0 to 31);
signal i, i_next : std_logic_vector(0 to 9);
signal localTPtr, localTPtr_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
mutexPtr <= mutexPtr_next;
packetIndexPtr <= packetIndexPtr_next;
foundStringIndexPtr <= foundStringIndexPtr_next;
foundStringsPtr <= foundStringsPtr_next;
sPrimaryCount <= sPrimaryCount_next;
sPrimaryPtr <= sPrimaryPtr_next;
TPtr <= TPtr_next;
i <= i_next;
localTPtr <= localTPtr_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when C_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when C_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when C_FUNCTION_START =>
current_state <= FUNCTION_START;
when C_ALLOCATE_MEMORY_3 =>
current_state <= ALLOCATE_MEMORY_3;
when C_ALLOCATE_MEMORY_5 =>
current_state <= ALLOCATE_MEMORY_5;
when C_INDEX_INCREMENT_1 =>
current_state <= INDEX_INCREMENT_1;
when C_INDEX_CHECK_2 =>
current_state <= INDEX_CHECK_2;
when C_INDEX_MUTEXUNLOCK_1 =>
current_state <= INDEX_MUTEXUNLOCK_1;
when C_CHAR_MATCH_LOOP_11 =>
current_state <= CHAR_MATCH_LOOP_11;
when C_CHAR_MATCH_LOOP_14 =>
current_state <= CHAR_MATCH_LOOP_14;
when C_MATCH_1 =>
current_state <= MATCH_1;
when C_MATCH_12 =>
current_state <= MATCH_12;
when C_MATCH_15 =>
current_state <= MATCH_15;
when C_MATCH_18 =>
current_state <= MATCH_18;
when C_REPORT_STRING_1 =>
current_state <= REPORT_STRING_1;
when C_REPORT_STRING_5 =>
current_state <= REPORT_STRING_5;
when C_REPORT_STRING_11 =>
current_state <= REPORT_STRING_11;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= C_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
mutexPtr_next <= mutexPtr;
packetIndexPtr_next <= packetIndexPtr;
foundStringIndexPtr_next <= foundStringIndexPtr;
foundStringsPtr_next <= foundStringsPtr;
sPrimaryCount_next <= sPrimaryCount;
sPrimaryPtr_next <= sPrimaryPtr;
TPtr_next <= TPtr;
i_next <= i;
localTPtr_next <= localTPtr;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= C_FUNCTION_START;
mutexPtr_next <= (others => '0');
packetIndexPtr_next <= (others => '0');
foundStringIndexPtr_next <= (others => '0');
foundStringsPtr_next <= (others => '0');
sPrimaryCount_next <= (others => '0');
sPrimaryPtr_next <= (others => '0');
-- sSecondaryCount_next <= (others => '0');
TPtr_next <= (others => '0');
localTPtr_next <= (others => '0');
i_next <= (others => '0');
reg1_next <= (others => '0');
reg2_next <= (others => '0');
reg3_next <= (others => '0');
reg4_next <= (others => '0');
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_STRUCT_1;
next_state <= WAIT_STATE;
-- argument = (struct threadArgument *) arg;
when READ_STRUCT_1 =>
-- reg1 will hold address of passed in struct
reg1_next <= toUser_value;
-- Read the mutex address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
return_state_next <= READ_STRUCT_2;
next_state <= WAIT_STATE;
when READ_STRUCT_2 =>
mutexPtr_next <= toUser_value;
-- Read the packetIndexPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 4;
return_state_next <= READ_STRUCT_4;
next_state <= WAIT_STATE;
when READ_STRUCT_4 =>
packetIndexPtr_next <= toUser_value;
-- Read the foundStringIndex address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 8;
return_state_next <= READ_STRUCT_5;
next_state <= WAIT_STATE;
when READ_STRUCT_5 =>
foundStringIndexPtr_next <= toUser_value;
-- Read the foundStrings address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 12;
return_state_next <= READ_STRUCT_6;
next_state <= WAIT_STATE;
when READ_STRUCT_6 =>
foundStringsPtr_next <= toUser_value;
-- Read the sPrimaryCount value
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 16;
return_state_next <= READ_STRUCT_7;
next_state <= WAIT_STATE;
when READ_STRUCT_7 =>
sPrimaryCount_next <= toUser_value(20 to 31);
-- Read the sSecondaryCount value
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 20;
return_state_next <= READ_STRUCT_8;
next_state <= WAIT_STATE;
when READ_STRUCT_8 =>
reg2_next <= toUser_value;
-- Read the T address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 24;
return_state_next <= READ_STRUCT_9;
next_state <= WAIT_STATE;
when READ_STRUCT_9 =>
TPtr_next <= toUser_value;
next_state <= ALLOCATE_MEMORY_1;
--Need to allocate two chunks of memory. The first is to hold the
--local copy of T. The second, is to hold the S data structures.
-- localTPtr = malloc( C_PACKET_LENGTH );
when ALLOCATE_MEMORY_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= C_PACKET_LENGTH;
return_state_next <= ALLOCATE_MEMORY_2;
next_state <= WAIT_STATE;
when ALLOCATE_MEMORY_2 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_ALLOCATE_MEMORY_3;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
when ALLOCATE_MEMORY_3 =>
localTPtr_next <= toUser_value;
-- malloc( (reg2 + sPrimaryCount) * 8 )
-- reg2 holds size of sSecondaryCount that was pushed to this thread
-- 8 is the length of a data element in S
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= (reg2(3 to 31) + ("0000000000000000" & sPrimaryCount)) & "000";
return_state_next <= ALLOCATE_MEMORY_4;
next_state <= WAIT_STATE;
when ALLOCATE_MEMORY_4 =>
-- decrementing sPrimaryCount here, so I don't have to instantiate a second adder in the search routine
sPrimaryCount_next <= sPrimaryCount - 1;
-- now back to our regularly scheduled statemachine
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_ALLOCATE_MEMORY_5;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
when ALLOCATE_MEMORY_5 =>
sPrimaryPtr_next <= toUser_value;
next_state <= INDEX_MUTEXLOCK_1;
-- while( 1 ) {
-- hthread_mutex_lock( argument->mutex );
when INDEX_MUTEXLOCK_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexPtr;
return_state_next <= INDEX_MUTEXLOCK_2;
next_state <= WAIT_STATE;
when INDEX_MUTEXLOCK_2 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_INDEX_INCREMENT_1;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
next_state <= WAIT_STATE;
-- index = *argument->packetIndex;
when INDEX_INCREMENT_1 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= packetIndexPtr;
return_state_next <= INDEX_INCREMENT_2;
next_state <= WAIT_STATE;
-- *argument->packetIndex = index + 1;
when INDEX_INCREMENT_2 =>
-- reg1 now holds the index into T (the argument ptr is not longer needed)
reg1_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= packetIndexPtr;
thrd2intrfc_value <= toUser_value + 1;
return_state_next <= INDEX_CHECK_1;
next_state <= WAIT_STATE;
-- if ( index >= NUMBER_PACKETS ) break;
when INDEX_CHECK_1 =>
if ( reg1(24 to 31) >= C_NUMBER_PACKETS ) then
next_state <= INDEX_MUTEXUNLOCK_1;
else
next_state <= COPY_T_1;
end if;
-- T = &argument->T[ index * C_PACKET_LENGTH ];
-- implemented as
-- memcpy( T[index * C_PACKET_LENGTH], localT, C_PACKET_LENGTH )
when COPY_T_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= C_PACKET_LENGTH;
return_state_next <= COPY_T_2;
next_state <= WAIT_STATE;
when COPY_T_2 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= TPtr + (reg1(10 to 31) & "0000000000");
return_state_next <= COPY_T_3;
next_state <= WAIT_STATE;
when COPY_T_3 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= localTPtr;
return_state_next <= COPY_T_4;
next_state <= WAIT_STATE;
when COPY_T_4 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_INDEX_MUTEXUNLOCK_1;
thrd2intrfc_function <= FUNCTION_MEMCPY;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( argument->mutex );
when INDEX_MUTEXUNLOCK_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexPtr;
return_state_next <= INDEX_MUTEXUNLOCK_2;
next_state <= WAIT_STATE;
when INDEX_MUTEXUNLOCK_2 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_INDEX_CHECK_2;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
next_state <= WAIT_STATE;
when INDEX_CHECK_2 =>
if ( reg1(24 to 31) >= C_NUMBER_PACKETS ) then
next_state <= EXIT_THREAD_1;
else
next_state <= CHAR_MATCH_LOOP_1;
end if;
-- for( i = 0; i<1021; i++ ) {
when CHAR_MATCH_LOOP_1 =>
i_next <= (others => '0');
next_state <= CHAR_MATCH_LOOP_2;
when CHAR_MATCH_LOOP_2 =>
case i is
when "1111111101" =>
next_state <= INDEX_MUTEXLOCK_1;
when others =>
next_state <= CHAR_MATCH_LOOP_3;
end case;
-- charString = *(unsigned int *)&T[i];
when CHAR_MATCH_LOOP_3 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= localTPtr(0 to 21) & (localTPtr(22 to 31) + i);
--return_state_next <= CHAR_MATCH_LOOP_4;
return_state_next <= SEARCH_1;
next_state <= WAIT_STATE;
-- subStringPtr = search( charString );
--when CHAR_MATCH_LOOP_4 =>
-- thrd2intrfc_opcode <= OPCODE_PUSH;
-- thrd2intrfc_value <= toUser_value;
-- return_state_next <= CHAR_MATCH_LOOP_5;
-- next_state <= WAIT_STATE;
--when CHAR_MATCH_LOOP_5 =>
-- thrd2intrfc_opcode <= OPCODE_CALL;
-- thrd2intrfc_value <= Z32(0 to 15) & C_CHAR_MATCH_LOOP_6;
-- thrd2intrfc_function <= C_SEARCH_1;
-- next_state <= WAIT_STATE;
-- if ( subStringPtr != NULL ) {
when CHAR_MATCH_LOOP_6 =>
--case toUser_value is
case reg1 is
when Z32 =>
next_state <= CHAR_MATCH_LOOP_14;
when others =>
-- reg1_next <= toUser_value;
next_state <= CHAR_MATCH_LOOP_7;
end case;
-- if ( subStringPtr->stringNumber > 0 ) {
when CHAR_MATCH_LOOP_7 =>
--load the data portion of the S dataset
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1 + 4;
return_state_next <= CHAR_MATCH_LOOP_8;
next_state <= WAIT_STATE;
when CHAR_MATCH_LOOP_8 =>
reg2_next <= toUser_value;
--inspect the stringNumber portion of datapacket
case toUser_value(2 to 13) is
when "000000000000" =>
-- so far, the match does not represent a string
next_state <= CHAR_MATCH_LOOP_11;
when others =>
next_state <= CHAR_MATCH_LOOP_9;
end case;
-- reportString( subStringPtr->stringNumber );
when CHAR_MATCH_LOOP_9 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32(0 to 19) & reg2(2 to 13);
return_state_next <= CHAR_MATCH_LOOP_10;
next_state <= WAIT_STATE;
when CHAR_MATCH_LOOP_10 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_CHAR_MATCH_LOOP_11;
thrd2intrfc_function <= C_REPORT_STRING_1;
next_state <= WAIT_STATE;
-- match( T, i, subStringPtr->nextPtr );
when CHAR_MATCH_LOOP_11 =>
--Check that the nextPtr is not zero
case reg2(15 to 31) is
when "00000000000000000" =>
next_state <= CHAR_MATCH_LOOP_14;
when OTHERS =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"630" & reg2(15 to 31) & "000";
return_state_next <= CHAR_MATCH_LOOP_12;
next_state <= WAIT_STATE;
end case;
when CHAR_MATCH_LOOP_12 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32(0 to 21) & i;
return_state_next <= CHAR_MATCH_LOOP_13;
next_state <= WAIT_STATE;
when CHAR_MATCH_LOOP_13 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_CHAR_MATCH_LOOP_14;
thrd2intrfc_function <= C_MATCH_1;
next_state <= WAIT_STATE;
-- continuation of: for( i = 0; i<1021; i++ ) {
when CHAR_MATCH_LOOP_14 =>
i_next <= i + 1;
next_state <= CHAR_MATCH_LOOP_2;
when EXIT_THREAD_1 =>
-- Return
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
--------------------------------------------------------------------------------
-- struct subString * search (unsigned int charString) {
-- reg1 = charString
-- reg2 = lowIndex
-- reg3 = highIndex
-- reg4 = midIndex
-- reg5 = value of ptr
--------------------------------------------------------------------------------
-- int lowIndex = 0;
-- int highIndex = globalSPrimaryCount-1;
when SEARCH_1 =>
reg1_next <= toUser_value;
-- initializing variables as pointers instead of indexes
-- note that sPrimaryCount was decremented in ALLOCATE_MEMORY_4
reg2_next <= sPrimaryPtr;
reg3_next <= sPrimaryPtr(0 to 16) & (sPrimaryPtr(17 to 28) + sPrimaryCount) & "000";
-- pop the charString
--thrd2intrfc_opcode <= OPCODE_POP;
--thrd2intrfc_value <= Z32;
return_state_next <= SEARCH_2;
next_state <= WAIT_STATE;
-- if ( charString < globalSPrimary[lowIndex].charString ) return NULL;
-- if ( charString == globalSPrimary[lowIndex].charString ) return &globalSPrimary[lowIndex];
when SEARCH_2 =>
--reg1_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
return_state_next <= SEARCH_3;
next_state <= WAIT_STATE;
when SEARCH_3 =>
if ( reg1 < toUser_value ) then
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= Z32;
--next_state <= WAIT_STATE;
reg1_next <= Z32;
next_state <= CHAR_MATCH_LOOP_6;
elsif (reg1 = toUser_value ) then
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= reg2;
--next_state <= WAIT_STATE;
reg1_next <= reg2;
next_state <= CHAR_MATCH_LOOP_6;
else
next_state <= SEARCH_4;
end if;
-- if ( charString > globalSPrimary[highIndex].charString ) return NULL;
-- if ( charString == globalSPrimary[highIndex].charString ) return &globalSPrimary[highIndex];
when SEARCH_4 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg3;
return_state_next <= SEARCH_5;
next_state <= WAIT_STATE;
when SEARCH_5 =>
if ( reg1 > toUser_value ) then
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= Z32;
--next_state <= WAIT_STATE;
reg1_next <= Z32;
next_state <= CHAR_MATCH_LOOP_6;
elsif (reg1 = toUser_value ) then
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= reg3;
--next_state <= WAIT_STATE;
reg1_next <= reg3;
next_state <= CHAR_MATCH_LOOP_6;
else
next_state <= SEARCH_6;
end if;
-- while ( lowIndex <= highIndex ) {
-- midIndex = (lowIndex + highIndex) / 2;
-- ...
-- }
-- return NULL
when SEARCH_6 =>
if ( reg2 <= reg3 ) then
reg4_next <= Z32(0 to 15) & (reg2(16 to 31) + reg3(16 to 31));
next_state <= SEARCH_6a;
else
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= Z32;
--next_state <= WAIT_STATE;
reg1_next <= Z32;
next_state <= CHAR_MATCH_LOOP_6;
end if;
when SEARCH_6a =>
reg4_next <= reg2(0 to 16) & reg4(16 to 27) & "000";
next_state <= SEARCH_7;
-- if ( charString > globalSPrimary[midIndex].charString ) lowIndex = midIndex+1;
-- else if ( charString < globalSPrimary[midIndex].charString ) highIndex = midIndex-1;
-- else return &globalSPrimary[midIndex];
when SEARCH_7 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
return_state_next <= SEARCH_8;
next_state <= WAIT_STATE;
when SEARCH_8 =>
if ( reg1 > toUser_value ) then
reg2_next <= reg4 + 8;
next_state <= SEARCH_6;
elsif ( reg1 < toUser_value ) then
reg3_next <= reg4 - 8;
next_state <= SEARCH_6;
else
--thrd2intrfc_opcode <= OPCODE_RETURN;
--thrd2intrfc_value <= reg3;
--next_state <= WAIT_STATE;
reg1_next <= reg3;
next_state <= CHAR_MATCH_LOOP_6;
end if;
--------------------------------------------------------------------------------
-- void match( int tIndex, struct subString * subStringPtr ) {
-- reg1 = tIndex
-- reg2 = subStringPtr
-- reg3 = charString
-- reg4 = data
--------------------------------------------------------------------------------
-- Save reg1 .. reg4
when MATCH_1 =>
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000004";
return_state_next <= MATCH_2;
next_state <= WAIT_STATE;
when MATCH_2 =>
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= reg1;
thrd2intrfc_address <= Z32;
return_state_next <= MATCH_3;
next_state <= WAIT_STATE;
when MATCH_3 =>
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= reg2;
thrd2intrfc_address <= x"00000001";
return_state_next <= MATCH_3a;
next_state <= WAIT_STATE;
when MATCH_3a =>
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= reg3;
thrd2intrfc_address <= x"00000002";
return_state_next <= MATCH_3b;
next_state <= WAIT_STATE;
when MATCH_3b =>
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= reg4;
thrd2intrfc_address <= x"00000003";
return_state_next <= MATCH_4;
next_state <= WAIT_STATE;
-- read the value of passed in parameters
when MATCH_4 =>
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
return_state_next <= MATCH_5;
next_state <= WAIT_STATE;
when MATCH_5 =>
reg1_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= x"00000001";
return_state_next <= MATCH_6;
next_state <= WAIT_STATE;
-- if ( tIndex >= 1020 ) return;
-- charString = *(unsigned int *)&T[ tIndex+4 ];
when MATCH_6 =>
reg2_next <= toUser_value;
if ( reg1 >= 1020 ) then
next_state <= MATCH_18;
else
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= TPtr + reg1 + 4;
return_state_next <= MATCH_7;
next_state <= WAIT_STATE;
end if;
-- if ( (subStringPtr->ignore==0 & charString == subStringPtr->charString)
-- || (subStringPtr->ignore==1 && (charString & 0xFFFFFF00) == (subStringPtr->charString & 0xFFFFFF00) )
-- || (subStringPtr->ignore==2 && (charString & 0xFFFF0000) == (subStringPtr->charString & 0xFFFF0000) )
-- || (subStringPtr->ignore==3 && (charString & 0xFF000000) == (subStringPtr->charString & 0xFF000000) ) ) {
when MATCH_7 =>
reg3_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2+4;
return_state_next <= MATCH_8;
next_state <= WAIT_STATE;
when MATCH_8 =>
reg4_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
return_state_next <= MATCH_9;
next_state <= WAIT_STATE;
when MATCH_9 =>
case reg4(0 to 1) is
when "00" => -- ignore=0
if ( toUser_value = reg3 ) then
next_state <= MATCH_10;
else
next_state <= MATCH_15;
end if;
when "01" => -- ignore=1
if ( toUser_value(0 to 23) = reg3(0 to 23) ) then
next_state <= MATCH_10;
else
next_state <= MATCH_15;
end if;
when "10" => -- ignore=2
if ( toUser_value(0 to 15) = reg3(0 to 15) ) then
next_state <= MATCH_10;
else
next_state <= MATCH_15;
end if;
when OTHERS => -- ignore=3
if ( toUser_value(0 to 7) = reg3(0 to 7) ) then
next_state <= MATCH_10;
else
next_state <= MATCH_15;
end if;
end case;
-- if ( subStringPtr->stringNumber > 0 ) {
-- reportString( subStringPtr->stringNumber );
-- }
when MATCH_10 =>
case reg4(3 to 14) is
when "000000000000" =>
next_state <= MATCH_12;
when OTHERS =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32(0 to 19) & reg4(2 to 13);
return_state_next <= MATCH_11;
next_state <= WAIT_STATE;
end case;
when MATCH_11 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_MATCH_12;
thrd2intrfc_function <= C_REPORT_STRING_1;
next_state <= WAIT_STATE;
-- if ( subStringPtr->nextPtr != NULL ) {
-- match( T, tIndex+4, subStringPtr->nextPtr );
-- }
when MATCH_12 =>
case reg4(15 to 31) is
when "00000000000000000" =>
next_state <= MATCH_15;
when OTHERS =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"630" & reg4(15 to 31) & "000";
return_state_next <= MATCH_13;
next_state <= WAIT_STATE;
end case;
when MATCH_13 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1 + 4;
return_state_next <= MATCH_14;
next_state <= WAIT_STATE;
when MATCH_14 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_MATCH_15;
thrd2intrfc_function <= C_MATCH_1;
next_state <= WAIT_STATE;
-- if ( subStringPtr->parrallelPtr != NULL ) {
-- match( T, tIndex, subStringPtr->parrallelPtr );
-- }
when MATCH_15 =>
case reg4(14) is
when '0' =>
next_state <= MATCH_18;
when OTHERS =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2 + 8;
return_state_next <= MATCH_16;
next_state <= WAIT_STATE;
end case;
when MATCH_16 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
return_state_next <= MATCH_17;
next_state <= WAIT_STATE;
when MATCH_17 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_MATCH_18;
thrd2intrfc_function <= C_MATCH_1;
next_state <= WAIT_STATE;
-- restore all the registers before returning
when MATCH_18 =>
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= Z32;
return_state_next <= MATCH_19;
next_state <= WAIT_STATE;
when MATCH_19 =>
reg1_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= x"00000001";
return_state_next <= MATCH_20;
next_state <= WAIT_STATE;
when MATCH_20 =>
reg2_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= x"00000002";
return_state_next <= MATCH_21;
next_state <= WAIT_STATE;
when MATCH_21 =>
reg3_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= x"00000003";
return_state_next <= MATCH_22;
next_state <= WAIT_STATE;
when MATCH_22 =>
reg4_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
--------------------------------------------------------------------------------
-- report_string(int stringNumber);
-- reg1 value of foundStringsIndexPtr
--------------------------------------------------------------------------------
-- Save reg1
when REPORT_STRING_1 =>
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000001";
return_state_next <= REPORT_STRING_2;
next_state <= WAIT_STATE;
when REPORT_STRING_2 =>
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= reg1;
return_state_next <= REPORT_STRING_3;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( mutex );
when REPORT_STRING_3 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexPtr;
return_state_next <= REPORT_STRING_4;
next_state <= WAIT_STATE;
when REPORT_STRING_4 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_REPORT_STRING_5;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
next_state <= WAIT_STATE;
-- index = *globalFoundStringIndex;
when REPORT_STRING_5 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= foundStringIndexPtr;
return_state_next <= REPORT_STRING_6;
next_state <= WAIT_STATE;
-- globalFoundStrings[ index ] = stringNum;
when REPORT_STRING_6 =>
reg1_next <= toUser_value;
-- pop the stringNum
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
return_state_next <= REPORT_STRING_7;
next_state <= WAIT_STATE;
when REPORT_STRING_7 =>
-- store the string number to the foundStrings array
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= toUser_value;
thrd2intrfc_address <= foundStringsPtr + (reg1(2 to 31) & "00");
return_state_next <= REPORT_STRING_8;
next_state <= WAIT_STATE;
-- *globalFoundStringIndex = index+1;
when REPORT_STRING_8 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= foundStringIndexPtr;
thrd2intrfc_value <= reg1 + 1;
return_state_next <= REPORT_STRING_9;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when REPORT_STRING_9 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexPtr;
return_state_next <= REPORT_STRING_10;
next_state <= WAIT_STATE;
when REPORT_STRING_10 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & C_REPORT_STRING_11;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
next_state <= WAIT_STATE;
-- restore all the registers before returning
when REPORT_STRING_11 =>
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= Z32;
return_state_next <= REPORT_STRING_12;
next_state <= WAIT_STATE;
when REPORT_STRING_12 =>
reg1_next <= toUser_value;
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
--------------------------------------------------------------------------------
-- Common states
--------------------------------------------------------------------------------
when ERROR_STATE =>
next_state <= ERROR_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 75c188ee2221945409b5997439239a00 | 0.525008 | 4.035963 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/opb_SynchManager.vhd | 10 | 35,627 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
| bsd-3-clause | 5aee11e26af43644820e8b71b7fc4231 | 0.519662 | 4.080518 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/Reg_addr.vhd | 1 | 1,452 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:49:07 11/11/2015
-- Design Name:
-- Module Name: Reg_addr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Reg_addr is
port( Re_clk: in std_logic;
Re_rst: in std_logic;
Re_ld: in std_logic;
Re_reg_in: in std_logic_vector(4 downto 0);
Re_reg_out: out std_logic_vector(4 downto 0)
);
end Reg_addr;
architecture Behavioral of Reg_addr is
begin
process(Re_clk, Re_rst, Re_ld)
begin
if Re_rst = '1' then
Re_reg_out<=(others=>'0');
--if (Re_rst='1') then
--Re_reg_out <= (Re_reg_out'range=>'0');
elsif (Re_clk'event and Re_clk='1') and (Re_ld='1') then
-- if (Re_ld='1') then
Re_reg_out <= Re_reg_in;
--end if;
end if;
end process;
end Behavioral;
| unlicense | 28c8506494ff11fe4b0d69927512b6a1 | 0.55303 | 3.384615 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_4.vhd | 2 | 17,135 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_4.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
--retVal = _read_thread_status( data->thread );
when STATE_12 =>
--Prepare cmd to send to Thread Manager
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"60000A00" and ( reg7(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
--retVal = retVal & 0x00000010;
when STATE_13 =>
retVal_next <= intrfc2thrd_value and x"00000010";
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b6ce5dd6f128b4f56d9c682de297238f | 0.544091 | 3.806932 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmISP.vhd | 1 | 3,235 | ---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmISP
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity zcpsmISP is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port(
reset : in std_logic;
clk : in std_logic;
port_ce : out std_logic_vector(15 downto 0);
port_id : out std_logic_vector(3 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
prog_we : in std_logic;
prog_clk: in std_logic;
prog_addr : in std_logic_vector( AWIDTH-1 downto 0 );
prog_din : in std_logic_vector( 17 downto 0 )
);
end zcpsmISP;
--}} End of automatically maintained section
architecture behavior of zcpsmISP is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic
);
end component;
component zcpsmProgRam
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
reset: in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 );
soft_rst : out std_logic;
prog_we : in std_logic;
prog_clk: in std_logic;
prog_addr : in std_logic_vector( AWIDTH-1 downto 0 );
prog_din : in std_logic_vector( 17 downto 0 )
);
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id_i : std_logic_vector(7 downto 0);
signal soft_reset : std_logic;
signal zcpsm_reset : std_logic;
begin
port_id <= port_id_i( 3 downto 0 );
zcpsm_reset <= reset or soft_reset;
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id_i,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => zcpsm_reset,
clk => clk
);
u_ram : zcpsmProgRam
generic map(
AWIDTH => 10,
PROG => PROG
)
port map(
clk => clk,
reset => reset,
addr => address( AWIDTH-1 downto 0 ),
dout => instruction,
soft_rst => soft_reset,
prog_we => prog_we,
prog_clk => prog_clk,
prog_addr => prog_addr,
prog_din => prog_din
);
u_decode : zcpsmDecode
port map(
port_id_H => port_id_i( 7 downto 4 ),
ce => port_ce
);
end behavior;
| gpl-2.0 | fb3974d28bf44ed3a490990e80ea23e1 | 0.56136 | 2.981567 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutexattr_init_2.vhd | 2 | 16,744 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_2.c
-- arg = * data
-- reg1 = * mutex
-- reg2 = * mutex_attr
-- The return value should be the mutexattr->num set by either the
-- software main thread, or the bfl in case of simulation.
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the value of mutex
thrd2intrfc_address <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Read the value of mutex_attr
thrd2intrfc_address <= arg + 4;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_mutexattr_init( data->attr );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_mutex_init( data->mutex, data->attr );
when STATE_5 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- data->attr->num = 4;
when STATE_8 =>
-- Store '4' for the value of attr->num
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= x"00000004";
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
--retVal = data->mutex->num
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fd07f6c135bf624ca742b98447b61d6e | 0.547062 | 3.794244 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/trylock_fsm.vhd | 11 | 6,378 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
| bsd-3-clause | d4a8d21212cda4bec4983937e18ee304 | 0.503449 | 4.300742 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/parallel.vhd | 11 | 9,985 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
end if;
end if;
end process find_best_next;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
case find_current is
when narrow_search =>
if( enable = '1' ) then
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
| bsd-3-clause | 00b8b383c3467fb9251b567ddaade009 | 0.66009 | 3.767925 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_slave_attach_sngl.vhd | 2 | 31,414 | -------------------------------------------------------------------------------
-- $Id: xbic_slave_attach_sngl.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_slave_attach_sngl.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_slave_attach_sngl.vhd
-- Version: v1_00_a
-- Description: Custom PLB slave attachment supporting only PLB single
-- beat transfers.
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- -- xbic_data_mirror_128.vhd
-- -- xbic_slave_attach_sngl.vhd
-- -- xbic_addr_reg_cntr_brst_flex.vhd
-- -- xbic_flex_addr_cntr.vhd
-- -- xbic_be_reset_gen.vhd
-- -- xbic_addr_be_support.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET Feb-9-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from xps_bram_if_cntlr_v1_00_b library
-- -- Bypassed input address and qualifiers registering to remove
-- one clock of latency during address phase.
-- -- Optimized for PLBV46 Baseline op mode
-- ^^^^^^
--
-- DET 6/5/2007 jm.10
-- ~~~~~~
-- - Added the request validation to the wait assertion logic.
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a library.
-- - Updated this core's library reference to V1_00_b.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_type"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
library xps_bram_if_cntlr_v1_00_b;
use xps_bram_if_cntlr_v1_00_b.xbic_addr_decode;
use xps_bram_if_cntlr_v1_00_b.xbic_addr_be_support;
use xps_bram_if_cntlr_v1_00_b.xbic_data_steer_mirror;
-------------------------------------------------------------------------------
entity xbic_slave_attach_sngl is
generic (
C_STEER_ADDR_SIZE : integer := 10;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_type :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF" -- IP user0 high address
);
C_SPLB_NUM_MASTERS : integer := 4;
C_SPLB_MID_WIDTH : integer := 2;
C_SPLB_P2P : integer := 0;
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : Integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_SMALLEST_MASTER : Integer := 32;
C_FAMILY : string := "virtex4"
);
port(
--System signals
Bus_Rst : in std_logic;
Bus_Clk : in std_logic;
-- PLB Bus signals
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector
(0 to C_SPLB_MID_WIDTH - 1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector
(0 to (C_SPLB_DWIDTH/8)-1);
PLB_Msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Controls to the IP/IPIF modules
Bus2Bram_CS : out std_logic;
Bus2Bram_WrReq : out std_logic;
Bus2Bram_RdReq : out std_logic;
Bus2Bram_Addr : out std_logic_vector (0 to C_SPLB_AWIDTH-1);
Bus2Bram_BE : out std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH/8-1);
Bus2Bram_WrData : out std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH-1);
-- Inputs from the BRAM interface logic
Bram2Bus_RdData : in std_logic_vector (0 to C_SPLB_NATIVE_DWIDTH-1);
Bram2Bus_WrAck : in std_logic;
Bram2Bus_RdAck : in std_logic
);
end entity xbic_slave_attach_sngl;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture implementation of xbic_slave_attach_sngl is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- Functions Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: encode_slave_size
--
-- Function Description:
-- This function encodes the Slave Native Data Width into
-- a 2-bit field for PLB_Ssize output.
--
-------------------------------------------------------------------
function encode_slave_size(native_dwidth : integer)
return std_logic_vector is
variable temp_size : std_logic_vector(0 to 1);
begin
case native_dwidth is
when 64 =>
temp_size := "01"; -- 64 bits wide
when 128 =>
temp_size := "10"; -- 128 bits wide
when others =>
temp_size := "00"; -- 32 bits wide
end case;
Return(temp_size);
end function encode_slave_size;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Fix the Slave Size response to the PLB DBus width
-- note "00" = 32 bits wide
-- "01" = 64 bits wide
-- "10" = 128 bits wide
constant SLAVE_SIZE : std_logic_vector(0 to 1) :=
encode_slave_size(C_SPLB_NATIVE_DWIDTH);
Constant STEER_ADDR_SIZE : integer := 5;
-------------------------------------------------------------------------------
-- Signal and type Declarations
-------------------------------------------------------------------------------
-- Intermediate Slave Reply output signals (to PLB)
signal sl_addrack_i : std_logic;
signal sl_wait_i : std_logic;
signal sl_rearbitrate_i : std_logic;
signal sl_wrdack_i : std_logic;
signal sl_wrbterm_i : std_logic;
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
signal sl_rddack_i : std_logic;
signal sl_rdcomp_i : std_logic;
signal sl_mbusy_i : std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
signal bus2ip_cs_i : std_logic;
signal bus2ip_wrreq_i : std_logic;
signal bus2ip_rdreq_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(0 to
C_SPLB_AWIDTH-1);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_be_i : std_logic_vector(0 to
(C_SPLB_NATIVE_DWIDTH/8)-1);
signal bus2ip_data_i : std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rddata_i : std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
signal valid_plb_type : boolean := False;
signal valid_plb_size : Boolean := False;
signal single_transfer : std_logic;
signal cacheln_transfer : std_logic;
signal burst_transfer : std_logic;
signal sig_valid_request : std_logic;
signal sig_internal_be : std_logic_vector(0 to
(C_SPLB_NATIVE_DWIDTH/8)-1);
signal sig_combined_abus : std_logic_vector(0 to
C_SPLB_AWIDTH-1);
signal sig_steer_addr : std_logic_vector(0 to
STEER_ADDR_SIZE-1);
signal sig_addr_decode_hit : std_logic;
signal sig_clr_addrack : std_logic;
signal sig_sl_busy : std_logic;
signal sig_clear_sl_busy : std_logic;
signal sig_set_sl_busy : std_logic;
Signal sig_clr_rearbitrate : std_logic;
-- DET signal rearbitrate_condition : std_logic;
signal wait_condition : std_logic;
Signal sig_clr_wait : std_logic;
signal sig_do_cmd : std_logic;
signal sig_cmd_cmplt : std_logic;
signal sig_clr_qualifiers : std_logic;
signal sig_mst_id : std_logic_vector(0 to
C_SPLB_MID_WIDTH-1);
signal sig_mst_id_int : integer range 0 to
C_SPLB_NUM_MASTERS-1 := 0;
signal sig_rd_dreg : std_logic_vector(0 to
C_SPLB_DWIDTH-1);
signal sig_rd_data_mirror_steer : std_logic_vector(0 to
C_SPLB_DWIDTH-1);
signal sig_rd_data_128 : std_logic_vector(0 to 127);
Signal sig_wr_req : std_logic;
Signal sig_ld_wr_dreg : std_logic;
signal sig_wr_dreg : std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
signal sig_clr_rdack : std_logic;
signal sig_plb_done : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
------------------------------------------------------------------
-- Misc. Logic Assignments
------------------------------------------------------------------
-- PLB Output port connections
Sl_addrAck <= sl_addrack_i ;
Sl_wait <= sl_wait_i ;
Sl_rearbitrate <= sl_rearbitrate_i ;
Sl_wrDAck <= sl_wrdack_i ;
Sl_wrComp <= sl_wrdack_i ;
Sl_wrBTerm <= '0' ;
Sl_rdDBus <= sl_rddbus_i ;
Sl_rdWdAddr <= (others => '0') ;
Sl_rdDAck <= sl_rddack_i ;
Sl_rdComp <= sl_rdcomp_i ;
Sl_rdBTerm <= '0' ;
Sl_MBusy <= sl_mbusy_i ;
Sl_MRdErr <= (others => '0') ;
Sl_MWrErr <= (others => '0') ;
Sl_SSize <= SLAVE_SIZE
when (sig_set_sl_busy = '1')
Else "00";
sl_rddbus_i <= sig_rd_dreg;
sl_rdcomp_i <= ip2bus_rdack_i;
sl_rearbitrate_i <= '0';
-- Backend output signals
Bus2Bram_CS <= bus2ip_cs_i ;
Bus2Bram_WrReq <= bus2ip_wrreq_i ;
Bus2Bram_RdReq <= bus2ip_rdreq_i ;
Bus2Bram_Addr <= bus2ip_addr_i ;
Bus2Bram_BE <= bus2ip_be_i ;
Bus2Bram_WrData <= bus2ip_data_i ;
-- Backend input signals
ip2bus_wrack_i <= Bram2Bus_WrAck ;
ip2bus_rdack_i <= Bram2Bus_RdAck ;
ip2bus_rddata_i <= Bram2Bus_RdData ;
bus2ip_data_i <= sig_wr_dreg;
--GAB - was kicking off a cycle even when the cycle was not a valid cycle, i.e. cachelines etc.
--GAB sig_do_cmd <= (sig_addr_decode_hit and
--GAB not(sig_sl_busy)) or
--GAB (sig_addr_decode_hit and
--GAB sig_clear_sl_busy);
sig_do_cmd <= sig_valid_request and
(
(sig_addr_decode_hit and
not(sig_sl_busy)) or
(sig_addr_decode_hit and
sig_clear_sl_busy)
);
-- DET -- Rearbitrate if another address hit occurs and slave is busy
-- DET rearbitrate_condition <= sig_addr_decode_hit
-- DET and sig_sl_busy
-- DET and not(sig_clear_sl_busy);
sig_mst_id_int <= CONV_INTEGER(sig_mst_id);
sig_clr_qualifiers <= sig_clear_sl_busy and
not(sig_do_cmd);
sig_ld_wr_dreg <= sig_set_sl_busy and
sig_wr_req;
-- Wait FLOP
-- DET This logic was not screening invalid requests
-- DET
-- DET wait_condition <= sig_addr_decode_hit
-- DET and sig_sl_busy;
wait_condition <= sig_valid_request and
sig_addr_decode_hit and
sig_sl_busy;
sig_clr_wait <= Bus_Rst or
sig_set_sl_busy;
I_FLOP_REARB : FDRE
port map(
Q => sl_wait_i ,
C => Bus_clk ,
CE => wait_condition ,
D => '1' ,
R => sig_clr_wait
);
-- Address Acknowledge Flops (needed for register duplication)
-- sig_clr_addrack <= Bus_Rst or
-- sig_set_sl_busy or
-- sig_sl_busy;
sig_clr_addrack <= Bus_Rst or
sig_set_sl_busy or
(sig_sl_busy and
not(sig_clear_sl_busy));
I_FLOP_ADDRACK : FDRE
port map(
Q => sl_addrack_i ,
C => Bus_clk ,
CE => sig_do_cmd ,
D => '1' ,
R => sig_clr_addrack
);
I_FLOP_SET_SLBUSY : FDRE
port map(
Q => sig_set_sl_busy,
C => Bus_clk ,
CE => sig_do_cmd ,
D => '1' ,
R => sig_clr_addrack
);
-- Write Acknowledge FLOP (WrAck is Same as Address Acknowledge signal)
-- Requires register duplication
sig_wr_req <= not(PLB_RNW);
I_FLOP_WRACK : FDRE
port map(
Q => sl_wrdack_i ,
C => Bus_clk ,
CE => sig_do_cmd ,
D => sig_wr_req ,
R => sig_clr_addrack
);
-- Read Acknowledge FLOPS needed for register duplication
sig_clr_rdack <= Bus_Rst or
not(bus2ip_rdreq_i);
I_FLOP_RDACK : FDRE
port map(
Q => sl_rddack_i ,
C => Bus_clk ,
CE => bus2ip_rdreq_i ,
D => ip2bus_rdack_i ,
R => sig_clr_rdack
);
sig_plb_done <= (ip2bus_rdack_i and bus2ip_rdreq_i) or
(ip2bus_wrack_i and bus2ip_wrreq_i);
I_FLOP_CLR_SL_BUSY : FDRE
port map(
Q => sig_clear_sl_busy,
C => Bus_clk ,
CE => sig_plb_done ,
D => '1' ,
R => sig_clear_sl_busy
);
------------------------------------------------------------
-- Instance: I_ADDR_BE_SUPRT
--
-- Description:
-- This instantiates the address and be support module.
--
------------------------------------------------------------
I_ADDR_BE_SUPRT : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_be_support
generic map (
C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
-- Inputs from PLB
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus ,
PLB_BE => PLB_BE ,
PLB_Msize => PLB_Msize,
-- Outputs to Internal logic
Internal_ABus => sig_combined_abus,
Internal_BE => sig_internal_be
);
-------------------------------------------------------------------------------
-- PLB Size Validation
-- This combinatorial process validates the PLB request attribute PLB_Size
-- that is supported by this slave. Slave Single only responds to single
-- data beat requests.
-------------------------------------------------------------------------------
VALIDATE_SIZE : process (PLB_Size)
begin
case PLB_Size is
-- single data beat transfer
when "0000" => -- one to eight bytes
valid_plb_size <= true;
single_transfer <= '1';
cacheln_transfer <= '0';
burst_transfer <= '0';
-- -- cacheline transfer
-- when "0001" | -- 4 word cache-line
-- "0010" | -- 8 word cache-line
-- "0011" => -- 16 word cache-line
--
-- valid_plb_size <= true;
-- single_transfer <= '0';
-- cacheln_transfer <= '1';
-- burst_transfer <= '0';
--
-- -- burst transfer (fixed length)
-- when "1000" | -- byte burst transfer
-- "1001" | -- halfword burst transfer
-- "1010" | -- word burst transfer
-- "1011" | -- double word burst transfer
-- "1100" => -- quad word burst transfer
-- -- octal widths are not allowed (256 wide bus)
--
-- valid_plb_size <= true;
-- single_transfer <= '0';
-- cacheln_transfer <= '0';
-- burst_transfer <= '1';
when others =>
valid_plb_size <= false;
single_transfer <= '0';
cacheln_transfer <= '0';
burst_transfer <= '0';
end case;
end process VALIDATE_SIZE;
-------------------------------------------------------------------------------
-- PLB Size Validation
-- This combinatorial process validates the PLB request attribute PLB_type
-- that is supported by this slave.
-------------------------------------------------------------------------------
VALIDATE_type : process (PLB_type)
begin
if(PLB_type="000")then
valid_plb_type <= true;
else
valid_plb_type <= false;
end if;
end process VALIDATE_type;
-------------------------------------------------------------------------------
-- Access Validation
-- This combinatorial process validates the PLB request attributes that are
-- supported by this slave.
-------------------------------------------------------------------------------
VALIDATE_REQUEST : process (PLB_PAvalid,
valid_plb_size,
valid_plb_type)
begin
if (PLB_PAvalid = '1') and -- Address Request
(valid_plb_size) and -- and a valid plb_size
(valid_plb_type) then -- and a memory xfer
sig_valid_request <= '1';
else
sig_valid_request <= '0';
end if;
end process VALIDATE_REQUEST;
------------------------------------------------------------
-- If Generate
--
-- Label: P2P_MODE_ENABLED
--
-- If Generate Description:
-- P2P Mode enabled so this IfGen removes the Address
-- Decoding function.
--
--
------------------------------------------------------------
P2P_MODE_ENABLED : if (C_SPLB_P2P = 1) generate
begin
-- Address Decoder Removed in P2P mode
sig_addr_decode_hit <= sig_valid_request;
end generate P2P_MODE_ENABLED;
------------------------------------------------------------
-- If Generate
--
-- Label: SHARED_MODE_ENABLED
--
-- If Generate Description:
-- Shared bus mode so include Address Decoder.
--
--
------------------------------------------------------------
SHARED_MODE_ENABLED : if (C_SPLB_P2P = 0) generate
begin
------------------------------------------------------------------
-- Address Decoder Component Instance
-- This component decodes the specified base address pair and
-- outputs the decode hit indication.
------------------------------------------------------------------
I_ADDR_DECODER : entity xps_bram_if_cntlr_v1_00_b.xbic_addr_decode
generic map(
C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_FAMILY => C_FAMILY
)
port map(
-- PLB Interface signals
Address_In => sig_combined_abus,
Address_Valid => sig_valid_request,
-- Decode output signals
Addr_Match => sig_addr_decode_hit
);
end generate SHARED_MODE_ENABLED;
---------------------------------------------------------------------
-- Generate the Slave Busy
-- This process implements the FLOP that indicates the Slave is Busy
-- with a command. The output of the FLOP is used internally.
---------------------------------------------------------------------
GENERATE_SL_BUSY : process (Bus_clk)
begin
if (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus_Rst = '1' or
sig_clear_sl_busy = '1') then
sig_sl_busy <= '0';
elsif (sig_set_sl_busy = '1') Then
sig_sl_busy <= '1';
else
null; -- hold current state
end if;
end if;
end process GENERATE_SL_BUSY;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_SL_MBUSY
--
-- Process Description:
-- This process implements the flops that drive the SL_MBusy
-- to the PLB. There is one FLOP per Master.
--
-------------------------------------------------------------
DO_SL_MBUSY : process(Bus_clk)
begin
if (Bus_clk'EVENT and Bus_clk = '1') Then
for i in 0 to C_SPLB_NUM_MASTERS - 1 loop
if (Bus_Rst = '1') then
sl_mbusy_i(i) <= '0';
elsif (i=sig_mst_id_int)then
if (sig_set_sl_busy = '1') Then
sl_mbusy_i(i) <= '1'; -- set specific bit for req master
elsif (sig_clear_sl_busy = '1') Then
sl_mbusy_i(i) <= '0'; -- clear specific bit for req master
end if;
else
sl_mbusy_i(i) <= '0';
end if;
end loop;
end if;
end process DO_SL_MBUSY;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_XFER_QUALIFIERS
--
-- Process Description:
-- This process implements the register that samples and holds
-- the command qualifiers
--
-------------------------------------------------------------
REG_XFER_QUALIFIERS : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
sig_clr_qualifiers = '1') then
bus2ip_cs_i <= '0';
bus2ip_wrreq_i <= '0';
bus2ip_rdreq_i <= '0';
bus2ip_addr_i <= (others => '0');
bus2ip_be_i <= (others => '0');
sig_mst_id <= (others => '0');
sig_steer_addr <= (others => '0');
elsif (sig_do_cmd = '1') then
bus2ip_cs_i <= '1';
bus2ip_wrreq_i <= not(PLB_RNW);
bus2ip_rdreq_i <= PLB_RNW;
bus2ip_addr_i <= sig_combined_abus;
bus2ip_be_i <= sig_internal_be;
sig_mst_id <= PLB_masterID;
sig_steer_addr <= sig_combined_abus(C_SPLB_AWIDTH -
C_STEER_ADDR_SIZE to
C_SPLB_AWIDTH-1);
else
null; -- hold state
end if;
end if;
end process REG_XFER_QUALIFIERS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_WR_DREG
--
-- Process Description:
-- This process implements the Write Data Register.
--
-------------------------------------------------------------
DO_WR_DREG : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
bus2ip_wrreq_i = '0') then
sig_wr_dreg <= (others => '0');
elsif (sig_ld_wr_dreg = '1') then
sig_wr_dreg <= PLB_wrDBus(0 to C_SPLB_NATIVE_DWIDTH-1);
else
null; -- hold current state
end if;
end if;
end process DO_WR_DREG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_DATA_REG
--
-- Process Description:
-- This process implements the Read Data Register.
-- Mirroring and Steeering is assumed to be done on the
-- input data to the register.
-------------------------------------------------------------
RD_DATA_REG : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_rd_dreg <= (others => '0');
elsif (ip2bus_rdack_i = '1') then
sig_rd_dreg <= sig_rd_data_mirror_steer;
else
sig_rd_dreg <= (others => '0');
end if;
end if;
end process RD_DATA_REG;
------------------------------------------------------------
-- Instance: I_MIRROR_STEER
--
-- Description:
-- This instantiates a parameterizable Mirror ands Steering
-- support module.
--
------------------------------------------------------------
I_MIRROR_STEER : entity xps_bram_if_cntlr_v1_00_b.xbic_data_steer_mirror
generic map (
C_STEER_ADDR_WIDTH => STEER_ADDR_SIZE ,
C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
C_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER
)
port map (
Steer_Addr_In => sig_steer_addr ,
Data_In => ip2bus_rddata_i ,
Data_Out => sig_rd_data_mirror_steer
);
end implementation;
| bsd-3-clause | 911e26a60ac149f0ea00ca213dc4d5d0 | 0.446202 | 4.174618 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/srl_fifo2.vhd | 3 | 14,481 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| bsd-3-clause | bece0d118033bfeabf83331481c4bdd8 | 0.465368 | 4.311104 | false | false | false | false |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/fpga_pkg_2_16zyyy.vhd | 1 | 2,844 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for IP-Core top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_16zyyy.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_16zyyy.vhd
-- - many_devices.vhd
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_16zyyy.vhd,v $
-- Revision 1.2 2009/02/17 11:37:42 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:57 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/24 16:39:58 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_16zyyy IS
GENERIC (
FPGA_FAMILY : family_type := CYCLONE
);
PORT(
dummy : IN std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_16zyyy_arch OF fpga_pkg_2_16zyyy IS
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE, CYCLONE2, A3P, ARRIA_GX);
COMPONENT many_devices
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
-- coverage off
ASSERT NOT NO_VALID_DEVICE(SUPPORTED_DEVICES => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "No valid DEVICE!" SEVERITY failure;
-- coverage on
the_many_devices : many_devices
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy
);
END ARCHITECTURE fpga_pkg_2_16zyyy_arch;
| gpl-3.0 | 7709001743e01f0554118a96b912fa51 | 0.450774 | 4.57971 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_mstr.vhd | 1 | 23,774 | --------------------------------------------------------------------------------
-- Title : DMA Master FSM
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_mstr.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 18/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of the main fsm for the dma.
-- It handles all actions which are required for dma
-- transmissions, including the wbm control signals.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_mstr
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: vme_dma_mstr.vhd,v $
-- Revision 1.4 2013/01/24 12:47:16 MMiehling
-- bugfix: termination by clearing dma_en bit interrupted wbb access => now wait until next ack is set and then terminate dma access
--
-- Revision 1.3 2012/09/25 11:21:45 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:16 MMiehling
-- added prep_write2/3 states for correct fifo handling
--
-- Revision 1.1 2012/03/29 10:14:42 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:02:26 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:26 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:19:43 mmiehling
-- improved timing
--
-- Revision 1.3 2004/08/13 15:41:16 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:26 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:52 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY vme_dma_mstr IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_master_bus
stb_o : OUT std_logic; -- request for wb_mstr_bus
ack_i : IN std_logic; -- acknoledge from wb_mstr_bus
err_i : IN std_logic; -- error answer from slave
cti : OUT std_logic_vector(2 DOWNTO 0);
-- fifo
fifo_empty : IN std_logic; -- indicates that no more data is available
fifo_full : in std_logic; -- indicates that no more data can be stored in fifo
fifo_almost_full : IN std_logic; -- indicates that only one data can be stored in the fifo
fifo_almost_empty : IN std_logic; -- indicates that only one data is stored in the fifo
fifo_wr : OUT std_logic; -- if asserted, fifo will be filled with another data
fifo_rd : OUT std_logic; -- if asserted, data will be read out from fifo
-- vme_dma_au
sour_dest : OUT std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : OUT std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd_int)
get_bd : OUT std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
dma_act_bd : IN std_logic_vector(7 DOWNTO 2); -- [7:3] = acti_intve bd number
load_cnt : OUT std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
we_o_int : IN std_logic; -- wbm write/read indicator
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
set_dma_err : OUT std_logic; -- sets dma error bit if vme error
clr_dma_en : OUT std_logic; -- clears dma_en bit and dma_act_bd if dma_mstr has done
dma_en : IN std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : IN std_logic; -- indicates the last bd
en_mstr_dat_i_reg : OUT std_logic; -- enable for data in
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0); -- size of data package
-- arbiter
mstr_req : OUT std_logic -- request for internal register access
);
END vme_dma_mstr;
ARCHITECTURE vme_dma_mstr_arch OF vme_dma_mstr IS
TYPE mstr_states IS (idle, read_bd, store_bd, prep_read, prep_read2, read_data, read_ws, prep_write, prep_write2, prep_write3, write_data, write_ws, prep_read_bd);
SIGNAL mstr_state : mstr_states;
SIGNAL get_bd_int : std_logic;
SIGNAL load_cnt_int : std_logic;
SIGNAL en_mstr_dat_i_reg_int : std_logic;
SIGNAL clr_dma_en_int : std_logic;
SIGNAL cti_int : std_logic_vector(2 DOWNTO 0);
BEGIN
cti <= cti_int;
load_cnt <= load_cnt_int;
get_bd <= get_bd_int;
en_mstr_dat_i_reg_int <= '1' WHEN get_bd_int = '1' AND ack_i = '1' ELSE '0';
en_mstr_dat_i_reg <= en_mstr_dat_i_reg_int;
clr_dma_en <= clr_dma_en_int;
fifo_wr <= '1' WHEN we_o_int = '0' AND ack_i = '1' AND get_bd_int = '0' ELSE '0';
set_dma_err <= '0' WHEN clr_dma_en_int = '1' AND fifo_empty = '1' AND reached_size = '1' AND dma_null = '1' ELSE clr_dma_en_int;
mstr_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_state <= idle;
load_cnt_int <= '0';
sour_dest <= '0';
get_bd_int <= '1';
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
ELSIF clk'EVENT AND clk = '1' THEN
load_cnt_int <= en_mstr_dat_i_reg_int;
IF dma_act_bd(3 DOWNTO 2) = "11" AND ack_i = '1' THEN
get_bd_int <= '0';
ELSIF clr_dma_en_int = '1' OR (ack_i = '1' AND fifo_empty = '1' AND reached_size = '1' AND mstr_state = write_data) THEN
get_bd_int <= '1';
END IF;
CASE mstr_state IS
WHEN idle =>
sour_dest <= '0';
clr_dma_en_int <= '0';
cti_int <= "000";
IF start_dma = '1' THEN -- if start of dma => read first bd
mstr_state <= read_bd;
stb_o <= '1';
ELSE
mstr_state <= idle;
stb_o <= '0';
END IF;
WHEN read_bd => -- part of bd requested from sram
sour_dest <= '0';
cti_int <= "000";
IF err_i = '1' OR dma_en /= '1' THEN
mstr_state <= idle; -- error from sram or dma disabled by sw => end of dma action
clr_dma_en_int <= '1';
stb_o <= '0';
ELSIF ack_i = '1' THEN
mstr_state <= store_bd;
clr_dma_en_int <= '0';
stb_o <= '0';
ELSE
mstr_state <= read_bd; -- stay until acknoledge of sram
clr_dma_en_int <= '0';
stb_o <= '1';
END IF;
WHEN store_bd => -- part of bd will be stored in internal registers
clr_dma_en_int <= '0';
cti_int <= "000";
IF dma_act_bd(3 DOWNTO 2) = "00" THEN
sour_dest <= '1';
mstr_state <= prep_read; -- hole bd was read => start reading data
stb_o <= '0';
ELSE
sour_dest <= '0';
mstr_state <= read_bd; -- read next part of bd
stb_o <= '1';
END IF;
WHEN prep_read =>
clr_dma_en_int <= '0';
sour_dest <= '1';
mstr_state <= prep_read2;
stb_o <= '0';
cti_int <= "000"; -- no burst if address gets not incremented
WHEN prep_read2 =>
clr_dma_en_int <= '0';
sour_dest <= '1';
mstr_state <= read_data;
stb_o <= '1';
if inc_dest = '0' and (almost_reached_size = '1' or reached_size = '1') then
cti_int <= "000"; -- last longword => perform single access
elsif inc_dest = '0' and almost_boundary = '1' then
cti_int <= "000"; -- first longword before boundary => perform single access
elsif inc_dest = '0' and almost_reached_size = '0' then
cti_int <= "010"; -- more than one longword => perform burst access
else
cti_int <= "000"; -- no burst if address gets not incremented
end if;
WHEN read_data => -- request read from source address
IF err_i = '1' OR (dma_en /= '1' AND ack_i = '1') THEN
mstr_state <= idle; -- error from source => end of dma acti_inton
sour_dest <= '0';
clr_dma_en_int <= '1';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND (reached_size = '1' or fifo_full = '1') THEN
mstr_state <= prep_write; -- block of data was read => write data to destination
sour_dest <= '0';
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
--GD
-- ELSIF ack_i = '1' AND inc_sour = '1' THEN
-- mstr_state <= read_ws; -- got ack from source address => waitstate, then new single cycle
-- sour_dest <= '1';
-- clr_dma_en_int <= '0';
-- stb_o <= '0';
-- cti_int <= "000";
--GD
ELSIF ack_i = '1' AND boundary = '1' THEN
mstr_state <= read_ws; -- got ack from source address => waitstate, then new single cycle
sour_dest <= '1';
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND (fifo_almost_full = '1' or almost_reached_size = '1' or almost_boundary = '1') THEN
mstr_state <= read_data;
sour_dest <= '1';
clr_dma_en_int <= '0';
stb_o <= '1';
if cti_int = "010" then
cti_int <= "111"; -- do last data phase of burst
else
cti_int <= "000"; -- if there was no burst, perform last single access
end if;
ELSE
mstr_state <= read_data; -- wait on ack_i even if fifo_almost_full or reached_size
sour_dest <= '1';
clr_dma_en_int <= '0';
stb_o <= '1';
cti_int <= cti_int;
END IF;
WHEN read_ws =>
sour_dest <= '1';
mstr_state <= read_data;
clr_dma_en_int <= '0';
stb_o <= '1';
if inc_dest = '0' and (reached_size = '1' or fifo_almost_full = '1') then
cti_int <= "000"; -- last longword => perform single access
elsif inc_dest = '0' and reached_size = '0' then
cti_int <= "010"; -- more than one longword => perform burst access
else
cti_int <= "000"; -- no burst if address gets not incremented
end if;
WHEN prep_write =>
sour_dest <= '0';
mstr_state <= prep_write2;
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
WHEN prep_write2 =>
sour_dest <= '0';
mstr_state <= prep_write3;
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
WHEN prep_write3 =>
sour_dest <= '0';
mstr_state <= write_data;
clr_dma_en_int <= '0';
stb_o <= '1';
if inc_dest = '0' and fifo_almost_empty = '1' then
cti_int <= "000"; -- last longword => perform single access
elsif inc_dest = '0' and almost_boundary = '1' then
cti_int <= "000"; -- first longword before boundary => perform single access
elsif inc_dest = '0' and (fifo_almost_empty = '0' and almost_boundary = '0') then
cti_int <= "010"; -- more than one longword => perform burst access
else
cti_int <= "000"; -- no burst if address gets not incremented
end if;
WHEN write_data =>
IF err_i = '1' OR (dma_en /= '1' AND ack_i = '1') THEN
sour_dest <= '0';
mstr_state <= idle; -- error from destination => end of dma action
clr_dma_en_int <= '1';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '1' AND dma_null = '1' THEN
sour_dest <= '0';
mstr_state <= idle; -- data of bd was written and end of bd list => dma finished
clr_dma_en_int <= '1'; -- end of dma => clear dma_en bit
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '1' THEN
sour_dest <= '0';
mstr_state <= prep_read_bd; -- data of bd was written => read next bd
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '0' THEN
sour_dest <= '1';
mstr_state <= prep_read; -- part data of bd was written => read next part of same bd
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND fifo_empty /= '1' AND (inc_dest = '1' OR boundary = '1') THEN
sour_dest <= '0';
mstr_state <= write_ws; -- got ack from destination address => make waitstate and then next single cycle
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
ELSIF ack_i = '1' AND inc_dest = '0' AND (fifo_almost_empty = '1' or almost_boundary = '1') THEN
sour_dest <= '0';
mstr_state <= write_data; -- got ack from destination address => write last data of burst
clr_dma_en_int <= '0';
stb_o <= '1';
cti_int <= "111";
ELSE
sour_dest <= '0';
mstr_state <= write_data; -- wait on ack_i
clr_dma_en_int <= '0';
stb_o <= '1';
cti_int <= cti_int;
END IF;
WHEN write_ws =>
sour_dest <= '0';
mstr_state <= write_data;
clr_dma_en_int <= '0';
stb_o <= '1';
if inc_dest = '0' and fifo_empty = '1' then
cti_int <= "000"; -- last longword => perform single access
elsif inc_dest = '0' and fifo_empty = '0' then
cti_int <= "010"; -- more than one longword => perform burst access
else
cti_int <= "000"; -- no burst if address gets not incremented
end if;
WHEN prep_read_bd =>
sour_dest <= '0';
mstr_state <= read_bd;
clr_dma_en_int <= '0';
stb_o <= '1';
cti_int <= "000";
WHEN OTHERS =>
sour_dest <= '0';
mstr_state <= idle;
clr_dma_en_int <= '0';
stb_o <= '0';
cti_int <= "000";
END CASE;
END IF;
END PROCESS mstr_fsm;
mstr_out : PROCESS (mstr_state, ack_i, err_i, fifo_empty, fifo_almost_full, reached_size,
dma_en, dma_null, inc_sour, inc_dest, boundary, fifo_full)
BEGIN
CASE mstr_state IS
WHEN idle =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN read_bd => -- part of bd requested from sram
IF err_i = '1' OR (dma_en /= '1' AND ack_i = '1') THEN
mstr_req <= '0';
inc_adr <= '0';
ELSIF ack_i = '1' THEN
mstr_req <= '1'; -- request access to internal registers
inc_adr <= '1'; -- increment bd adress for next bd
ELSE
mstr_req <= '0';
inc_adr <= '0';
END IF;
fifo_rd <= '0';
WHEN store_bd => -- part of bd will be stored in internal registers
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_read =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_read2 =>
fifo_rd <= '0';
inc_adr <= '1'; -- if not first read then inc because of reached size
mstr_req <= '0';
WHEN read_data => -- request read from source address
IF err_i = '1' OR (dma_en /= '1' AND ack_i = '1') THEN
inc_adr <= '0';
-- ELSIF ack_i = '1' AND fifo_almost_full /= '1' AND reached_size /= '1' AND inc_sour = '0' AND boundary /= '1' THEN
-- inc_adr <= '1'; -- increment source address
-- ELSIF ack_i = '1' AND fifo_almost_full /= '1' AND reached_size /= '1' AND (inc_sour = '1' OR boundary = '1') THEN
-- inc_adr <= '1'; -- increment source address
-- ELSIF ack_i = '1' AND fifo_almost_full = '1' AND reached_size = '0' THEN
-- inc_adr <= '1'; -- increment source address for last write to fifo before full
-- ELSIF ack_i = '1' AND reached_size = '1' THEN
-- inc_adr <= '0'; -- no further data should be read => no increment
ELSIF ack_i = '1' and fifo_full = '0' and reached_size = '0' then
inc_adr <= '1';
ELSE
inc_adr <= '0';
END IF;
fifo_rd <= '0';
mstr_req <= '0';
WHEN read_ws =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_write =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_write2 =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_write3 =>
fifo_rd <= '1'; -- prepare for first write
inc_adr <= '1';
mstr_req <= '0';
WHEN write_data =>
IF err_i = '1' OR (dma_en /= '1' AND ack_i = '1') THEN
fifo_rd <= '0';
inc_adr <= '0';
ELSIF ack_i = '1' AND fifo_empty /= '1' AND inc_dest = '0' AND boundary /= '1' THEN
fifo_rd <= '1'; -- get next data from fifo
inc_adr <= '1'; -- read next data from fifo
ELSIF ack_i = '1' AND fifo_empty /= '1' AND (inc_dest = '1' OR boundary = '1') THEN
fifo_rd <= '1'; -- get next data from fifo
inc_adr <= '1'; -- read next data from fifo
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '1' AND dma_null = '1' THEN
fifo_rd <= '0'; -- no more data in fifo
inc_adr <= '0'; -- no more increment
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '1' THEN
fifo_rd <= '0'; -- no more data in fifo
inc_adr <= '1'; -- increment dma_act_bd
ELSIF ack_i = '1' AND fifo_empty = '1' AND reached_size = '0' THEN
fifo_rd <= '0'; -- no more data in fifo
inc_adr <= '0';
ELSE
fifo_rd <= '0';
inc_adr <= '0';
END IF;
mstr_req <= '0';
WHEN write_ws =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN prep_read_bd =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
WHEN OTHERS =>
fifo_rd <= '0';
inc_adr <= '0';
mstr_req <= '0';
END CASE;
END PROCESS mstr_out;
END vme_dma_mstr_arch;
| gpl-3.0 | 7df121343c202e5991122e4969916578 | 0.427442 | 4.017914 | false | false | false | false |
iocoder/graduation | hardware/kbd/debouncer.vhd | 1 | 786 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debouncer is
Port (
CLK : in STD_LOGIC;
Din : in STD_LOGIC;
Dout : out STD_LOGIC := '0'
);
end entity;
architecture Behavioral of debouncer is
signal counter: integer range 0 to 10000000 := 0;
signal last_d: STD_LOGIC := '0';
begin
process(CLK)
begin
if (CLK = '1' and CLK'event) then
if (Din /= last_d) then
if (counter = 100) then
counter <= 0;
last_d <= Din;
Dout <= Din;
else
counter <= counter + 1;
end if;
else
counter <= 0;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 5b07da16d3117a01b56aa50b4694e361 | 0.522901 | 3.605505 | false | false | false | false |
jevinskie/aes-over-pcie | source/experiment/tb_bus_test.vhd | 1 | 1,097 | -- File name: tb_bus_test.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: bus_test tester
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_bus_test is
generic (
clk_per : time := 5 ns
);
end tb_bus_test;
architecture test of tb_bus_test is
component bus_test is
port (
clk : in std_logic;
nrst : in std_logic;
b : out unsigned(7 downto 0)
);
end component bus_test;
signal clk : std_logic := '0';
signal nrst : std_logic := '1';
signal stop : std_logic := '1';
signal b : unsigned(7 downto 0);
begin
dut : bus_test port map (
clk => clk, nrst => nrst, b => b
);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
nrst <= '0';
wait for clk_per*2;
nrst <= '1';
stop <= '0';
wait for clk_per*32;
stop <= '1';
wait for clk_per*4;
wait;
end process;
end test;
| bsd-3-clause | 6d3d44f9a9a57df25a44ce2fd9ce3a68 | 0.552416 | 3.264881 | false | true | false | false |
jevinskie/aes-over-pcie | source/sbox.vhd | 1 | 7,850 | -- File name: sbox.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael S-Box
use work.aes.all;
use work.reduce_pack.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sbox is
port (
clk : in std_logic;
a : in byte;
b : out byte
);
type matrix_type is array (7 downto 0) of byte;
function square_gf4 (q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(3);
k(2) := q(3) xor q(2);
k(1) := q(2) xor q(1);
k(0) := q(3) xor q(1) xor q(0);
return k;
end function square_gf4;
function mullambda_gf4 (q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(2) xor q(0);
k(2) := q(3) xor q(2) xor q(1) xor q(0);
k(1) := q(3);
k(0) := q(2);
return k;
end function mullambda_gf4;
function mul_gf2(q : pair; w : pair)
return pair
is
variable k : pair;
begin
k(1) := (q(1) and w(1)) xor (q(0) and w(1)) xor (q(1) and w(0));
k(0) := (q(1) and w(1)) xor (q(0) and w(0));
return k;
end function mul_gf2;
function mul_alt_gf2(q : pair; w : pair)
return pair
is
variable k : pair;
begin
k(1) := ((q(1) xor q(0)) and (w(1) xor w(0))) xor (q(0) and w(0));
k(0) := (q(1) and w(1)) xor (q(0) and w(0));
return k;
end function mul_alt_gf2;
function mulphi_gf2(q : pair)
return pair
is
variable k : pair;
begin
k(1) := q(1) xor q(0);
k(0) := q(1);
return k;
end function mulphi_gf2;
function mul_gf4(q : nibble; w : nibble)
return nibble
is
variable qh, ql, wh, wl : pair;
variable res_top, res_mid, res_bot : pair;
variable k : nibble;
begin
qh := q(3 downto 2);
ql := q(1 downto 0);
wh := w(3 downto 2);
wl := w(1 downto 0);
res_top := mulphi_gf2(mul_gf2(qh, wh));
res_mid := mul_alt_gf2(qh xor ql, wh xor wl);
res_bot := mul_alt_gf2(ql, wl);
k(3 downto 2) := res_mid xor res_bot;
k(1 downto 0) := res_top xor res_bot;
return k;
end function mul_gf4;
function iso_map(q : byte)
return byte
is
variable k : byte;
constant iso : matrix_type :=
("10100000",
"11011110",
"10101100",
"10101110",
"11000110",
"10011110",
"01010010",
"01000011");
begin
for i in iso'range loop
k(i) := xor_reduce(q and iso(i));
end loop;
return k;
end function iso_map;
function inv_iso_map(q : byte)
return byte
is
variable k : byte;
constant iso_inv : matrix_type :=
("11100010",
"01000100",
"01100010",
"01110110",
"00111110",
"10011110",
"00110000",
"01110101");
begin
for i in iso_inv'range loop
k(i) := xor_reduce(q and iso_inv(i));
end loop;
return k;
end function inv_iso_map;
function mulinv_gf4(q : nibble)
return nibble
is
variable k : nibble;
begin
k(3) := q(3) xor (q(3) and q(2) and q(1)) xor (q(3) and q(0)) xor q(2);
k(2) := (q(3) and q(2) and q(1)) xor (q(3) and q(2) and q(0)) xor
(q(3) and q(0)) xor q(2) xor (q(2) and q(1));
k(1) := q(3) xor (q(3) and q(2) and q(1)) xor (q(3) and q(1) and q(0)) xor
q(2) xor (q(2) and q(0)) xor q(1);
k(0) := (q(3) and q(2) and q(1)) xor (q(3) and q(2) and q(0)) xor
(q(3) and q(1)) xor (q(3) and q(1) and q(0)) xor (q(3) and q(0)) xor
q(2) xor (q(2) and q(1)) xor (q(2) and q(1) and q(0)) xor q(1) xor q(0);
return k;
end function mulinv_gf4;
function mulinv_lut_gf4(q : nibble)
return nibble
is
variable k : nibble;
begin
case q is
when x"0" => k := x"0";
when x"1" => k := x"1";
when x"2" => k := x"3";
when x"3" => k := x"2";
when x"4" => k := x"f";
when x"5" => k := x"c";
when x"6" => k := x"9";
when x"7" => k := x"b";
when x"8" => k := x"a";
when x"9" => k := x"6";
when x"a" => k := x"8";
when x"b" => k := x"7";
when x"c" => k := x"5";
when x"d" => k := x"e";
when x"e" => k := x"d";
when x"f" => k := x"4";
when others => k := x"0";
end case;
return k;
end function mulinv_lut_gf4;
function af(a : byte)
return byte
is
variable b : byte;
variable d : byte;
constant m : matrix_type :=
("11111000",
"01111100",
"00111110",
"00011111",
"10001111",
"11000111",
"11100011",
"11110001");
constant c : byte := "01100011";
begin
for i in m'range loop
b(i) := xor_reduce(a and m(i));
end loop;
b := b xor c;
return b;
end function af;
function iso_inv_af(a : byte)
return byte
is
variable b : byte;
variable d : byte;
constant m : matrix_type :=
("10001100",
"11110000",
"10000100",
"10010011",
"00000111",
"01111101",
"10000001",
"11000111");
constant c : byte := "01100011";
begin
for i in m'range loop
b(i) := xor_reduce(a and m(i));
end loop;
b := b xor c;
return b;
end function iso_inv_af;
end entity sbox;
architecture dataflow of sbox is
signal iso : byte;
signal isoh, isol : nibble;
signal left_top, left_bot : nibble;
signal right_top, right_bot : nibble;
signal mulinv : nibble;
begin
process(clk)
begin
if rising_edge(clk) then
end if;
end process;
iso <= iso_map(a);
isoh <= iso(7 downto 4);
isol <= iso(3 downto 0);
left_top <= mullambda_gf4(square_gf4(isoh));
left_bot <= mul_gf4(isoh xor isol, isol);
mulinv <= mulinv_lut_gf4(left_top xor left_bot);
right_top <= mul_gf4(mulinv, isoh);
right_bot <= mul_gf4(mulinv, isoh xor isol);
b <= iso_inv_af(right_top & right_bot);
end architecture dataflow;
architecture pipelined of sbox is
signal iso : byte;
signal isoh, isol : nibble;
signal isoh_q, isol_q : nibble;
signal left_top, left_bot : nibble;
signal left_top_q, left_bot_q : nibble;
signal right_top, right_bot : nibble;
signal mulinv : nibble;
signal subbyte : byte;
begin
process(clk)
begin
if (rising_edge(clk)) then
isoh_q <= isoh;
isol_q <= isol;
left_top_q <= left_top;
left_bot_q <= left_bot;
b <= subbyte;
end if;
end process;
iso <= iso_map(a);
isoh <= iso(7 downto 4);
isol <= iso(3 downto 0);
left_top <= mullambda_gf4(square_gf4(isoh));
left_bot <= mul_gf4(isoh xor isol, isol);
mulinv <= mulinv_lut_gf4(left_top_q xor left_bot_q);
right_top <= mul_gf4(mulinv, isoh_q);
right_bot <= mul_gf4(mulinv, isoh_q xor isol_q);
subbyte <= iso_inv_af(right_top & right_bot);
end architecture pipelined;
architecture lut of sbox is
begin
process(clk)
begin
if rising_edge(clk) then
end if;
end process;
b <= work.aes.sbox(to_integer(a));
end architecture lut;
| bsd-3-clause | f322367b8cd97ae75780fa97e991cd8f | 0.48051 | 3.169156 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/steer_module_read.vhd | 2 | 23,737 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_read.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Read - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: steer_module_read.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- steer_module_read.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 4-26-2002 -- First version
-- ^^^^^^
-- First version of steering logic module.
-- ~~~~~~
-- BLT 11-18-2002 -- Update to version v1.00b
-- ^^^^^^
-- Updated to use ipif_common_v1_00_b, which fixed a simulation problem
-- in the ipif_steer logic
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.STEER_TYPES.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_LARGEST : integer := width of largest device (not access size)
-- attached to the IPIF
-- C_MIRROR_SIZE : integer := smallest unit of data that is mirrored
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity Steer_Module_Read is
generic (
C_DWIDTH_IN : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_OUT : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_OUT : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IN : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end entity Steer_Module_Read;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of Steer_Module_Read is
-------------------------------------------------------------------------------
-- Function max -- returns maximum of x and y
-------------------------------------------------------------------------------
function max(x : integer; y : integer) return integer is
begin
if x > y then return x;
else return y;
end if;
end function max;
-------------------------------------------------------------------------------
-- Function min -- returns minimum of x and y
-------------------------------------------------------------------------------
function min(x : integer; y : integer) return integer is
begin
if x < y then return x;
else return y;
end if;
end function min;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- returns x**y for integers x and y, y>=0
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
function Addr_Start_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Start;
end function Addr_Start_Func;
function Addr_Stop_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Stop;
end function Addr_Stop_Func;
constant Addr_Size : integer_array_type(0 to 63) :=
(1=>1,3=>1,5=>1,7=>1,9=>1,11=>1,13=>1,15=>1,
17=>1,19=>1,21=>1,23=>1,25=>1,27=>1,29=>1,31=>1,
33=>1,35=>1,37=>1,39=>1,41=>1,43=>1,45=>1,47=>1,
49=>1,51=>1,53=>1,55=>1,57=>1,59=>1,61=>1,63=>1,
2=>2,6=>2,10=>2,14=>2,18=>2,22=>2,26=>2,30=>2,
34=>2,38=>2,42=>2,46=>2,50=>2,54=>2,58=>2,62=>2,
4=>4,12=>4,20=>4,28=>4,36=>4,44=>4,52=>4,60=>4,
8=>8,24=>8,40=>8,56=>8,16=>16,48=>16,32=>32,0=>64);
constant IP_Addr_Start : integer := Addr_Start_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
constant IP_Addr_Stop : integer := Addr_Stop_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
MUX_PROCESS: process( Data_In,Decode_size,Addr ) is
variable factor : integer;
variable addr_loop : integer;
variable addr_integer : integer;
variable num_addr_bits : integer;
variable size : integer;
variable address : integer;
variable data_address : integer;
variable replicate_factor : integer;
begin
num_addr_bits := IP_Addr_Stop-IP_Addr_Start+1;
-- Set up default condition
if C_DWIDTH_IN <= C_DWIDTH_OUT then
for i in 0 to C_DWIDTH_OUT/C_DWIDTH_IN-1 loop
Data_Out(i*C_DWIDTH_IN to (i+1)*C_DWIDTH_IN-1) <= Data_In;
end loop;
else
Data_Out <= Data_In(0 to C_DWIDTH_OUT-1);
end if;
if C_DWIDTH_IN > C_SMALLEST_IN then -- Data_Out is a function of Decode_size
for k in log2(C_SMALLEST_IN/8)+1 to log2(C_DWIDTH_IN/8)+1 loop -- 1,2,3,4,5,6,7 6 for now
factor := pwr(2,k)/2; -- 1,2,4,8,16,32,64 number of byte lanes
if Decode_size = Conv_std_logic_vector(k,3) then
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
data_address := address;
if address = 0 then -- special case for address zero
size := factor*8; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
while data_address >= factor loop -- modulo operator since mod doesn't work in Synplify if right side isn't constant
data_address := data_address - factor;
end loop;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(data_address*8 + m);
end loop;
end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
if factor*8 <= C_DWIDTH_OUT then
for m in 0 to C_DWIDTH_OUT/(factor*8)-1 loop
Data_Out(factor*8*m to factor*8*(m+1)-1) <= Data_In(0 to factor*8-1);
end loop;
else
for m in 0 to C_DWIDTH_OUT-1 loop
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end if;
end loop;
else -- Data_Out is not a function of Decode_Size
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
if address = 0 then -- special case for address zero
size := C_DWIDTH_IN; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(address*8+m);
end loop;
end loop;
-- for m in size to C_DWIDTH_OUT-1 loop -- set remaining bits to default
-- Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- mod in case host data bus larger than Data_In
-- end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
for m in 0 to C_DWIDTH_OUT-1 loop -- 0 to 3
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end process MUX_PROCESS;
end architecture IMP;
| bsd-3-clause | 36da7d6c6b7967d385ac9ae828c3f77a | 0.448077 | 3.700811 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd | 2 | 10,267 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
| bsd-3-clause | 9634e91a19f78e825e85920f1dc198bf | 0.419499 | 5.182736 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_arbiter.vhd | 3 | 15,932 | -------------------------------------------------------------------------------
-- $Id: opb_arbiter.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_arbiter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_arbiter.vhd
-- Version: v1.02e
-- Description: This is the top-level design file for the OPB Arbiter. It
-- supports 1-16 masters and both fixed and dynamic priority
-- algorithms via user-configurable parameters. The user can
-- also include support for bus parking and the OPB slave
-- interface by setting parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- -- opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP1
--
-- Fixed issue with REG_HIGHADDR constant not being defined correctly. This
-- issue was causing a synthesis error.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
--
-- Modified the processes MASTER_LOOP and MASTERLOOP to remove the latch it was
-- creating in priority_register_logic.vhd and arbitration_logic.vhd
-- modules respectively.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: JAC
-- History:
-- JAC 09/25/01
-- ^^^^^^
-- Version 1.01a creation to create COREGEN simple wrapper.
-- ~~~~~~
--
-- ALS 10/04/01
-- ^^^^^^
-- Version 1.02a creation to include IPIF v1.23a. Also changed C_BASEADDR
-- back to std_logic_vector.
-- ~~~~~~
--
-- ALS 10/12/01
-- ^^^^^^
-- Replaced generic C_DEV_ADDR_DECODE_WIDTH with C_HIGHADDR.
-- C_DEV_ADDR_DECODE_WIDTH will be calcuated from C_HIGHADDR and C_BASEADDR.
-- ~~~~~~
--
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem. Also, replaced
-- C_OPBDATA_WIDTH and C_OPBADDR_WIDTH with C_OPB_DWIDTH and
-- C_OPB_AWIDTH.
-- ~~~~~~
--
-- ALS 12/04/01
-- ^^^^^^
-- Replaced C_OPBDATA_WIDTH and C_OPBADDR_WIDTH with C_OPB_DWIDTH and
-- C_OPB_AWIDTH.
-- ~~~~~~
-- ALS 12/06/01
-- ^^^^^^
-- Modified default values for C_BASEADDR and C_HIGHADDR to the values
-- required by the system build environment.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 07/05/05
-- ^^^^^^
-- Fixed XST issue in ipif_regonly_slave.vhd. This fixes CR211277.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
-- CONV_FUNS_PKG containts functions to convert simple generic types to more
-- complex data types (ie: strings to std_logic_vector).
--library proc_utils_v1_00_a;
--use proc_utils_v1_00_a.conv_funs_pkg.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_OPB_DWIDTH -- width of OPB data bus
-- C_OPB_AWIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
--
-- output ARB_DBus -- Arbiter's data bus to OPB
-- output ARB_ErrAck -- Arbiter's error acknowledge - unused
-- output ARB_Retry -- Arbiter's retry signal - unused
-- output ARB_XferAck -- Arbiter's xfer acknowledge
-- input OPB_Clk -- Clock
-- input M_request -- Masters' request signals
-- input OPB_Abus -- OPB Address bus
-- input OPB_BE -- OPB Byte Enables
-- input OPB_buslock -- Bus lock
-- input OPB_Dbus -- OPB Data bus
-- output OPB_MGrant -- Masters' grant signals
-- input OPB_retry -- Retry
-- input OPB_RNW -- Read not Write
-- input OPB_select -- Master has control of bus
-- input OPB_seqAddr -- Sequential Address
-- output OPB_timeout -- Timeout
-- input OPB_toutSup -- Timeout suppress
-- input OPB_xferAck -- OPB xfer acknowledge
-- input OPB_Rst -- Reset
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_arbiter is
generic (
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_NUM_MASTERS : integer := 4;
C_OPB_DWIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_DYNAM_PRIORITY : integer := 0;
C_PARK : integer := 0;
C_PROC_INTRFCE : integer := 0;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
ARB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
ARB_ErrAck : out std_logic;
ARB_Retry : out std_logic;
ARB_ToutSup : out std_logic;
ARB_XferAck : out std_logic;
OPB_Clk : in std_logic;
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_Abus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_buslock : in std_logic;
OPB_Dbus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : in std_logic;
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : in std_logic;
OPB_xferAck : in std_logic;
OPB_Rst : in std_logic
);
end entity opb_arbiter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of opb_arbiter is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- none
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- none
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- none
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
OPB_ARBITER_CORE_I: entity opb_v20_v1_10_d.opb_arbiter_core
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_OPBDATA_WIDTH => C_OPB_DWIDTH,
C_OPBADDR_WIDTH => C_OPB_AWIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY /= 0,
C_REG_GRANTS => C_REG_GRANTS /= 0,
C_PARK => C_PARK /= 0,
C_PROC_INTRFCE => C_PROC_INTRFCE /= 0,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE)
port map (
ARB_DBus => ARB_DBus,
ARB_ErrAck => ARB_ErrAck,
ARB_Retry => ARB_Retry,
ARB_ToutSup => ARB_ToutSup,
ARB_XferAck => ARB_XferAck,
OPB_Clk => OPB_Clk,
M_request => M_request,
OPB_Abus => OPB_Abus,
OPB_BE => OPB_BE,
OPB_buslock => OPB_buslock,
OPB_Dbus => OPB_Dbus,
OPB_MGrant => OPB_MGrant,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck,
OPB_Rst => OPB_Rst);
end implementation;
| bsd-3-clause | 174848445888376290386d4437b631b3 | 0.429262 | 4.780078 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_fifo_d1.vhd | 1 | 3,918 | ---------------------------------------------------------------
-- Title : FIFO with depth one word
-- Project :
---------------------------------------------------------------
-- File : z126_01_fifo_d1.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
-- This module describes a fifo with depth one word.
-- No EAB-Block is required, just registers.
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_fifo_d1.vhd,v $
-- Revision 1.1 2014/03/03 17:49:40 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_fifo_d1 IS
GENERIC (
width : IN integer:=8 );
PORT (
rstn : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END z126_01_fifo_d1;
ARCHITECTURE z126_01_fifo_d1_arch OF z126_01_fifo_d1 IS
SIGNAL wr_ptr : std_logic;
SIGNAL rd_ptr : std_logic;
SIGNAL wr_ptr_b : std_logic;
SIGNAL rd_ptr_a : std_logic;
SIGNAL full_a_int : std_logic;
SIGNAL full_b_int : std_logic;
SIGNAL data_a_q : std_logic_vector(width-1 DOWNTO 0);
BEGIN
full_a_int <= '1' WHEN (wr_ptr = '1' AND rd_ptr_a = '0') OR (wr_ptr = '0' AND rd_ptr_a = '1') ELSE '0';
full_a <= full_a_int;
full_b_int <= '1' WHEN (wr_ptr_b = '1' AND rd_ptr = '0') OR (wr_ptr_b = '0' AND rd_ptr = '1') ELSE '0';
full_b <= full_b_int;
proca : PROCESS (clk_a, rstn)
BEGIN
IF rstn = '0' THEN
data_a_q <= (OTHERS => '0');
wr_ptr <= '0';
rd_ptr_a <= '0';
ELSIF clk_a'EVENT AND clk_a = '1' THEN
rd_ptr_a <= rd_ptr;
IF wr_a = '1' AND full_a_int = '0' THEN
data_a_q <= data_a;
wr_ptr <= NOT wr_ptr;
END IF;
END IF;
END PROCESS proca;
procb : PROCESS (clk_b, rstn)
BEGIN
IF rstn = '0' THEN
data_b <= (OTHERS => '0');
rd_ptr <= '0';
wr_ptr_b <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
wr_ptr_b <= wr_ptr;
IF rd_b = '1' AND full_b_int = '1' THEN
data_b <= data_a_q;
rd_ptr <= NOT rd_ptr;
END IF;
END IF;
END PROCESS procb;
END z126_01_fifo_d1_arch;
| gpl-3.0 | b0637e053c5b600f78b132ef4e366f05 | 0.476008 | 3.624422 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_counter_top.vhd | 2 | 8,384 | -------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v3_00_a.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
| bsd-3-clause | 787f00b11427977696ee1e27f42457fc | 0.42271 | 4.963884 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/smp_synch_core_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 17,674 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Aug 4 00:06:12 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 16
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg8 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg9 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg10 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg11 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg12 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg13 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg14 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg15 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 15);
signal slv_reg_read_sel : std_logic_vector(0 to 15);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 15);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 15);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
-- JA: Writing slv_reg0 updates both slv_reg0 and slv_reg1
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100000000000000" =>
-- JA: Upon writing, slv_reg1 auto increments
slv_reg1 <= slv_reg1 + 1;
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15 ) is
begin
case slv_reg_read_sel is
when "1000000000000000" => slv_ip2bus_data <= slv_reg0;
when "0100000000000000" => slv_ip2bus_data <= slv_reg1;
when "0010000000000000" => slv_ip2bus_data <= slv_reg2;
when "0001000000000000" => slv_ip2bus_data <= slv_reg3;
when "0000100000000000" => slv_ip2bus_data <= slv_reg4;
when "0000010000000000" => slv_ip2bus_data <= slv_reg5;
when "0000001000000000" => slv_ip2bus_data <= slv_reg6;
when "0000000100000000" => slv_ip2bus_data <= slv_reg7;
when "0000000010000000" => slv_ip2bus_data <= slv_reg8;
when "0000000001000000" => slv_ip2bus_data <= slv_reg9;
when "0000000000100000" => slv_ip2bus_data <= slv_reg10;
when "0000000000010000" => slv_ip2bus_data <= slv_reg11;
when "0000000000001000" => slv_ip2bus_data <= slv_reg12;
when "0000000000000100" => slv_ip2bus_data <= slv_reg13;
when "0000000000000010" => slv_ip2bus_data <= slv_reg14;
when "0000000000000001" => slv_ip2bus_data <= slv_reg15;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | a3586f7b7fee2067ba35de612218c182 | 0.499321 | 3.727119 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_pkg.vhd | 3 | 5,988 | -------------------------------------------------------------------------------
-- $Id: dma_sg_pkg.vhd,v 1.2 2003/05/19 05:42:44 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg_pkg.vhd - package
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_pkg.vhd
--
-- Description: This package contains types, constants and functions that
-- support the DMA/Scatter Gather IP block (entity dma_sg).
--
-------------------------------------------------------------------------------
-- Structure: No dependencies.
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 04/24/01 -- First version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dma_sg_pkg is
constant UPCB : natural := 10; -- The number of bits implemented in UPC.
constant PWBB : natural := 10; -- The number of bits implemented in PWB.
-- Word offsets of registers from the channel register base addr.
constant r_RSTMIR : natural := 0;
constant r_DMACR : natural := 1;
constant r_SA : natural := 2;
constant r_DA : natural := 3;
constant r_LENGTH : natural := 4;
constant r_DMASR : natural := 5;
constant r_BDA : natural := 6;
constant r_SWCR : natural := 7;
constant r_UPC : natural := 8;
constant r_PCT : natural := 9;
constant r_PWB : natural :=10;
constant r_ISR : natural :=11;
constant r_IER : natural :=12;
constant r_PLENGTH : natural :=15;
-- Word offsets of fields in the Buffer Descriptor.
constant bd_SR : natural := 0;
constant bd_DMACR : natural := 1;
constant bd_SA : natural := 2;
constant bd_DA : natural := 3;
constant bd_LENGTH : natural := 4;
constant bd_DMASR : natural := 5;
constant bd_BDA : natural := 6;
-- Bit numbers.
constant b_BSY : natural := 0;
constant b_SINC : natural := 0;
constant b_DINC : natural := 1;
constant b_SLOCAL : natural := 2;
constant b_DLOCAL : natural := 3;
constant b_SGS : natural := 4;
constant b_L_dmacr: natural := 6;
constant b_L_dmasr: natural := 3;
constant b_SGE : natural := 0;
constant b_DD : natural :=31;
constant b_DE : natural :=30;
constant b_PD : natural :=29;
constant b_PCTR : natural :=28;
constant b_PWBR : natural :=27;
constant b_SGDA : natural :=26;
constant b_SGEND : natural :=25;
-- Conversion of a boolean scalar to a std_logic scalar.
function bo2sl(b: boolean) return std_logic;
-- Returns the base 2 logarithm of n, rounded up, if non-integral,
-- to the next integer.
function ceil_log2(n : natural) return natural;
-- Returns the the value, i, for which (2**i)*base_period
-- is closest to target_period.
function Div_Stages(base_period, target_period: natural) return natural;
end;
package body dma_sg_pkg is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
function ceil_log2(n : natural) return natural is
variable m : natural := 0;
variable nn : natural := n;
variable some_non_even : boolean := false;
begin
while nn /= 1 loop
m := m+1;
some_non_even := some_non_even or (nn rem 2)/=0;
nn := nn / 2;
end loop;
if some_non_even then m := m+1; end if;
return m;
end ceil_log2;
function Div_Stages(base_period, target_period: natural) return natural is
variable i: natural;
variable t: natural;
begin
assert base_period <= target_period
report "Div_Stages: base_period is not <= target_period, as required."
severity failure;
i := 0; t := base_period;
while t <= target_period loop
i := i + 1;
t := 2*t; -- t = (2**i)*base_period
end loop;
-- Pick either i or i-1 as the number of stages to give a power-or-2
-- division of 1/base_period that gives the value closest to
-- 1/target_period.
if t - target_period < target_period - t/2 then
return i;
else
return i-1;
end if;
end Div_Stages;
end;
| bsd-3-clause | 4eab528f0f07ff61e33a34f42a91e940 | 0.47161 | 4.25889 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/ip_16z091_01.vhd | 1 | 36,744 | --------------------------------------------------------------------------------
-- Title : 16z091-01 module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 22.11.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines modules to build the 16z091-01 module
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01 is
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111"; -- = 1015 DW
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, one place spare for put_stuffing
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111"; -- = 1015 DW
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end entity ip_16z091_01;
architecture ip_16z091_01_arch of ip_16z091_01 is
-- functions ------------------------------------------------------------------
function convert_family(
fpga_family_in : family_type
) return string is
begin
case fpga_family_in is
when CYCLONE4 => return "Cyclone IV GX";
when CYCLONE5 => return "Cyclone V";
when ARRIA2_GX => return "Arria II GX";
when others =>
assert false report "undefined family_type in function convert_family in rx_module.vhd" severity failure;
return "none";
end case;
end function convert_family;
-- constants ------------------------------------------------------------------
constant DEVICE_FAMILY_INT : string := convert_family(FPGA_FAMILY);
-- internal signals -----------------------------------------------------------
-- rx_module:
signal rx_fifo_wr_out_int : std_logic_vector(31 downto 0);
signal rx_fifo_wr_empty_int : std_logic;
signal rx_fifo_wr_rd_enable_int : std_logic;
signal rx_fifo_c_rd_enable_int : std_logic;
signal rx_fifo_c_empty_int : std_logic;
signal rx_fifo_c_out_int : std_logic_vector(31 downto 0);
signal tag_nbr_int : std_logic_vector(7 downto 0);
signal rx_tag_rcvd_int : std_logic;
signal ecrc_err_int : std_logic;
signal type_fmt_err_int : std_logic_vector(1 downto 0);
-- tx_module:
signal tx_fifo_c_head_clr_int : std_logic;
signal tx_fifo_c_data_clr_int : std_logic;
signal tx_fifo_c_head_full_int : std_logic;
signal tx_fifo_c_data_full_int : std_logic;
signal tx_fifo_c_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_c_head_enable_int : std_logic;
signal tx_fifo_c_data_enable_int : std_logic;
signal tx_fifo_c_head_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_c_data_in_int : std_logic_vector(31 downto 0);
signal bus_dev_func_int : std_logic_vector(15 downto 0);
signal max_read_int : std_logic_vector(2 downto 0);
signal max_payload_int : std_logic_vector(2 downto 0);
signal tx_fifo_wr_head_clr_int : std_logic;
signal tx_fifo_wr_head_enable_int : std_logic;
signal tx_fifo_wr_head_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_wr_head_full_int : std_logic;
signal tx_fifo_w_data_clr_int : std_logic;
signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_w_data_full_int : std_logic;
signal tx_fifo_w_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(4 downto 0);
-- error:
signal ecrc_err_wb_int : std_logic;
signal tag_id_wb_int : std_logic_vector(7 downto 0);
signal tx_timeout_int : std_logic;
signal timeout_wb_int : std_logic;
signal wb_num_err_int : std_logic;
signal tx_compl_abort_int : std_logic;
-- interrupt
signal cfg_msicsr_int : std_logic_vector(15 downto 0);
signal wb_pwr_en_int : std_logic;
signal wb_num_int_int : std_logic_vector(4 downto 0);
signal wb_inter_int : std_logic;
signal inter_ack_int : std_logic;
signal num_allowed_int : std_logic_vector(5 downto 0);
signal ack_ok_int : std_logic;
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component rx_module
generic(
DEVICE_FAMILY : string := "unused";
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
rst : in std_logic;
-- IP Core
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
-- FIFO
rx_fifo_c_rd_enable : in std_logic;
rx_fifo_wr_rd_enable : in std_logic;
rx_fifo_c_empty : out std_logic;
rx_fifo_wr_empty : out std_logic;
rx_fifo_c_out : out std_logic_vector(31 downto 0);
rx_fifo_wr_out : out std_logic_vector(31 downto 0);
-- Tx Module
rx_tag_nbr : out std_logic_vector(7 downto 0);
rx_tag_rcvd : out std_logic;
-- error
rx_type_fmt_err : out std_logic_vector(1 downto 0);
rx_ecrc_err : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component z091_01_wb_master
generic(
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_fifo_wr_out : in std_logic_vector(31 downto 0);
rx_fifo_wr_empty : in std_logic;
rx_fifo_wr_rd_enable : out std_logic;
-- Tx Module
tx_fifo_c_head_full : in std_logic;
tx_fifo_c_data_full : in std_logic;
tx_fifo_c_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_c_head_enable : out std_logic;
tx_fifo_c_data_enable : out std_logic;
tx_fifo_c_head_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_clr : out std_logic;
tx_fifo_c_head_clr : out std_logic;
-- Wishbone
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- error
ecrc_err_in : in std_logic;
err_tag_id : in std_logic_vector(7 downto 0);
ecrc_err_out : out std_logic
);
end component;
component error
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
-- RxModule
rx_tag_id : in std_logic_vector(7 downto 0);
rx_ecrc_err : in std_logic;
rx_type_fmt_err : in std_logic_vector(1 downto 0);
-- TxModule
tx_compl_abort : in std_logic;
tx_timeout : in std_logic;
-- Interrupt
wb_num_err : in std_logic;
-- Wishbone
error_ecrc_err : out std_logic;
error_timeout : out std_logic;
error_tag_id : out std_logic_vector(7 downto 0);
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- IP Core
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic
);
end component;
component tx_module
generic(
DEVICE_FAMILY : string := "unused";
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
-- IP Core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- Wishbone Master
tx_fifo_c_data_clr : in std_logic;
tx_fifo_c_head_clr : in std_logic;
tx_fifo_c_head_enable : in std_logic;
tx_fifo_c_data_enable : in std_logic;
tx_fifo_c_head_in : in std_logic_vector(31 downto 0);
tx_fifo_c_data_in : in std_logic_vector(31 downto 0);
tx_fifo_c_head_full : out std_logic;
tx_fifo_c_data_full : out std_logic;
tx_fifo_c_data_usedw : out std_logic_vector(9 downto 0);
-- Wishbone Slave
tx_fifo_wr_head_clr : in std_logic;
tx_fifo_wr_head_enable : in std_logic;
tx_fifo_wr_head_in : in std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : in std_logic;
tx_fifo_w_data_enable : in std_logic;
tx_fifo_w_data_in : in std_logic_vector(31 downto 0);
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(4 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0);
-- error
tx_compl_abort : out std_logic;
tx_timeout : out std_logic
);
end component;
component init
port(
core_clk : in std_logic; -- synchronous to core_clk from hard IP core
clk : in std_logic;
rst : in std_logic;
-- IP core
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
-- interrupt module
cfg_msicsr : out std_logic_vector(15 downto 0);
-- Tx Module
bus_dev_func : out std_logic_vector(15 downto 0);
max_read : out std_logic_vector(2 downto 0);
max_payload : out std_logic_vector(2 downto 0)
);
end component;
component z091_01_wb_slave
generic(
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, must be < or = (FIFO max size - 6)
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- Rx Module
rx_fifo_c_empty : in std_logic;
rx_fifo_c_out : in std_logic_vector(31 downto 0);
rx_fifo_c_rd_enable : out std_logic;
-- Tx Module
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(4 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : out std_logic;
tx_fifo_w_data_enable : out std_logic;
tx_fifo_w_data_in : out std_logic_vector(31 downto 0);
max_read : in std_logic_vector(2 downto 0);
-- error
error_ecrc_err : in std_logic;
error_timeout : in std_logic
);
end component;
component interrupt_core
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
-- interrupt_wb
wb_pwr_en : in std_logic;
wb_num_int : in std_logic_vector(4 downto 0);
wb_inter : in std_logic;
ack_ok : in std_logic;
inter_ack : out std_logic;
num_allowed : out std_logic_vector(5 downto 0);
-- init
cfg_msicsr : in std_logic_vector(15 downto 0);
-- error
wb_num_err : out std_logic
);
end component;
component interrupt_wb
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- interrupt_core
inter_ack : in std_logic;
num_allowed : in std_logic_vector(5 downto 0);
wb_pwr_en : out std_logic;
wb_num_int : out std_logic_vector(4 downto 0);
wb_inter : out std_logic;
ack_ok : out std_logic;
-- Wishbone
wb_int : in std_logic;
wb_pwr_enable : in std_logic; -- =1 if wb_int_num should be for power management, else
-- for normal interrupt
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0) -- =0 if MSI not allowed, else: nbr. of allocated signals
);
end component;
-------------------------------------------------------------------------------
begin
-- instanciate components --------------------------------------------------
rx_module_comp : rx_module
generic map(
DEVICE_FAMILY => DEVICE_FAMILY_INT,
READY_LATENCY => READY_LATENCY,
FIFO_MAX_USEDW => FIFO_MAX_USEDW,
RX_FIFO_DEPTH => RX_FIFO_DEPTH,
RX_LPM_WIDTHU => RX_LPM_WIDTHU
)
port map(
clk => clk,
wb_clk => wb_clk,
rst => rst,
-- IP Core
rx_st_data0 => rx_st_data0,
rx_st_err0 => rx_st_err0,
rx_st_valid0 => rx_st_valid0,
rx_st_sop0 => rx_st_sop0,
rx_st_eop0 => rx_st_eop0,
rx_st_be0 => rx_st_be0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_mask0 => rx_st_mask0,
rx_st_ready0 => rx_st_ready0,
-- FIFO
rx_fifo_c_rd_enable => rx_fifo_c_rd_enable_int,
rx_fifo_wr_rd_enable => rx_fifo_wr_rd_enable_int,
rx_fifo_c_empty => rx_fifo_c_empty_int,
rx_fifo_wr_empty => rx_fifo_wr_empty_int,
rx_fifo_c_out => rx_fifo_c_out_int,
rx_fifo_wr_out => rx_fifo_wr_out_int,
-- Tx Module
rx_tag_nbr => tag_nbr_int,
rx_tag_rcvd => rx_tag_rcvd_int,
-- error
rx_type_fmt_err => type_fmt_err_int,
rx_ecrc_err => ecrc_err_int,
-- debug port
rx_debug_out => rx_debug_out
);
wb_master_comp : z091_01_wb_master
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
SUSPEND_FIFO_ACCESS => WBM_SUSPEND_FIFO_ACCESS,
RESUME_FIFO_ACCESS => WBM_RESUME_FIFO_ACCESS
)
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- Rx Module
rx_fifo_wr_out => rx_fifo_wr_out_int,
rx_fifo_wr_empty => rx_fifo_wr_empty_int,
rx_fifo_wr_rd_enable => rx_fifo_wr_rd_enable_int,
-- Tx Module
tx_fifo_c_head_full => tx_fifo_c_head_full_int,
tx_fifo_c_data_full => tx_fifo_c_data_full_int,
tx_fifo_c_data_usedw => tx_fifo_c_data_usedw_int,
tx_fifo_c_head_enable => tx_fifo_c_head_enable_int,
tx_fifo_c_data_enable => tx_fifo_c_data_enable_int,
tx_fifo_c_head_in => tx_fifo_c_head_in_int,
tx_fifo_c_data_in => tx_fifo_c_data_in_int,
tx_fifo_c_data_clr => tx_fifo_c_data_clr_int,
tx_fifo_c_head_clr => tx_fifo_c_head_clr_int,
-- Wishbone
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => wbm_cyc,
wbm_cyc_o => wbm_cyc_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => wb_bar_dec,
-- error
ecrc_err_in => ecrc_err_wb_int,
err_tag_id => tag_id_wb_int,
ecrc_err_out => open
);
error_comp : error
port map(
clk => clk,
rst => rst,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- RxModule
rx_tag_id => tag_nbr_int,
rx_ecrc_err => ecrc_err_int,
rx_type_fmt_err => type_fmt_err_int,
-- TxModule
tx_compl_abort => tx_compl_abort_int,
tx_timeout => tx_timeout_int,
-- Interrupt
wb_num_err => wb_num_err_int,
-- Wishbone
error_ecrc_err => ecrc_err_wb_int,
error_timeout => timeout_wb_int,
error_tag_id => tag_id_wb_int,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- IP Core
derr_cor_ext_rcv => derr_cor_ext_rcv,
derr_cor_ext_rpl => derr_cor_ext_rpl,
derr_rpl => derr_rpl,
r2c_err0 => r2c_err0,
cpl_err => cpl_err,
cpl_pending => cpl_pending
);
tx_module_comp : tx_module
generic map(
DEVICE_FAMILY => DEVICE_FAMILY_INT,
TX_HEADER_FIFO_DEPTH => TX_HEADER_FIFO_DEPTH,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => TX_DATA_FIFO_DEPTH,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => clk,
rst => rst,
wb_clk => wb_clk,
wb_rst => wb_rst,
clk_500 => clk_500,
-- IP Core
tx_st_ready0 => tx_st_ready0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
pme_to_sr => pme_to_sr,
tx_st_err0 => tx_st_err0,
tx_st_valid0 => tx_st_valid0,
tx_st_sop0 => tx_st_sop0,
tx_st_eop0 => tx_st_eop0,
tx_st_data0 => tx_st_data0,
pme_to_cr => pme_to_cr,
-- Wishbone Master
tx_fifo_c_data_clr => tx_fifo_c_data_clr_int,
tx_fifo_c_head_clr => tx_fifo_c_head_clr_int,
tx_fifo_c_head_enable => tx_fifo_c_head_enable_int,
tx_fifo_c_data_enable => tx_fifo_c_data_enable_int,
tx_fifo_c_head_in => tx_fifo_c_head_in_int,
tx_fifo_c_data_in => tx_fifo_c_data_in_int,
tx_fifo_c_head_full => tx_fifo_c_head_full_int,
tx_fifo_c_data_full => tx_fifo_c_data_full_int,
tx_fifo_c_data_usedw => tx_fifo_c_data_usedw_int,
-- Wishbone Slave
tx_fifo_wr_head_clr => tx_fifo_wr_head_clr_int,
tx_fifo_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_fifo_wr_head_in => tx_fifo_wr_head_in_int,
tx_fifo_wr_head_full => tx_fifo_wr_head_full_int,
tx_fifo_w_data_clr => tx_fifo_w_data_clr_int,
tx_fifo_w_data_enable => tx_fifo_w_data_enable_int,
tx_fifo_w_data_in => tx_fifo_w_data_in_int,
tx_fifo_w_data_full => tx_fifo_w_data_full_int,
tx_fifo_w_data_usedw => tx_fifo_w_data_usedw_int,
tx_fifo_wr_head_usedw => tx_fifo_wr_head_usedw_int,
-- Rx Module
rx_tag_nbr => tag_nbr_int,
rx_tag_rcvd => rx_tag_rcvd_int,
-- init
bus_dev_func => bus_dev_func_int,
-- max_read => max_read_int,
max_payload => max_payload_int,
-- error
tx_compl_abort => tx_compl_abort_int,
tx_timeout => tx_timeout_int
);
init_comp : init
port map(
core_clk => core_clk, -- synchronous to core_clk from hard IP core
clk => clk,
rst => rst,
-- IP core
tl_cfg_add => tl_cfg_add,
tl_cfg_ctl => tl_cfg_ctl,
tl_cfg_ctl_wr => tl_cfg_ctl_wr,
tl_cfg_sts => tl_cfg_sts,
tl_cfg_sts_wr => tl_cfg_sts_wr,
-- interrupt module
cfg_msicsr => cfg_msicsr_int,
-- Tx Module
bus_dev_func => bus_dev_func_int,
max_read => max_read_int,
max_payload => max_payload_int
);
wb_slave_comp : z091_01_wb_slave
generic map(
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH, -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS => WBS_SUSPEND_FIFO_ACCESS, -- = 1020 DW, one place spare for put_stuffing
RESUME_FIFO_ACCESS => WBS_RESUME_FIFO_ACCESS -- = 1015 DW
)
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- Wishbone
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- Rx Module
rx_fifo_c_empty => rx_fifo_c_empty_int,
rx_fifo_c_out => rx_fifo_c_out_int,
rx_fifo_c_rd_enable => rx_fifo_c_rd_enable_int,
-- Tx Module
tx_fifo_wr_head_full => tx_fifo_wr_head_full_int,
tx_fifo_w_data_full => tx_fifo_w_data_full_int,
tx_fifo_w_data_usedw => tx_fifo_w_data_usedw_int,
tx_fifo_wr_head_usedw => tx_fifo_wr_head_usedw_int,
tx_fifo_wr_head_clr => tx_fifo_wr_head_clr_int,
tx_fifo_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_fifo_wr_head_in => tx_fifo_wr_head_in_int,
tx_fifo_w_data_clr => tx_fifo_w_data_clr_int,
tx_fifo_w_data_enable => tx_fifo_w_data_enable_int,
tx_fifo_w_data_in => tx_fifo_w_data_in_int,
max_read => max_read_int,
-- error
error_ecrc_err => ecrc_err_wb_int,
error_timeout => timeout_wb_int
);
interrupt_core_comp : interrupt_core
port map(
clk => clk,
rst => rst,
-- IP Core
app_int_ack => app_int_ack,
app_msi_ack => app_msi_ack,
app_int_sts => app_int_sts,
app_msi_req => app_msi_req,
app_msi_tc => app_msi_tc,
app_msi_num => app_msi_num,
pex_msi_num => pex_msi_num,
-- interrupt_wb
wb_pwr_en => wb_pwr_en_int,
wb_num_int => wb_num_int_int,
wb_inter => wb_inter_int,
ack_ok => ack_ok_int,
inter_ack => inter_ack_int,
num_allowed => num_allowed_int,
-- init
cfg_msicsr => cfg_msicsr_int,
-- error
wb_num_err => wb_num_err_int
);
interrupt_wb_comp : interrupt_wb
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- interrupt_core
inter_ack => inter_ack_int,
num_allowed => num_allowed_int,
wb_pwr_en => wb_pwr_en_int,
wb_num_int => wb_num_int_int,
wb_inter => wb_inter_int,
ack_ok => ack_ok_int,
-- Wishbone
wb_int => wb_int,
wb_pwr_enable => wb_pwr_enable,
wb_int_num => wb_int_num,
wb_int_ack => wb_int_ack,
wb_int_num_allowed => wb_int_num_allowed
);
-------------------------------------------------------------------------------
error_timeout <= timeout_wb_int;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_arch;
| gpl-3.0 | 903bb91a428a86ac5f3099a64e40c5b4 | 0.471859 | 3.469361 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/original.vhd | 3 | 28,019 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstNum -- IP to Bus burst size indicator
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
------------------------------------------------------------------------------
entity user_logic is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 8
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity user_logic;
architecture IMP of user_logic is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 5);
signal slv_reg_read_select : std_logic_vector(0 to 5);
signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for write/read data
signal mst_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal mst_reg_read_request : std_logic;
signal mst_reg_write_select : std_logic_vector(0 to 1);
signal mst_reg_read_select : std_logic_vector(0 to 1);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_ip2bus_be : std_logic_vector(0 to C_DWIDTH/8-1);
signal mst_go : std_logic;
-- signals for master control state machine
type MASTER_CNTL_SM_TYPE is (IDLE, SINGLE, BURST_16, LAST_BURST, CHK_BURST_DONE);
signal mst_cntl_state : MASTER_CNTL_SM_TYPE;
signal mst_sm_set_done : std_logic;
signal mst_sm_busy : std_logic;
signal mst_sm_clr_go : std_logic;
signal mst_sm_rd_req : std_logic;
signal mst_sm_wr_req : std_logic;
signal mst_sm_burst : std_logic;
signal mst_sm_bus_lock : std_logic;
signal mst_sm_ip2bus_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_sm_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mst_sm_ip2bus_be : std_logic_vector(0 to C_DWIDTH/8-1);
signal mst_sm_ip2bus_mstnum : std_logic_vector(0 to 4);
signal mst_xfer_length : integer;
signal mst_xfer_count : integer;
signal mst_ip_addr_count : integer;
signal mst_bus_addr_count : integer;
signal tid_reg : std_logic_vector(0 to C_DWIDTH-1);
signal tmr_reg : std_logic_vector(0 to C_DWIDTH-1);
signal sta_reg : std_logic_vector(0 to C_DWIDTH-1);
signal cmd_reg : std_logic_vector(0 to C_DWIDTH-1);
signal arg_reg : std_logic_vector(0 to C_DWIDTH-1);
signal res_reg : std_logic_vector(0 to C_DWIDTH-1);
alias tid_read : std_logic is Bus2IP_RdCE(0);
alias tmr_read : std_logic is Bus2IP_RdCE(1);
alias sta_read : std_logic is Bus2IP_RdCE(2);
alias cmd_read : std_logic is Bus2IP_RdCE(3);
alias arg_read : std_logic is Bus2IP_RdCE(4);
alias res_read : std_logic is Bus2IP_RdCE(5);
alias tid_write : std_logic is Bus2IP_WrCE(0);
alias tmr_write : std_logic is Bus2IP_WrCE(1);
alias sta_write : std_logic is Bus2IP_WrCE(2);
alias cmd_write : std_logic is Bus2IP_WrCE(3);
alias arg_write : std_logic is Bus2IP_WrCE(4);
alias res_write : std_logic is Bus2IP_WrCE(5);
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 5);
slv_reg_read_select <= Bus2IP_RdCE(0 to 5);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
else
case slv_reg_write_select is
when "100000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "000001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5 ) is
begin
case slv_reg_read_select is
when "100000" => slv_ip2bus_data <= slv_reg0;
when "010000" => slv_ip2bus_data <= slv_reg1;
when "001000" => slv_ip2bus_data <= slv_reg2;
when "000100" => slv_ip2bus_data <= slv_reg3;
when "000010" => slv_ip2bus_data <= slv_reg4;
when "000001" => slv_ip2bus_data <= slv_reg5;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the IPIF IP master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the IPIF
-- IP master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Bsy (User Logic Master is Busy)
-- bit 2-7 - Spare (Spare Status Bits)
-- IP2IP Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - IP2IP Address (This 32-bit value is used to populate the
-- IP2IP_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- IP2Bus Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-31 - IP2Bus Address (This 32-bit value is used to populate the
-- IP2Bus_Addr(0:31) address bus during a Read or Write user
-- logic master operation)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-15 - Transfer Length (This 16-bit value is used to specify the
-- number of bytes (1 to 65,536) to transfer during user logic
-- master read or write operations)
-- BE Register (C_BASEADDR + OFFSET + 0xE):
-- bit 0-7 - IP2Bus master BE (This 8-bit value is used to populate the
-- IP2Bus_MstBE byte enable bus during user logic master read or
-- write operations, only used in single data beat operation)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (A write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus register
-- - note: this address will be put on the target bus address line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write operation
--
------------------------------------------
mst_reg_read_request <= Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
mst_reg_write_select <= Bus2IP_WrCE(6 to 7);
mst_reg_read_select <= Bus2IP_RdCE(6 to 7);
mst_write_ack <= Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
mst_read_ack <= Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- user logic master request output assignments
IP2Bus_Addr <= mst_sm_ip2bus_addr;
IP2Bus_MstBE <= mst_sm_ip2bus_be;
IP2Bus_MstBurst <= mst_sm_burst;
IP2Bus_MstBusLock <= mst_sm_bus_lock;
IP2Bus_MstNum <= mst_sm_ip2bus_mstnum;
IP2Bus_MstRdReq <= mst_sm_rd_req;
IP2Bus_MstWrReq <= mst_sm_wr_req;
IP2IP_Addr <= mst_sm_ip2ip_addr;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2ip_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_addr <= mst_reg(8) & mst_reg(9) & mst_reg(10) & mst_reg(11);
mst_xfer_length <= CONV_INTEGER(mst_reg(12) & mst_reg(13));
mst_ip2bus_be <= mst_reg(14);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, Bus2IP_WrReq, mst_reg_write_select ) is
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= Bus2IP_WrReq and
mst_reg_write_select(byte_index/(C_DWIDTH/8)) and
Bus2IP_BE(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8));
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/(C_DWIDTH/8))*(C_DWIDTH/8))*8);
else
-- 'Done' from master control state machine
mst_reg(1)(0) <= mst_sm_set_done or mst_reg(1)(0);
end if;
-- ip2ip address register (byte 4 to 7)
-- ip2bus address register (byte 8 to 11)
-- length register (byte 12 to 13)
-- be register (byte 14)
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8 to
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/(C_DWIDTH/8))*(C_DWIDTH/8))*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/(C_DWIDTH/8))*(C_DWIDTH/8))*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_select, mst_reg ) is
begin
case mst_reg_read_select is
when "10" =>
for byte_index in 0 to C_DWIDTH/8-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "01" =>
for byte_index in 0 to C_DWIDTH/8-1 loop
if ( byte_index = C_DWIDTH/8-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg((C_DWIDTH/8)*1+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
--implement master model control state machine
MASTER_CNTL_STATE_MACHINE : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_cntl_state <= IDLE;
mst_sm_clr_go <= '0';
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
mst_sm_burst <= '0';
mst_sm_bus_lock <= '0';
mst_sm_ip2bus_addr <= (others => '0');
mst_sm_ip2bus_be <= (others => '0');
mst_sm_ip2ip_addr <= (others => '0');
mst_sm_ip2bus_mstnum <= "00000";
mst_sm_set_done <= '0';
mst_sm_busy <= '0';
mst_xfer_count <= 0;
mst_bus_addr_count <= 0;
mst_ip_addr_count <= 0;
else
-- default condition
mst_sm_clr_go <= '0';
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
mst_sm_burst <= '0';
mst_sm_bus_lock <= '0';
mst_sm_ip2bus_addr <= (others => '0');
mst_sm_ip2bus_be <= (others => '0');
mst_sm_ip2ip_addr <= (others => '0');
mst_sm_ip2bus_mstnum <= "00000";
mst_sm_set_done <= '0';
mst_sm_busy <= '1';
-- state transition
case mst_cntl_state is
when IDLE =>
if ( mst_go = '1' and mst_xfer_length <= 8 ) then
-- single beat transfer
mst_cntl_state <= SINGLE;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
elsif ( mst_go = '1' and mst_xfer_length < 128 ) then
-- burst transfer less than 128 bytes
mst_cntl_state <= LAST_BURST;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
elsif ( mst_go = '1' ) then
-- burst transfer greater than 128 bytes
mst_cntl_state <= BURST_16;
mst_sm_clr_go <= '1';
mst_xfer_count <= CONV_INTEGER(mst_xfer_length);
mst_bus_addr_count <= CONV_INTEGER(mst_ip2bus_addr);
mst_ip_addr_count <= CONV_INTEGER(mst_ip2ip_addr);
else
mst_cntl_state <= IDLE;
mst_sm_busy <= '0';
end if;
when SINGLE =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= IDLE;
mst_sm_set_done <= '1';
mst_sm_busy <= '0';
else
mst_cntl_state <= SINGLE;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= mst_ip2bus_be;
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= "00001";
end if;
when BURST_16 =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= CHK_BURST_DONE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_xfer_count <= mst_xfer_count-128;
mst_bus_addr_count <= mst_bus_addr_count+128;
mst_ip_addr_count <= mst_ip_addr_count+128;
else
mst_cntl_state <= BURST_16;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_burst <= mst_cntl_burst;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= (others => '1');
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= "10000"; -- 16 double words
end if;
when LAST_BURST =>
if ( Bus2IP_MstLastAck = '1' ) then
mst_cntl_state <= CHK_BURST_DONE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_xfer_count <= mst_xfer_count-((mst_xfer_count/8)*8);
mst_bus_addr_count <= mst_bus_addr_count+(mst_xfer_count/8)*8;
mst_ip_addr_count <= mst_ip_addr_count+(mst_xfer_count/8)*8;
else
mst_cntl_state <= LAST_BURST;
mst_sm_rd_req <= mst_cntl_rd_req;
mst_sm_wr_req <= mst_cntl_wr_req;
mst_sm_burst <= mst_cntl_burst;
mst_sm_bus_lock <= mst_cntl_bus_lock;
mst_sm_ip2bus_addr <= CONV_STD_LOGIC_VECTOR(mst_bus_addr_count, C_AWIDTH);
mst_sm_ip2bus_be <= (others => '1');
mst_sm_ip2ip_addr <= CONV_STD_LOGIC_VECTOR(mst_ip_addr_count, C_AWIDTH);
mst_sm_ip2bus_mstnum <= CONV_STD_LOGIC_VECTOR((mst_xfer_count/8), 5);
end if;
when CHK_BURST_DONE =>
if ( mst_xfer_count = 0 ) then
-- transfer done
mst_cntl_state <= IDLE;
mst_sm_set_done <= '1';
mst_sm_busy <= '0';
elsif ( mst_xfer_count <= 8 ) then
-- need single beat transfer
mst_cntl_state <= SINGLE;
mst_sm_bus_lock <= mst_cntl_bus_lock;
elsif ( mst_xfer_count < 128 ) then
-- need burst transfer less than 128 bytes
mst_cntl_state <= LAST_BURST;
mst_sm_bus_lock <= mst_cntl_bus_lock;
else
-- need burst transfer greater than 128 bytes
mst_cntl_state <= BURST_16;
mst_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when others =>
mst_cntl_state <= IDLE;
mst_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CNTL_STATE_MACHINE;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= mst_ip2bus_data when mst_reg_read_request = '1' else
slv_ip2bus_data;
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
| bsd-3-clause | 5e23cb6b6397698a85ea0858a0f3772e | 0.523288 | 3.452316 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethtx.vhd | 1 | 11,185 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ethtx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RD_CYCLE : natural := 1;
RD_DELAY : natural := 1;
RAM_AWIDTH : natural := 32
);
port (
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
-- ram_raddr : out std_logic_vector(23 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- ram_rdata : in std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- local time --
localtime : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch_ethtx of ethtx is
component ethtx_output
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_rdata : in std_logic_vector(7 downto 0);
dma_start : out std_logic;
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
-- local time --
localtime: in std_logic_vector(31 downto 0)
);
end component;
component Tx_queue
generic(
HEAD_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RAM_TYPE : STRING := "DIS_RAM");
port(
clk : in std_logic;
reset : in std_logic;
queue_empty : out std_logic;
head_raddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component disdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
A : in std_logic_vector((Awidth-1) downto 0);
CLK : in std_logic;
D : in std_logic_vector((Dwidth-1) downto 0);
WE : in std_logic;
DPRA : in std_logic_vector((Awidth-1) downto 0);
DPO : out std_logic_vector((Dwidth-1) downto 0);
QDPO : out std_logic_vector((Dwidth-1) downto 0));
end component;
component dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((DWIDTH-1) downto 0));
end component;
signal tx_queue_empty : std_logic;
signal tx_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal tx_head_rdata : std_logic_vector(7 downto 0);
signal tx_head_rd_block : std_logic;
signal db_queue_empty : std_logic;
signal db_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal db_head_rdata : std_logic_vector(7 downto 0);
signal db_head_rd_block : std_logic;
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(7 downto 0);
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(7 downto 0);
signal dma_length : std_logic_vector(15 downto 0);
-- signal dma_start_raddr : std_logic_vector(23 downto 0);
signal dma_start_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
-- signal dma_raddr : std_logic_vector(23 downto 0);
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_rdata : std_logic_vector(7 downto 0);
signal dma_rdata : std_logic_vector(15 downto 0);
signal dma_wdata_word : std_logic_vector(15 downto 0);
signal dma_length_word : std_logic_vector(15 downto 0);
signal dma_waddr_word : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wren_word : std_logic;
signal flag : std_logic;
signal buff_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal buff_wdata_reg : std_logic_vector(15 downto 0);
signal dma_wren_reg : std_logic;
-- signal dma_wren : std_logic;
-- signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_wdata : std_logic_vector(7 downto 0);
signal dma_ena : std_logic;
signal buff_wr_diff : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
begin
u_output : ethtx_output
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen,
tx_queue_empty => tx_queue_empty,
tx_head_raddr => tx_head_raddr,
tx_head_rdata => tx_head_rdata,
tx_head_rd_block => tx_head_rd_block,
db_queue_empty => db_queue_empty,
db_head_raddr => db_head_raddr,
db_head_rdata => db_head_rdata,
db_head_rd_block => db_head_rd_block,
buff_raddr => buff_raddr,
buff_rdata => buff_rdata,
dma_start => dma_start,
dma_start_addr => dma_start_raddr,
dma_length => dma_length,
dma_step => dma_rstep,
-- local time
localtime => localtime
);
u_db_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 0,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => db_queue_empty,
head_raddr => db_head_raddr,
head_rdata => db_head_rdata,
head_rd_block => db_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_tx_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => tx_queue_empty,
head_raddr => tx_head_raddr,
head_rdata => tx_head_rdata,
head_rd_block => tx_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_tx_buffer : disdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 8
)
port map(
A => buff_waddr(BUFF_AWIDTH - 1 downto 0),
CLK => clk,
D => buff_wdata,
WE => buff_wren,
DPRA => buff_raddr(BUFF_AWIDTH - 1 downto 0),
DPO => buff_rdata,
QDPO => open
);
u_dma : dma_ctrl
generic map(
DWIDTH => 16,
RD_CYCLE => RD_CYCLE,
RD_DELAY => RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => dma_ena,
start => dma_start,
length => dma_length_word,
start_waddr => (others => '0'),
start_raddr => dma_start_raddr,
wstep => X"01",
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren_word,
waddr => dma_waddr_word,
wdata => dma_wdata_word
);
----------
dma_length_word <= '0'&dma_length(15 downto 1);
--- process(reset, clk)
---- begin
-- if reset = '1' then
--- wren_byte <= '0';
-- elsif rising_edge(clk) then
-- if dma_wren_byte = '1' then
-- wren_byte <= dma_wren_byte;
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'0';
-- buff_wdata <= dma_wdata_byte(7 downto 0);
-- elsif flag = '1' then
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'1';
-- buff_wdata <= dma_wdata_byte(15 downto 8);
-- end if;
-- end if;
-- end process;
process(reset, clk)
begin
if reset = '1' then
buff_waddr_reg <= (others => '0');
buff_wdata_reg <= (others => '0');
dma_wren_reg <= '0';
elsif rising_edge(clk) then
if dma_wren_word = '1' then
buff_waddr_reg <= dma_waddr_word;
buff_wdata_reg <= dma_wdata_word;
end if;
dma_wren_reg <= dma_wren_word;
end if;
end process;
buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'0' when dma_wren_reg = '1' else
buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'1' ;
buff_wdata <= buff_wdata_reg(7 downto 0) when dma_wren_reg = '1' else
buff_wdata_reg(15 downto 8);
process(reset, clk)
begin
if reset = '1' then
flag <= '0';
elsif rising_edge(clk) then
-- if wren_byte = '1' then
flag <= dma_wren_reg;
-- end if;
end if;
end process;
buff_wren <= flag or dma_wren_reg;
ram_raddr <= dma_raddr;
dma_rdata <= ram_rdata;
-- buff_wren <= dma_wren;
-- buff_waddr <= dma_waddr(BUFF_AWIDTH - 1 downto 0);
-- buff_wdata <= dma_wdata;
buff_wr_diff <= buff_waddr - buff_raddr;
p_dma_ena : process(clk, reset)
begin
if reset = '1' then
dma_ena <= '1';
elsif rising_edge(clk) then
if buff_wr_diff >= 2 ** BUFF_AWIDTH - RD_CYCLE - RD_DELAY - 4 then
dma_ena <= '0';
elsif buff_wr_diff <= RD_CYCLE + RD_DELAY + 2 then
dma_ena <= '1';
end if;
end if;
end process;
end arch_ethtx;
| gpl-2.0 | f7bfadf39e6fc86f238185ab6e93394c | 0.612785 | 2.671364 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/bram_if_cntlr_v1_00_b/hdl/vhdl/bram_if.vhd | 2 | 12,177 | -------------------------------------------------------------------------------
-- $Id: bram_if.vhd,v 1.2 2004/02/19 17:55:27 gburch Exp $
-------------------------------------------------------------------------------
-- bram_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: bram_if.vhd
-- Version: v1.00b
-- Description: This design module is for a simple byte addressable memory
-- using the Xilinx BRAM primitives present in Xilinx FPGA
-- devices.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- bram_if.vhd
-------------------------------------------------------------------------------
-- Author: DAB
-- Revision: $Revision: 1.2 $
-- Date: $4/5/2002$
--
-- History:
-- dab 6/12/2002 Initial Version
--
-- GAB 01-05-2003
-- ^^^^^^
-- Update to support plb_ipif_v1_00_e
-- Fixed problem where Bus2IP_RdReq was only a single clock cycle
-- causing a problem with burst transfers
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IPIF_DWIDTH -- IPIC data width
-- C_IPIF_AWIDTH -- IPIC address width
--
-- Definition of Ports:
-- -- Clock and reset
-- bus_reset -- Reset
-- bus_clk -- PLB/OPB clock
--
-- -- IPIC
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_Data -- Processor data
-- Bus2IP_BRAM_CS -- BRAM is being accessed
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_RdReq -- Processor read request
--
-- -- IPIC outputs
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_Retry -- Retry indicator
-- IP2Bus_ToutSup -- Suppress watch dog timer
--
-- -- BRAM interface signals
-- BRAM_Rst -- BRAM reset
-- BRAM_CLK -- BRAM clock
-- BRAM_EN -- BRAM chip enable
-- BRAM_WEN -- BRAM write enable
-- BRAM_Addr -- BRAM address
-- BRAM_Dout -- BRAM write data
-- BRAM_Din -- BRAM read data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity bram_if is
generic (
C_IPIF_AWIDTH : Integer := 32;
-- The width if the IPIF address bus
C_IPIF_DWIDTH : Integer := 64
-- The width of the IPIF data bus
);
port (
-- input ports
bus_reset : in std_logic;
bus_clk : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BRAM_CS : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
-- Output ports
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
--BRAM Ports
BRAM_Rst : out std_logic;
BRAM_CLK : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1); --Qualified WE
BRAM_Addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
BRAM_Din : in std_logic_vector(0 to C_IPIF_DWIDTH-1)
);
end entity bram_if;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of bram_if is
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others=>r);
return( l and rex );
end function "and";
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal IP2Bus_Data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal IP2Bus_RdAck_i : std_logic;
signal IP2Bus_WrAck_i : std_logic;
signal address_bus_i : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal write_data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal read_data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal read_enable : std_logic;
signal BRAM_QWEN : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- (architecture implementation)
-- (Misc Assignments)
address_bus_i <= Bus2IP_ADDR;
write_data_i <= Bus2IP_Data;
read_enable <= Bus2IP_BRAM_CS and Bus2IP_RdReq;
IP2Bus_Data <= IP2Bus_Data_i;
IP2Bus_RdAck <= IP2Bus_RdAck_i;
IP2Bus_WrAck_i <= Bus2IP_BRAM_CS and Bus2IP_WrReq;
IP2Bus_WrAck <= IP2Bus_WrAck_i;
IP2Bus_AddrAck <= Bus2IP_BRAM_CS and (Bus2IP_RdReq or IP2Bus_WrAck_i);
IP2Bus_Retry <= '0';
IP2Bus_Error <= '0';
IP2Bus_ToutSup <= '0';
BRAM_QWEN <= (Bus2IP_BE and Bus2IP_WrReq);
-------------------------------------------------------------
-- Synchronous Process
--
-- Label: GEN_RD_ACK
--
-- Process Description:
-- This process generates the read acknowledge 1 clock after
-- read enable signal is presented to the BRAM block. The
-- BRAM block primitive has a 1 clock delay from read enable
-- to data out.
---------------------------------------------------------------
-- GEN_RD_ACK : process (bus_clk)
-- begin
-- if (bus_clk'event and bus_clk = '1') then
-- if (bus_reset = '1') then
--
-- read_enable_dly1 <= '0';
--
-- else
--
-- read_enable_dly1 <= read_enable;
--
-- end if;
--
--
-- if (bus_reset = '1') then
--
-- IP2Bus_RdAck_i <= '0';
--
-- elsif (read_enable_dly1 = '0' and
-- read_enable = '1') then
--
-- IP2Bus_RdAck_i <= '1';
--
-- else
--
-- IP2Bus_RdAck_i <= '0';
--
-- end if;
--
-- else
-- null;
-- end if;
--
-- end process GEN_RD_ACK;
GEN_RD_ACK : process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (bus_reset = '1') then
IP2Bus_RdAck_i <= '0';
else
IP2Bus_RdAck_i <= read_enable;
end if;
end if;
end process GEN_RD_ACK;
-------------------------------------------------------------
-- Assign the read data
--
-- No mux is necessary since the bram data is the only data
-- source
-------------------------------------------------------------
IP2Bus_Data_i <= read_data_i;
------------------------------------------------------------
-- Label: CONNECT_BRAM
--
-- Concurrent signal assignments to connect the BRAM
-- interface
------------------------------------------------------------
-- Port A signals
BRAM_Rst <= bus_reset;
BRAM_Clk <= bus_clk;
BRAM_EN <= Bus2IP_BRAM_CS;
BRAM_WEN <= BRAM_QWEN;
BRAM_Addr <= address_bus_i;
BRAM_Dout <= write_data_i;
read_data_i <= BRAM_Din;
end implementation;
| bsd-3-clause | bbfb516e958e39e557c7e93c7f8e6c31 | 0.416769 | 4.359828 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_top.vhd | 3 | 19,639 | -------------------------------------------------------------------------------
-- $Id: rdpfifo_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--rdpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Read Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
-- rdpfifo_top.vhd
-- |
-- |---> ipif_control_rd.vhd
-- |
-- |---> rdpfifo_dp_cntl.vhd
-- | |
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |---> pf_dpram_select.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET APR-24-01
-- - Changed dual port configuration name to
-- rdport_512x32 from dport_512x32.
--
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- - Commented out the rpfifo_lib declarations.
--
-- DET June-11-01 V1.00b
-- - Modified the IPIF Interface callout for the version b.
--
-- DET June-23-01 V1.00b
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
--
-- DET June-25-01 V1.00b
-- - Upadated the IPIF read control module to version c as part of the
-- removal of redundant logic warnings from Synplicity synthesis.
-- - Updated the Dual Port control module to version d as part of the
-- removal of redundant logic warnings from Synplicity synthesis.
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
--
-- DET Aug 19, 2001 v1.01a
-- - Platform Generator compilancy modifications
-- - Added generic to select Virtex E or Virtex II DP core
-- - Imbedded configurations for DP simulation in the design
-- body.
--
--
-- DET Sept. 26, 2001 (part of v1.02a version)
-- - Added the optimization changes
-- - Added additional parameters (generics)
--
--
-- DET Oct. 7, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ipif_control_rd;
use opb_ipif_v2_00_h.rdpfifo_dp_cntl;
use opb_ipif_v2_00_h.pf_dpram_select;
use opb_ipif_v2_00_h.srl16_fifo;
-------------------------------------------------------------------------------
entity rdpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
-- True = virtex ii family
-- False = virtex family
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2RFIFO_WrReq : In std_logic;
IP2RFIFO_WrMark : In std_logic;
IP2RFIFO_WrRestore : In std_logic;
IP2RFIFO_WrRelease : In std_logic;
IP2RFIFO_Data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
-- Outputs to the IP
RFIFO2IP_WrAck : Out std_logic;
RFIFO2IP_AlmostFull : Out std_logic;
RFIFO2IP_Full : Out std_logic;
RFIFO2IP_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty : Out std_logic;
RFIFO2DMA_Empty : Out std_logic;
RFIFO2DMA_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end rdpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_top is
-- COMPONENTS
-- The IPIF Local Bus Interface Block
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the RPFIFO design
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the RPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 2;
-- IPIF block protocol Type
-- (Read Packet FIFO = 2, Write PFIFO = 3)
-- General Use Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to
C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to
C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to
C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_data_wrack: std_logic;
Signal sig_bramfifo_rdack: std_logic;
Signal sig_srlfifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_rd_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_bram_rdreq : std_logic;
Signal sig_srl_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
Signal sig_bus_dbus_lsnib: std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
------------- start processes -------------------------------------------------
begin
sig_bus_dbus_lsnib <= Bus_DBus(C_IPIF_DBUS_WIDTH-4 to C_IPIF_DBUS_WIDTH-1);
-- connect I/O signals to internals
RFIFO2IP_WrAck <= sig_data_wrack;
RFIFO2IP_Full <= sig_fifo_full;
RFIFO2IP_AlmostFull <= sig_fifo_almost_full;
RFIFO2DMA_AlmostEmpty <= sig_fifo_almost_empty;
RFIFO2DMA_Empty <= sig_fifo_empty;
RFIFO2IP_Vacancy <= sig_fifo_vacancy;
RFIFO2DMA_Occupancy <= sig_fifo_occupancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_wrreq <= IP2RFIFO_WrReq;
sig_mem_wr_data <= IP2RFIFO_Data;
I_IPIF_INTERFACE_BLOCK : entity opb_ipif_v2_00_h.ipif_control_rd
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_Clk => Bus_Clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => sig_bus_dbus_lsnib,
-- Inputs from the FIFO Interface Logic
Fifo_rd_data => sig_mem_rd_data ,
BRAMFifo_RdAck => sig_bramfifo_rdack ,
SRLFifo_RdAck => sig_srlfifo_rdack ,
Occupancy => sig_fifo_occupancy ,
AlmostEmpty => sig_fifo_almost_empty ,
Empty => sig_fifo_empty ,
Deadlock => sig_fifo_deadlock ,
-- Outputs to the FIFO
Fifo_rst => sig_fifo_logic_reset ,
BRAMFifo_RdReq => sig_bram_rdreq ,
SRLFifo_RdReq => sig_srl_rdreq ,
Fifo_burst_rd_xfer => sig_burst_rd_xfer ,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
-- The Dual Port Control Block
begin
sig_srlfifo_rdack <= '0';
-- Connect the Dual Port Address Controller to the VHDL wrapper
I_DP_CONTROLLER: entity opb_ipif_v2_00_h.rdpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_Clk ,
Rdreq => sig_bram_rdreq,
Wrreq => sig_mem_wrreq,
Burst_rd_xfer => sig_burst_rd_xfer,
Mark => IP2RFIFO_WrMark ,
Restore => IP2RFIFO_WrRestore,
Release => IP2RFIFO_WrRelease,
-- Outputs
WrAck => sig_data_wrack,
RdAck => sig_bramfifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_ipif_v2_00_h.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_srlfifo_rdack <= sig_srl_rdreq and not(sig_fifo_empty);
sig_data_wrack <= sig_mem_wrreq and not(sig_fifo_full);
sig_bramfifo_rdack <= '0';
I_SRL_MEM : entity opb_ipif_v2_00_h.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_srl_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
| bsd-3-clause | 9aa346a8802683f0669f1c9902fb1602 | 0.451398 | 4.014513 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/tx_compl_timeout.vhd | 1 | 27,762 | --------------------------------------------------------------------------------
-- Title : tx_compl_timeout
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_compl_timeout.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module controls the tag ID timeout timer, the maximum number of tags
-- is limited to 32
-- at present counters are only started for read requests and reset when the
-- appropriate completion is received
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- * tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_compl_timeout is
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25 -- timeout for one tag ID
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end entity tx_compl_timeout;
-- ****************************************************************************
architecture tx_compl_timeout_arch of tx_compl_timeout is
-- internal signals -----------------------------------------------------------
signal clk_500_q : std_logic;
signal clk_500_qq : std_logic;
signal clk_500_qqq : std_logic;
signal rise : std_logic;
signal timer_overview : std_logic_vector(31 downto 0);
-- initial values assigned due to Quartus II Synthesis critical warning
signal timer_0 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_1 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_2 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_3 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_4 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_5 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_6 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_7 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_8 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_9 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_10 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_11 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_12 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_13 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_14 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_15 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_16 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_17 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_18 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_19 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_20 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_21 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_22 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_23 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_24 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_25 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_26 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_27 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_28 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_29 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_30 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_31 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timeout_int : std_logic;
-------------------------------------------------------------------------------
begin
-- sample clock that processes 50ms timeout counting
clk_500_q <= '0' when rst = '1' else
clk_500 when rising_edge(clk);
clk_500_qq <= '0' when rst = '1' else
clk_500_q when rising_edge(clk);
clk_500_qqq <= '0' when rst = '1' else
clk_500_qq when rising_edge(clk);
-------------------------------------------------------------------------------
count : process(clk, rst)
begin
if(rst = '1') then
-- ports:
timeout <= '0';
-- signals:
timer_overview <= (others => '0');
timer_0 <= TIMEOUT_TIME;
timer_1 <= TIMEOUT_TIME;
timer_2 <= TIMEOUT_TIME;
timer_3 <= TIMEOUT_TIME;
timer_4 <= TIMEOUT_TIME;
timer_5 <= TIMEOUT_TIME;
timer_6 <= TIMEOUT_TIME;
timer_7 <= TIMEOUT_TIME;
timer_8 <= TIMEOUT_TIME;
timer_9 <= TIMEOUT_TIME;
timer_10 <= TIMEOUT_TIME;
timer_11 <= TIMEOUT_TIME;
timer_12 <= TIMEOUT_TIME;
timer_13 <= TIMEOUT_TIME;
timer_14 <= TIMEOUT_TIME;
timer_15 <= TIMEOUT_TIME;
timer_16 <= TIMEOUT_TIME;
timer_17 <= TIMEOUT_TIME;
timer_18 <= TIMEOUT_TIME;
timer_19 <= TIMEOUT_TIME;
timer_20 <= TIMEOUT_TIME;
timer_21 <= TIMEOUT_TIME;
timer_22 <= TIMEOUT_TIME;
timer_23 <= TIMEOUT_TIME;
timer_24 <= TIMEOUT_TIME;
timer_25 <= TIMEOUT_TIME;
timer_26 <= TIMEOUT_TIME;
timer_27 <= TIMEOUT_TIME;
timer_28 <= TIMEOUT_TIME;
timer_29 <= TIMEOUT_TIME;
timer_30 <= TIMEOUT_TIME;
timer_31 <= TIMEOUT_TIME;
timeout_int <= '0';
rise <= '0';
elsif(clk'event and clk = '1') then
-- when rising edge on clk_500 then enable counting
if(clk_500_qq = '1' and clk_500_qqq = '0') then
rise <= '1';
else
rise <= '0';
end if;
-- state of counters (running or not) is administered using the internal register timer_overview
-- if a timer (diplayed by tag_nbr_in) is started, set equivalent bit in register
if(start = '1') then -- start timers
case tag_nbr_in is
when "00000" =>
timer_overview(0) <= '1';
when "00001" =>
timer_overview(1) <= '1';
when "00010" =>
timer_overview(2) <= '1';
when "00011" =>
timer_overview(3) <= '1';
when "00100" =>
timer_overview(4) <= '1';
when "00101" =>
timer_overview(5) <= '1';
when "00110" =>
timer_overview(6) <= '1';
when "00111" =>
timer_overview(7) <= '1';
when "01000" =>
timer_overview(8) <= '1';
when "01001" =>
timer_overview(9) <= '1';
when "01010" =>
timer_overview(10) <= '1';
when "01011" =>
timer_overview(11) <= '1';
when "01100" =>
timer_overview(12) <= '1';
when "01101" =>
timer_overview(13) <= '1';
when "01110" =>
timer_overview(14) <= '1';
when "01111" =>
timer_overview(15) <= '1';
when "10000" =>
timer_overview(16) <= '1';
when "10001" =>
timer_overview(17) <= '1';
when "10010" =>
timer_overview(18) <= '1';
when "10011" =>
timer_overview(19) <= '1';
when "10100" =>
timer_overview(20) <= '1';
when "10101" =>
timer_overview(21) <= '1';
when "10110" =>
timer_overview(22) <= '1';
when "10111" =>
timer_overview(23) <= '1';
when "11000" =>
timer_overview(24) <= '1';
when "11001" =>
timer_overview(25) <= '1';
when "11010" =>
timer_overview(26) <= '1';
when "11011" =>
timer_overview(27) <= '1';
when "11100" =>
timer_overview(28) <= '1';
when "11101" =>
timer_overview(29) <= '1';
when "11110" =>
timer_overview(30) <= '1';
when "11111" =>
timer_overview(31) <= '1';
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded case in tag_nbr_in" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
-- if a tag number is received from rx_module reset according bit in timer_overview register and thus deactivate
-- the timer
if(rx_tag_rcvd = '1') then -- clear timers
case rx_tag_nbr(4 downto 0) is
when "00000" =>
timer_overview(0) <= '0';
when "00001" =>
timer_overview(1) <= '0';
when "00010" =>
timer_overview(2) <= '0';
when "00011" =>
timer_overview(3) <= '0';
when "00100" =>
timer_overview(4) <= '0';
when "00101" =>
timer_overview(5) <= '0';
when "00110" =>
timer_overview(6) <= '0';
when "00111" =>
timer_overview(7) <= '0';
when "01000" =>
timer_overview(8) <= '0';
when "01001" =>
timer_overview(9) <= '0';
when "01010" =>
timer_overview(10) <= '0';
when "01011" =>
timer_overview(11) <= '0';
when "01100" =>
timer_overview(12) <= '0';
when "01101" =>
timer_overview(13) <= '0';
when "01110" =>
timer_overview(14) <= '0';
when "01111" =>
timer_overview(15) <= '0';
when "10000" =>
timer_overview(16) <= '0';
when "10001" =>
timer_overview(17) <= '0';
when "10010" =>
timer_overview(18) <= '0';
when "10011" =>
timer_overview(19) <= '0';
when "10100" =>
timer_overview(20) <= '0';
when "10101" =>
timer_overview(21) <= '0';
when "10110" =>
timer_overview(22) <= '0';
when "10111" =>
timer_overview(23) <= '0';
when "11000" =>
timer_overview(24) <= '0';
when "11001" =>
timer_overview(25) <= '0';
when "11010" =>
timer_overview(26) <= '0';
when "11011" =>
timer_overview(27) <= '0';
when "11100" =>
timer_overview(28) <= '0';
when "11101" =>
timer_overview(29) <= '0';
when "11110" =>
timer_overview(30) <= '0';
when "11111" =>
timer_overview(31) <= '0';
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded case in rx_tag_nbr" severity warning;
-- synthesis translate_on
-- coverage on
end case;
end if;
-- if a timer is set and signal rise is asserted to propagate that enough time has passed
-- then decrement all active counters
-- if a counter has reached 0 assert signal timeout and reset timer_overview register
if(timer_overview(0) = '1' and rise = '1') then
if(timer_0 > 0) then
timer_0 <= timer_0 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(0) <= '0';
end if;
elsif(timer_overview(0) = '0') then
timer_0 <= TIMEOUT_TIME;
end if;
if(timer_overview(1) = '1' and rise = '1') then
if(timer_1 > 0) then
timer_1 <= timer_1 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(1) <= '0';
end if;
elsif(timer_overview(1) = '0') then
timer_1 <= TIMEOUT_TIME;
end if;
if(timer_overview(2) = '1' and rise = '1') then
if(timer_2 > 0) then
timer_2 <= timer_2 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(2) <= '0';
end if;
elsif(timer_overview(2) = '0') then
timer_2 <= TIMEOUT_TIME;
end if;
if(timer_overview(3) = '1' and rise = '1') then
if(timer_3 > 0) then
timer_3 <= timer_3 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(3) <= '0';
end if;
elsif(timer_overview(3) = '0') then
timer_3 <= TIMEOUT_TIME;
end if;
if(timer_overview(4) = '1' and rise = '1') then
if(timer_4 > 0) then
timer_4 <= timer_4 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(4) <= '0';
end if;
elsif(timer_overview(4) = '0') then
timer_4 <= TIMEOUT_TIME;
end if;
if(timer_overview(5) = '1' and rise = '1') then
if(timer_5 > 0) then
timer_5 <= timer_5 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(5) <= '0';
end if;
elsif(timer_overview(5) = '0') then
timer_5 <= TIMEOUT_TIME;
end if;
if(timer_overview(6) = '1' and rise = '1') then
if(timer_6 > 0) then
timer_6 <= timer_6 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(6) <= '0';
end if;
elsif(timer_overview(6) = '0') then
timer_6 <= TIMEOUT_TIME;
end if;
if(timer_overview(7) = '1' and rise = '1') then
if(timer_7 > 0) then
timer_7 <= timer_7 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(7) <= '0';
end if;
elsif(timer_overview(7) = '0') then
timer_7 <= TIMEOUT_TIME;
end if;
if(timer_overview(8) = '1' and rise = '1') then
if(timer_8 > 0) then
timer_8 <= timer_8 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(8) <= '0';
end if;
elsif(timer_overview(8) = '0') then
timer_8 <= TIMEOUT_TIME;
end if;
if(timer_overview(9) = '1' and rise = '1') then
if(timer_9 > 0) then
timer_9 <= timer_9 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(9) <= '0';
end if;
elsif(timer_overview(9) = '0') then
timer_9 <= TIMEOUT_TIME;
end if;
if(timer_overview(10) = '1' and rise = '1') then
if(timer_10 > 0) then
timer_10 <= timer_10 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(10) <= '0';
end if;
elsif(timer_overview(10) = '0') then
timer_10 <= TIMEOUT_TIME;
end if;
if(timer_overview(11) = '1' and rise = '1') then
if(timer_11 > 0) then
timer_11 <= timer_11 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(11) <= '0';
end if;
elsif(timer_overview(11) = '0') then
timer_11 <= TIMEOUT_TIME;
end if;
if(timer_overview(12) = '1' and rise = '1') then
if(timer_12 > 0) then
timer_12 <= timer_12 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(12) <= '0';
end if;
elsif(timer_overview(12) = '0') then
timer_12 <= TIMEOUT_TIME;
end if;
if(timer_overview(13) = '1' and rise = '1') then
if(timer_13 > 0) then
timer_13 <= timer_13 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(13) <= '0';
end if;
elsif(timer_overview(13) = '0') then
timer_13 <= TIMEOUT_TIME;
end if;
if(timer_overview(14) = '1' and rise = '1') then
if(timer_14 > 0) then
timer_14 <= timer_14 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(14) <= '0';
end if;
elsif(timer_overview(14) = '0') then
timer_14 <= TIMEOUT_TIME;
end if;
if(timer_overview(15) = '1' and rise = '1') then
if(timer_15 > 0) then
timer_15 <= timer_15 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(15) <= '0';
end if;
elsif(timer_overview(15) = '0') then
timer_15 <= TIMEOUT_TIME;
end if;
if(timer_overview(16) = '1' and rise = '1') then
if(timer_16 > 0) then
timer_16 <= timer_16 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(16) <= '0';
end if;
elsif(timer_overview(16) = '0') then
timer_16 <= TIMEOUT_TIME;
end if;
if(timer_overview(17) = '1' and rise = '1') then
if(timer_17 > 0) then
timer_17 <= timer_17 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(17) <= '0';
end if;
elsif(timer_overview(17) = '0') then
timer_17 <= TIMEOUT_TIME;
end if;
if(timer_overview(18) = '1' and rise = '1') then
if(timer_18 > 0) then
timer_18 <= timer_18 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(18) <= '0';
end if;
elsif(timer_overview(18) = '0') then
timer_18 <= TIMEOUT_TIME;
end if;
if(timer_overview(19) = '1' and rise = '1') then
if(timer_19 > 0) then
timer_19 <= timer_19 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(19) <= '0';
end if;
elsif(timer_overview(19) = '0') then
timer_19 <= TIMEOUT_TIME;
end if;
if(timer_overview(20) = '1' and rise = '1') then
if(timer_20 > 0) then
timer_20 <= timer_20 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(20) <= '0';
end if;
elsif(timer_overview(20) = '0') then
timer_20 <= TIMEOUT_TIME;
end if;
if(timer_overview(21) = '1' and rise = '1') then
if(timer_21 > 0) then
timer_21 <= timer_21 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(21) <= '0';
end if;
elsif(timer_overview(21) = '0') then
timer_21 <= TIMEOUT_TIME;
end if;
if(timer_overview(22) = '1' and rise = '1') then
if(timer_22 > 0) then
timer_22 <= timer_22 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(22) <= '0';
end if;
elsif(timer_overview(22) = '0') then
timer_22 <= TIMEOUT_TIME;
end if;
if(timer_overview(23) = '1' and rise = '1') then
if(timer_23 > 0) then
timer_23 <= timer_23 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(23) <= '0';
end if;
elsif(timer_overview(23) = '0') then
timer_23 <= TIMEOUT_TIME;
end if;
if(timer_overview(24) = '1' and rise = '1') then
if(timer_24 > 0) then
timer_24 <= timer_24 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(24) <= '0';
end if;
elsif(timer_overview(24) = '0') then
timer_24 <= TIMEOUT_TIME;
end if;
if(timer_overview(25) = '1' and rise = '1') then
if(timer_25 > 0) then
timer_25 <= timer_25 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(25) <= '0';
end if;
elsif(timer_overview(25) = '0') then
timer_25 <= TIMEOUT_TIME;
end if;
if(timer_overview(26) = '1' and rise = '1') then
if(timer_26 > 0) then
timer_26 <= timer_26 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(26) <= '0';
end if;
elsif(timer_overview(26) = '0') then
timer_26 <= TIMEOUT_TIME;
end if;
if(timer_overview(27) = '1' and rise = '1') then
if(timer_27 > 0) then
timer_27 <= timer_27 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(27) <= '0';
end if;
elsif(timer_overview(27) = '0') then
timer_27 <= TIMEOUT_TIME;
end if;
if(timer_overview(28) = '1' and rise = '1') then
if(timer_28 > 0) then
timer_28 <= timer_28 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(28) <= '0';
end if;
elsif(timer_overview(28) = '0') then
timer_28 <= TIMEOUT_TIME;
end if;
if(timer_overview(29) = '1' and rise = '1') then
if(timer_29 > 0) then
timer_29 <= timer_29 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(29) <= '0';
end if;
elsif(timer_overview(29) = '0') then
timer_29 <= TIMEOUT_TIME;
end if;
if(timer_overview(30) = '1' and rise = '1') then
if(timer_30 > 0) then
timer_30 <= timer_30 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(30) <= '0';
end if;
elsif(timer_overview(30) = '0') then
timer_30 <= TIMEOUT_TIME;
end if;
if(timer_overview(31) = '1' and rise = '1') then
if(timer_31 > 0) then
timer_31 <= timer_31 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(31) <= '0';
end if;
elsif(timer_overview(31) = '0') then
timer_31 <= TIMEOUT_TIME;
end if;
if(timeout_int = '1') then
timeout <= '0';
timeout_int <= '0';
end if;
end if;
end process count;
-------------------------------------------------------------------------------
end architecture tx_compl_timeout_arch;
| gpl-3.0 | d648a9efdf5ddd4f0c3c6ad820a7a500 | 0.405482 | 4.217867 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/priority_register_logic.vhd | 3 | 24,319 | -------------------------------------------------------------------------------
-- $Id: priority_register_logic.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- OPB Arbiter - Priority Register Logic
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: priority_register_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the priority registers and the logic to
-- update the registers for a LRU algorithm if the design is
-- parameterized for dynamic priority and dynamic priority
-- has been enabled in the control register. The number of
-- priority levels is determined by the number of masters.
-- There is a priority register for each priority level
-- containing the id of the master at that priority level. The
-- master id's are right justified in each register. Each
-- register is padded with leading zeros.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- chandan 05/25/06
-- ^^^^^^
-- Modified the process MASTER_LOOP to remove the latch it was creating.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
--
-- library unsigned is used for overloading of '=' which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
--
-- Library OPB_ARBITER contains the package OPB_ARB_PKG with contant definitions
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-- Library UNISIM contains Xilinx primitives
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
-- C_NUM_MID_BITS -- number of bits required to encode masterIDs
-- C_DYNAM_PRIORITY -- dynamic priority is supported
--
-- Definition of Ports:
--
-- -- Master Grant signals
-- input MGrant -- Active high Master grant signals
-- input MGrant_n -- Active low Master grant signals
--
-- -- IPIF interface
-- input Bus2ip_data -- Data from OPB bus
-- input Bus2Ip_Reg_WrCE -- Clock enables for priority regs
--
-- -- Control register interface
-- input Dpen -- Dynamic priority enable
-- input Prv -- Priority registers valid
--
-- -- Priority register output
-- output Priority_register -- Priority register with leading zeros
-- output Priority_IDs -- Master IDs for each priority level
--
-- input Clk -- Clock
-- input Rst -- Reset
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity priority_register_logic is
generic ( C_NUM_MASTERS : integer := 16;
C_OPBDATA_WIDTH : integer := 32;
C_NUM_MID_BITS : integer := 4;
C_DYNAM_PRIORITY : boolean := true
);
port (
MGrant : in std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus2IP_Data : in std_logic_vector(0 to C_OPBDATA_WIDTH-1 );
Bus2IP_Reg_WrCE : in std_logic_vector(0 to C_NUM_MASTERS-1);
Dpen : in std_logic;
Prv : in std_logic;
Priority_register : out std_logic_vector(0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
Priority_IDs : out std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
Clk : in std_logic;
Rst : in std_logic
);
end priority_register_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of priority_register_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters to nearest power of 2
constant NUM_MSTRS_PAD : integer := pad_power2(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- Internal priority register
signal priority_register_i : std_logic_vector(0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
-- Internal master ids at each priority level
signal priority_ids_i : std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
-- create default set of priority IDs for use when the Prv bit is negated
-- indicating that the priority registers are being updated by the processor
signal default_ids : std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
-- Register shift controls
-- Set default to zeros, if dynamic priority is not supported, this bus will
-- stay zero.
signal shift : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- ID of master granted the bus, defaults to zero if dynamic priority is not
-- supported.
signal granted_mid : std_logic_vector(0 to C_NUM_MID_BITS-1) := (others => '0');
-- Need active low grant signals to properly drive select lines of muxes
-- this bus will use NUM_MSTRS_PAD so that bus is sized to nearest power of 2.
-- Bus defaults to '0', only the bits up to C_NUM_MASTERS
-- will get assigned a real value.
signal mgrant_n_pad : std_logic_vector(0 to NUM_MSTRS_PAD-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign internal priority register to output ports
-- Use default priority IDs when the priority registers are being updated, i.e.
-- PRV=0.
-------------------------------------------------------------------------------
Priority_register <= priority_register_i;
Priority_IDs <= priority_ids_i when Prv = '1'
else default_ids;
-- Create the default master IDs for each priority level
-- The default is that LVL0 = Master 0, LVL1 = Master 1, LVLn = Mastern
DEF_IDS_GEN: for i in 0 to C_NUM_MASTERS-1 generate
-- create default set of priority IDs for use when the Prv bit is negated
-- indicating that the priority registers are being updated by the processor
begin
default_ids(i*C_NUM_MID_BITS to i*C_NUM_MID_BITS+C_NUM_MID_BITS-1) <=
conv_std_logic_vector(i, C_NUM_MID_BITS);
end generate DEF_IDS_GEN;
-- assign the padded mgrant_n bus the MGrant_n signals
mgrant_n_pad(0 to C_NUM_MASTERS-1) <= MGrant_n;
-------------------------------------------------------------------------------
-- Dynamic Priority Support
-------------------------------------------------------------------------------
-- If the design has been parameterized for each master, have to first decode
-- the grant signals with the current priority register values to determine
-- which priority level was granted the bus. This is then used to determine
-- which priority registers need to shift in the master ID from the lower
-- priority registers. If dynamic priority is not supported, the shift controls
-- are left at their default value of 0.
-------------------------------------------------------------------------------
DYNAM_PRIORITY_GEN: if C_DYNAM_PRIORITY generate
-- one-hot active-low indicator of which priority level was granted the bus
signal grant_lvl_n : std_logic_vector(0 to C_NUM_MASTERS-1);
begin
MASTER_LOOP: for i in 0 to C_NUM_MASTERS-1 generate
-- decode each master ID in the priority registers to determine
-- which priority level was granted the bus
MASTER_4 : if C_NUM_MID_BITS = 4 generate
signal priority_ids_int : std_logic_vector(0 to 3);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "0000" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "0001" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "0010" => grant_lvl_n(i) <= mgrant_n_pad(2);
when "0011" => grant_lvl_n(i) <= mgrant_n_pad(3);
when "0100" => grant_lvl_n(i) <= mgrant_n_pad(4);
when "0101" => grant_lvl_n(i) <= mgrant_n_pad(5);
when "0110" => grant_lvl_n(i) <= mgrant_n_pad(6);
when "0111" => grant_lvl_n(i) <= mgrant_n_pad(7);
when "1000" => grant_lvl_n(i) <= mgrant_n_pad(8);
when "1001" => grant_lvl_n(i) <= mgrant_n_pad(9);
when "1010" => grant_lvl_n(i) <= mgrant_n_pad(10);
when "1011" => grant_lvl_n(i) <= mgrant_n_pad(11);
when "1100" => grant_lvl_n(i) <= mgrant_n_pad(12);
when "1101" => grant_lvl_n(i) <= mgrant_n_pad(13);
when "1110" => grant_lvl_n(i) <= mgrant_n_pad(14);
when others => grant_lvl_n(i) <= mgrant_n_pad(15);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_4;
MASTER_3 : if C_NUM_MID_BITS = 3 generate
signal priority_ids_int : std_logic_vector(0 to 2);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "000" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "001" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "010" => grant_lvl_n(i) <= mgrant_n_pad(2);
when "011" => grant_lvl_n(i) <= mgrant_n_pad(3);
when "100" => grant_lvl_n(i) <= mgrant_n_pad(4);
when "101" => grant_lvl_n(i) <= mgrant_n_pad(5);
when "110" => grant_lvl_n(i) <= mgrant_n_pad(6);
when others => grant_lvl_n(i) <= mgrant_n_pad(7);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_3;
MASTER_2 : if C_NUM_MID_BITS = 2 generate
signal priority_ids_int : std_logic_vector(0 to 1);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "00" => grant_lvl_n(i) <= mgrant_n_pad(0);
when "01" => grant_lvl_n(i) <= mgrant_n_pad(1);
when "10" => grant_lvl_n(i) <= mgrant_n_pad(2);
when others => grant_lvl_n(i) <= mgrant_n_pad(3);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_2;
MASTER_1 : if C_NUM_MID_BITS = 1 generate
signal priority_ids_int : std_logic_vector (0 to 0);
begin
priority_ids_int <= priority_ids_i(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(mgrant_n_pad, priority_ids_int)
begin
case priority_ids_int is
when "0" => grant_lvl_n(i) <= mgrant_n_pad(0);
when others => grant_lvl_n(i) <= mgrant_n_pad(1);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_1;
-- generate the OR chain which determines the shift signals for the
-- priority registers. LVL0 shifts if GRANT_LVL0 was asserted, LVL1
-- shifts if GRANT_LVL0 or GRANT_LVL1 was asserted, LVLn shifts if
-- any grants LVL0 - LVLn were asserted
MUX0_GEN: if i = 0 generate
MUX_LVL0: MUXCY
port map (
O => shift(i), --[out]
CI => '0', --[in]
DI => '1', --[in]
S => grant_lvl_n(i) --[in]
);
end generate MUX0_GEN;
OTHER_MUXES: if i /= 0 generate
MUX_LVLS: MUXCY
port map (
O => shift(i), --[out]
CI => shift(i-1), --[in]
DI => '1', --[in]
S => grant_lvl_n(i) --[in]
);
end generate OTHER_MUXES;
end generate MASTER_LOOP;
-- have to encode the grant signals to the proper Master ID for shifting
-- into the lowest priority register
GRANT_MID_ENC: entity opb_v20_v1_10_d.onehot2encoded
generic map( C_1HOT_BUS_SIZE => C_NUM_MASTERS)
port map (
Bus_1hot => MGrant,
Bus_enc => granted_mid
);
end generate DYNAM_PRIORITY_GEN;
-------------------------------------------------------------------------------
-- Priority Registers
-------------------------------------------------------------------------------
-- The following instantiations of PRIORITY_REG provide registers for each
-- priority level which hold the id of the master at that priority level. There
-- is a priority register for each master. The default reset condition is that
-- Master 0 is at level 0 priority, Master 1 is at level 1 priority, etc.
-- Note that if dynamic priority is not supported, DPEN is set to zero and the
-- SHIFT control is set to zero.
--
-- Also note that if dynamic priority is supported, the lowest level priority
-- register shifts in the granted master id. If dynamic priority is not
-- supported, this ID is set to zeros since it will be unused.
-------------------------------------------------------------------------------
PRIOR_REG_GEN: for i in 0 to C_NUM_MASTERS-1 generate
LAST_REG: if i = C_NUM_MASTERS-1 generate
LOW_PRIOR_REG: entity opb_v20_v1_10_d.priority_reg
generic map (
C_RESET_VALUE => conv_std_logic_vector(i, C_NUM_MID_BITS),
C_NUM_MID_BITS => C_NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH
)
port map (
Priorreg_wrce => Bus2IP_Reg_WrCE(i),
Bus2Ip_Data => Bus2IP_Data,
Dpen => Dpen,
Shift => shift(i),
Master_id_in => granted_mid,
Master_id_out => priority_ids_i(i*C_NUM_MID_BITS to
i*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Priority => priority_register_i(i*C_OPBDATA_WIDTH to
i*C_OPBDATA_WIDTH + C_OPBDATA_WIDTH-1),
Clk => Clk,
Rst => Rst
);
end generate LAST_REG;
OTHER_REGS: if i /= C_NUM_MASTERS-1 generate
PRIOR_REG: entity opb_v20_v1_10_d.priority_reg
generic map (
C_RESET_VALUE => conv_std_logic_vector(i, C_NUM_MID_BITS),
C_NUM_MID_BITS => C_NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH
)
port map (
Priorreg_wrce => Bus2IP_Reg_WrCE(i),
Bus2Ip_Data => Bus2IP_Data,
Dpen => Dpen,
Shift => shift(i),
Master_id_in => priority_ids_i((i+1)*C_NUM_MID_BITS to
(i+1)*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Master_id_out => priority_ids_i(i*C_NUM_MID_BITS to
i*C_NUM_MID_BITS + C_NUM_MID_BITS-1),
Priority => priority_register_i(i*C_OPBDATA_WIDTH to
i*C_OPBDATA_WIDTH + C_OPBDATA_WIDTH-1),
Clk => Clk,
Rst => Rst
);
end generate OTHER_REGS;
end generate PRIOR_REG_GEN;
end implementation;
| bsd-3-clause | 2f86509264906184550709df2e37cb89 | 0.466631 | 4.438584 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_dbeat_control.vhd | 2 | 35,707 | -------------------------------------------------------------------------------
-- $Id: xbic_dbeat_control.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_dbeat_control.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_dbeat_control.vhd
-- Version: v1_00_a
-- Description:
-- This VHDL design implements burst support features that are used for fixed
-- length bursts and cacheline transfers.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $5/15/2002$
--
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from plbv46_slave_burst_V1_00_a library
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.counter_f;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity xbic_dbeat_control is
generic (
-- Generics
C_NATIVE_DWIDTH : integer := 32 ;
C_FAMILY : string := "virtex5"
);
port (
-- Input ports
Bus_Rst : in std_logic ;
Bus_clk : in std_logic ;
-- Start Control
Req_Init : in std_logic ;
-- Qualifiers
Doing_Single : in std_logic ;
Doing_Cacheline : in std_logic ;
Doing_FLBurst : in std_logic ;
RNW_In : in std_logic ;
BE_In : in std_logic_vector(0 to 3);
Size_In : in std_logic_vector(0 to 3);
MSize_In : in std_logic_vector(0 to 1);
-- Count Enables
Wr_DAck : in std_logic ;
Rd_DAck : in std_logic ;
-- Special Case Output signals
Cline_Spec_1DBeat_Case : out std_logic ;
-- Done State signals
AlmostDone : out std_logic ;
Done : out std_logic
);
end entity xbic_dbeat_control;
architecture implementation of xbic_dbeat_control is
-- functions
-- none
-- Constants
--Constant COUNTER_SIZE : integer := 5;
constant DBEAT_CNTR_SIZE : integer := 4;
Constant CNTR_LD_ZEROS : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1):= (others => '0');
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant ZERO : integer := 0;
Constant ONE : integer := 1;
Constant COUNT_ZERO : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ZERO, DBEAT_CNTR_SIZE));
Constant CYCLE_CNT_ZERO : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ZERO, DBEAT_CNTR_SIZE));
Constant CYCLE_CNT_ONE : std_logic_vector(0 to DBEAT_CNTR_SIZE-1)
:= std_logic_vector(to_unsigned(ONE, DBEAT_CNTR_SIZE));
-- Types
-- Signals
signal req_init_reg : std_logic;
signal req_init_strt : std_logic;
signal dbeat_cnt_en : std_logic;
signal dbeat_cnt_init : std_logic;
signal dbeat_count : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_cline_value : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_flburst_value : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal almst_done_comp_value_reg : std_logic_vector(0 to
DBEAT_CNTR_SIZE-1);
signal dbeat_cnt_almst_done_raw : std_logic;
signal dbeat_cnt_almst_done : std_logic;
signal dbeat_cnt_done : std_logic;
signal mult_by_done : std_logic;
signal mult_by_almost_done : std_logic;
signal mult_by_1 : std_logic;
signal mult_by_2 : std_logic;
signal mult_by_4 : std_logic;
signal doing_multi_dbeat : std_logic;
signal mult_cnt_sreg : std_logic_vector(0 to 3);
signal Cline_special_case1 : std_logic;
signal Cline_special_case2 : std_logic;
signal Burst_special_case1 : std_logic;
signal Burst_special_case2 : std_logic;
signal Cline_special_case1_reg : std_logic;
signal Cline_special_case2_reg : std_logic;
signal Burst_special_case1_reg : std_logic;
signal Burst_special_case2_reg : std_logic;
-------------------------------------------------------------------------------
begin --(architecture implementation)
-- Misc assignments
AlmostDone <= (dbeat_cnt_almst_done and mult_by_almost_done)
When (Cline_special_case1_reg = '1')
else (dbeat_cnt_almst_done and mult_by_done);
Done <= dbeat_cnt_done and mult_by_done;
-- Detect a FLBurst of 2 data beats as a special case
Burst_special_case1 <= '1'
when (BE_In = "0001" and
Doing_FLBurst = '1')
Else '0';
-- Detect a FLBurst of 3 data beats as a special case
Burst_special_case2 <= '1'
when (BE_In = "0010" and
Doing_FLBurst = '1')
Else '0';
-- DET req_init_strt <= Req_Init and
-- DET not(req_init_reg);
req_init_strt <= Req_Init;
dbeat_cnt_init <= Bus_Rst or
req_init_strt or
--(not(mult_by_done) and
dbeat_cnt_done or
Cline_special_case1_reg or
Burst_special_case1_reg;
doing_multi_dbeat <= Doing_Cacheline or
Doing_FLBurst;
dbeat_cnt_en <= Wr_DAck or
Rd_DAck;
mult_by_done <= mult_cnt_sreg(0);
mult_by_almost_done <= mult_cnt_sreg(0) or
mult_cnt_sreg(1);
dbeat_cnt_almst_done_raw <= '1'
when (dbeat_count = almst_done_comp_value_reg)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_REQ_INIT
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_REQ_INIT : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
req_init_reg <= '0';
else
req_init_reg <= Req_Init;
end if;
end if;
end process REG_REQ_INIT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SPEC_CASES
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_SPEC_CASES : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(dbeat_cnt_done = '1'and
mult_by_done = '1' and
req_init_strt = '0')) then
Cline_special_case1_reg <= '0';
Cline_special_case2_reg <= '0';
Burst_special_case1_reg <= '0';
Burst_special_case2_reg <= '0';
Cline_Spec_1DBeat_Case <= '0';
elsif (req_init_strt = '1') then
Cline_special_case1_reg <= Cline_special_case1;
Cline_special_case2_reg <= Cline_special_case2;
Burst_special_case1_reg <= Burst_special_case1;
Burst_special_case2_reg <= Burst_special_case2;
Cline_Spec_1DBeat_Case <= Cline_special_case1 and
mult_by_1;
else
null; -- hold current state
end if;
end if;
end process REG_SPEC_CASES;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_FLB_DONE_COMP_VALUE
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Fixed Length Burst Operations.
--
-------------------------------------------------------------
CALC_FLB_DONE_COMP_VALUE : process (BE_In)
begin
case BE_In is
-- when "0001" =>
-- almst_done_flburst_value <= "0000"
-- when "0010" =>
-- almst_done_flburst_value <= "0000"
when "0011" =>
almst_done_flburst_value <= "0001";
when "0100" =>
almst_done_flburst_value <= "0010";
when "0101" =>
almst_done_flburst_value <= "0011";
when "0110" =>
almst_done_flburst_value <= "0100";
when "0111" =>
almst_done_flburst_value <= "0101";
when "1000" =>
almst_done_flburst_value <= "0110";
when "1001" =>
almst_done_flburst_value <= "0111";
when "1010" =>
almst_done_flburst_value <= "1000";
when "1011" =>
almst_done_flburst_value <= "1001";
when "1100" =>
almst_done_flburst_value <= "1010";
when "1101" =>
almst_done_flburst_value <= "1011";
when "1110" =>
almst_done_flburst_value <= "1100";
when "1111" =>
almst_done_flburst_value <= "1101";
when others =>
almst_done_flburst_value <= "0000";
end case;
end process CALC_FLB_DONE_COMP_VALUE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_COMP_VALUE
--
-- Process Description:
--
--
-------------------------------------------------------------
REG_COMP_VALUE : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(Req_Init = '1' and
Doing_Single = '1')) then
almst_done_comp_value_reg <= (others => '0');
elsif (Req_Init = '1' and
Doing_FLBurst = '1') then
almst_done_comp_value_reg <= almst_done_flburst_value;
Elsif (Req_Init = '1' and
Doing_Cacheline = '1') Then
almst_done_comp_value_reg <= almst_done_cline_value;
else
null; -- hold current value
end if;
end if;
end process REG_COMP_VALUE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DONE_FLAGS
--
-- Process Description:
-- This process implements the almost_done and done flags.
--
-------------------------------------------------------------
REG_DONE_FLAGS : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1' or
(dbeat_cnt_en = '1' and
dbeat_cnt_done = '1' and
mult_by_done = '1')) then
dbeat_cnt_almst_done <= '0';
dbeat_cnt_done <= '0';
-- Special case Singles
Elsif (req_init_strt = '1' and
Doing_Single = '1') Then
--dbeat_cnt_almst_done <= '0';
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '1';
-- Special case Cachelines (1 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_Cacheline = '1' and
Cline_special_case1 = '1') Then
--dbeat_cnt_almst_done <= '0';
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '1';
-- Special case Cachelines (2 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_Cacheline = '1' and
Cline_special_case2 = '1') Then
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '0';
-- Special case Fixed Length Burst (2 data beat case)
Elsif (req_init_strt = '1' and
--mult_by_1 = '1' and
Doing_FLBurst = '1' and
Burst_special_case1 = '1') Then
dbeat_cnt_almst_done <= '1';
dbeat_cnt_done <= '0';
-- Starting a non-special case cacheline or flburst -- new DET
Elsif (req_init_strt = '1') Then -- new DET
-- new DET
dbeat_cnt_almst_done <= '0'; -- new DET
dbeat_cnt_done <= '0'; -- new DET
-- new DET
-- Normal termination case based on Dbeat Counter
elsif (dbeat_cnt_en = '1') then
dbeat_cnt_almst_done <= (dbeat_cnt_almst_done_raw and
not(dbeat_cnt_almst_done)) or
Cline_special_case1_reg;
dbeat_cnt_done <= dbeat_cnt_almst_done;
else
null; -- hold current state
end if;
end if;
end process REG_DONE_FLAGS;
----------------------------------------------------------------------------
-- Data Beat Counter Logic
-- This counter is reset at command start and counts up with every data
-- acknowledge assertion. A primary requirement for its implementation is
-- that it be ready to count a Write data acknowledge on the same clock
-- cycle that the Sl_Addrack is being asserted to the PLB.
----------------------------------------------------------------------------
-- RESP_LOAD_VALUE : process(Num_Data_Beats)
-- begin
-- if(C_MAX_DBEAT_CNT > Num_Data_Beats)then
-- resp_db_load_value <= std_logic_vector(to_unsigned(Num_Data_Beats, DBEAT_CNTR_SIZE));
-- else
-- resp_db_load_value <= std_logic_vector(to_unsigned(C_MAX_DBEAT_CNT-1,DBEAT_CNTR_SIZE));
-- end if;
-- end process RESP_LOAD_VALUE;
--
-- resp_db_cnten <= Target_DataAck and
-- not(Response_Done_i);
I_DBEAT_CNTR : entity proc_common_v3_00_a.counter_f
generic map(
C_NUM_BITS => DBEAT_CNTR_SIZE,
C_FAMILY => C_FAMILY
)
port map (
Clk => Bus_clk,
Rst => dbeat_cnt_init,
Load_In => CNTR_LD_ZEROS,
Count_Enable => dbeat_cnt_en,
Count_Load => LOGIC_LOW,
Count_Down => '0', -- count up
Count_Out => dbeat_count,
Carry_Out => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_32_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 32.
--
--
------------------------------------------------------------
BLE_32_BIT_SLAVE : if (C_NATIVE_DWIDTH = 32) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S32
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
--
-- 32-bit Slave can transfer 1 wds per data beat
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S32 : process (Size_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (4 dbeats)
almst_done_cline_value <= "0001";
when "0010" => -- Cacheline 8wrds (8 dbeats)
almst_done_cline_value <= "0101";
when "0011" => -- Cacheline 16wrds (16 dbeats)
almst_done_cline_value <= "1101";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S32;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S32
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 32.
--
-------------------------------------------------------------
GET_MULT_BY_S32 : process (Doing_FLBurst,
Doing_Cacheline,
--MSize_In,
Size_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
If (Doing_FLBurst = '1') Then
case Size_In is
-- when "1010" => -- 32-bit burst request
--
-- mult_by_1 <= '1';
--
when "1011" => -- 64-bit burst request
mult_by_1 <= '0';
mult_by_2 <= '1';
when "1100" => -- 128-bit burst request
mult_by_1 <= '0';
mult_by_4 <= '1';
when others => -- default to 32-bit
null; -- use defaults
end case;
Elsif (Doing_Cacheline = '1') Then
mult_by_1 <= '1';
-- case MSize_In is
-- when "00" => -- 32-bit master/32-bit slave
--
-- mult_by_1 <= '1';
--
-- when "01" => -- 64-bit Master/32-bit slave
--
-- mult_by_1 <= '0';
-- mult_by_2 <= '1';
--
-- when others => -- 128 bit master/32-bit slave
--
-- mult_by_1 <= '0';
-- mult_by_4 <= '1';
--
-- end case;
End if;
end process GET_MULT_BY_S32;
end generate BLE_32_BIT_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_64_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 64.
--
--
------------------------------------------------------------
BLE_64_BIT_SLAVE : if (C_NATIVE_DWIDTH = 64) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S64
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
-- 64-bit Slave can transfer 2 wds per data beat but if
-- requesting Master is 32-bits, then only 32-bits per
-- data beat.
--
-- Cline_special_case1 is asserted when the resolved dbeat
-- count is 1 data beat (only possible with 128-bit Master and
-- 128-bit Slave and 4wrd cacheline)
-- Cline_special_case12 is asserted when the resolved dbeat
-- count is 2 data beats
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S64 : process (Size_In)
--,MSize_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (2 dbeats minimum)
almst_done_cline_value <= "0001"; -- special case value
Cline_special_case1 <= '0';
Cline_special_case2 <= '1';
-- If (MSize_In = "00") Then -- 32-bit Master
-- -- requires 4 data beats
--
-- almst_done_cline_value <= "0001"; -- special case value
-- Cline_special_case1 <= '0';
-- Cline_special_case2 <= '1';
--
-- else -- 64 or 128-bit Master (only 2 data beats)
--
-- --almst_done_cline_value <= "0000";
-- almst_done_cline_value <= "0000";
-- Cline_special_case1 <= '0';
-- Cline_special_case2 <= '1';
--
--
-- End if;
when "0010" => -- Cacheline 8wrds (4 dbeats)
almst_done_cline_value <= "0001";
when "0011" => -- Cacheline 16wrds (8 dbeats)
almst_done_cline_value <= "0101";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S64;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S64
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 64.
--
-------------------------------------------------------------
GET_MULT_BY_S64 : process (Doing_FLBurst,
Doing_Cacheline,
MSize_In,
Size_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
If (Doing_FLBurst = '1') Then
case Size_In is
when "1100" => -- 128-bit burst request
mult_by_1 <= '0';
mult_by_2 <= '1';
-- when "1010" => -- 32-bit burst request
--
-- mult_by_1 <= '1';
--
-- when "1011" => -- 64-bit burst request
--
-- mult_by_1 <= '1';
when others => -- default to 32 or 64 bit burst request
null; -- use defaults
-- mult_by_1 <= '0';
-- mult_by_2 <= '1';
end case;
Elsif (Doing_Cacheline = '1') Then
case MSize_In is
when "00" => -- 32-bit master/64-bit Slave
mult_by_1 <= '0';
mult_by_2 <= '1';
-- when "01" => -- 64-bit Master/64-bit Slave
--
-- mult_by_1 <= '1';
when others => -- 128 bit master/64-bit Slave
null; -- use defaults
-- mult_by_1 <= '1';
end case;
End if;
end process GET_MULT_BY_S64;
end generate BLE_64_BIT_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: BLE_128_BIT_SLAVE
--
-- If Generate Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 128. Will always be 1 in this case.
--
--
------------------------------------------------------------
BLE_128_BIT_SLAVE : if (C_NATIVE_DWIDTH = 128) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_CLINE_DONE_COMP_VALUE_S128
--
-- Process Description:
-- This process is a simple lookup table for generating the
-- compare to value for the data beat up-counter during
-- Cacheline Operations.
--
-- 128-bit Slave can transfer 4 wds per data beat
-------------------------------------------------------------
CALC_CLINE_DONE_COMP_VALUE_S128 : process (Size_In)
begin
Cline_special_case1 <= '0';
Cline_special_case2 <= '0';
case Size_In is
when "0001" => -- Cacheline 4wrds (1 dbeat minimum)
Cline_special_case1 <= '1';
almst_done_cline_value <= "0000";
when "0010" => -- Cacheline 8wrds (2 dbeats minimum)
Cline_special_case2 <= '1';
--almst_done_cline_value <= "0000";
almst_done_cline_value <= "0001"; -- special case
when "0011" => -- Cacheline 16wrds (4 dbeats minimum)
almst_done_cline_value <= "0001";
when others =>
almst_done_cline_value <= "0000";
end case;
end process CALC_CLINE_DONE_COMP_VALUE_S128;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GET_MULT_BY_S128
--
-- Process Description:
-- Detirmine the Burst Length Expansion factor when the
-- Slave width is 128.
--
-------------------------------------------------------------
GET_MULT_BY_S128 : process (Doing_Cacheline,
MSize_In)
begin
mult_by_1 <= '1';
mult_by_2 <= '0';
mult_by_4 <= '0';
if (Doing_Cacheline = '1') Then
case MSize_In is
when "00" => -- 32-bit master/128-bit Slave
mult_by_1 <= '0';
mult_by_4 <= '1';
when "01" => -- 64-bit Master/128-bit Slave
mult_by_1 <= '0';
mult_by_2 <= '1';
when others => -- 128 bit master/128-bit Slave
null; -- use defaults
-- mult_by_1 <= '1';
end case;
End if;
end process GET_MULT_BY_S128;
end generate BLE_128_BIT_SLAVE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: MULT_CNTR
--
-- Process Description:
-- This process implements a shift register that is set at
-- command start to the appropriate multipy value for
-- multi-data beat commands.
-- This is needed to support Burst Length Expansion, a
-- requirement when the requesting Master is wider than the
-- Slave's native data width.
--
-------------------------------------------------------------
MULT_CNTR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
mult_cnt_sreg <= (others => '0');
elsif (Req_Init = '1') then
mult_cnt_sreg(0) <= mult_by_1;
mult_cnt_sreg(1) <= mult_by_2;
mult_cnt_sreg(2) <= '0';
mult_cnt_sreg(3) <= mult_by_4;
Elsif (dbeat_cnt_en = '1' and
dbeat_cnt_done = '1') Then
-- shift the set pulse down shift register
mult_cnt_sreg(0) <= mult_cnt_sreg(1);
mult_cnt_sreg(1) <= mult_cnt_sreg(2);
mult_cnt_sreg(2) <= mult_cnt_sreg(3);
mult_cnt_sreg(3) <= '0';
else
null; -- hold current state
end if;
end if;
end process MULT_CNTR;
end implementation;
| bsd-3-clause | fcc47eba2384e78e8ecf8d2a4961fc10 | 0.401798 | 4.719403 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_top.vhd | 3 | 4,524 | -------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
| bsd-3-clause | fa3a6bf1a917e604ba50c36ad6a47513 | 0.390805 | 4.320917 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hw_acc_vector_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 3 | 17,108 |
--Piplelining the rad and write from BRAMS, it processes the 4k data in 40us ( 100MHZ)
--accm
-- ************************************
-- Automatically Generated FSM
-- vector_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32;
OPCODE_BITS : integer := 6;
FUNC_BITS : integer := 6
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity vector_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of vector_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
fetch,
get_instr,
read_arg,
decode,
state1,
halt,
extra1,
addv_state1,
mulv_state1,
mulv_state2,
redv_state1
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal instruction, instruction_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal index, index_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal ret, ret_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataMUL, dataMUL_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal op, op_next : std_logic_vector(0 to 1);
signal rs, rs_next : std_logic_vector(2 to 16);
signal rt, rt_next : std_logic_vector(17 to 31);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OP_ADDV : std_logic_vector(0 to 1) := "00";
constant OP_MULV : std_logic_vector(0 to 1) := "01";
constant OP_REDV : std_logic_vector(0 to 1) := "10";
--constant OP_R : std_logic_vector(0 to OPCODE_BITS-1) := "000000";
--constant FN_NOP : std_logic_vector(0 to FUNC_BITS-1) := "000000"; -- 0/00H
--constant FN_ADDV : std_logic_vector(0 to FUNC_BITS-1) := "110000"; -- 0/30H
--constant FN_MULV : std_logic_vector(0 to FUNC_BITS-1) := "110001"; -- 0/31
--constant FN_REDV : std_logic_vector(0 to FUNC_BITS-1) := "110010"; -- 0/32
--constant OP_NOP : std_logic_vector(0 to OPCODE_BITS-1) := x"0";
--constant OP_ADD : std_logic_vector(0 to OPCODE_BITS-1) := x"1";
--constant OP_SUB : std_logic_vector(0 to OPCODE_BITS-1) := x"2";
--constant OP_ADDi : std_logic_vector(0 to OPCODE_BITS-1) := x"3";
--constant OP_SUBi : std_logic_vector(0 to OPCODE_BITS-1) := x"4";
--constant OP_ADDV : std_logic_vector(0 to OPCODE_BITS-1) := x"5";
--constant OP_SUBV : std_logic_vector(0 to OPCODE_BITS-1) := x"6";
--constant OP_ADDVS : std_logic_vector(0 to OPCODE_BITS-1) := x"7";
--constant OP_SUBVS : std_logic_vector(0 to OPCODE_BITS-1) := x"8";
--constant OP_SNEV : std_logic_vector(0 to OPCODE_BITS-1) := x"9";
--constant OP_SNEVS : std_logic_vector(0 to OPCODE_BITS-1) := x"A";
--constant OP_SLTV : std_logic_vector(0 to OPCODE_BITS-1) := x"B";
--constant OP_SLTVS : std_logic_vector(0 to OPCODE_BITS-1) := x"C";
--constant OP_CVM : std_logic_vector(0 to OPCODE_BITS-1) := x"D";
--constant OP_SVLR : std_logic_vector(0 to OPCODE_BITS-1) := x"E";
--constant OP_SVMR : std_logic_vector(0 to OPCODE_BITS-1) := x"F";
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
instruction_next,
index_next,
ret_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
dataMUL_next,
op_next,
rs_next,
rt_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
instruction <= (others => '0');
index <= (others => '0');
ret <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
dataMUL <= (others => '0');
op <= (others => '0');
rs <= (others => '0');
rt <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
instruction <= instruction_next;
index <= index_next;
ret <= ret_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
dataMUL <= dataMUL_next;
op <= op_next;
rs <= rs_next;
rt <= rt_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
instruction,
index,
ret,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
dataMUL,
op,
rs,
rt,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
instruction_next <= instruction;
index_next <= index;
ret_next <= ret;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
dataMUL_next <= dataMUL;
op_next <= op;
rs_next <= rs;
rt_next <= rt;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when reset =>
next_state <= fetch;
when fetch =>
if chan1_exists = '0' then
next_state <= fetch;
elsif chan1_exists /= '0' then
index_next <= "00000000000000000" & chan1_channelDataOut(17 to 31);
n_next <= "00000000000000000" & chan1_channelDataOut(2 to 16);
op_next <= chan1_channelDataOut(0 to 1);
ret_next <= (others => '0');
chan1_channelRead <= '1';
next_state <= decode;
end if;
when decode =>
i_next <= index;
in_Vector_A_addr0 <= index;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= index;
Vector_B_rENA0 <= '1';
-- ADDV --
if ( op = OP_ADDV ) then
next_state <= addv_state1;
-- MULV --
elsif ( op = OP_MULV ) then
next_state <= mulv_state1;
-- REDV --
elsif ( op = OP_REDV ) then
next_state <= redv_state1;
end if;
when addv_state1 =>
if ( i >= n-1 ) then
next_state <= halt;
elsif ( i < n-1 ) then
-- Write VC i
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= Vector_A_dOUT0 + Vector_B_dOUT0;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
-- Read VA i+1
in_Vector_A_addr0 <= i+1;
Vector_A_rENA0 <= '1';
-- Read VB i+1
in_Vector_B_addr0 <= i+1;
Vector_B_rENA0 <= '1';
-- i++
i_next <= i+1;
-- Loop
next_state <= addv_state1;
end if;
when mulv_state1 =>
ret_next <= Vector_A_dOUT0 * Vector_B_dOUT0;
-- Read VA i+1
in_Vector_A_addr0 <= i+1;
Vector_A_rENA0 <= '1';
-- Read VB i+1
in_Vector_B_addr0 <= i+1;
Vector_B_rENA0 <= '1';
-- i++
i_next <= i+1;
-- next
next_state <= mulv_state2;
when mulv_state2 =>
if ( i >= n-1 ) then
ret_next <= Vector_A_dOUT0 * Vector_B_dOUT0;
-- Write VC i
in_Vector_C_addr0 <= i-1;
Vector_C_dIN0 <= ret(32 to 63);
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
-- Loop
next_state <= halt;
elsif ( i < n-1 ) then
ret_next <= Vector_A_dOUT0 * Vector_B_dOUT0;
-- Write VC i
in_Vector_C_addr0 <= i-1;
Vector_C_dIN0 <= ret(32 to 63);
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
-- Read VA i+1
in_Vector_A_addr0 <= i+1;
Vector_A_rENA0 <= '1';
-- Read VB i+1
in_Vector_B_addr0 <= i+1;
Vector_B_rENA0 <= '1';
-- i++
i_next <= i+1;
-- Loop
next_state <= mulv_state2;
end if;
when redv_state1 =>
if ( i >= n-1 ) then
ret_next <= Vector_A_dOUT0 * Vector_B_dOUT0 + ret;
next_state <= halt;
elsif ( i < n-1 ) then
ret_next <= Vector_A_dOUT0 * Vector_B_dOUT0 + ret;
-- Read VA i+1
in_Vector_A_addr0 <= i+1;
Vector_A_rENA0 <= '1';
-- Read VB i+1
in_Vector_B_addr0 <= i+1;
Vector_B_rENA0 <= '1';
-- i++
i_next <= i+1;
-- loop
next_state <= redv_state1;
end if;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
if ( op = OP_ADDV ) then
-- Write VC last one
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= Vector_A_dOUT0 + Vector_B_dOUT0;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
-- Send arg back say : Done!
chan1_channelDataIn <= ret(32 to 63);
chan1_channelWrite <= '1';
next_state <= fetch;
elsif ( op = OP_MULV ) then
-- Write VC i
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= ret(32 to 63);
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
-- Send arg back say : Done!
chan1_channelDataIn <= ret(32 to 63);
chan1_channelWrite <= '1';
next_state <= fetch;
elsif ( op = OP_REDV ) then
-- Send arg back say : Done!
chan1_channelDataIn <= ret(32 to 63);
chan1_channelWrite <= '1';
next_state <= fetch;
end if;
end if;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
| bsd-3-clause | f6a3cdb5ad6686e68d75c55b626d084b | 0.532733 | 3.049011 | false | false | false | false |
jevinskie/aes-over-pcie | source/fifo.vhd | 1 | 2,517 | -- File name: fifo.vhd
-- Created: 2009-04-20 (^-^)y-~~'`
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: FIFO
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
size : positive := 32
);
port (
clk : in std_logic;
nrst : in std_logic;
re : in std_logic;
we : in std_logic;
w_data : in byte;
r_data : out byte;
empty : out std_logic;
full : out std_logic
);
subtype fifo_pntr is integer range 0 to (size-1);
type fifo_array is array (fifo_pntr) of byte;
end entity fifo;
architecture behavioral of fifo is
signal r_pntr, next_r_pntr : fifo_pntr;
signal w_pntr, next_w_pntr : fifo_pntr;
signal fifo, next_fifo : fifo_array;
signal re_int, we_int : std_logic;
signal empty_int, full_int : std_logic;
begin
fifo_reg : process(clk)
begin
if rising_edge(clk) then
fifo <= next_fifo;
end if;
end process fifo_reg;
fifo_nsl : process(fifo, w_pntr, we_int, w_data)
begin
next_fifo <= fifo;
if (we_int = '1') then
next_fifo(w_pntr) <= w_data;
end if;
end process fifo_nsl;
r_pntr_reg : process(clk, nrst)
begin
if (nrst = '0') then
r_pntr <= 0;
elsif rising_edge(clk) then
r_pntr <= next_r_pntr;
end if;
end process r_pntr_reg;
r_pntr_nsl : process(re_int, r_pntr)
begin
if (re_int = '1') then
next_r_pntr <= (r_pntr + 1) mod size;
else
next_r_pntr <= r_pntr;
end if;
end process;
w_pntr_reg : process(clk, nrst)
begin
if (nrst = '0') then
w_pntr <= 0;
elsif rising_edge(clk) then
w_pntr <= next_w_pntr;
end if;
end process w_pntr_reg;
w_pntr_nsl : process(we_int, w_pntr)
begin
if (we_int = '1') then
next_w_pntr <= (w_pntr + 1) mod size;
else
next_w_pntr <= w_pntr;
end if;
end process w_pntr_nsl;
re_int <= '1' when re = '1' and empty_int = '0' else '0';
we_int <= '1' when we = '1' and full_int = '0' else '0';
r_data <= fifo(r_pntr);
empty_int <= '1' when r_pntr = w_pntr else '0';
full_int <= '1' when r_pntr = (w_pntr + 1) mod size else '0';
empty <= empty_int;
full <= full_int;
end architecture behavioral;
| bsd-3-clause | 5e4ca8073479819140e3d28c1d6cfa1c | 0.531585 | 3.103576 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_plbv46_bridge_v1_01_a/hdl/vhdl/buffer_x16.vhd | 3 | 7,900 | -------------------------------------------------------------------------------
-- $Id: buffer_x16.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: buffer_x16.vhd
--
-- Description: This block provides a 16-deep fifo buffer with LocalLink
-- interfaces on both ends. SOF and EOF bits are stored along
-- with the data in the fifo.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY buffer_x16 IS
GENERIC (
C_DWIDTH : INTEGER := 32;
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-- Source Interface
bfs_data : OUT std_logic_vector(0 TO 31); -- Read data output to user logic
bfs_sof_n : OUT std_logic; -- Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n : OUT std_logic; -- Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n : OUT std_logic; -- Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n : OUT std_logic; -- Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n : IN std_logic; -- Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n : IN std_logic; -- Active low signal that the read local link destination needs to discontinue the transfer.
-- Destination (Sink) Interface
bfd_data : IN std_logic_vector(0 TO 31);
bfd_sof_n : IN std_logic;
bfd_eof_n : IN std_logic;
bfd_src_rdy_n : IN std_logic;
bfd_src_dsc_n : IN std_logic;
bfd_dst_rdy_n : OUT std_logic;
bfd_dst_dsc_n : OUT std_logic;
-- System Interface
rst : IN std_logic; -- reset
clk : IN std_logic -- clock
);
END ENTITY buffer_x16;
-------------------------------------------------------------------------------
LIBRARY proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
ARCHITECTURE syn OF buffer_x16 IS
CONSTANT PDLY : time := 1 NS;
CONSTANT C_DEPTH : integer := 16;
CONSTANT ZEROES : std_logic_vector(0 TO log2(C_DEPTH)-1) := (OTHERS => '0');
SIGNAL bfs_src_rdy_n_i : std_logic;
SIGNAL bfd_dst_rdy_n_i : std_logic;
SIGNAL FIFO_write : std_logic;
SIGNAL FIFO_read : std_logic;
SIGNAL read_data : std_logic_vector(0 TO C_DWIDTH-1+2);
SIGNAL write_data : std_logic_vector(0 TO C_DWIDTH-1+2);
BEGIN
s0 : write_data <= bfd_sof_n & bfd_eof_n & bfd_data AFTER PDLY;
-- Source data valid and not fifo full
s1 : FIFO_write <= bfd_src_rdy_n NOR bfd_dst_rdy_n_i AFTER PDLY;
-- Fifo not empty and destination ready to receive
s2 : FIFO_read <= bfs_src_rdy_n_i NOR bfs_dst_rdy_n AFTER PDLY;
I_SRL_FIFO_RBU_F : ENTITY proc_common_v3_00_a.srl_fifo_rbu_f
GENERIC MAP (
C_DWIDTH => C_DWIDTH+2,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
PORT MAP (
Clk => Clk,
Reset => rst,
FIFO_Write => FIFO_Write,
Data_In => write_data,
FIFO_Read => FIFO_Read,
Data_Out => read_data,
FIFO_Full => bfd_dst_rdy_n_i,
FIFO_Empty => bfs_src_rdy_n_i,
Addr => OPEN,
Num_To_Reread => ZEROES,
Underflow => OPEN,
Overflow => OPEN
);
s3 : bfd_dst_rdy_n <= bfd_dst_rdy_n_i AFTER PDLY;
s4 : bfs_src_rdy_n <= bfs_src_rdy_n_i AFTER PDLY;
s5 : bfs_sof_n <= read_data(0) AFTER PDLY;
s6 : bfs_data <= read_data(2 TO 31+2) AFTER PDLY;
s7 : bfs_eof_n <= read_data(1) AFTER PDLY;
s8 : bfd_dst_dsc_n <= '1'; -- Can't terminate
s9 : bfs_src_dsc_n <= '1'; -- Can't terminate
END ARCHITECTURE syn;
| bsd-3-clause | 204a526e9680a30e2ea7300e7a3ace1f | 0.543418 | 4.065878 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_dverif.vhd | 1 | 6,022 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF FiFo512Core32W32R_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 42e719c5c108b6f3cc0e5471bd45f87a | 0.55646 | 3.91293 | false | false | false | false |
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