repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
xdsopl/vhdl | detdff.vhd | 1 | 835 | -- detdff - Double Edge Triggered Data Flip-Flop
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity detdff is
port (
input : in std_logic;
clock : in std_logic;
output : out std_logic
);
end detdff;
architecture bs of detdff is
signal lo, hi : std_logic;
begin
lo <= input when clock = '0' else lo;
hi <= input when clock = '1' else hi;
output <= lo when clock = '1' else hi;
end bs;
| cc0-1.0 | 89f9ecd71ed7ae3e51d43eb056d02b07 | 0.729341 | 3.538136 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/control.vhd | 1 | 3,599 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:02 11/11/2015
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( c_clk : in STD_LOGIC;
c_rst : in STD_LOGIC;
c_cpu_wr : in STD_LOGIC;
c_cpu_sc : in STD_LOGIC;
parity : in STD_LOGIC;
c_address_enable : out STD_LOGIC;
c_wr_enable : out STD_LOGIC;
--stored_enable: out STD_LOGIC;
wr_strobe : out STD_LOGIC );
end control;
architecture Behavioral of control is
type states is (idle, hold0, load_addr, hold1, strobe, hold2, hold3, write_data, write_data2);
signal nState, cState: states;
begin
control: process(c_clk, c_rst)
begin
if (c_rst = '1') then
cState <= idle;
elsif (c_clk'event and c_clk = '1') then
cState <= nState;
end if;
end process;
control_unit: process(cState, parity, c_cpu_sc, c_cpu_wr) --, parity, c_cpu_sc
begin
case cState is
when idle =>
c_address_enable <= '1';
c_wr_enable <= '0';
--stored_enable<= '0';
wr_strobe <= '1';
if (c_cpu_sc = '1') and (parity = '1')and (c_cpu_wr = '1') then -- if still '1'
nState <= hold0;
else
nState <= idle;
end if;
when hold0 =>
c_address_enable <= '0';
c_wr_enable <= '0';
--stored_enable<= '0';
wr_strobe <= '1';
--if (c_cpu_wr = '1') then
nState <= load_addr;
-- else nState <= idle;
-- end if;
when load_addr =>
c_address_enable <= '0';
c_wr_enable <= '0';
--stored_enable<= '0';
wr_strobe <= '1';
nState <= hold1;
when hold1 =>
c_address_enable <= '0';
c_wr_enable <= '0';
--stored_enable<= '0';
wr_strobe <= '1';
nState <= strobe;
when strobe =>
c_address_enable <= '0';
c_wr_enable <= '0';
--stored_enable<= '1';
wr_strobe <= '0';
nState <= hold2;
when hold2 =>
c_address_enable <= '0';
c_wr_enable <= '0';
--stored_enable <= '0';
wr_strobe <= '1';
nState <= hold3;
when hold3 =>
c_address_enable <= '0';
c_wr_enable <= '0';
wr_strobe <= '1';
nState <= write_data;
when write_data =>
c_address_enable <= '0';
c_wr_enable <= '1';
wr_strobe <= '1';
nState <= idle;
when others =>
c_address_enable <= '0';
c_wr_enable <= '0';
wr_strobe <= '1';
nState <= idle;
end case;
end process;
end Behavioral;
| unlicense | 8c9dbbba799bfa3c8688f5a5f93c800f | 0.45596 | 3.602603 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/rx_get_data.vhd | 1 | 19,861 | --------------------------------------------------------------------------------
-- Title : RX data path
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_get_data.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-24
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- manages RX data path and provides information contained in rx_st_data0
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- * rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_get_data is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end entity rx_get_data;
architecture rx_get_data_arch of rx_get_data is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
signal int_cntr_val_temp : std_logic_vector(9 downto 0); -- internal length counter
signal int_len_is_odd : std_logic; -- =1 if length is odd else 0
signal int_c_wr : std_logic; -- =0 cpl, =1 write/read
signal int_is_read : std_logic; -- =1 if transfer is a read, else 0
signal int_aligned : std_logic; -- =1 if data is QWORD aligned else 0
signal int_tag_rcvd : std_logic; -- =1 if tag number for last of multiple
-- completions is received, else 0
-------------------------------------
-- signals to register port signals
-------------------------------------
signal int_rxstvalid0_q : std_logic;
signal int_rxstdata0_q : std_logic_vector(63 downto 0);
signal int_rxstsop0_q : std_logic;
signal int_sopqi_q : std_logic;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
len_cntr_val_o <= int_cntr_val_temp;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
------------------------------------------
-- process to register necessary signals
------------------------------------------
reg_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_rxstvalid0_q <= '0';
int_rxstdata0_q <= (others => '0');
int_rxstsop0_q <= '0';
int_sopqi_q <= '0';
elsif clk_i'event and clk_i = '1' then
int_rxstvalid0_q <= rx_st_valid0;
int_rxstsop0_q <= rx_st_sop0;
int_sopqi_q <= sop_q_i;
if rx_st_valid0 = '1' then
int_rxstdata0_q <= rx_st_data0;
end if;
end if;
end process reg_proc;
main : process(rst_i, clk_i)
begin
if rst_i = '1' then
rx_fifo_in_o <= (others => '0');
tag_nbr_o <= (others => '0');
tag_rcvd_o <= '0';
type_fmt_err_o <= (others => '0');
int_c_wr <= '0';
int_is_read <= '0';
int_tag_rcvd <= '0';
int_cntr_val_temp <= (others => '0');
int_len_is_odd <= '0';
int_aligned <= '0';
elsif clk_i'event and clk_i = '1' then
------------------------------------------------------
-- tag_rcvd_o must be a registered version of
-- int_tag_rcvd because the tag nbr for completions
-- can be stored one clock cycle later than
-- for memory writes/reads
------------------------------------------------------
tag_rcvd_o <= int_tag_rcvd;
if rx_st_valid0 = '1' then
if rx_st_sop0 = '1' then
int_len_is_odd <= rx_st_data0(0);
int_aligned <= int_aligned;
if rx_st_data0(28 downto 24) = TYPE_IS_CPL then
int_c_wr <= '0';
-----------------------------------------
-- check if this is the last completion
-- byte count value must be the same or
-- less than length value *4
-----------------------------------------
if rx_st_data0(43 downto 32) <= rx_st_data0(9 downto 0) & "00" then
int_tag_rcvd <= '1';
else
int_tag_rcvd <= '0';
end if;
elsif (rx_st_data0(28 downto 24) = TYPE_IS_MEMORY or rx_st_data0(28 downto 24) = TYPE_IS_IO) then
int_c_wr <= '1';
tag_nbr_o <= rx_st_data0(47 downto 40);
end if;
if rx_st_data0(31 downto 29) = FMT_IS_READ then
int_is_read <= '1';
else
int_is_read <= '0';
end if;
---------------------------------------------
-- check if a type or format error occurred
-- if I/O length is ok
-- and if a completion error occurred
---------------------------------------------
case rx_st_data0(31 downto 24) is
when "00000000" | "01000000" => -- memory
type_fmt_err_o <= (others => '0');
when "00000010" | "01000010" => -- I/O
if(rx_st_data0(9 downto 0) > "0000000001") then -- I/O requests must have length = 1
type_fmt_err_o <= "01";
else
type_fmt_err_o <= (others => '0');
end if;
when "00001010" => -- completion, no data
type_fmt_err_o <= (others => '0');
when "01001010" => -- completion, data
type_fmt_err_o <= (others => '0');
when "00110000" | "00110001" | "00110010" | "00110011" | -- message
"00110100" | "00110101" | "00110110" | "00110111" |
"01110000" | "01110001" | "01110010" | "01110011" |
"01110100" | "01110101" | "01110110" | "01110111" =>
type_fmt_err_o <= (others => '0');
when "00100000" | "00000001" | "00100001" | "01001100" | -- non-posted
"01101100" | "01001101" | "01101101" | "01001110" |
"01101110" =>
type_fmt_err_o <= "01";
when "01100000" => --posted
type_fmt_err_o <= "10";
when others =>
type_fmt_err_o <= "11"; -- e.g. TLP prefix or TCfg
end case;
------------------------------------------------------------------
-- calculate the amount of 64bit packets that must be stored to
-- the FIFO:
-- -> read length is always 2
-- -> 2 packets for the header information
-- -> length value divided by 2 because it represents the amount
-- of 32bit packets
-- length = 0 represents 1024DW otherwise as specified by length
------------------------------------------------------------------
if rx_st_data0(31 downto 29) = FMT_IS_READ then
int_cntr_val_temp <= std_logic_vector(to_unsigned(2,10));
elsif rx_st_data0(9 downto 0) = ZERO_10B then
int_cntr_val_temp <= std_logic_vector(unsigned('1' & rx_st_data0(9 downto 1)) + to_unsigned(2,10));
else
int_cntr_val_temp <= std_logic_vector(unsigned('0' & rx_st_data0(9 downto 1)) + to_unsigned(2,10));
end if;
elsif sop_q_i = '1' then
-------------------------------------------
-- reset int_tag_rcvd value one clock cycle
-- after it was asserted
-------------------------------------------
int_tag_rcvd <= '0';
if int_c_wr = '0' then
tag_nbr_o <= rx_st_data0(15 downto 8);
end if;
if int_rxstdata0_q(2) = '0' then
int_aligned <= '1';
else
int_aligned <= '0';
end if;
----------------------------------------------------------------
-- set counter value to temp value +1 if length is odd and
-- data is aligned
-- otherwise set counter value to temp value
-- don't change counter for read transactions
----------------------------------------------------------------
if int_is_read = '0' and int_len_is_odd = '1' and rx_st_data0(2) = '0' then
int_cntr_val_temp <= std_logic_vector(unsigned(int_cntr_val_temp) + to_unsigned(1,10));
else
int_cntr_val_temp <= int_cntr_val_temp;
end if;
else
int_len_is_odd <= int_len_is_odd;
int_cntr_val_temp <= int_cntr_val_temp;
int_aligned <= int_aligned;
end if;
else
int_len_is_odd <= int_len_is_odd;
int_aligned <= int_aligned;
end if;
if int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
int_aligned <= '0';
if int_rxstdata0_q(28 downto 24) = TYPE_IS_MEMORY or int_rxstdata0_q(28 downto 24) = TYPE_IS_IO then
-------------------------------------------------------------------------
-- data alignment in FIFO for writes or reads
-- h : header information stored to FIFO
-- d : data packet stored to FIFO
-- x : data at this position is invalid (can differ from 0)
--+---------+--------------+--------------+--------------+--------------+
--| | aligned | aligned | not aligned | not aligned |
--| | even length | odd length | even length | odd length |
--+---------+--------------+--------------+--------------+--------------+
--| RX FIFO | | | | | | | | | | | | |
--| 63 | | | | | | | | | | | | |
--| ... | h1 | x | d1 | h1 | x | x | h1 | d0 | x | h1 | d0 | d2 |
--| 32 | | | | | | | | | | | | |
--|---------|----|----|----|----|----|----|----|----|----|----|----|----|
--| 31 | | | | | | | | | | | | |
--| ... | h0 | h2 | d0 | h0 | h2 | d0 | h0 | h2 | d1 | h0 | h2 | d1 |
--| 0 | | | | | | | | | | | | |
--+---------+----+----+----+----+----+----+----+----+----+----+----+----+
-------------------------------------------
-- store header for write or read to FIFO
-------------------------------------------
rx_fifo_in_o(63 downto 54) <= (others => '0'); -- R
rx_fifo_in_o(53 downto 51) <= int_rxstdata0_q(18) & int_rxstdata0_q(13 downto 12); -- Attr
rx_fifo_in_o(50 downto 48) <= int_rxstdata0_q(22 downto 20); -- TC
rx_fifo_in_o(47 downto 32) <= int_rxstdata0_q(63 downto 48); -- requester ID
rx_fifo_in_o(31) <= int_rxstdata0_q(30); -- write flag
if int_rxstdata0_q(28 downto 24) = TYPE_IS_IO then
rx_fifo_in_o(30) <= '1'; -- I/O flag
else
rx_fifo_in_o(30) <= '0';
end if;
rx_fifo_in_o(29) <= '0'; -- R
---------------------------------------
-- decode and store which BAR was hit
---------------------------------------
case rx_st_bardec0 is
when "00000001" =>
rx_fifo_in_o(28 downto 26) <= "000"; -- BAR0 hit
when "00000010" =>
rx_fifo_in_o(28 downto 26) <= "001"; -- BAR1 hit
when "00000100" =>
rx_fifo_in_o(28 downto 26) <= "010"; -- BAR2 hit
when "00001000" =>
rx_fifo_in_o(28 downto 26) <= "011"; -- BAR3 hit
when "00010000" =>
rx_fifo_in_o(28 downto 26) <= "100"; -- BAR4 hit
when "00100000" =>
rx_fifo_in_o(28 downto 26) <= "101"; -- BAR5 hit
when "01000000" =>
rx_fifo_in_o(28 downto 26) <= "110"; -- expansion ROM hit
when others =>
rx_fifo_in_o(28 downto 26) <= "111"; -- no BAR hit / reserved
end case;
rx_fifo_in_o(25 downto 18) <= int_rxstdata0_q(47 downto 40); -- tag ID
rx_fifo_in_o(17 downto 14) <= int_rxstdata0_q(35 downto 32); -- first DW BE
rx_fifo_in_o(13 downto 10) <= int_rxstdata0_q(39 downto 36); -- last DW BE
rx_fifo_in_o(9 downto 0) <= int_rxstdata0_q(9 downto 0); -- length
elsif int_rxstdata0_q(28 downto 24) = TYPE_IS_CPL then
-------------------------------------------------------------------------
-- data alignment in FIFO for completions
-- h : header information stored to FIFO
-- d : data packet stored to FIFO
-- x : data at this position is invalid (can differ from 0)
--+---------+--------------+--------------+--------------+--------------+
--| | aligned | aligned | not aligned | not aligned |
--| | even length | odd length | even length | odd length |
--+---------+--------------+--------------+--------------+--------------+
--| RX FIFO | | | | | | | | | | | | |
--| 63 | | | | | | | | | | | | |
--| ... | x | x | d1 | x | x | x | x | d0 | x | x | d0 | d2 |
--| 32 | | | | | | | | | | | | |
--|---------|----|----|----|----|----|----|----|----|----|----|----|----|
--| 31 | | | | | | | | | | | | |
--| ... | h0 | x | d0 | h0 | x | d0 | h0 | x | d1 | h0 | x | d1 |
--| 0 | | | | | | | | | | | | |
--+---------+----+----+----+----+----+----+----+----+----+----+----+----+
----------------------------------------
-- store header for completion to FIFO
----------------------------------------
rx_fifo_in_o(63 downto 22) <= (others => '0'); -- R
rx_fifo_in_o(21 downto 10) <= int_rxstdata0_q(43 downto 32); -- byte count
rx_fifo_in_o(9 downto 0) <= int_rxstdata0_q(9 downto 0); -- length
end if;
elsif int_rxstvalid0_q = '1' and int_sopqi_q = '1' then
rx_fifo_in_o <= int_rxstdata0_q; -- address and D0 or R
elsif int_rxstvalid0_q = '1' then
rx_fifo_in_o <= int_rxstdata0_q;
end if;
end if;
end process main;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
-- NONE
-------------------------------------------------------------------------------
end architecture rx_get_data_arch;
| gpl-3.0 | f028f7a0d9757dec357df77d7e95afb9 | 0.34248 | 4.599583 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_pwm.vhd | 1 | 4,043 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:11 08/28/2013
-- Design Name:
-- Module Name: wishbone_pwm - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.control_pack.all ;
entity wishbone_pwm is
generic( nb_chan : positive := 7;
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
pwm_out : out std_logic_vector(nb_chan-1 downto 0)
);
end wishbone_pwm;
architecture Behavioral of wishbone_pwm is
signal pwm_regs : slv16_array(0 to (nb_chan+1)) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal reverse_outputs : std_logic_vector(0 to (nb_chan-1));
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= pwm_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
register_mngmt : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
pwm_regs(conv_integer(wbs_address)) <= wbs_writedata;
end if ;
end if;
end process register_mngmt;
pwm_ctrl : pwm
generic map(NB_CHANNEL => nb_chan)
port map(
clk => gls_clk,
resetn => (NOT gls_reset),
divider => pwm_regs(0),
period => pwm_regs(1),
pulse_width => pwm_regs(2 to (2+(nb_chan-1))),
pwm => reverse_outputs
);
gen_reverse : for i in 0 to nb_chan-1 generate
pwm_out(i) <= reverse_outputs(i) ;
end generate ;
end Behavioral;
| lgpl-3.0 | 6db46d0de806e84bf8e3f189101a3e53 | 0.598318 | 3.581045 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd | 2 | 53,624 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
| bsd-3-clause | 28d0ef52940c0ffed90cf5f1240ffa7b | 0.489949 | 4.85329 | false | false | false | false |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/fpga_pkg_2_top_example.vhd | 1 | 3,086 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_top.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_top.vhd
-- - fpga_pkg_2_16zxxx.vhd
-- - - one_device.vhd
-- - fpga_pkg_2_16zyyy.vhd
-- - - many_devices.vhd
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_top_example.vhd,v $
-- Revision 1.2 2009/02/17 11:37:37 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:55 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:55 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_top IS
PORT(
dummy_o : OUT std_logic;
dummy_i : IN std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_top_arch OF fpga_pkg_2_top IS
CONSTANT FPGA_FAMILY : family_type := CYCLONE;
COMPONENT fpga_pkg_2_16zxxx
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
COMPONENT fpga_pkg_2_16zyyy
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
the_one_device : fpga_pkg_2_16zxxx
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_o
);
the_fpga_pkg_2_16zyyy : fpga_pkg_2_16zyyy
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_i
);
END ARCHITECTURE fpga_pkg_2_top_arch;
| gpl-3.0 | c33034bb2c43943018125e0aaf01876d | 0.447829 | 4.304045 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/plb_cond_vars.vhd | 9 | 34,063 | ------------------------------------------------------------------------------
-- plb_cond_vars.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_cond_vars.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_cond_vars_v1_00_a;
use plb_cond_vars_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_cond_vars is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := X"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_cond_vars;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_cond_vars is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_cond_vars_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_TM_BASE => C_TM_BASE,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
end IMP;
| bsd-3-clause | 0150d5a6aee9541b06592f41ebe072f2 | 0.458562 | 4.248846 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_cond_vars_v1_00_a/hdl/vhdl/axi_cond_vars.vhd | 2 | 27,381 | ------------------------------------------------------------------------------
-- axi_cond_vars.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_cond_vars.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Jun 26 14:24:54 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_lite_v1_00_a;
use axi_master_lite_v1_00_a.axi_master_lite;
library axi_cond_vars_v1_00_a;
use axi_cond_vars_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_LITE_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_LITE_DATA_WIDTH -- Master-Intf data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_lite_aclk -- AXI4LITE master: Clock
-- m_axi_lite_aresetn -- AXI4LITE master: Reset
-- md_error -- AXI4LITE master: Error
-- m_axi_lite_arready -- AXI4LITE master: Read address ready
-- m_axi_lite_arvalid -- AXI4LITE master: read address valid
-- m_axi_lite_araddr -- AXI4LITE master: read address protection
-- m_axi_lite_arprot -- AXI4LITE master: Read address protection
-- m_axi_lite_rready -- AXI4LITE master: Read data ready
-- m_axi_lite_rvalid -- AXI4LITE master: Read data valid
-- m_axi_lite_rdata -- AXI4LITE master: Read data
-- m_axi_lite_rresp -- AXI4LITE master: read data response
-- m_axi_lite_awready -- AXI4LITE master: write address ready
-- m_axi_lite_awvalid -- AXI4LITE master: write address valid
-- m_axi_lite_awaddr -- AXI4LITE master: write address valid
-- m_axi_lite_awprot -- AXI4LITE master: write address protection
-- m_axi_lite_wready -- AXI4LITE master: write data ready
-- m_axi_lite_wvalid -- AXI4LITE master: write data valid
-- m_axi_lite_wdata -- AXI4LITE master: write data
-- m_axi_lite_wstrb -- AXI4LITE master: write data strobe
-- m_axi_lite_bready -- AXI4LITE master: read response ready
-- m_axi_lite_bvalid -- AXI4LITE master: read response valid
-- m_axi_lite_bresp -- AXI4LITE master: read response
------------------------------------------------------------------------------
entity axi_cond_vars is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_TM_BASE : std_logic_vector := X"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"00FFFFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_M_AXI_LITE_ADDR_WIDTH : integer := 32;
C_M_AXI_LITE_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_lite_aclk : in std_logic;
m_axi_lite_aresetn : in std_logic;
md_error : out std_logic;
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_araddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_arprot : out std_logic_vector(2 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_rdata : in std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_rresp : in std_logic_vector(1 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_awprot : out std_logic_vector(2 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
m_axi_lite_wdata : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_wstrb : out std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
m_axi_lite_bready : out std_logic;
m_axi_lite_bvalid : in std_logic;
m_axi_lite_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_lite_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_lite_aresetn : signal is "10000";
attribute SIGIS of m_axi_lite_aclk : signal is "Clk";
attribute SIGIS of m_axi_lite_aresetn : signal is "Rst";
end entity axi_cond_vars;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_cond_vars is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
);
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
-- 1 => (USER_MST_NUM_REG) -- number of ce for user logic master space
);
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_M_AXI_LITE_ADDR_WIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_M_AXI_LITE_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1);
signal ipif_ip2bus_mst_be : std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate axi_master_lite
------------------------------------------
AXI_MASTER_LITE_I : entity axi_master_lite_v1_00_a.axi_master_lite
generic map
(
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_lite_aclk => m_axi_lite_aclk,
m_axi_lite_aresetn => m_axi_lite_aresetn,
md_error => md_error,
m_axi_lite_arready => m_axi_lite_arready,
m_axi_lite_arvalid => m_axi_lite_arvalid,
m_axi_lite_araddr => m_axi_lite_araddr,
m_axi_lite_arprot => m_axi_lite_arprot,
m_axi_lite_rready => m_axi_lite_rready,
m_axi_lite_rvalid => m_axi_lite_rvalid,
m_axi_lite_rdata => m_axi_lite_rdata,
m_axi_lite_rresp => m_axi_lite_rresp,
m_axi_lite_awready => m_axi_lite_awready,
m_axi_lite_awvalid => m_axi_lite_awvalid,
m_axi_lite_awaddr => m_axi_lite_awaddr,
m_axi_lite_awprot => m_axi_lite_awprot,
m_axi_lite_wready => m_axi_lite_wready,
m_axi_lite_wvalid => m_axi_lite_wvalid,
m_axi_lite_wdata => m_axi_lite_wdata,
m_axi_lite_wstrb => m_axi_lite_wstrb,
m_axi_lite_bready => m_axi_lite_bready,
m_axi_lite_bvalid => m_axi_lite_bvalid,
m_axi_lite_bresp => m_axi_lite_bresp,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_cond_vars_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_TM_BASE => C_TM_BASE,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_WrCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
-- user_Bus2IP_RdCE(USER_NUM_REG-1 downto USER_NUM_REG-USER_MST_NUM_REG) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
-- user_Bus2IP_WrCE(USER_NUM_REG-1 downto USER_NUM_REG- USER_MST_NUM_REG) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
| bsd-3-clause | e1159c31793f21833c0e5084285c4055 | 0.489756 | 3.746716 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_counter_bit.vhd | 3 | 9,741 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common_v2_00_a library.
-- ^^^^^^
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| bsd-3-clause | 8ff875acb34992b13209e1a583ae9901 | 0.43127 | 4.756348 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/gen_sync_dpram.vhd | 2 | 5,005 | -------------------------------------------------------------------------------
-- $Id: gen_sync_dpram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- gen_sync_dpram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2004-03-24 New Version
--
-- Description:
-- Code to infer synchronous dual port lut ram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Sync_DPRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end Sync_DPRAM;
architecture syn of Sync_DPRAM is
type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
-- signal RAM : ram_type := (others => (others => '0'));
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
dpo <= RAM(conv_integer(dpra));
end syn;
| bsd-3-clause | 5335efb5cfe8ef51d6be71e1387ac098 | 0.562238 | 4.398067 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/eth/eth.vhd | 1 | 29,123 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity eth is
generic(
MII_WIDTH : natural := 8;
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32;
RAM_DWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(MII_WIDTH-1 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(MII_WIDTH-1 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
----------------------------------------------
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
progIO_id : out std_logic_vector(3 downto 0);
progIO_reset : out std_logic;
progIO_wren : out std_logic;
progIO_addr : out std_logic_vector(9 downto 0);
progIO_wdata : out std_logic_vector(15 downto 0);
progIO_rdata : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(RAM_DWIDTH-1 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(RAM_DWIDTH-1 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of eth is
component ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(15 downto 0));
end component;
component g_ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component g_ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
component macAddrConfig
port (
ethtx_port_id : in std_logic_vector(7 downto 0);
ethrx_port_id : in std_logic_vector(7 downto 0);
db_port_id : in std_logic_vector(7 downto 0);
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0);
ethtx_in_port : out std_logic_vector(7 downto 0);
ethrx_in_port : out std_logic_vector(7 downto 0);
db_in_port : out std_logic_vector(7 downto 0)
);
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal txen_buf : std_logic;
signal db_ce : std_logic_vector(15 downto 0);
signal ethtx_ce : std_logic_vector(15 downto 0);
signal ethrx_ce : std_logic_vector(15 downto 0);
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
Eth100BaseRx : if MII_WIDTH = 4 generate
u_rx : ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
end generate Eth100BaseRx;
Eth1000BaseRx : if MII_WIDTH = 8 generate
u_rx : g_ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
end generate Eth1000BaseRx;
-- db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
-- eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
-- eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
db_rx_ce <= db_ce(conv_integer(PORTS_DB_RX));
eth_rx_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX));
eth_rxdma_ce <= ethrx_ce(conv_integer(PORTS_ETH_RXDMA));
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethrx_port_id( 7 downto 4),
ce => ethrx_ce
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
-- ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
ethrx_task_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX_TASK));
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
-- ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
Eth100BaseTx : if MII_WIDTH = 4 generate
u_tx : ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
end generate Eth100BaseTx;
Eth1000BaseTx : if MII_WIDTH = 8 generate
u_tx : g_ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
end generate Eth1000BaseTx;
txen <= txen_buf;
-- db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
-- eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
db_tx_ce <= db_ce(conv_integer(PORTS_DB_TX));
eth_tx_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX));
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethtx_port_id( 7 downto 4),
ce => ethtx_ce
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
-- ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_task_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX_TASK));
-- ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
-- local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
u_db_zcpsm_ce : zcpsmDecode
port map(
port_id_H => db_port_id( 7 downto 4),
ce => db_ce
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
-- db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
db_debug_ce <= db_ce(conv_integer(PORTS_DB_DEBUG));
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
-- db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
-- local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
-- (others => 'Z');
u_macAddr : macAddrConfig
port map(
ethtx_port_id => ethtx_port_id,
ethrx_port_id => ethrx_port_id,
db_port_id => db_port_id,
local_id_MAC0_Req => local_id_MAC0_Req,
local_id_MAC0_A => local_id_MAC0_A,
local_id_MAC0_B => local_id_MAC0_B,
local_id => local_id,
ethtx_in_port => ethtx_in_port,
ethrx_in_port => ethrx_in_port,
db_in_port => db_in_port
);
end arch_eth;
| gpl-2.0 | 8e8147e63535d324192d98766b39edfa | 0.581362 | 2.704085 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutexattr_destroy_2.vhd | 2 | 15,479 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutexattr_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutexattr_init( mutexattr );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_mutexattr_destroy( mutexattr );
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutexattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | a06c72d29dee8e7af5eb3ccd7033fe42 | 0.541249 | 3.848583 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/logi_wishbone_pack.vhd | 1 | 6,206 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural;
type wishbone16_bus is
record
address : std_logic_vector(15 downto 0);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
cycle: std_logic;
write : std_logic;
strobe : std_logic;
ack : std_logic;
end record;
type array_of_addr is array(NATURAL range <>) of std_logic_vector(15 downto 0);
type array_of_slv16 is array(NATURAL range <>) of std_logic_vector(15 downto 0);
component gpmc_wishbone_wrapper is
generic(sync : boolean := false ; burst : boolean := false );
port
(
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component spi_wishbone_wrapper is
generic(BIG_ENDIAN : boolean := true);
port
(
-- SPI SIGNALS
mosi, ss, sck : in std_logic;
miso : out std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end component;
end logi_wishbone_pack;
package body logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural is
begin
for i in slv'range loop
if slv(i) ='X' then
return i+1 ;
end if;
end loop;
return 0;
end function find_X;
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return natural is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(data, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '1' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return 1;
--end function sim_wishbone_write;
--
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return std_logic_vector(15 downto 0) is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(0, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '0' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return wish_bus.readdata;
--end function sim_wishbone_write;
end logi_wishbone_pack;
| lgpl-3.0 | 8093dffb9d5f3c8736ad8902096fc164 | 0.619723 | 3.233976 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_pkg.vhd | 1 | 4,717 | --------------------------------------------------------------------------------
-- Title : Definitions and Constants for WBB2VME
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_pkg.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 02/02/12
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision 1.4 2017/06/13 07:00:14 MMiehling
-- changed vme_acc_type setting for CR/CSR and D32 to be compliant to DMA configuration bits
--
-- Revision 1.3 2014/02/07 17:00:14 MMiehling
-- bugfix: IACK addressing
--
-- Revision 1.2 2012/08/27 12:57:11 MMiehling
-- changed polarity of swapped bit in constants
--
-- Revision 1.1 2012/03/29 10:14:34 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE vme_pkg IS
CONSTANT CONST_VME_REGS : std_logic_vector(6 DOWNTO 0):="1000000";
CONSTANT CONST_VME_IACK : std_logic_vector(6 DOWNTO 0):="0100011";
CONSTANT CONST_VME_A16D16 : std_logic_vector(6 DOWNTO 0):="0100010";
CONSTANT CONST_VME_A16D32 : std_logic_vector(6 DOWNTO 0):="0100110";
CONSTANT CONST_VME_A24D16 : std_logic_vector(6 DOWNTO 0):="0100000";
CONSTANT CONST_VME_A24D32 : std_logic_vector(6 DOWNTO 0):="0100100";
CONSTANT CONST_VME_CRCSR : std_logic_vector(6 DOWNTO 0):="0101000";
CONSTANT CONST_VME_A32D32 : std_logic_vector(6 DOWNTO 0):="0100101";
CONSTANT CONST_VME_A16D16S : std_logic_vector(6 DOWNTO 0):="0000010";
CONSTANT CONST_VME_A16D32S : std_logic_vector(6 DOWNTO 0):="0000110";
CONSTANT CONST_VME_A24D16S : std_logic_vector(6 DOWNTO 0):="0000000";
CONSTANT CONST_VME_A24D32S : std_logic_vector(6 DOWNTO 0):="0000100";
CONSTANT CONST_VME_A32D32S : std_logic_vector(6 DOWNTO 0):="0000101";
CONSTANT CONST_VME_A24D16B : std_logic_vector(6 DOWNTO 0):="0110000";
CONSTANT CONST_VME_A24D32B : std_logic_vector(6 DOWNTO 0):="0110100";
CONSTANT CONST_VME_A32D32B : std_logic_vector(6 DOWNTO 0):="0110101";
CONSTANT CONST_VME_A32D64B : std_logic_vector(6 DOWNTO 0):="0111101";
CONSTANT CONST_VME_A24D16BS : std_logic_vector(6 DOWNTO 0):="0010000";
CONSTANT CONST_VME_A24D32BS : std_logic_vector(6 DOWNTO 0):="0010100";
CONSTANT CONST_VME_A32D32BS : std_logic_vector(6 DOWNTO 0):="0010101";
CONSTANT CONST_VME_A32D64BS : std_logic_vector(6 DOWNTO 0):="0011101";
TYPE io_ctrl_type IS record
d_dir : std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : std_logic; -- external driver control data output enable low active
am_dir : std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : std_logic; -- external driver control address modifier output enable low activ
a_dir : std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : std_logic; -- external driver control address output enable low activ
END record;
TYPE test_vec_type IS record
ato : std_logic; -- arbitration time out
END record;
END vme_pkg;
PACKAGE BODY vme_pkg IS
END;
| gpl-3.0 | 9d739c953fc6a067341fa8f565d0104f | 0.567734 | 4.062877 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/plb_sync_manager.vhd | 9 | 47,769 | ------------------------------------------------------------------------------
-- plb_sync_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_sync_manager_v1_00_a;
use plb_sync_manager_v1_00_a.user_logic;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_sync_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_sync_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_sync_manager is
-------------------------------------------------------------------
-- BEGIN CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - 2 to
C_SPLB_AWIDTH - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_SPLB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-------------------------------------------------------------------
-- END CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
-- constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
-- constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
--
-- constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- (
-- ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
-- ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
-- ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
-- ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
-- );
-- ------------------------------------------
-- -- Array of desired number of chip enables for each address range
-- ------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG+USER_MST_NUM_REG;
--
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
-- 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
-- 1 => pad_power2(USER_MST_NUM_REG) -- number of ce for user logic master space
-- );
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_MST_CS_INDEX : integer := 1;
constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
-- ------------------------------------------
-- -- instantiate User Logic
-- ------------------------------------------
-- USER_LOGIC_I : entity plb_sync_manager_v1_00_a.user_logic
-- generic map
-- (
-- -- MAP USER GENERICS BELOW THIS LINE ---------------
-- --USER generics mapped here
-- -- MAP USER GENERICS ABOVE THIS LINE ---------------
--
-- C_SLV_DWIDTH => USER_SLV_DWIDTH,
-- C_MST_AWIDTH => USER_MST_AWIDTH,
-- C_MST_DWIDTH => USER_MST_DWIDTH,
-- C_NUM_REG => USER_NUM_REG
-- )
-- port map
-- (
-- -- MAP USER PORTS BELOW THIS LINE ------------------
-- --USER ports mapped here
-- -- MAP USER PORTS ABOVE THIS LINE ------------------
--
-- Bus2IP_Clk => ipif_Bus2IP_Clk,
-- Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => ipif_Bus2IP_Addr,
-- Bus2IP_CS => ipif_Bus2IP_CS,
-- Bus2IP_RNW => ipif_Bus2IP_RNW,
-- Bus2IP_Data => ipif_Bus2IP_Data,
-- Bus2IP_BE => ipif_Bus2IP_BE,
-- Bus2IP_RdCE => user_Bus2IP_RdCE,
-- Bus2IP_WrCE => user_Bus2IP_WrCE,
-- IP2Bus_Data => user_IP2Bus_Data,
-- IP2Bus_RdAck => user_IP2Bus_RdAck,
-- IP2Bus_WrAck => user_IP2Bus_WrAck,
-- IP2Bus_Error => user_IP2Bus_Error,
-- IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
-- IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
-- IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
-- IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
-- IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
-- IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
-- Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
-- Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
-- Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
-- Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
-- Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
-- Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
-- Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
-- IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
-- Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
-- );
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => iBus2IP_Addr,
-- Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
-- Bus2IP_RNW => iBus2IP_RNW,
-- Bus2IP_RdCE => uBus2IP_RdCE,
-- Bus2IP_WrCE => uBus2IP_WrCE,
-- Bus2IP_RdReq => iBus2IP_RdReq,
-- Bus2IP_WrReq => iBus2IP_WrReq,
-- Bus2IP_MstError => iBus2IP_MstError,
-- Bus2IP_MstLastAck => iBus2IP_MstLastAck,
-- Bus2IP_MstRdAck => iBus2IP_MstRdAck,
-- Bus2IP_MstWrAck => iBus2IP_MstWrAck,
-- Bus2IP_MstRetry => iBus2IP_MstRetry,
-- Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
-- IP2Bus_Addr => iIP2Bus_Addr,
-- IP2Bus_MstBE => uIP2Bus_MstBE,
-- IP2Bus_MstBurst => iIP2Bus_MstBurst,
-- IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
-- IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
-- IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
-- IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
-- begin
--
-- case ipif_Bus2IP_CS is
-- when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
--
-- end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
end IMP;
| bsd-3-clause | 6bcc2511777b97d86b33ba93281e46d2 | 0.475455 | 4.066485 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hw_acc_bubblesort_v1_00_a/hdl/vhdl/hw_acc_bubblesort.vhd | 2 | 4,217 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_sort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_sort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_sort is
component bubblesort is
port
(
array0_addr0 : out std_logic_vector(0 to (32 - 1));
array0_dIN0 : out std_logic_vector(0 to (32 - 1));
array0_dOUT0 : in std_logic_vector(0 to (32 - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal in_BRAM_A_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_A_wEN : std_logic;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
BRAM_A_addr <= in_BRAM_A_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_A_wEN <= in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN;
uut : bubblesort
port map (
array0_addr0 => in_BRAM_A_addr,
array0_dIN0 => BRAM_A_din,
array0_dOUT0 => BRAM_A_dout,
array0_rENA0 => BRAM_A_en,
array0_wENA0 => in_BRAM_A_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause | c6666e401090ac62e3e2e5930df8c4de | 0.562959 | 3.139985 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_control_rd.vhd | 3 | 37,875 | -------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_rd.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Read Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_control_rd.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe March 19,2001 -- V1.00a
--
-- Doug Thorpe June 08-12,2001 -- V1.00b
-- - Corrected an error condition where the FIFO2Bus_Error was getting set
-- at the end of a legitimate burst read operation. If the RdFIFO goes
-- empty after the initiation of the read (at least one FIFO2Bus_RdAck
-- has been issued), an 'Empty' condition causes only an inhibit of the
-- FIFO2Bus_RdAck signal.
-- - Fixed the implimentation of the MIR inclusion/occlusion through the
-- use of if--generate clauses.
--
-- DET June 25, 2001 V1.00c
-- - Removed redundant logic assignments flagged by
-- Synplicity
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Aug 20, 2001 Version v1.01a
-- - Platform Generator Compliancy modifications
--
-- DET Sept 17, 2001
-- - Size optimization changes
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_rd is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 2;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 26 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates read burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(C_IPIF_DBUS_WIDTH-4 to
C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_rd_data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
BRAMFifo_RdAck : In std_logic;
SRLFifo_RdAck : In std_logic;
Occupancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostEmpty : In std_logic;
Empty : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_rst : Out std_logic;
BRAMFifo_RdReq : Out std_logic;
SRLFifo_RdReq : Out std_logic;
Fifo_burst_rd_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_rd ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_rd is
-- FUNCTIONS
-----------------------------------------------------------------------------
-- Function set_fwidth
--
-- This function is used to set the value of FIFO width status
-- field based on the setting of the width parameter.
-----------------------------------------------------------------------------
function set_fwidth (fifo_width : integer) return integer is
constant byte_lane_num : Integer := (fifo_width+7)/8;
Variable enc_size : Integer := 0;
begin
case byte_lane_num is
when 0|1 =>
enc_size := 1;
when 2 =>
enc_size := 2;
when 3 | 4 =>
enc_size := 3;
when 5|6|7|8 =>
enc_size := 4;
When 9|10|11|12|13|14|15|16 =>
enc_size := 5;
when others =>
enc_size := 6;
end case;
return(enc_size);
end function set_fwidth;
-- COMPONENTS
-- No components
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Bus Width Matching constant
Constant ENC_FIFO_WIDTH : integer := set_fwidth(C_FIFO_WIDTH);
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal sw_reset_error : std_logic;
signal reg_occupancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostempty : std_logic;
Signal reg_empty : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_rd_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal fifo_rd_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_srl_rdack : std_logic;
Signal sig_bram_rdack : std_logic;
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_rd_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
---------- start architecture logic -------------------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW; -- output signal not currently used so
-- drive low .
FIFO2Bus_Retry <= LOGIC_LOW; -- output signal not currently used so
-- drive low.
FIFO2Bus_WrAck <= write_ack and write_req; -- connect the write
-- acknowledge (drive only
-- if a request is present)
FIFO2Bus_RdAck <= read_ack and read_req; -- connect the read
-- acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
BRAMFifo_RdReq <= Bus_RdReq and Bus2FIFO_RdCE3; -- Read Request to BRAM
-- based FIFO.
SRLFifo_RdReq <= reg_rdreq and Bus2FIFO_RdCE3; -- Read Request to SRL
-- based FIFO
Fifo_burst_rd_xfer <= burst_rd_xfer; -- Burst detect signal to FIFO read
-- controller
sig_srl_rdack <= SRLFifo_RdAck;
sig_bram_rdack <= BRAMFifo_RdAck;
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
sig_fifo_rd_data <= (others => '0'); --default bus state
for j in 0 to C_FIFO_WIDTH-1 loop
sig_fifo_rd_data(C_IPIF_DBUS_WIDTH-C_FIFO_WIDTH+j)
<= fifo_rd_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
sig_fifo_rd_data <= fifo_rd_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
sig_fifo_rd_data(j) <= fifo_rd_data(C_FIFO_WIDTH-
C_IPIF_DBUS_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_rdce2 <= '0';
reg_wrce1 <= '0';
reg_rdreq <= '0';
reg_read_req <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
INCLUDE_BURST : if (C_SUPPORT_BURST = true) generate
--burst_rd_xfer <= reg_rdreq and Bus_RdReq;
-------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data
-- read cycle during a burst read.
-------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
burst_rd_xfer <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1' ) Then
burst_rd_xfer <= reg_rdreq and Bus_RdReq;
If (Bus2FIFO_RdCE3 = '1' and sig_bram_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and sig_srl_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
end generate INCLUDE_BURST;
OMIT_BURST : if (C_SUPPORT_BURST = false) generate
burst_rd_xfer <= '0';
fifo_errack_inhibit <= '0';
end generate OMIT_BURST;
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_occupancy <= (others => '0');
reg_deadlock <= '0';
reg_almostempty <= '0';
reg_empty <= '1';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during
-- read operation.
null;
else -- register new status every clock
reg_occupancy <= Occupancy ;
reg_deadlock <= Deadlock ;
reg_almostempty <= AlmostEmpty ;
reg_empty <= Empty ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
Fifo_rst <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
Fifo_rst <= '1';
sw_reset_error <= '0';
When "01" =>
Fifo_rst <= '0';
sw_reset_error <= '1';
When others =>
Fifo_rst <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- Conversion to std_logic_vector is required
----------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to C_IPIF_DBUS_WIDTH-1 loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(C_IPIF_DBUS_WIDTH-28 to C_IPIF_DBUS_WIDTH-26)
-- <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(3) <= '0' ;
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Occupancy is scaled in this case
status_bus(3) <= '1';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
sig_fifo_rd_data, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When "1100" => -- Read FIFO data port
bus_data_out <= sig_fifo_rd_data;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-------------------------------------------------------------------------------
-- Synthesis for MIR occlusion
-------------------------------------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus(4 to C_IPIF_DBUS_WIDTH-1) <= (others => '0');
-- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, sig_fifo_rd_data,
status_bus, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When "1100" =>
bus_data_out <= sig_fifo_rd_data;
When others =>
bus_data_out <= (others => '0');
End case;
End process ; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then
reg_read_ack <= sig_bram_rdack;
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack
or rd_access_error
or sig_srl_rdack;
write_ack <= reg_wrce1 or wr_access_error;
-------------------------------------------------------------------------------
-- Generate the Write Error Acknowledge Reply to the Bus when
-- an attempted write access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
--GEN_WR_ERROR : process (Bus2FIFO_WrCE2, Bus2FIFO_WrCE3)
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE2 = '1') Then -- attempting to write to the status
-- register.
wr_access_error <= '1';
ElsIf (Bus2FIFO_WrCE3 = '1') Then -- attempting a write to the FIFO
-- Read data port.
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause | e93e5fe06a360bb8ec30ef11a5e2b51d | 0.450297 | 4.52509 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/ctrl_reg.vhd | 3 | 4,906 | -------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/05/07 21:48:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ctrl_reg.vhd
--
-- Description: Control register with parameterizable width and two
-- write enables.
--
-------------------------------------------------------------------------------
-- Structure:
-- ctrl_reg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- -- Two point solution registers are declared
-- -- for this version as XST E.33 does not handle
-- -- the parameterized width.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end ctrl_reg;
architecture sim of ctrl_reg is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_6 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end ctrl_reg_0_to_6;
architecture sim of ctrl_reg_0_to_6 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_0 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end ctrl_reg_0_to_0;
architecture sim of ctrl_reg_0_to_0 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
-- XGR_E33 q <= C_RESET_VAL;
q <= C_RESET_VAL(0);
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
| bsd-3-clause | 4dc0cd7b39cdf67f0404ad9d019d412a | 0.387281 | 4.171769 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/srl16_fifo.vhd | 3 | 9,197 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_adder;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| bsd-3-clause | b5fb7a45faff04d22a967740cf75bd0d | 0.451886 | 3.913617 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_data_steer_mirror.vhd | 2 | 15,374 | -------------------------------------------------------------------------------
-- $Id: xbic_data_steer_mirror.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_data_steer_mirror.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_data_steer_mirror.vhd
--
-- Description:
-- This file implements the logic needed to mirror a Slave's Read Data
-- bus to a 32/64/128 bit PLBV46 Bus. This module also provides the required
-- read data steering logic when interfaceing with masters that are narrower
-- than the Slave's Native Data Width.
--
--
-- Notes:
-- 1) The PLBV46 Bus Width cannot be narrower than the Slave's Native Dwidth.
--
-- 2) Byte and Half-word transfers are not supported in the Xilinx PLBV46
-- simplifications so the associated steering mux logic for those transfer
-- widths is omitted.
--
-- 3) Data Steering has been simplified by omitting the requesting Master's
-- size (PLB_msize(0:1) from the mux control logic. Steering is implemented
-- only as a function of the address of the Data Beat presented to the PLB.
-- This implementation is more general and less resource intensive.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Change Log:
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $01/18/2007$
--
-- History:
-- DET 02/12/2007 Initial Version
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim; -- Required for Xilinx primitives
use unisim.all;
-------------------------------------------------------------------------------
entity xbic_data_steer_mirror is
generic (
C_STEER_ADDR_WIDTH : integer range 1 to 36 := 8;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_SMALLEST_MASTER : integer range 32 to 128 := 32
);
port (
Steer_Addr_In : in std_logic_vector(0 to
C_STEER_ADDR_WIDTH-1);
Data_In : in std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
Data_Out : out std_logic_vector(0 to
C_SPLB_DWIDTH-1)
);
end entity xbic_data_steer_mirror;
architecture implementation of xbic_data_steer_mirror is
-- Constants
Constant WRD_OFFSET_BIT : integer := 3;
Constant DWRD_OFFSET_BIT : integer := 4;
-- Signals
signal sig_addr_bits_dwrd_wrd : std_logic_vector(0 to 1);
signal sig_addr_bit_wrd : std_logic;
signal sig_addr_bit_dwrd : std_logic;
begin --(architecture implementation)
sig_addr_bits_dwrd_wrd <= Steer_Addr_In(C_STEER_ADDR_WIDTH -
DWRD_OFFSET_BIT)
&
Steer_Addr_In(C_STEER_ADDR_WIDTH -
WRD_OFFSET_BIT);
sig_addr_bit_wrd <= Steer_Addr_In(C_STEER_ADDR_WIDTH -
WRD_OFFSET_BIT);
sig_addr_bit_dwrd <= Steer_Addr_In(C_STEER_ADDR_WIDTH -
DWRD_OFFSET_BIT);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_B128_S128
--
-- If Generate Description:
-- Bus Data width is 128 bits and the Slave Data width is
-- 128 bits.
--
------------------------------------------------------------
CASE_B128_S128 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 128) generate
begin
-- direct connect for byte lanes 8 - 15
Data_Out(64 to 127) <= Data_In(64 to 127);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: STEER_MUX_0_3
--
-- Process Description:
-- Steering Mux for byte lanes 0-3.
--
-------------------------------------------------------------
STEER_MUX_0_3 : process (sig_addr_bits_dwrd_wrd,
Data_In)
begin
case sig_addr_bits_dwrd_wrd is
-- when "00" =>
-- Data_Out(0 to 31) <= Data_In(0 to 31);
when "01" =>
Data_Out(0 to 31) <= Data_In(32 to 63);
when "10" =>
Data_Out(0 to 31) <= Data_In(64 to 95);
when "11" =>
Data_Out(0 to 31) <= Data_In(96 to 127);
when others => -- '00' case
Data_Out(0 to 31) <= Data_In(0 to 31);
end case;
end process STEER_MUX_0_3;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: STEER_MUX_4_7
--
-- Process Description:
-- Steering Mux for byte lanes 4-7.
--
-------------------------------------------------------------
STEER_MUX_4_7 : process (sig_addr_bit_dwrd,
Data_In)
begin
If (sig_addr_bit_dwrd = '1') Then
Data_Out(32 to 63) <= Data_In(96 to 127);
else
Data_Out(32 to 63) <= Data_In(32 to 63);
End if;
end process STEER_MUX_4_7;
end generate CASE_B128_S128;
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_B128_S64
--
-- If Generate Description:
-- Bus is 128 bits and Slave is 64 bits
--
--
------------------------------------------------------------
CASE_B128_S64 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 64) generate
begin
-- direct connect for byte lanes 4 - 15
Data_Out(64 to 127) <= Data_In(0 to 63);
Data_Out(32 to 63) <= Data_In(32 to 63);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: STEER_MUX_0_3
--
-- Process Description:
-- Steering Mux for byte lanes 0-3.
--
-------------------------------------------------------------
STEER_MUX_0_3 : process (sig_addr_bit_wrd,
Data_In)
begin
If (sig_addr_bit_wrd = '1') Then
Data_Out(0 to 31) <= Data_In(32 to 63);
else
Data_Out(0 to 31) <= Data_In(0 to 31);
End if;
end process STEER_MUX_0_3;
end generate CASE_B128_S64;
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_B128_S32
--
-- If Generate Description:
-- Bus is 128 bits and Slave is 32 bits
--
--
------------------------------------------------------------
CASE_B128_S32 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
-- Just mirror the data
-- no steering is required
Data_Out(96 to 127) <= Data_In(0 to 31);
Data_Out(64 to 95) <= Data_In(0 to 31);
Data_Out(32 to 63) <= Data_In(0 to 31);
Data_Out(0 to 31) <= Data_In(0 to 31);
end generate CASE_B128_S32;
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_S64_B64
--
-- If Generate Description:
-- Bus Data width is 64 bits and the Slave Data width is
-- 64 bits.
--
------------------------------------------------------------
CASE_S64_B64 : if (C_SPLB_DWIDTH = 64 and
C_SPLB_NATIVE_DWIDTH = 64) generate
begin
-- direct connect for byte lanes 4 - 7
Data_Out(32 to 63) <= Data_In(32 to 63);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: STEER_MUX_0_3
--
-- Process Description:
-- Steering Mux for byte lanes 0-3.
--
-------------------------------------------------------------
STEER_MUX_0_3 : process (sig_addr_bit_wrd,
Data_In)
begin
If (sig_addr_bit_wrd = '1') Then
Data_Out(0 to 31) <= Data_In(32 to 63);
else
Data_Out(0 to 31) <= Data_In(0 to 31);
End if;
end process STEER_MUX_0_3;
end generate CASE_S64_B64;
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_B64_S32
--
-- If Generate Description:
-- Bus is 64 bits and Slave is 32 bits
--
--
------------------------------------------------------------
CASE_B64_S32 : if (C_SPLB_DWIDTH = 64 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
-- Mirror byte lanes 0 to 3 to byte lanes 4 - 7
-- No steering required
Data_Out(32 to 63) <= Data_In(0 to 31);
Data_Out(0 to 31) <= Data_In(0 to 31);
end generate CASE_B64_S32;
------------------------------------------------------------
-- If Generate
--
-- Label: CASE_B32_S32
--
-- If Generate Description:
-- Bus Data width is 32 bits and the Slave Data width is
-- 32 bits.
--
------------------------------------------------------------
CASE_B32_S32 : if (C_SPLB_DWIDTH = 32 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
-- direct connect for byte lanes 0 - 3
Data_Out(0 to 31) <= Data_In(0 to 31);
end generate CASE_B32_S32;
-- end generate GEN_NOTSAME;
end implementation;
| bsd-3-clause | 67f3af04e139d92c0672fd87d85c8ae7 | 0.415181 | 4.792394 | false | false | false | false |
iocoder/graduation | hardware/vga/crt.vhd | 1 | 5,696 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity crt is
Port (CLK : in STD_LOGIC;
MODE : in STD_LOGIC;
VBLANK : out STD_LOGIC;
HS : out STD_LOGIC := '0';
VS : out STD_LOGIC := '0';
SE : out STD_LOGIC := '0';
DE : out STD_LOGIC := '0';
X : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
Y : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
B9 : out STD_LOGIC := '0');
end crt;
architecture Behavioral of crt is
signal hcounter : integer range 0 to 1024 := 0;
signal vcounter : integer range 0 to 1024 := 0;
signal oVBLANK : STD_LOGIC := '1';
signal cur_x : integer range 0 to 10240 := 0;
signal cur_y : integer range 0 to 10240 := 0;
signal colindx : integer range -1 to 16 := 0;
signal HORIZ_TOTAL : integer; -- horizontal cycle in pixels
signal HORIZ_PULSEWIDTH : integer; -- pulse width in pixels
signal HORIZ_BACKPORCH : integer; -- back porch in pixels
signal HORIZ_ACTIVE : integer; -- active time in pixels
signal HORIZ_FRONTPORCH : integer; -- front porch in pixels
signal VERTI_TOTAL : integer; -- vertical cycle in lines
signal VERTI_PULSEWIDTH : integer; -- pulse width in lines
signal VERTI_BACKPORCH : integer; -- back porch in lines
signal VERTI_ACTIVE : integer; -- active time in lines
signal VERTI_FRONTPORCH : integer; -- front porch in lines
signal enable_spacing : boolean;
begin
process (CLK)
begin
if (CLK = '1' and CLK'event) then
-- next pixel:
if (hcounter < HORIZ_PULSEWIDTH) then
-- HS low pulse
HS <= '0';
elsif (hcounter < HORIZ_PULSEWIDTH+HORIZ_BACKPORCH) then
-- Back porch
HS <= '1';
if (hcounter = HORIZ_PULSEWIDTH+HORIZ_BACKPORCH-1 and
oVBLANK = '0') then
-- end of back porch cycle
SE <= '1';
cur_x <= cur_x + 1;
colindx <= 0;
end if;
elsif (hcounter < HORIZ_PULSEWIDTH+HORIZ_BACKPORCH+HORIZ_ACTIVE) then
-- Display time
if (oVBLANK = '0') then
DE <= '1';
SE <= '1';
if (colindx = 7 and enable_spacing) then
B9 <= '1';
colindx <= -1;
else
B9 <= '0';
X <= conv_std_logic_vector(cur_x, 16);
cur_x <= cur_x + 1;
colindx <= colindx + 1;
end if;
end if;
if (hcounter=HORIZ_PULSEWIDTH+HORIZ_BACKPORCH+HORIZ_ACTIVE-1) then
SE <= '0';
X <= "0000000000000000";
cur_x <= 0;
end if;
else
-- Front porch
-- Display disabled:
DE <= '0';
end if;
-- increase hcounter
if (hcounter = HORIZ_TOTAL-1) then
hcounter <= 0; -- the new value
else
hcounter <= hcounter + 1; -- the new value
end if;
-- New line?
if (hcounter = 0) then
-- next line:
if (vcounter < VERTI_PULSEWIDTH) then
-- VS low pulse
VS <= '0';
elsif (vcounter < VERTI_PULSEWIDTH+VERTI_BACKPORCH) then
-- Back porch
VS <= '1';
elsif (vcounter<VERTI_PULSEWIDTH+VERTI_BACKPORCH+VERTI_ACTIVE) then
-- Display time
oVBLANK <= '0';
Y <= conv_std_logic_vector(cur_y, 16);
cur_y <= cur_y + 1;
else
-- Front porch
-- Display disabled:
oVBLANK <= '1';
cur_y <= 0;
Y <= "0000000000000000";
end if;
-- increase vcounter
if (vcounter = VERTI_TOTAL-1) then
vcounter <= 0;
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process;
VBLANK <= oVBLANK;
process (MODE)
begin
if (MODE = '0') then
-- 720x400@70Hz
HORIZ_TOTAL <= 900; -- horizontal cycle in pixels
HORIZ_PULSEWIDTH <= 108; -- pulse width in pixels
HORIZ_BACKPORCH <= 51; -- back porch in pixels
HORIZ_ACTIVE <= 720; -- active time in pixels
HORIZ_FRONTPORCH <= 21; -- front porch in pixels
VERTI_TOTAL <= 449; -- vertical cycle in lines
VERTI_PULSEWIDTH <= 2; -- pulse width in lines
VERTI_BACKPORCH <= 32; -- back porch in lines
VERTI_ACTIVE <= 400; -- active time in lines
VERTI_FRONTPORCH <= 15; -- front porch in lines
enable_spacing <= true; -- char is 9-column wide.
else
-- 640x480@60Hz
HORIZ_TOTAL <= 800; -- horizontal cycle in pixels
HORIZ_PULSEWIDTH <= 96; -- pulse width in pixels
HORIZ_BACKPORCH <= 48; -- back porch in pixels
HORIZ_ACTIVE <= 640; -- active time in pixels
HORIZ_FRONTPORCH <= 16; -- front porch in pixels
VERTI_TOTAL <= 521; -- vertical cycle in lines
VERTI_PULSEWIDTH <= 2; -- pulse width in lines
VERTI_BACKPORCH <= 29; -- back porch in lines
VERTI_ACTIVE <= 480; -- active time in lines
VERTI_FRONTPORCH <= 10; -- front porch in lines
enable_spacing <= false; -- char is 8-column wide.
end if;
end process;
end Behavioral;
| gpl-3.0 | 571b6c8a100d9e750af6fde9434fa650 | 0.505267 | 4.142545 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pselect.vhd | 3 | 12,432 | -------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:02 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
| bsd-3-clause | eb6047efbf8695c7e079b5fc77d96cb7 | 0.402349 | 5.319641 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd | 2 | 15,967 | -------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| bsd-3-clause | f4fc957272ac8f9b81f5353276b54107 | 0.470533 | 4.534791 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/rx_len_cntr.vhd | 1 | 5,497 | --------------------------------------------------------------------------------
-- Title : RX length counter
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_len_cntr.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-23
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- length counter to manage data stored to the RX FIFOs
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- * rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_len_cntr is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- rx_get_data
load_cntr_val_i : in std_logic_vector(9 downto 0);
-- rx_ctrl
load_cntr_i : in std_logic;
enable_cntr_i : in std_logic;
len2fifo_o : out std_logic_vector(9 downto 0)
);
end entity rx_len_cntr;
architecture rx_len_cntr_arch of rx_len_cntr is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
signal int_cntr_val : std_logic_vector(9 downto 0);
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
len2fifo_o <= int_cntr_val;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
cntr_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_cntr_val <= (others => '0');
elsif clk_i'event and clk_i = '1' then
-----------------------------------------------
-- load new value if load_cntr_i is asserted
-- subtract one if counter is already enabled
-----------------------------------------------
if load_cntr_i = '1' then
if enable_cntr_i = '0' then
int_cntr_val <= load_cntr_val_i;
else
int_cntr_val <= std_logic_vector(unsigned(load_cntr_val_i) - to_unsigned(1,10));
end if;
-----------------------------------------------------------
-- decrement counter as long as enable_cntr_i is set
-- but stop decrementing as soon as int_cntr_val is zero
-----------------------------------------------------------
else
if int_cntr_val > ZERO_10B and enable_cntr_i = '1' then
int_cntr_val <= std_logic_vector(unsigned(int_cntr_val) - to_unsigned(1,10));
elsif int_cntr_val > ZERO_10B and enable_cntr_i = '0' then
int_cntr_val <= int_cntr_val;
else
int_cntr_val <= (others => '0');
end if;
end if;
end if;
end process cntr_proc;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
-- NONE
-------------------------------------------------------------------------------
end architecture rx_len_cntr_arch;
| gpl-3.0 | 674caf6aaf13794f05e400e037a18680 | 0.372931 | 5.161502 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd | 2 | 12,704 | -------------------------------------------------------------------------------
-- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| bsd-3-clause | 00e3c25eb6724d16b2cd9b25d907d833 | 0.436398 | 4.765191 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_unlock_3.vhd | 2 | 15,427 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_unlock_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_mutex_unlock( mutex );
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrc_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | f8780020446307ccc7c3b0ab07f61304 | 0.539703 | 3.8347 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_wb_pkg.vhd | 1 | 76,241 | ---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : z126_01_wb_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_pkg.vhd,v $
-- Revision 1.1 2014/03/03 17:49:58 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE z126_01_wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
bte : std_logic_vector(1 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END z126_01_wb_pkg;
PACKAGE BODY z126_01_wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.bte <= wbo_0.bte;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
| gpl-3.0 | e97bd3f8052eeedf0887a244e65deb36 | 0.497541 | 3.979175 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/valid_be.vhd | 3 | 9,947 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: valid_be.vhd
-- Version: v1.00a
-- Description: Determines valid OPB access for memory devices
--
-------------------------------------------------------------------------------
-- Structure:
--
-- valid_be.vhd
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 09/21/01 -- First version
-- ^^^^^^
-- First version of valid_be created from BLT's file, valid_access. Made
-- modifications to support a target data bus width and a host data bus
-- width.
-- ~~~~~~
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity valid_be is
generic (
C_HOST_DW : integer range 8 to 256 := 32;
C_TARGET_DW : integer range 8 to 32 := 32
);
port (
OPB_BE_Reg : in std_logic_vector(0 to C_HOST_DW/8-1);
Valid : out std_logic
);
end entity valid_be;
architecture implementation of valid_be is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant HOST_LOGVAL : integer := log2(C_HOST_DW/8); -- log value for host bus
constant TAR_LOGVAL : integer := log2(C_TARGET_DW/8); -- log value for target bus
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- VALID_ACCESS_PROCESS: this is a general purpose process that returns
-- whether or not a particular byte enable code is valid for a particular host
-- bus size and target bus size. The byte enable bus can be up to 32 bits wide,
-- supporting host bus widths up to 256 bits.
--
-- Example:
-- HOST BUS SIZE(OPB) TARGET BUS SIZE (SRAM) Valid BE
-- ----------------- ---------------------- --------
-- 8 8 '1'
-- 16 8 "01"
-- "10"
-- 16 16 "01"
-- "10"
-- "11"
-- 32 8 "0001"
-- "0010"
-- "0100"
-- "1000"
-- 32 16 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- 32 32 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- "1111"
-------------------------------------------------------------------------------
VALID_ACCESS_PROCESS: process (OPB_BE_Reg) is
variable compare_Val : integer := 0;
begin
Valid <= '0';
for i in 0 to TAR_LOGVAL loop -- loop for bits in target data bus
compare_Val := pwr(2,pwr(2,i))-1;
for j in 0 to pwr(2,HOST_LOGVAL-i) loop
if Conv_integer('0' & OPB_BE_Reg) = compare_Val then Valid <= '1'; end if;
compare_Val := compare_Val*pwr(2,pwr(2,i));
end loop;
end loop;
end process VALID_ACCESS_PROCESS;
end architecture implementation;
| bsd-3-clause | 7cd10f39974c68784ffd406322d49f6f | 0.373681 | 5.591343 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v3_00_a/hdl/vhdl/reset_mir.vhd | 2 | 6,674 | -------------------------------------------------------------------------------
-- $Id: reset_mir.vhd,v 1.1 2003/05/19 22:14:03 anitas Exp $
-------------------------------------------------------------------------------
--reset_mir.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: reset_mir.vhd
--
-- Description: SW reset / MIR register.
--
-------------------------------------------------------------------------------
-- Structure:
-- reset_mir.vhd
--
-------------------------------------------------------------------------------
-- Author: F.Ostler
--
-- History:
-- FLO Aug 16, 2001
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.conv_std_logic_vector;
----------------------------------------------------------------------
entity reset_mir is
Generic (
C_DWIDTH : integer := 32;
C_INCLUDE_SW_RST : integer := 1;
C_INCLUDE_MIR : integer := 0;
C_MIR_MAJOR_VERSION : integer := 0;
C_MIR_MINOR_VERSION : integer := 0;
C_MIR_REVISION : integer := 1;
C_MIR_BLK_ID : integer := 1;
C_MIR_TYPE : integer := 1
);
port (
Reset : in std_logic;
Bus2IP_Clk : in std_logic;
SW_Reset_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Reset : out std_logic;
Reset2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Reset2Bus_Ack : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end reset_mir;
architecture implementation of reset_mir is
--------------------------------------------------------------------------------
-- Value of data LSBs required for a reset-register write to be valid.
--------------------------------------------------------------------------------
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
signal sw_reset : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
begin
----------------------------------------------------------------------------
-- Response signal generation
----------------------------------------------------------------------------
Reset2Bus_Ack <= '1' -- Always acknowledge immediately
when C_INCLUDE_SW_RST = 1 or C_INCLUDE_MIR = 1
else '0';
Reset2Bus_Error <= SW_Reset_WrCE and data_is_non_reset_match
when C_INCLUDE_SW_RST = 1
else '0';
Reset2Bus_Retry <= '0';
Reset2Bus_ToutSup <= '0';
data_is_non_reset_match <=
'0' when Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1) = RESET_MATCH
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
INCLUDE_SW_RESET_GEN : if C_INCLUDE_SW_RST = 1 generate
----------------------------------------------------------------------------
-- ToDo, sw_reset could be implemented by instantiating a LUT, muxcy,
-- orcy and two FFs.
----------------------------------------------------------------------------
sw_rst_cond <= SW_Reset_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Reset = '1') Then
sw_rst_cond_d1 <= '0';
sw_reset <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
sw_reset <= sw_rst_cond or sw_rst_cond_d1;
end if;
end if;
End process;
--
Bus2IP_Reset <= Reset or sw_reset;
end generate;
--
--
EXCLUDE_SW_RESET : if C_INCLUDE_SW_RST = 0 generate
Bus2IP_Reset <= Reset;
end generate;
--------------------------------------------------------------------------------
-- MIR
--------------------------------------------------------------------------------
EXCLUDE_MIR_GEN : if C_INCLUDE_MIR = 0 generate
Reset2Bus_Data <= (others => '0');
end generate;
--
--
INCLUDE_MIR_GEN : if C_INCLUDE_MIR = 1 generate
signal mir_value : std_logic_vector(0 to 31);
begin
----------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics
----------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_MIR_MAJOR_VERSION, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_MIR_MINOR_VERSION, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_MIR_REVISION, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_MIR_BLK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_MIR_TYPE, 8);
Reset2Bus_Data <= mir_value;
end generate;
end implementation;
| bsd-3-clause | 20f5bdb5a467241ecf91b8ccda3bf823 | 0.374888 | 4.574366 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd | 2 | 9,551 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
--
architecture imp of srl_fifo_f is
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity proc_common_v3_00_a.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
| bsd-3-clause | 26f9f1390b7b3d6e61f271102b014dd0 | 0.431892 | 5.048097 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/db_zcpsm/db_zcpsm.vhd | 1 | 1,544 | library ieee;
use ieee.std_logic_1164.all;
entity db_zcpsm is
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end entity;
architecture struct of db_zcpsm is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component dbrom_romonly
port(
addrb : in std_logic_vector(11 downto 0);
clkb : in std_logic;
dob : out std_logic_vector(17 downto 0));
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
begin
u_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rom : dbrom_romonly
port map(
addrb => address,
clkb => clk,
dob => instruction
);
end struct;
| gpl-2.0 | 36bd558aff93b5883fd7c9edfee6ac31 | 0.61658 | 2.767025 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 16,928 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal yAddr, yAddr_next : std_logic_vector(0 to 31);
signal zAddr, zAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal yVal, yVal_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=FUNCTION_EXIT_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, exist) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
index <= index_next;
xAddr <= xAddr_next;
yAddr <= yAddr_next;
zAddr <= zAddr_next;
xVal <= xVal_next;
yVal <= yVal_next;
mutexAddr <= mutexAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
index_next <= index;
xAddr_next <= xAddr;
yAddr_next <= yAddr;
zAddr_next <= zAddr;
xVal_next <= xVal;
yVal_next <= yVal;
count_next <= count;
mutexAddr_next <= mutexAddr ;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of xAddr
xAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, yAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of yAddr
yAddr_next <= toUser_value;
-- Initiate the reading of the fifth variable in the struct, zAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= SETUP_5;
when SETUP_5 =>
-- Read the value of zAddr
zAddr_next <= toUser_value;
-- Initiate the reading of the sixth variable in the struct, mutexAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
-- Read the value of mutexAddr
mutexAddr_next <= toUser_value;
next_state <=WHILE_LOOP_1;
new_request <= '0';
when WHILE_LOOP_1 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_2;
when WHILE_LOOP_2 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_3;
next_state <= WAIT_STATE;
when WHILE_LOOP_3 =>
-- We now have a lock on index, initiate the read on index
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4;
when WHILE_LOOP_4 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000004";
thrd2intrfc_value <= toUser_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4a;
when WHILE_LOOP_4a =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_5;
when WHILE_LOOP_5 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_6;
next_state <= WAIT_STATE;
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( index < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
new_request <= '0';
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
-- Initiate the read of the Y matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= yAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_8;
when WHILE_LOOP_8 =>
yVal_next <= ToUser_value;
next_state <= WHILE_LOOP_9;
new_request <= '0';
when WHILE_LOOP_9 =>
-- Initiate the writing of the Z matrix
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= zAddr + (index(2 to 31) & "00");
thrd2intrfc_value <= xVal + yVal;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_1;
-- Increment count
count_next <= count + x"00000001";
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= timer;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b8ac4787c45d1eeceaf6bc6835a20904 | 0.573724 | 3.843778 | false | false | false | false |
iocoder/graduation | hardware/vga/vgaseq.vhd | 1 | 4,125 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
Color : out STD_LOGIC_VECTOR ( 3 downto 0) := "0000");
end vgaseq;
architecture Dataflow of vgaseq is
signal row_base_i : integer range 0 to 10240;
signal row_indx : integer range 0 to 10240;
signal row : integer range 0 to 10240;
signal col : integer range 0 to 10240;
signal addr : integer range 0 to 10240;
signal fg : std_logic_vector (3 downto 0);
signal bg : std_logic_vector (3 downto 0);
signal tcolor : std_logic_vector (3 downto 0);
signal xcolor : std_logic_vector (3 downto 0);
signal font_index : integer range 0 to 255;
signal font_row : integer range 0 to 15;
signal font_addr : integer range 0 to 4095;
signal font_bit : integer range 0 to 15;
signal fg_or_bg : STD_LOGIC;
signal cursor_vis : boolean := true;
signal cursor_ctr : integer range 0 to 20000000 := 0;
begin
-- character place on screen:
row_base_i <= conv_integer(unsigned(ROW_BASE));
row_indx <= conv_integer(unsigned(Y))/16; -- row = y/16;
row <= row_base_i + row_indx when row_base_i + row_indx < 25 else
row_base_i + row_indx - 25;
col <= conv_integer(unsigned(X))/8; -- col = x/8;
addr <= row*80+col; -- the address of the character in VRAM0.
-- setup VRAM0 and VRAM1 signals:
VRAM0Read <= SE;
VRAM0Addr <= conv_std_logic_vector( addr, VRAM0Addr'length );
VRAM1Read <= SE;
VRAM1Addr <= conv_std_logic_vector( addr, VRAM1Addr'length );
-- VRAM0Data contains the character, VRAM1Data contains colors
fg(0) <= VRAM1Data(0);
fg(1) <= VRAM1Data(1);
fg(2) <= VRAM1Data(2);
fg(3) <= VRAM1Data(3);
bg(0) <= VRAM1Data(4);
bg(1) <= VRAM1Data(5);
bg(2) <= VRAM1Data(6);
bg(3) <= VRAM1Data(7);
-- Font parameters:
font_index <= conv_integer(unsigned(VRAM0Data));
font_row <= conv_integer(unsigned(Y)) mod 16;
font_addr <= font_index*8+font_row/2;
-- Setup VRAM2 signals:
VRAM2Read <= SE when (conv_integer(unsigned(Y)) mod 2) = 0 else '0';
VRAM3Read <= SE when (conv_integer(unsigned(Y)) mod 2) = 1 else '0';
VRAM2Addr <= conv_std_logic_vector(font_addr, VRAM2Addr'length);
VRAM3Addr <= conv_std_logic_vector(font_addr, VRAM3Addr'length);
-- VRAM2Data contains a font row.
font_bit <= (8-(conv_integer(unsigned(X)) mod 8)) when B9='0' else 0;
fg_or_bg <= VRAM2Data(font_bit) or VRAM3Data(font_bit);
-- select color:
with fg_or_bg select tcolor <= fg when '1',
bg when others;
-- apply cursor
xcolor <= fg when (row_indx = conv_integer(cursor_row) and
col = conv_integer(cursor_col) and
cursor_vis and
font_row > 13) else tcolor;
-- fetch color and update cursor counter
process(CLK)
begin
if (CLK='1' and CLK'event) then
color <= xcolor;
if (cursor_ctr = 14000000) then
cursor_ctr <= 0;
cursor_vis <= NOT cursor_vis;
else
cursor_ctr <= cursor_ctr + 1;
end if;
end if;
end process;
end Dataflow;
| gpl-3.0 | 1eda574bfd3dfef9200e63d4aadadf9c | 0.607758 | 3.139269 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_matrixAdd.vhd | 2 | 16,456 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal yAddr, yAddr_next : std_logic_vector(0 to 31);
signal zAddr, zAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal yVal, yVal_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
index <= index_next;
xAddr <= xAddr_next;
yAddr <= yAddr_next;
zAddr <= zAddr_next;
xVal <= xVal_next;
yVal <= yVal_next;
mutexAddr <= mutexAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
index_next <= index;
xAddr_next <= xAddr;
yAddr_next <= yAddr;
zAddr_next <= zAddr;
xVal_next <= xVal;
yVal_next <= yVal;
mutexAddr_next <= mutexAddr;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of xAddr
xAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, yAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of yAddr
yAddr_next <= toUser_value;
-- Initiate the reading of the fifth variable in the struct, zAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= SETUP_5;
when SETUP_5 =>
-- Read the value of zAddr
zAddr_next <= toUser_value;
-- Initiate the reading of the sixth variable in the struct, mutexAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
-- Read the value of mutexAddr
mutexAddr_next <= toUser_value;
next_state <= WHILE_LOOP_1;
when WHILE_LOOP_1 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_2;
when WHILE_LOOP_2 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_TRYLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_3;
next_state <= WAIT_STATE;
when WHILE_LOOP_3 =>
-- We now have a lock on index, initiate the read on index
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4;
when WHILE_LOOP_4 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000004";
thrd2intrfc_value <= toUser_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_4a;
when WHILE_LOOP_4a =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_5;
when WHILE_LOOP_5 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_WHILE_LOOP_6;
next_state <= WAIT_STATE;
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( index < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
-- Initiate the read of the Y matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= yAddr + (index(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_8;
when WHILE_LOOP_8 =>
yVal_next <= ToUser_value;
next_state <= WHILE_LOOP_9;
when WHILE_LOOP_9 =>
-- Initiate the writing of the Z matrix
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= zAddr + (index(2 to 31) & "00");
thrd2intrfc_value <= xVal + yVal;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_1;
-- Increment count
count_next <= count + x"00000001";
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= count;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 33c0bc1d4d20e7cd8ab8a84a51ba6c2f | 0.569944 | 3.953868 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ipif_steer128.vhd | 2 | 44,925 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-- GAB 06-27-2005
-- ~~~~~~
-- Modified to support C_DWIDTH=128
-- Added second Decode_size input to reduce fanout for 128-bit cases
-- Renamed to ipif_steer128.vhd
-- ^^^^^^
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_steer128 is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64, 128
C_SMALLEST : integer := 32; -- 8, 16, 32, 64, 128
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size1 : in std_logic_vector(0 to 2);
Decode_size2 : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_steer128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_steer128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
-- Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_128_8: if C_DWIDTH = 128 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 3);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-1);
case addr_bits is
when "0001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "0010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "1000" =>
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(8);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(64 to 71) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(72 to 79);
Wr_Data_Out(8 to 15) <= Wr_Data_In(72 to 79);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(9);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(72 to 79) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(10);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(80 to 87) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(88 to 95);
Wr_Data_Out(8 to 15) <= Wr_Data_In(88 to 95);
Wr_Data_Out(24 to 31) <= Wr_Data_In(88 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(11);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(88 to 95) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(12);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(96 to 103) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(104 to 111);
Wr_Data_Out(8 to 15) <= Wr_Data_In(104 to 111);
Wr_Data_Out(40 to 47) <= Wr_Data_In(104 to 111);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(13);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(104 to 111) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(14);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(112 to 119) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(120 to 127);
Wr_Data_Out(8 to 15) <= Wr_Data_In(120 to 127);
Wr_Data_Out(24 to 31) <= Wr_Data_In(120 to 127);
Wr_Data_Out(56 to 63) <= Wr_Data_In(120 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(15);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(120 to 127) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_8;
GEN_128_16: if C_DWIDTH = 128 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-2);
case addr_bits is
when "001" => --2
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "010" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "011" => --6
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "100" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "101" => --A
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "110" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "111" => --E
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_16;
GEN_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "10" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "11" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_32;
GEN_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_64;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause | b132ea0a732a2dec5e3c98dfe9b86f8a | 0.414736 | 3.482288 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/switch_fab_4.vhd | 1 | 13,320 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_4.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.6 $
--
-- $Log: switch_fab_4.vhd,v $
-- Revision 1.6 2015/06/15 16:39:59 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.5 2007/08/13 13:58:56 FWombacher
-- added intermediate for output wbi_slave_cyc
--
-- Revision 1.4 2007/08/13 10:14:24 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.3 2005/02/09 14:29:20 mmiehling
-- sw_2 and sw_3 does not work correct
--
-- Revision 1.2 2005/01/18 15:17:29 mmiehling
-- changed muxes to process structure
--
-- Revision 1.1 2004/08/13 15:16:07 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:51 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:06:23 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_4 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
cyc_3 : IN std_logic;
ack_3 : OUT std_logic;
err_3 : OUT std_logic;
wbo_3 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_4;
ARCHITECTURE switch_fab_4_arch OF switch_fab_4 IS
SUBTYPE sw_states IS std_logic_vector(2 DOWNTO 0);
CONSTANT sw_0 : sw_states := "001";
CONSTANT sw_1 : sw_states := "010";
CONSTANT sw_2 : sw_states := "011";
CONSTANT sw_3 : sw_states := "100";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL ack_2_int : std_logic;
SIGNAL ack_3_int : std_logic;
SIGNAL wbi_slave_stb : std_logic;
SIGNAL wbi_slave_cyc_q : std_logic;
BEGIN
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_2.stb;
ELSIF wbo_slave.ack = '1' AND wbo_2.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_3 =>
IF cyc_3 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_3.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_3.stb;
ELSIF wbo_slave.ack = '1' AND wbo_3.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_3.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2, cyc_3)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_2;
END IF;
WHEN sw_3 =>
IF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSE
sw_nxt_state <= sw_3;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat, wbo_2.dat, wbo_3.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN sw_2 => wbi_slave.dat <= wbo_2.dat;
WHEN sw_3 => wbi_slave.dat <= wbo_3.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr, wbo_2.adr, wbo_3.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN sw_2 => wbi_slave.adr <= wbo_2.adr;
WHEN sw_3 => wbi_slave.adr <= wbo_3.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel, wbo_2.sel, wbo_3.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN sw_2 => wbi_slave.sel <= wbo_2.sel;
WHEN sw_3 => wbi_slave.sel <= wbo_3.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we, wbo_2.we, wbo_3.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN sw_2 => wbi_slave.we <= wbo_2.we;
WHEN sw_3 => wbi_slave.we <= wbo_3.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti, wbo_2.cti, wbo_3.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN sw_2 => wbi_slave.cti <= wbo_2.cti;
WHEN sw_3 => wbi_slave.cti <= wbo_3.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga, wbo_2.tga, wbo_3.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN sw_2 => wbi_slave.tga <= wbo_2.tga;
WHEN sw_3 => wbi_slave.tga <= wbo_3.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc_q <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') OR (sw_state = sw_2 AND cyc_2 = '1') OR (sw_state = sw_3 AND cyc_3 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_3 <= '1' WHEN sw_state = sw_3 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_3 <= '1' WHEN sw_state = sw_3 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
wbi_slave_cyc <= wbi_slave_cyc_q;
---------------------------------------------------------------------
END switch_fab_4_arch;
| gpl-3.0 | 60b4b8b7d2888a202017150610ab5ba0 | 0.446321 | 3.485998 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/async_fifo.vhd | 2 | 22,005 | -------------------------------------------------------------------------------
-- $Id: async_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- Async_FIFO.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: Async_FIFO.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Async_FIFO.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- goran 2003-10-27 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
entity Async_FIFO is
generic (
WordSize : Integer := 8;
MemSize : Integer := 16;
Protect : Boolean := False
);
port (
Reset : in Std_Logic;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic
);
end Async_FIFO;
architecture VHDL_RTL of ASync_FIFO is
-----------------------------------------------------------------------------
-- A function which tries to calculate the best Mem_Size and by that the best
-- counting scheme
-----------------------------------------------------------------------------
function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
begin -- Calculate_Right_Mem_Size
case Mem_Size is
when 0 to 3 =>
assert false report "To small FIFO" severity failure;
return 0;
when 4 to 16 => return 16;
when 17 to 32 => return 32;
when 33 to 64 => return 64;
when 65 to 128 =>
-- Do not yet need to check if to use the up/down counting scheme since
-- there is not true 7-bit counter implemented yet
return ((MemSize+15)/16)*16;
when others =>
assert false
report "Unsupported FIFO Depth (Not yet implemented)"
severity failure;
return 0;
end case;
end Calculate_Right_Mem_Size;
-----------------------------------------------------------------------------
-- Create a resolved Boolean type (rboolean)
-----------------------------------------------------------------------------
-- Create a Boolean array type
type boolean_array is array (natural range <>) of boolean;
-- Function for resolved boolean
-- If any boolean in the array is false, then the result is false
function resolve_boolean( values: in boolean_array ) return boolean is
variable result: boolean := TRUE;
begin
if (values'length = 1) then
result := values(values'low);
else
-- coverage off
for index in values'range loop
if values(index) = FALSE then
result := FALSE;
end if;
end loop;
-- coverage on
end if;
return result;
end function resolve_boolean;
subtype rboolean is resolve_boolean boolean;
-- Convert the FIFO memsize to memsizes in steps of 16
constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
-- component Gen_DpRAM
-- generic (
-- Use_Muxes : Boolean := False;
-- Mem_Size : Integer := 36;
-- Addr_Size : Integer := 6;
-- Data_Size : Integer := 16
-- );
-- port (
-- Reset : in Std_Logic;
-- -- Read/Write port 1
-- Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
-- WrClk : in Std_Logic;
-- WE : in Std_Logic;
-- DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
-- DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
-- -- Read port 2
-- Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
-- DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
-- );
-- end component;
----------------------------------------------------------------------
-- Returns the vector size needed to represent the X
-- The result is > 0
----------------------------------------------------------------------
function Vec_Size( X : in Natural) return Natural is
variable I : Natural := 1;
begin
while (2**I) < X loop
I := I + 1;
end loop;
return I;
end function Vec_Size;
-- Declare the types and constant counting schemes
subtype Count_Word is Std_Logic_Vector(3 downto 0);
type Count_Array_Type is array (integer range <>) of Count_Word;
-- Even if there is four bits for the Cnt8, the fourth bit will never be used
constant Cnt8 : Count_Array_Type(0 to 7) := ( "0000","0001","0011","0010",
"0110","0111","0101","0100");
constant Cnt10 : Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
"0011","0010","0110","0111",
"0101","0100" );
constant Cnt12 : Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
"1010","0010","0011","0001",
"0101","0111","0110","0100" );
constant Cnt14 : Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
"1001","1011","1010","0010",
"0011","0001","0101","0111",
"0110","0100");
constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
"0110","0100","0101","0111",
"1111","1110","1100","1101",
"1001","1011","1010","1000");
-----------------------------------------------------------------------------
-- A function that do all the boolean equations for a counting scheme
-- given as a parameter
-- The synthesis tool will unroll the loops and then do the boolean equation
-- minimization (hopefully the optimimal).
-- At present it only handles counting scheme with 4 bits due to the
-- Count_Array_Type definition
-----------------------------------------------------------------------------
function Gen_Counter(Count_Scheme : in Count_Array_Type;
Up : in Boolean;
Count : in Std_Logic_Vector)
return Std_Logic_Vector is
variable Temp : Std_Logic;
variable L : Integer range Count_Scheme'Range;
variable Q : Std_Logic_Vector(Count'Length-1 downto 0);
variable Q_Temp : Std_Logic_Vector(Count'Length-1 downto 0);
begin -- Gen_Counter
Q := Count;
for G in Q'Range loop
Q_Temp(G) := '0';
for I in Count_Scheme'range loop
if Count_Scheme(I)(G) = '1' then
if Up then
L := I - 1;
else
if I /= Count_Scheme'High then
L := I + 1;
else
L := Count_Scheme'Low;
end if;
end if;
Temp := '1';
for J in Q'Range loop
if Count_Scheme(L)(J) = '1' then
Temp := Temp and Q(J);
else
Temp := Temp and not Q(J);
end if;
end loop;
Q_Temp(G) := Q_Temp(G) or Temp;
end if;
end loop; -- I
end loop; -- G
return Q_Temp;
end Gen_Counter;
----------------------------------------------------------------------
-- Generate the Address counter for FIFO handling
-- generates different counters depending of the counter size
----------------------------------------------------------------------
Procedure FIFO_Count( Count : inout Std_Logic_Vector;
Incr : in Boolean;
Up : inout Boolean;
Change : inout Boolean) is
variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
begin
if True_Mem_Size = 16 then
if Incr then
Res := Gen_Counter(Cnt16,True,Cnt);
end if;
elsif True_Mem_Size = 32 then
if Incr then
if not Change and
(( (Cnt(2 downto 0) = "100") and Up) or
( (Cnt(2 downto 0) = "000") and not Up)) then
Res(4) := Cnt(3);
Res(3) := not Cnt(4);
Res(2 downto 0) := Cnt(2 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(4 downto 3) := Cnt(4 downto 3);
Res(2 downto 0) := Gen_Counter(Cnt8,Up,Cnt(2 downto 0));
end if;
end if;
elsif True_Mem_Size = 64 then
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
Res(5) := Cnt(4);
Res(4) := not Cnt(5);
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(5 downto 4) := Cnt(5 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 128 then
-- Do a 3-bit grey counter + a 4-bit grey counter
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(6 downto 4) := Cnt(6 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
end if;
end if;
else
assert false
report "To BIG FIFO (not yet supported)"
severity failure;
end if;
Count := Res;
end FIFO_Count;
Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector;
Incr : in Boolean;
Up : inout Boolean;
Change : inout Boolean) is
variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
begin
FIFO_Count(Res,Incr,Up,Change);
Count <= Res;
end FIFO_Counter;
constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
-- The read and write pointers
subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
signal Write_Ptr : Pointer_Type;
signal Read_Ptr : Pointer_Type;
signal Write_Addr : Pointer_Type;
signal Read_Addr : Pointer_Type;
signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
signal Dir_Latched : Boolean;
signal Direction : Boolean;
signal Equal : Boolean;
signal Full_I : Boolean;
signal Empty_I : Boolean;
signal Full_Out : Boolean;
signal Empty_Out : Boolean;
signal Read : rboolean;
signal Write : rboolean;
-----------------------------------------------------------------------------
-- Implement the RAM with pure RTL
-----------------------------------------------------------------------------
type RAM_TYPE is array (natural range 0 to MemSize-1) of std_logic_vector(WordSize-1 downto 0);
signal Memory : RAM_TYPE := (others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- Change the Read and Write pointer to get the FIFO addresses
-- This will get the four lowest bits from the Read/Write pointers to be the
-- higest bits in FIFO addresses. This assures that when the FIFO depth is
-- not a power of 2, that the FIFO addresses is within the FIFO depth range
-----------------------------------------------------------------------------
Do_FIFO_Addr : process (Write_Ptr, Read_Ptr)
begin -- process Do_FIFO_Addr
Write_Addr(Write_Addr'High downto Write_Addr'High-3) <=
Write_Ptr(3 downto 0);
if Write_Ptr'Length > 4 then
Write_Addr(Write_Addr'High-4 downto Write_Addr'Low) <=
Write_Ptr(Write_Ptr'High downto 4);
end if;
Read_Addr(Read_Addr'High downto Read_Addr'High-3) <=
Read_Ptr(3 downto 0);
if Read_Ptr'Length > 4 then
Read_Addr(Read_Addr'High-4 downto Read_Addr'Low) <=
Read_Ptr(Read_Ptr'High downto 4);
end if;
end process Do_FIFO_Addr;
----------------------------------------------------------------------
-- Instansiate the Dual Port memory
----------------------------------------------------------------------
Write_To_Memory: process (WrClk) is
begin -- process Write_To_Memory
if WrClk'event and WrClk = '1' then -- rising clock edge
if WE = '1' then
Memory(to_integer(unsigned(Write_Addr))) <= DataIn;
end if;
end if;
end process Write_To_Memory;
DataOut1 <= Memory(to_integer(unsigned(Write_Addr)));
DataOut <= Memory(to_integer(unsigned(Read_Addr)));
-- FIFO_MEM : Gen_DpRAM
-- generic map(
-- Use_Muxes => true,
-- Mem_Size => MemSize,
-- Addr_Size => Log2_Mem_Size,
-- Data_Size => WordSize
-- )
-- port map (
-- Reset => Reset,
-- Addr1 => Write_Addr,
-- WrClk => WrClk,
-- WE => WE,
-- DataIn => DataIn,
-- DataOut1 => DataOut1,
-- Addr2 => Read_Addr,
-- DataOut2 => DataOut
-- );
Protect_FIFO : if Protect generate
Read <= (Rd = '1') and not Empty_Out;
Write <= (We = '1') and not Full_Out;
end generate Protect_FIFO;
Non_Protect_FIFO : if not Protect generate
Read <= (Rd = '1');
Write <= (We = '1');
end generate Non_Protect_FIFO;
----------------------------------------------------------------------
-- Read Pointer
----------------------------------------------------------------------
Read_Ptr_Counter : process(Reset,RdClk)
variable Up : Boolean;
variable Change : Boolean;
begin
if (Reset = '1') then
Read_Ptr <= (others => '0');
Up := True;
Change := False;
elsif RdClk'Event and RdClk = '1' then
FIFO_Counter(Read_Ptr,Read,Up,Change);
end if;
end process Read_Ptr_Counter;
----------------------------------------------------------------------
-- Write Pointer
----------------------------------------------------------------------
Write_Ptr_Counter : process(Reset,WrClk)
variable Up : Boolean;
variable Change : Boolean;
begin
if (Reset = '1') then
Write_Ptr <= (others => '0');
Up := True;
Change := False;
elsif WrClk'Event and WrClk = '1' then
FIFO_Counter(Write_Ptr,Write,Up,Change);
end if;
end process Write_Ptr_Counter;
----------------------------------------------------------------------
-- Flag handling
----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Dir_Latched is false after reset and then true after the first write
---------------------------------------------------------------------------
Direction_Latch : process(Reset,WE,WrClk)
begin
if (Reset = '1') then
Dir_Latched <= False;
elsif WrClk'Event and WrClk = '1' then
Dir_Latched <= Dir_Latched or (WE = '1');
end if;
end process Direction_Latch;
-----------------------------------------------------------------------------
-- Trying to see if the read pointer is catching up the write pointer or
-- vice verse
-- The top two bits of the pointers always counts as follows
-- 00
-- 01
-- 11
-- 10
-- 00
-- ..
-- So if read pointer is one step behind the write pointer => Reset = True
-- And if write pointer is one step behind the read pointer => Set = True
-----------------------------------------------------------------------------
Direction_Proc : process(Read_Ptr, Write_Ptr, Dir_Latched, Direction)
variable Set : Boolean;
variable Clear : Boolean;
variable Read_MSB : Std_Logic_Vector(1 downto 0);
variable Write_MSB : Std_Logic_Vector(1 downto 0);
begin
Read_MSB := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1);
Write_MSB := Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1);
if (Read_MSB = "00" and Write_MSB = "01") or
(Read_MSB = "01" and Write_MSB = "11") or
(Read_MSB = "11" and Write_MSB = "10") or
(Read_MSB = "10" and Write_MSB = "00") then
Clear := True;
else
Clear := False;
end if;
if (Write_MSB = "00" and Read_MSB = "01") or
(Write_MSB = "01" and Read_MSB = "11") or
(Write_MSB = "11" and Read_MSB = "10") or
(Write_MSB = "10" and Read_MSB = "00") then
Set := True;
else
Set := False;
end if;
Direction <= not ((not Dir_Latched) or Clear or not(Set or Direction));
end process Direction_Proc;
Equal <= (Read_Ptr = Write_Ptr);
Full_I <= Equal and Direction;
Empty_I <= Equal and not Direction;
-- Allow Empty to go active directly since the change is due to a read
-- which means that the Empty_I is synchronized with RdClk.
-- But is only allow to go inactive when RdClk is High since the transaction
-- is due to a Write and Empty_I is NOT synchronized with RdClk.
-- By this way the Empty is not changed state just before rising edge of RdClk
Empty_DFF : process(Empty_I,RdClk)
begin
if Empty_I then
Empty_Out <= True;
elsif RdClk'Event and RdClk = '1' then
Empty_Out <= Empty_I;
end if;
end process Empty_DFF;
Exists <= '0' when Empty_Out else '1';
-- See above but for Full and WrClk
Full_DFF : process(Full_I,WrClk)
begin
if Full_I then
Full_Out <= True;
elsif WrClk'Event and WrClk = '1' then
Full_Out <= Full_I;
end if;
end process Full_DFF;
Full <= '1' when Full_Out else '0';
end VHDL_RTL;
| bsd-3-clause | 917bf7f44a582604d32e256314345283 | 0.502795 | 4.299531 | false | false | false | false |
QuickJack/logi-hard | hdl/utils/up_down_counter.vhd | 2 | 1,848 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity up_down_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en, load : in STD_LOGIC;
up_downn : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end up_down_counter;
architecture Behavioral of up_down_counter is
signal Qp : std_logic_vector(NBIT - 1 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
Qp <= (others => '0') ;
elsif load = '1' then
Qp <= E ;
elsif en = '1' then
if up_downn = '1' then
Qp <= Qp + 1;
else
Qp <= Qp - 1;
end if ;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Qp;
end Behavioral; | lgpl-3.0 | 8f7cb706dadfcab79fb03ecd77cb5653 | 0.550866 | 3.533461 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/devl/bfmsim/pcores/plb_hwt_tb_v1_00_a/simhdl/vhdl/plb_hwt_tb.vhd | 2 | 19,307 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library fsl_v20_v2_10_a;
use fsl_v20_v2_10_a.all;
entity plb_hwt_tb is
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_MANAG_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MUTEX_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_CONDV_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
-- PLB bus interface, do not add or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_hwt_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_hwt_tb is
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant INTERRUPT : integer := 31;
------------------------------------------
-- FSL Link Signals To HWTI
------------------------------------------
signal FSL_M_Data : std_logic_vector(0 to 63);
signal FSL_M_Control : std_logic;
signal FSL_M_Write : std_logic;
signal FSL_M_Full : std_logic;
signal FSL_S_Data : std_logic_vector(0 to 63);
signal FSL_S_Control : std_logic;
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
------------------------------------------
-- Signals for the HWTUL
------------------------------------------
signal tid : std_logic_vector(0 to 7);
signal arg : std_logic_vector(0 to 31);
begin
------------------------------------------
-- Instance of the PLB HWTI
------------------------------------------
hwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_MANAG_BASE => C_MANAG_BASEADDR,
C_SCHED_BASE => C_SCHED_BASEADDR,
C_MUTEX_BASE => C_MUTEX_BASEADDR,
C_CONDV_BASE => C_CONDV_BASEADDR,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
H2ULOW_S_READ => FSL_S_READ,
H2ULOW_S_DATA => FSL_S_DATA(32 to 63),
H2ULOW_S_CONTROL => FSL_S_CONTROL,
H2ULOW_S_EXISTS => FSL_S_EXISTS,
H2UHIGH_S_READ => FSL_S_READ,
H2UHIGH_S_DATA => FSL_S_DATA(0 to 31),
H2UHIGH_S_CONTROL => open,
H2UHIGH_S_EXISTS => open,
U2HLOW_M_WRITE => FSL_M_WRITE,
U2HLOW_M_DATA => FSL_M_DATA(32 to 63),
U2HLOW_M_CONTROL => FSL_M_CONTROL,
U2HLOW_M_FULL => FSL_M_FULL,
U2HHIGH_M_WRITE => FSL_M_WRITE,
U2HHIGH_M_DATA => FSL_M_DATA(0 to 31),
U2HHIGH_M_CONTROL => FSL_M_CONTROL,
U2HHIGH_M_FULL => open,
-- MAP USER PORTS ABOVE THIS LINE ------------------
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize
);
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
procedure reset is
begin
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
FSL_S_READ <= '0';
wait for 20 ns;
wait until falling_edge(PLB_Rst);
wait for 20 ns;
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
end procedure;
procedure dostart is
begin
wait until rising_edge(PLB_Clk);
SYNCH_OUT(START) <= '1';
wait until rising_edge(PLB_Clk);
SYNCH_OUT(START) <= '0';
end procedure;
procedure dostop is
begin
wait until rising_edge(SYNCH_IN(STOP));
wait for 1 us;
end procedure;
procedure dowake(signal tid : out std_logic_vector(0 to 7);
signal arg : out std_logic_vector(0 to 31)) is
begin
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
tid <= FSL_S_DATA(24 to 31);
arg <= FSL_S_DATA(32 to 63);
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
procedure dohwti(fsl : std_logic_vector(0 to 63)) is
begin
wait until rising_edge(PLB_Clk) and FSL_M_FULL='0';
FSL_M_WRITE <= '1';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= fsl;
wait until rising_edge(PLB_Clk);
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
end procedure;
procedure waitres is
begin
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
procedure mtx_lock(mtx : in integer) is
begin
dohwti( hwti_mtx_lock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_unlock(mtx : in integer) is
begin
dohwti( hwti_mtx_unlock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_trylock(mtx : in integer) is
begin
dohwti( hwti_mtx_trylock(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_owner(mtx : in integer) is
begin
dohwti( hwti_mtx_owner(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_kind(mtx : in integer) is
begin
dohwti( hwti_mtx_kind(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure mtx_count(mtx : in integer) is
begin
dohwti( hwti_mtx_count(conv_std_logic_vector(mtx,6)) );
end procedure;
procedure cdv_owner(cdv : in integer) is
begin
dohwti( hwti_cdv_owner(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_wait(cdv : in integer) is
begin
dohwti( hwti_cdv_wait(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_signal(cdv : in integer) is
begin
dohwti( hwti_cdv_signal(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure cdv_broadcast(cdv : in integer) is
begin
dohwti( hwti_cdv_broadcast(conv_std_logic_vector(cdv,6)) );
end procedure;
procedure man_exit(res : in std_logic_vector(0 to 31)) is
begin
dohwti( hwti_thr_exit(res) );
end procedure;
procedure mem_read(addr : std_logic_vector(0 to 31);
byte : integer) is
begin
dohwti( hwti_mem_read(addr,conv_std_logic_vector(byte,24)) );
end procedure;
procedure mem_write(addr : std_logic_vector(0 to 31);
byte : integer) is
begin
dohwti( hwti_mem_write(addr,conv_std_logic_vector(byte,24)) );
end procedure;
procedure mem_fill( byte : integer ) is
begin
for i in 0 to (byte/8)-1 loop
wait until rising_edge(PLB_Clk) and FSL_M_FULL='0';
FSL_M_WRITE <= '1';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= conv_std_logic_vector(2*i,32) &
conv_std_logic_vector(2*i+1,32);
end loop;
wait until rising_edge(PLB_Clk);
FSL_M_WRITE <= '0';
FSL_M_CONTROL <= '0';
FSL_M_DATA <= (others => '0');
end procedure;
procedure mem_drain( byte : integer ) is
begin
for i in 0 to (byte/8)-1 loop
FSL_S_READ <= '1';
wait until rising_edge(PLB_Clk) and FSL_S_EXISTS='1';
end loop;
wait until rising_edge(PLB_Clk);
FSL_S_READ <= '0';
end procedure;
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
------------------------------------------
-- Reset the System
------------------------------------------
reset;
------------------------------------------
-- Setup the memory values
------------------------------------------
assert FALSE report "*** Memory Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** Memory Setup Finished ***" severity NOTE;
------------------------------------------
-- Setup the Hthreads System
------------------------------------------
assert FALSE report "*** System Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** System Setup Finished ***" severity NOTE;
------------------------------------------
-- Setup the Hardware Thread
------------------------------------------
assert FALSE report "*** HWT Setup Starting ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** HWT Setup Finished ***" severity NOTE;
------------------------------------------
-- Wait until we are woken up by the system
------------------------------------------
dowake(tid,arg);
------------------------------------------
-- Attempt to mutex operations
------------------------------------------
assert FALSE report "*** Mutex Operations Starting ***" severity NOTE;
mtx_lock(0); waitres;
mtx_lock(1); waitres;
mtx_lock(2); waitres;
mtx_trylock(2); waitres;
mtx_unlock(2); waitres;
mtx_owner(0); waitres;
mtx_kind(0); waitres;
mtx_count(0); waitres;
assert FALSE report "*** Mutex Operations Finished ***" severity NOTE;
------------------------------------------
-- Attempt condition variable operations
------------------------------------------
assert FALSE report "*** Condition Variables Starting ***" severity NOTE;
cdv_wait(0); wait for 1 us; dostart; dostop; waitres;
cdv_wait(1); wait for 1 us; dostart; dostop; waitres;
cdv_signal(0); waitres;
cdv_signal(1); waitres;
cdv_broadcast(0); waitres;
cdv_broadcast(1); waitres;
assert FALSE report "*** Condition Variables Finished ***" severity NOTE;
------------------------------------------
-- Attempt burst memory read and write
------------------------------------------
mem_read(x"10000000", 256); mem_drain(256);
mem_write(x"20000000", 256); mem_fill(256);
------------------------------------------
-- End the test
------------------------------------------
man_exit(x"CAFEBABE");
wait for 2000 ns;
------------------------------------------
-- Setup the Hthreads System
------------------------------------------
assert FALSE report "*** Starting Results Reading ***" severity NOTE;
dostart;
dostop;
assert FALSE report "*** Finished Results Reading ***" severity NOTE;
wait;
end process TEST_PROCESS;
end architecture testbench;
| bsd-3-clause | f4839877ff963013aad41a16be564a5c | 0.467343 | 3.961223 | false | false | false | false |
michaelmiehling/A25_VME | Source/sram.vhd | 1 | 9,186 | --------------------------------------------------------------------------------
-- Title : external SRAM Interface
-- Project : A15
--------------------------------------------------------------------------------
-- File : sram.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 24/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- Interface controller to asynchronous RAM with 1 MB.
-- Longword accesses will be performed by two SRAM accesses.
--------------------------------------------------------------------------------
-- Hierarchy:
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: sram.vhd,v $
-- Revision 1.1 2012/03/29 10:21:15 MMiehling
-- Initial Revision
--
-- Revision 1.4 2004/07/27 17:15:30 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.3 2003/12/01 10:03:31 MMiehling
-- now whishbone bus
--
-- Revision 1.2 2003/06/24 13:46:54 MMiehling
-- removed burst
--
-- Revision 1.1 2003/04/01 13:04:31 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY sram IS
PORT (
clk66 : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- local bus
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic; -- high active write enable
sel_i : IN std_logic_vector(3 DOWNTO 0); -- high active byte enables
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(31 DOWNTO 0);
dat_i : IN std_logic_vector(31 DOWNTO 0);
adr_i : IN std_logic_vector(19 DOWNTO 0);
-- pins to sram
bwn : OUT std_logic; -- global byte write enable:
bwan : OUT std_logic; -- byte a write enable:
bwbn : OUT std_logic; -- byte b write enable:
adscn : OUT std_logic; -- Synchronous Address Status Controller: .
roen : OUT std_logic; -- data output enable of sram data signals
ra : OUT std_logic_vector(18 DOWNTO 0); -- address lines:
rd_in : IN std_logic_vector(15 DOWNTO 0); -- fpga data input vector
rd_out : OUT std_logic_vector(15 DOWNTO 0); -- fpga data output vector
rd_oe : OUT std_logic -- fpga data output enable (if '1', rd_out should be driven to sram)
);
END sram;
ARCHITECTURE sram_arch OF sram IS
TYPE sram_states IS (sram_idle, sram_wait, sram_low, sram_high, sram_read_end);
SIGNAL sram_state : sram_states;
SIGNAL ra_1 : std_logic;
SIGNAL ra_int : std_logic_vector(19 DOWNTO 2);
SIGNAL roen_int : std_logic;
SIGNAL we_i_q : std_logic;
BEGIN
ra <= ra_int & ra_1;
roen <= roen_int;
--oe : PROCESS (rd_oe, rd_out, rd)
-- BEGIN
-- IF rd_oe = '1' THEN
-- rd <= rd_out AFTER 3 ns;
-- rd_in <= rd;
-- ELSE
-- rd <= (OTHERS => 'Z');
-- rd_in <= rd AFTER 3 ns;
-- END IF;
-- END PROCESS oe;
reg : PROCESS (clk66, rst)
BEGIN
IF rst = '1' THEN
ra_int <= (OTHERS => '0');
dat_o <= (OTHERS => '0');
rd_out <= (OTHERS => '0');
we_i_q <= '0';
ELSIF clk66'EVENT AND clk66 = '1' THEN
we_i_q <= we_i;
IF ra_1 = '1' THEN -- low byte
rd_out <= dat_i(15 DOWNTO 0);
ELSE -- high byte
rd_out <= dat_i(31 DOWNTO 16);
END IF;
IF ra_1 = '1' AND roen_int = '0' THEN -- low byte
dat_o(15 DOWNTO 0) <= rd_in;
ELSIF ra_1 = '0' AND roen_int = '0' THEN -- high_byte
dat_o(31 DOWNTO 16) <= rd_in;
END IF;
ra_int <= adr_i(19 DOWNTO 2);
END IF;
END PROCESS reg;
sram_fsm : PROCESS (clk66, rst)
BEGIN
IF rst = '1' THEN
ack_o <= '0';
sram_state <= sram_idle;
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
ELSIF clk66'EVENT AND clk66 = '1' THEN
CASE sram_state IS
WHEN sram_idle =>
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
IF stb_i = '1' AND cyc_i = '1' THEN
sram_state <= sram_wait;
IF we_i = '1' THEN -- write
adscn <= '1';
rd_oe <= '1';
ELSE -- read
adscn <= '0';
rd_oe <= '0';
END IF;
ra_1 <= '1';
ELSE
sram_state <= sram_idle;
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
END IF;
WHEN sram_wait =>
ra_1 <= '0';
IF stb_i = '1' AND cyc_i = '1' THEN
sram_state <= sram_low;
adscn <= '0';
IF we_i = '1' THEN -- write
ack_o <= '1';
bwn <= '0';
bwan <= NOT sel_i(0);
bwbn <= NOT sel_i(1);
rd_oe <= '1';
roen_int <= '1';
ELSE -- read
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '0';
END IF;
ELSE
sram_state <= sram_idle;
ack_o <= '0';
adscn <= '1';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '1';
END IF;
WHEN sram_low =>
sram_state <= sram_high;
ra_1 <= '1';
IF we_i = '1' THEN -- write
ack_o <= '0';
bwn <= '0';
bwan <= NOT sel_i(2);
bwbn <= NOT sel_i(3);
rd_oe <= '1';
roen_int <= '1';
adscn <= '0';
ELSE -- read
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '0';
adscn <= '1';
END IF;
WHEN sram_high =>
sram_state <= sram_read_end;
adscn <= '1';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
ra_1 <= '0';
IF we_i_q = '1' THEN -- write
ack_o <= '0';
rd_oe <= '1';
roen_int <= '1';
ELSE -- read
ack_o <= '1';
rd_oe <= '0';
roen_int <= '1';
END IF;
WHEN sram_read_end =>
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
sram_state <= sram_idle;
ra_1 <= '0';
adscn <= '1';
rd_oe <= '0';
WHEN OTHERS =>
ack_o <= '0';
sram_state <= sram_idle;
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
END CASE;
END IF;
END PROCESS sram_fsm;
END sram_arch;
| gpl-3.0 | f3778a3e9906a767fdfdda710750ff01 | 0.383736 | 4.071809 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter_top.vhd | 3 | 8,770 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| bsd-3-clause | fa57ebe96f07bb9930d81f1de2a9045f | 0.420296 | 4.125118 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_pkg.vhd | 2 | 49,682 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.3 2003/04/28 20:47:23 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
Type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
Type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
Type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- xst work around!!! Type ARD_NAME_TYPE is array (natural range <>) of string(1 to 32);
--ToDo, at some time when this file is otherwise stable, remove the
-- "xst work around!!!" stuff. The work arounds are permanent, now.
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
-- xst work around!!! function find_ard_name (name_array : ARD_NAME_TYPE;
-- xst work around!!! name : string) return boolean;
-- xst work around!!! function get_name_index (name_array :ARD_NAME_TYPE;
-- xst work around!!! name : string) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
-- xst work around!!! function find_a_dwidth (name_array : ARD_NAME_TYPE;
-- xst work around!!! dwidth_array: INTEGER_ARRAY_TYPE;
-- xst work around!!! name : string;
-- xst work around!!! default : integer) return integer;
function S32 (in_string : string) return string;
-- xst work around!!! function cnt_ipif_blks (name_array : ARD_NAME_TYPE) return integer;
-- xst work around!!! function get_ipif_dbus_index (name_array: ARD_NAME_TYPE;
-- xst work around!!! name : string)
-- xst work around!!! return integer ;
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- Hopefully temporary functions that use an array of integers to identify
-- functions specified in the ARD arrays
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
--/////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- xst debug!!! -- constant declarations of ARD Name array reserved words of IPIF modules
-- xst debug!!! Constant IPIF_WRFIFO_REG : string := "ipif_wrfifo_reg ";
-- xst debug!!! Constant IPIF_WRFIFO_DATA : string := "ipif_wrfifo_data ";
-- xst debug!!! Constant IPIF_RDFIFO_REG : string := "ipif_rdfifo_reg ";
-- xst debug!!! Constant IPIF_RDFIFO_DATA : string := "ipif_rdfifo_data ";
-- xst debug!!! Constant IPIF_RST : string := "ipif_reset ";
-- xst debug!!! Constant IPIF_INTR : string := "ipif_interrupt ";
-- xst debug!!! Constant IPIF_DMA_SG : string := "ipif_dma_sg ";
-- xst debug!!! Constant IPIF_SESR_SEAR : string := "ipif_sear_sesr ";
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- temporary integer aliases of ARD ID (in place of strings)
-- IPIF Module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_EVENT_FIFO : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
--/////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range). There is one property, i.e. one parameter, encoded as
-- an integer at each index of the properties array. There is one properties
-- array for each address range.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 6;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
------------------------------------------------------------------------------ ---
--constant EXCLUDE_DEV_ISC : integer := 0;
-- -- 1 specifies that only the global interrupt
-- -- enable is present in the device interrupt source
-- -- controller and that the only source of interrupts
-- -- in the device is the IP interrupt source controller.
-- -- 0 specifies that the full device interrupt
-- -- source controller structure will be included.
--constant INCLUDE_DEV_PENCODER : integer := 1;
---- -- 1 will include the Device IID in the device interrupt
---- -- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_CHANNELS : integer := 0;
constant INTR_COALESCE : integer := 1;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer := 2;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- Relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer := 3;
-- Gives the unit for used for timing pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ps (1 ms).
-- Relevant only if (INTR_COALESCE = 1).
constant DISALLOW_BURST : integer := 4;
-- 0 allows DMA to initiate burst transfers
-- 1 inhibits DMA initiated burst transfers
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function is used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function find_ard_name
-- xst work around!!! --
-- xst work around!!! -- This function is used to process the array specifying the target function
-- xst work around!!! -- assigned to a Base Address pair address range. The dest_name_array and a
-- xst work around!!! -- string name is input to the function. A boolean is returned reflecting the
-- xst work around!!! -- presence (or not) of a string matching the name input string.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function find_ard_name (name_array : ARD_NAME_TYPE;
-- xst work around!!! name : string) return boolean is
-- xst work around!!!
-- xst work around!!! Variable match : Boolean := false;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!! If (match = true) Then -- match already found so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! else -- compare string characters one by one
-- xst work around!!!
-- xst work around!!! match := equaluseCase(temp_string, name);
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(match);
-- xst work around!!!
-- xst work around!!! end function find_ard_name;
-- optional implementation -----------------------------------------------------------------------------
-- optional implementation -- Function find_ard_name
-- optional implementation --
-- optional implementation -- This function is used to process the array specifying the target function
-- optional implementation -- assigned to a Base Address pair address range. The dest_name_array and a
-- optional implementation -- string name is input to the function. A boolean is returned reflecting the
-- optional implementation -- presence (or not) of a string matching the name input string.
-- optional implementation -----------------------------------------------------------------------------
-- optional implementation function find_ard_name (name_array : ARD_NAME_TYPE;
-- optional implementation name : string) return boolean is
-- optional implementation
-- optional implementation Variable match : Boolean := false;
-- optional implementation Variable temp_string : string(1 to 32);
-- optional implementation
-- optional implementation begin
-- optional implementation
-- optional implementation --for array_index in 0 to name_array'length-1 loop
-- optional implementation for array_index in 0 to name_array'length-1 loop
-- optional implementation
-- optional implementation temp_string := name_array(array_index);
-- optional implementation
-- optional implementation If (match = true) Then -- match already found so do nothing
-- optional implementation
-- optional implementation null;
-- optional implementation
-- optional implementation else -- compare the strings using "=" overload function
-- optional implementation
-- optional implementation If (temp_string = name) Then
-- optional implementation match := true;
-- optional implementation else
-- optional implementation null;
-- optional implementation End if;
-- optional implementation
-- optional implementation End if;
-- optional implementation
-- optional implementation End loop;
-- optional implementation
-- optional implementation return(match);
-- optional implementation
-- optional implementation end function find_ard_name;
-- optional implementation
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function get_name_index
-- xst work around!!! --
-- xst work around!!! -- This function is used to process the array specifying the target function
-- xst work around!!! -- assigned to a Base Address pair address range. The dest_name_array and a
-- xst work around!!! -- string name is input to the function. A integer is returned reflecting the
-- xst work around!!! -- array index of the string matching the name input string. This function
-- xst work around!!! -- should only be called if the compare string is known to exist in the
-- xst work around!!! -- name_array input. This can be detirmined by using the find_ard_name
-- xst work around!!! -- function.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function get_name_index (name_array :ARD_NAME_TYPE;
-- xst work around!!! name : string) return integer is
-- xst work around!!!
-- xst work around!!! Variable match : Boolean := false;
-- xst work around!!! Variable match_index : Integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (match = true) Then -- match already found so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! else -- compare string characters one by one
-- xst work around!!!
-- xst work around!!! match := equaluseCase(temp_string, name);
-- xst work around!!! match_index := array_index;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(match_index);
-- xst work around!!!
-- xst work around!!! end function get_name_index;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function find_a_dwidth
-- xst work around!!! --
-- xst work around!!! -- This function is used to find the data width of a target module. If the
-- xst work around!!! -- target module exists, the data width is extracted from the input dwidth
-- xst work around!!! -- array. If the module is not in the name array, the default input is
-- xst work around!!! -- returned. This function is needed to assign data port size constraints.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function find_a_dwidth (name_array : ARD_NAME_TYPE;
-- xst work around!!! dwidth_array: INTEGER_ARRAY_TYPE;
-- xst work around!!! name : string;
-- xst work around!!! default : integer) return integer is
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! Variable name_present : Boolean := false;
-- xst work around!!! Variable array_index: Integer := 0;
-- xst work around!!! Variable dwidth : Integer := default;
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! name_present := find_ard_name(name_array, name);
-- xst work around!!!
-- xst work around!!! If (name_present) Then
-- xst work around!!! array_index := get_name_index (name_array, name);
-- xst work around!!! dwidth := dwidth_array(array_index);
-- xst work around!!! else
-- xst work around!!! null; -- use default input
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! Return (dwidth);
-- xst work around!!!
-- xst work around!!! end function find_a_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-- xst work around!!! function cnt_ipif_blks (name_array : ARD_NAME_TYPE) return integer is
-- xst work around!!!
-- xst work around!!! Variable blk_count : integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (temp_string = IPIF_WRFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RDFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RST or
-- xst work around!!! temp_string = IPIF_INTR or
-- xst work around!!! temp_string = IPIF_DMA_SG or
-- xst work around!!! temp_string = IPIF_SESR_SEAR
-- xst work around!!! ) Then -- IPIF block found
-- xst work around!!!
-- xst work around!!! blk_count := blk_count+1;
-- xst work around!!!
-- xst work around!!! else -- go to next loop iteration
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(blk_count);
-- xst work around!!!
-- xst work around!!! end function cnt_ipif_blks;
-- xst work around!!! function get_ipif_dbus_index (name_array: ARD_NAME_TYPE;
-- xst work around!!! name : string)
-- xst work around!!! return integer is
-- xst work around!!!
-- xst work around!!! Variable blk_index : integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!! Variable name_found : Boolean := false;
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (name_found) then
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! elsif (temp_string = name) then
-- xst work around!!!
-- xst work around!!! name_found := true;
-- xst work around!!!
-- xst work around!!! elsif (temp_string = IPIF_WRFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RDFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RST or
-- xst work around!!! temp_string = IPIF_INTR or
-- xst work around!!! temp_string = IPIF_DMA_SG or
-- xst work around!!! temp_string = IPIF_SESR_SEAR
-- xst work around!!! ) Then -- IPIF block found
-- xst work around!!!
-- xst work around!!! blk_index := blk_index+1;
-- xst work around!!!
-- xst work around!!! else -- user block so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(blk_index);
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! end function get_ipif_dbus_index;
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- Hopefully temporary functions
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
-- End of xst debug functions
--/////////////////////////////////////////////////////////////////////////////
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
end package body ipif_pkg;
| bsd-3-clause | 08c9ce2d82f69007a1ed5ec8a216dd74 | 0.498209 | 4.725319 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/counter_bit.vhd | 2 | 8,806 | -------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
| bsd-3-clause | 6f30ea09d62b6c4ea5a94bdd251e9026 | 0.403475 | 5.003409 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_dp_cntl.vhd | 3 | 47,901 | -------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
use opb_ipif_v2_00_h.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
| bsd-3-clause | cd30d79da37b923fb4905a9fc92442e1 | 0.351809 | 5.024229 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/plb_bus_wrapper.vhd | 3 | 14,698 | -------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_00_a;
use plb_v46_v1_00_a.all;
entity plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 31);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 255);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 3);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 255);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end plb_bus_wrapper;
architecture STRUCTURE of plb_bus_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_NUM_CLK_PLB2OPB_REARB : integer;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Bus_Error_Det : out std_logic
);
end component;
begin
plb_bus : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 2,
C_PLBV46_NUM_SLAVES => 2,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 128,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 0,
C_IRQ_ACTIVE => '1',
C_NUM_CLK_PLB2OPB_REARB => 5,
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| bsd-3-clause | ed7b2a81d6ba81d4bc6f5fe11f5a3005 | 0.610763 | 3.031766 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 15,205 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
library plb_hwti_v1_00_a;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstNum -- IP to Bus burst size indicator
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
------------------------------------------------------------------------------
entity user_logic is
generic
(
MTX_BITS : natural := 6;
TID_BITS : natural := 8;
CMD_BITS : natural := 3;
MTX_BASE : std_logic_vector := x"75000000";
CDV_BASE : std_logic_vector := x"74000000";
SCH_BASE : std_logic_vector := x"61000000";
MNG_BASE : std_logic_vector := x"60000000";
USR_BASE : std_logic_vector := x"30000000";
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 8
);
port
(
FSL_S_READ : out std_logic;
FSL_S_DATA : in std_logic_vector(0 to 63);
FSL_S_CONTROL : in std_logic;
FSL_S_EXISTS : in std_logic;
FSL_M_WRITE : out std_logic;
FSL_M_DATA : out std_logic_vector(0 to 63);
FSL_M_CONTROL : out std_logic;
FSL_M_FULL : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity user_logic;
architecture behavioral of user_logic is
constant BUS_ADDR : std_logic_vector(0 to C_AWIDTH-1) := USR_BASE(0 to 23) & x"18";
signal tid_data : std_logic_vector(0 to 31);
--signal bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal sta_data : std_logic_vector(0 to 31);
--signal cmd_data : std_logic_vector(0 to C_DWIDTH-1);
signal arg_data : std_logic_vector(0 to 31);
signal res_data : std_logic_vector(0 to 31);
signal mux_data : std_logic_vector(0 to 31);
signal mem_rd : std_logic;
signal mem_wr : std_logic;
signal mem_addr : std_logic_vector(0 to C_AWIDTH-1);
signal mem_res : std_logic_vector(0 to C_DWIDTH-1);
signal mem_ack : std_logic;
signal mem_last : std_logic;
signal mem_err : std_logic;
signal mem_data : std_logic_vector(0 to C_DWIDTH-1);
signal mem_length : std_logic_vector(0 to 23);
signal cmd_wr : std_logic;
signal sta_wr : std_logic;
signal res_wr : std_logic;
signal tid_rdack : std_logic;
signal bus_rdack : std_logic;
signal sta_rdack : std_logic;
--signal cmd_rdack : std_logic;
signal arg_rdack : std_logic;
signal res_rdack : std_logic;
signal tid_wrack : std_logic;
signal bus_wrack : std_logic;
signal sta_wrack : std_logic;
--signal cmd_wrack : std_logic;
signal arg_wrack : std_logic;
--signal res_wrack : std_logic;
signal tid_value : std_logic_vector(0 to 7);
--signal bus_value : std_logic_vector(0 to C_DWIDTH-1);
signal sta_value : std_logic_vector(0 to 7);
--signal cmd_value : std_logic_vector(0 to 3);
signal arg_value : std_logic_vector(0 to 31);
signal res_value : std_logic_vector(0 to 31);
--signal cmd_iwr : std_logic;
--signal sta_iwr : std_logic;
--signal sta_idata : std_logic_vector(0 to C_DWIDTH-1);
--signal cmd_idata : std_logic_vector(0 to C_DWIDTH-1);
signal sta_wdata : std_logic_vector(0 to 31);
signal res_wdata : std_logic_vector(0 to 31);
--signal cmd_wdata : std_logic_vector(0 to C_DWIDTH-1);
alias tid_read : std_logic is Bus2IP_RdCE(0);
alias tmr_read : std_logic is Bus2IP_RdCE(1);
alias sta_read : std_logic is Bus2IP_RdCE(2);
alias cmd_read : std_logic is Bus2IP_RdCE(3);
alias arg_read : std_logic is Bus2IP_RdCE(4);
alias res_read : std_logic is Bus2IP_RdCE(5);
alias bus_read : std_logic is Bus2IP_RdCE(6);
alias tid_write : std_logic is Bus2IP_WrCE(0);
alias tmr_write : std_logic is Bus2IP_WrCE(1);
alias sta_write : std_logic is Bus2IP_WrCE(2);
alias cmd_write : std_logic is Bus2IP_WrCE(3);
alias arg_write : std_logic is Bus2IP_WrCE(4);
alias res_write : std_logic is Bus2IP_WrCE(5);
alias bus_write : std_logic is Bus2IP_WrCE(6);
begin
mux_data <= tid_data or sta_data or arg_data or res_data;
IP2Bus_Data <= (mux_data & x"00000000") or mem_data
when Bus2IP_RdReq='1' else (others => '0');
IP2Bus_WrAck <= tid_wrack or sta_wrack or arg_wrack or res_write or
bus_wrack or cmd_write;
IP2Bus_RdAck <= tid_rdack or sta_rdack or arg_rdack or res_rdack or
bus_rdack or cmd_read;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= Bus2IP_RdReq or Bus2IP_WrReq;
-- Instantiate the Thread ID register as a read/write register
tidreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => TID_BITS,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => tid_read,
wr => tid_write,
data => Bus2IP_Data(0 to 31),
rdack => tid_rdack,
wrack => tid_wrack,
value => tid_value,
output => tid_data
);
-- Instantiate the Timer register as a read/write register
--busreg : entity hwti_common_v1_00_a.hwtireg
--generic map
--(
-- REG_WIDTH => C_DWIDTH,
-- C_AWIDTH => C_AWIDTH,
-- C_DWIDTH => C_DWIDTH
--)
--port map
--(
-- clk => Bus2IP_Clk,
-- rst => Bus2IP_Reset,
-- rd => bus_read,
-- wr => bus_write,
-- data => Bus2IP_Data,
-- rdack => bus_rdack,
-- wrack => bus_wrack,
-- value => bus_value,
-- output => bus_data
--);
-- Instantiate the Status register as a read/write register
stareg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 8,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => sta_read,
wr => sta_wr,
data => sta_wdata,
rdack => sta_rdack,
wrack => sta_wrack,
value => sta_value,
output => sta_data
);
-- Make a mux for the command register data and status register data
--cmd_idata <= Bus2IP_Data when cmd_write = '1' else cmd_wdata;
--cmd_iwr <= cmd_wr or cmd_write;
--sta_idata <= Bus2IP_Data when sta_write = '1' else sta_wdata;
--sta_iwr <= sta_wr or sta_write;
-- Instantiate the Command register as a read/write register
--cmdreg : entity hwti_common_v1_00_a.hwtireg
--generic map
--(
-- REG_WIDTH => 4,
-- C_AWIDTH => C_AWIDTH,
-- C_DWIDTH => C_DWIDTH
--)
--port map
--(
-- clk => Bus2IP_Clk,
-- rst => Bus2IP_Reset,
-- rd => cmd_read,
-- wr => cmd_iwr,
-- data => cmd_idata,
-- rdack => cmd_rdack,
-- wrack => cmd_wrack,
-- value => cmd_value,
-- output => cmd_data
--);
-- Instantiate the Argument register as a read/write register
argreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 32,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => arg_read,
wr => arg_write,
data => Bus2IP_Data(0 to 31),
rdack => arg_rdack,
wrack => arg_wrack,
value => arg_value,
output => arg_data
);
-- Instantiate the Result register as a read/write register
resreg : entity hwti_common_v1_00_a.hwtireg
generic map
(
REG_WIDTH => 32,
USE_HIGH => true,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => 32
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => res_read,
wr => res_wr,
data => res_wdata,
rdack => res_rdack,
wrack => open,
value => res_value,
output => res_data
);
-- Instantiate the memory read/write state machine
imemory : entity plb_hwti_v1_00_a.memory
generic map
(
MEM_ADDR => BUS_ADDR,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
rd => mem_rd,
wr => mem_wr,
addr => mem_addr,
length => mem_length,
ack => mem_ack,
last => mem_last,
Bus2IP_MstError => Bus2IP_MstError,
Bus2IP_MstLastAck => Bus2IP_MstLastAck,
Bus2IP_MstRdAck => Bus2IP_MstRdAck,
Bus2IP_MstWrAck => Bus2IP_MstWrAck,
Bus2IP_MstRetry => Bus2IP_MstRetry,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut,
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
IP2Bus_MstNum => IP2Bus_MstNum,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2IP_Addr => IP2IP_Addr
);
-- Instantiate the command processing state machine
icommand : entity hwti_common_v1_00_a.command
generic map
(
MTX_BITS => MTX_BITS,
TID_BITS => TID_BITS,
CMD_BITS => CMD_BITS,
MTX_BASE => MTX_BASE,
CDV_BASE => CDV_BASE,
SCH_BASE => SCH_BASE,
MNG_BASE => MNG_BASE,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
tid => tid_value,
arg => arg_value,
opcode_read => FSL_S_READ,
opcode_data => FSL_S_DATA,
opcode_control => FSL_S_CONTROL,
opcode_exists => FSL_S_EXISTS,
result_write => FSL_M_WRITE,
result_data => FSL_M_DATA,
result_control => FSL_M_CONTROL,
result_full => FSL_M_FULL,
command => Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1),
status => sta_value,
setsta => sta_wr,
outsta => sta_wdata,
setres => res_wr,
outres => res_wdata,
memrd => bus_read,
memwr => bus_write,
memrdack => bus_rdack,
memwrack => bus_wrack,
rd => mem_rd,
wr => mem_wr,
addr => mem_addr,
data => mem_data,
bytes => mem_length,
ack => mem_ack,
last => mem_last,
err => '0',
results => Bus2IP_Data
);
end behavioral;
| bsd-3-clause | aabb53d4a43caa761ec6d1924182d322 | 0.508648 | 3.477813 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plbv46_opb_bridge_v1_01_a/hdl/vhdl/opb_master.vhd | 3 | 22,716 |
-------------------------------------------------------------------------------
-- $Id: opb_master.vhd,v 1.1.2.1 2008/12/19 20:58:34 mlovejoy Exp $
-------------------------------------------------------------------------------
-- opb_master.vhd - Version v1_0_a
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-- Filename: opb_master.vhd
-- Version: v1_01_a
-- Description:
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: <Tim Davis>
--
-- History:
--
-- TRD 9/8/2006
-- ~~~~~~
-- - Initial release of v1_00_a
-- ^^^^^^
-- MLL 8/28/2008
-- New version plbv46_opb_bridge_v1_01_a to include new
-- plbv46_slave_burst_v1_01_a and proc_common v3.00.a.
-- Also added coverage off/on for code coverage testing.
-- Removed Changelog and DISCLAIMER OF LIABILITY updated.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- NOTES:
-- 1) The CE's from the IPIC are not used but included for consistency to make
-- it easier to connect things up. That unfortunately makes it necessary to
-- include the C_ARD_ADDR_RANGE_ARRAY and C_ARD_NUM_CE_ARRAY generics. **Maybe**
-- there is a chance these might be used in the future.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--use ieee.std_logic_misc.all;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.proc_common_pkg.ALL;
--use proc_common_v2_00_a.proc_common_pkg.log2;
--use proc_common_v2_00_a.proc_common_pkg.max2;
USE proc_common_v3_00_a.family.ALL;
USE proc_common_v3_00_a.ipif_pkg.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY plbv46_opb_bridge_v1_01_a;
USE plbv46_opb_bridge_v1_01_a.ALL;
-------------------------------------------------------------------------------
ENTITY opb_master IS
GENERIC (
-- Base address and high address pairs.
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
-- This array speifies the number of Chip Enables (CE) that is
-- required by the cooresponding baseaddr pair.
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
-- width of the PLB Address Bus (in bits)
C_SPLB_AWIDTH : integer RANGE 32 TO 36 := 32;
-- Width of IPIF (Hence IPIC) Data Bus (in bits). This parameter is kept
-- for consistency with the plbv46_slave_burst core but should always be
-- 32 to match the OPB data width.
C_SPLB_DWIDTH : integer RANGE 32 TO 128 := 128;
C_SIPIF_DWIDTH : integer RANGE 32 TO 32 := 32;
-- PLB:OPB clock period ratio. 1=1:1, 2=1:2
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
C_FAMILY : string := virtex4 -- Select the target architecture type
);
PORT (
-- IP Interconnect (IPIC) Interface from PLBv46 IPIF
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
IP2Bus_Data : OUT std_logic_vector(0 TO C_SIPIF_DWIDTH-1);
IP2Bus_WrAck : OUT std_logic;
IP2Bus_RdAck : OUT std_logic;
IP2Bus_AddrAck : OUT std_logic;
IP2Bus_Error : OUT std_logic;
Bus2IP_Addr : IN std_logic_vector(0 TO C_SPLB_AWIDTH-1);
Bus2IP_Data : IN std_logic_vector(0 TO C_SIPIF_DWIDTH-1);
Bus2IP_RNW : IN std_logic;
Bus2IP_BE : IN std_logic_vector(0 TO C_SIPIF_DWIDTH/8-1);
Bus2IP_Burst : IN std_logic;
Bus2IP_BurstLength : IN std_logic_vector(0 TO log2(16 * (C_SPLB_DWIDTH/8)));
Bus2IP_WrReq : IN std_logic;
Bus2IP_RdReq : IN std_logic;
Bus2IP_CS : IN std_logic_vector(0 TO ((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
Bus2IP_RdCE : IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- OPB Bus Master Interface
OPB_Clk : IN std_logic;
OPB_Rst : IN std_logic;
Mn_request : OUT std_logic;
Mn_busLock : OUT std_logic;
Mn_select : OUT std_logic;
Mn_RNW : OUT std_logic;
Mn_BE : OUT std_logic_vector(0 TO 32/8-1);
Mn_seqAddr : OUT std_logic;
Mn_DBus : OUT std_logic_vector(0 TO 32-1);
Mn_ABus : OUT std_logic_vector(0 TO 32-1);
OPB_MGrant : IN std_logic := '0';
OPB_xferAck : IN std_logic := '0';
OPB_errAck : IN std_logic := '0';
OPB_retry : IN std_logic := '0';
OPB_timeout : IN std_logic := '0';
OPB_DBus : IN std_logic_vector(0 TO 32 - 1)
);
END ENTITY opb_master;
ARCHITECTURE syn OF opb_master IS
CONSTANT prop_delay : time := 1 NS; -- For simulation clarity only
CONSTANT ce_all_zero : std_logic_vector(Bus2IP_WrCE'range) := (OTHERS => '0');
TYPE bridge_state_type IS (REQUEST, TRANSACT, WAIT_DESELECT, FORCEWT);
SIGNAL bridge_ns, bridge_cs : bridge_state_type;
SIGNAL Mn_select_ns, Mn_select_cs : std_logic;
SIGNAL Mn_busLock_ns, Mn_busLock_cs : std_logic;
SIGNAL Mn_seqAddr_ns, Mn_seqAddr_cs : std_logic;
SIGNAL Mn_RNW_ns, Mn_RNW_cs : std_logic;
SIGNAL Mn_BE_ns, Mn_BE_cs : std_logic_vector(0 TO 3);
SIGNAL IP2Bus_AddrAck_ns, IP2Bus_AddrAck_cs : std_logic;
SIGNAL IP2Bus_WrAck_ns, IP2Bus_WrAck_cs : std_logic;
SIGNAL IP2Bus_RdAck_ns, IP2Bus_RdAck_cs : std_logic;
SIGNAL IP2Bus_Error_ns, IP2Bus_Error_cs : std_logic;
SIGNAL ce_reduce : std_logic; -- 'OR' Reduce of the Bus2IP chip enables
SIGNAL bus2ip_select : std_logic; -- Indicates transaction req from bus
BEGIN
--coverage off
ASSERT (C_SPLB_AWIDTH = 32)
REPORT "The PLB Address Width does not equal 32 which is required by the OPB bus."
SEVERITY FAILURE;
--coverage on
-- The bridge reacts when one of the chip enables from the IPIC interface
-- asserts indicating a request to the bridge. For smallest amount of logic
-- there should only be one chip enable per (chip select) address region.
-- The s1, s2, and s3 signal assignments below use an OR-reduce operation on
-- the read and write IPIC chip enables to identify when the
-- plbv46_slave_burst is requesting access to the OPB bus. In the 1:2 clock
-- ratio case the select signal deassertion period needs to be stretched.
s1 : ce_reduce <= '0' AFTER prop_delay WHEN
Bus2IP_WrCE = ce_all_zero
AND Bus2IP_RdCE = ce_all_zero
ELSE
'1' AFTER prop_delay;
select_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- No pulse stretching is required in the 1:1 clock ratio case.
s2 : bus2ip_select <= ce_reduce;
END GENERATE select_gen1;
select_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This process stretches the low going pulse of the ce_reduce to
-- ensure that it lasts for two Bus2IP_clk periods which equals one
-- OPB_CLK period. That way the state machine can see the
-- deassertion of the IPIC interface request.
PROCESS (Bus2IP_Clk, ce_reduce) IS
VARIABLE ce_reduce_dly1 : std_logic;
BEGIN
s3 : bus2ip_select <= ce_reduce AND ce_reduce_dly1;
IF (rising_edge(Bus2IP_Clk)) THEN
ce_reduce_dly1 := ce_reduce;
END IF;
END PROCESS;
END GENERATE select_gen2;
--
-- The state machine connects the two protocols -- opb and ipic
--
bfsm : PROCESS (Bus2IP_BE, Bus2IP_Burst, Bus2IP_RNW, IP2Bus_AddrAck_cs,
IP2Bus_Error_cs, IP2Bus_RdAck_cs, IP2Bus_WrAck_cs, Mn_BE_cs,
Mn_RNW_cs, Mn_busLock_cs, Mn_select_cs,
Mn_seqAddr_cs, OPB_MGrant, OPB_errAck, OPB_retry,
OPB_timeout, OPB_xferAck, bridge_cs, bus2ip_select) IS
-- Combinatorial Next state and output decoding
BEGIN
-- Default to holding current state of all outputs
bridge_ns <= bridge_cs AFTER prop_delay;
Mn_select_ns <= Mn_select_cs AFTER prop_delay;
Mn_busLock_ns <= Mn_busLock_cs AFTER prop_delay;
Mn_seqAddr_ns <= Mn_seqAddr_cs AFTER prop_delay;
Mn_RNW_ns <= Mn_RNW_cs AFTER prop_delay;
Mn_BE_ns <= Mn_BE_cs AFTER prop_delay;
IP2Bus_AddrAck_ns <= IP2Bus_AddrAck_cs AFTER prop_delay;
IP2Bus_WrAck_ns <= IP2Bus_WrAck_cs AFTER prop_delay;
IP2Bus_RdAck_ns <= IP2Bus_RdAck_cs AFTER prop_delay;
IP2Bus_Error_ns <= IP2Bus_Error_cs AFTER prop_delay;
CASE bridge_cs IS
WHEN REQUEST =>
IP2Bus_Error_ns <= '0' AFTER prop_delay;
IP2Bus_AddrAck_ns <= '0' AFTER prop_delay;
IP2Bus_WrAck_ns <= '0' AFTER prop_delay;
IP2BUS_RdAck_ns <= '0' AFTER prop_delay;
-- Waiting for a request from the PLBv46 IPIF
-- (plbv46_slave_burst_v1_01_a) via Chip enable assertion
IF (OPB_MGrant = '1') THEN
-- Because Mn_request is combinatorially dependent on
-- bus2ip_select='1' already it would seem that the following if
-- condition is redundant. This is true except when bus parking
-- is activated in which case the OPB_MGrant can assert without
-- Mn_request ever asserting. DONT'T REMOVE THIS CONDITION!
-- (OPB Arbiter bus parking on this Master permits a faster
-- response by pre-issuing the grant prior to a request. Note
-- that the request never has to be asserted. I'm assuming it
-- can be without harm.)
IF (bus2ip_select = '1') THEN
bridge_ns <= TRANSACT AFTER prop_delay;
Mn_select_ns <= '1' AFTER prop_delay;
Mn_busLock_ns <= Bus2IP_Burst AFTER prop_delay;
Mn_seqAddr_ns <= Bus2IP_Burst AFTER prop_delay;
Mn_RNW_ns <= Bus2IP_RNW AFTER prop_delay;
Mn_BE_ns <= Bus2IP_BE AFTER prop_delay;
END IF;
END IF;
WHEN TRANSACT =>
IP2Bus_AddrAck_ns <= OPB_xferAck AND NOT OPB_retry AFTER prop_delay;
IP2Bus_WrAck_ns <= OPB_xferAck AND NOT Bus2IP_RNW AFTER prop_delay;
IP2BUS_RdAck_ns <= OPB_xferAck AND Bus2IP_RNW AFTER prop_delay;
IP2BUS_Error_ns <= (OPB_xferAck AND OPB_errAck)
OR (OPB_timeout AND NOT OPB_xferAck) AFTER prop_delay;
IF (bus2ip_select = '1') THEN
IF (OPB_retry = '1') THEN
-- IPIF still wants to get it's request satisfied but the SM
-- must go back to re-request the OPB bus again. Retry and
-- xferAck are mutually exclusive so the IPIF won't be ack'd
-- on retry. The slave can retry indefinately. (Note: This
-- should be fixed eventually via a retry timeout counter.)
bridge_ns <= FORCEWT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
ELSIF (OPB_xferAck) = '1' THEN
IF(NOT Bus2IP_Burst) = '1' THEN
-- End of transaction from IPIF
bridge_ns <= WAIT_DESELECT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
ELSIF OPB_timeout = '1' THEN
-- OPB_xferAck takes precedence over OPB_timeout
bridge_ns <= WAIT_DESELECT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
ELSE
-- This represents an OPB "Master Abort"
bridge_ns <= REQUEST AFTER prop_delay;
-- Must deassert bus lock here in case of abnormal termination
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
WHEN WAIT_DESELECT =>
-- The plbv46_burst_slave_v1_00_a pipelines its Bus2IP chip
-- selects. They won't disappear until the *ack is sampled
-- high at the next rising edge. This state checks that it IS
-- deasserted. Otherwise, the state machine will recognize a NEW
-- transaction immediately after the first one completes.
IP2Bus_AddrAck_ns <= '0' AFTER prop_delay;
IP2Bus_WrAck_ns <= '0' AFTER prop_delay;
IP2BUS_RdAck_ns <= '0' AFTER prop_delay;
IP2BUS_Error_ns <= '0' AFTER prop_delay;
bridge_ns <= REQUEST AFTER prop_delay;
WHEN FORCEWT =>
-- After a retry the master is required to stay off the bus for one
-- clock.
bridge_ns <= REQUEST AFTER prop_delay;
--coverage off
WHEN OTHERS => NULL;
--coverage on
END CASE;
END PROCESS bfsm;
state : PROCESS (OPB_Clk, OPB_Rst) IS
-- State Machine state register
BEGIN
IF (OPB_Rst = '1') THEN
bridge_cs <= REQUEST AFTER prop_delay;
ELSIF (rising_edge(OPB_Clk)) THEN
bridge_cs <= bridge_ns AFTER prop_delay;
END IF;
END PROCESS state;
oreg : PROCESS (OPB_Clk, OPB_Rst) IS
-- State Machine output registers
BEGIN
IF (OPB_Rst = '1') THEN
Mn_select_cs <= '0' AFTER prop_delay;
Mn_busLock_cs <= '0' AFTER prop_delay;
Mn_seqAddr_cs <= '0' AFTER prop_delay;
Mn_RNW_cs <= '0' AFTER prop_delay;
Mn_BE_cs <= (OTHERS => '0') AFTER prop_delay;
IP2Bus_AddrAck_cs <= '0' AFTER prop_delay;
IP2Bus_WrAck_cs <= '0' AFTER prop_delay;
IP2Bus_RdAck_cs <= '0' AFTER prop_delay;
IP2Bus_Error_cs <= '0' AFTER prop_delay;
ELSIF (rising_edge(OPB_Clk)) THEN
Mn_select_cs <= Mn_select_ns AFTER prop_delay;
Mn_busLock_cs <= Mn_busLock_ns AFTER prop_delay;
Mn_seqAddr_cs <= Mn_seqAddr_ns AFTER prop_delay;
Mn_RNW_cs <= Mn_RNW_ns AFTER prop_delay;
Mn_BE_cs <= Mn_BE_ns AFTER prop_delay;
IP2Bus_AddrAck_cs <= IP2Bus_AddrAck_ns AFTER prop_delay;
IP2Bus_WrAck_cs <= IP2Bus_WrAck_ns AFTER prop_delay;
IP2Bus_RdAck_cs <= IP2Bus_RdAck_ns AFTER prop_delay;
IP2Bus_Error_cs <= IP2Bus_Error_ns AFTER prop_delay;
END IF;
END PROCESS oreg;
apath : PROCESS (Bus2IP_Addr(0 TO 31), Mn_select_cs) IS
-- Master address bus registers
BEGIN
IF Mn_select_cs = '0' THEN
-- The Master's ABus is or'd externally with the other Master ABus'.
-- The master must not drive its ABus unless it is selected.
Mn_ABus <= (OTHERS => '0');
ELSE
-- PLBv46 spec, pg 32, sect 2.5.1.1, "For non-line transfers, this
-- 32-bit bus indicates the lowest numbered byte address of the target
-- data to be read/written over the PLB."
Mn_ABus <= Bus2IP_Addr(0 TO 31);
END IF;
END PROCESS apath;
mn_dpath : PROCESS (Bus2IP_Data(0 TO 31), Bus2IP_RNW, Mn_select_cs) IS
-- Master data bus registers
BEGIN
IF (NOT Mn_select_cs OR Bus2IP_RNW) = '1' THEN
-- The Master's DBus is or'd externally with the slave's bus. On Reads
-- the master must not be driving anything or the data on the OPB_DBus
-- will be corrupted. It must not drive anything on writes if not
-- selected either.
Mn_DBus <= (OTHERS => '0');
ELSE
Mn_DBus <= Bus2IP_Data(0 TO 31);
END IF;
END PROCESS mn_dpath;
s2 : IP2Bus_Data(0 TO 31) <= OPB_DBus AFTER prop_delay;
clkratio1to1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- Does the opb_master only see acks when its select is asserted? Or does it
-- see every device's ack? IE Does it need to qualify the acks w/ select?
s3 : IP2Bus_AddrAck <= IP2Bus_AddrAck_ns;
s4 : IP2Bus_WrAck <= IP2Bus_WrAck_ns;
s5 : IP2Bus_RdAck <= IP2Bus_RdAck_ns;
s6 : IP2Bus_Error <= IP2Bus_Error_ns;
END GENERATE clkratio1to1;
clkratio1to2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
--
-- To jump the clock domain boundary the longer (OPB_Clk period) acks are
-- translated to a single pulse in the (PLB_Clk period) domain. Note that
-- the OPB_CLK is "data" with respect to the BUS2IP_CLK (plb clock) even
-- though both are presumably generated from the same DLL.
--
-- __ __ __
-- BUS2IP_Clk __/ \__/ \__/ \__/
-- _____ _____
-- OPB_Clk __/ \_____/ \
-- ___________
-- IP2Bus_AddrAck_ns ___/ \______
-- _____
-- IP2Bus_AddrAck _________/ \______
--
s3 : IP2Bus_AddrAck <= IP2Bus_AddrAck_ns AND NOT OPB_CLK;
s4 : IP2Bus_WrAck <= IP2Bus_WrAck_ns AND NOT OPB_CLK;
s5 : IP2Bus_RdAck <= IP2Bus_RdAck_ns AND NOT OPB_CLK;
s6 : IP2Bus_Error <= IP2Bus_Error_ns AND NOT OPB_CLK;
END GENERATE clkratio1to2;
s10 : Mn_request <= '1' AFTER prop_delay WHEN bus2ip_select = '1' AND bridge_cs = REQUEST ELSE
'0' AFTER prop_delay; -- The request has to drop synchronously
-- in case the grant is simply the
-- request fed back asynchronously.
s11 : Mn_select <= Mn_select_cs;
s12 : Mn_busLock <= Mn_busLock_cs;
s13 : Mn_seqAddr <= Mn_seqAddr_cs;
s14 : Mn_RNW <= Mn_RNW_cs;
s15 : Mn_BE <= Mn_BE_cs;
END ARCHITECTURE syn;
| bsd-3-clause | e9407afa9e519a7210f3e4f3f8befb0d | 0.543978 | 3.839108 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/reset_mir.vhd | 3 | 10,901 | -------------------------------------------------------------------------------
-- $Id: reset_mir.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--reset_mir.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_mir.vhd
--
-- Description: SW reset / MIR register.
--
-------------------------------------------------------------------------------
-- Structure:
-- reset_mir.vhd
--
-------------------------------------------------------------------------------
-- Author: F.Ostler
--
-- History:
-- FLO Aug 16, 2001
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.conv_std_logic_vector;
----------------------------------------------------------------------
entity reset_mir is
Generic (
C_DWIDTH : integer := 32;
C_INCLUDE_SW_RST : integer := 1;
C_INCLUDE_MIR : integer := 1;
C_MIR_MAJOR_VERSION : integer := 0;
C_MIR_MINOR_VERSION : integer := 0;
C_MIR_REVISION : integer := 1;
C_MIR_BLK_ID : integer := 1;
C_MIR_TYPE : integer := 1
);
port (
Reset : in std_logic;
Bus2IP_Clk : in std_logic;
SW_Reset_WrCE : in std_logic;
SW_Reset_RdCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Reset : out std_logic;
Reset2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Reset2Bus_Ack : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end reset_mir;
architecture implementation of reset_mir is
--------------------------------------------------------------------------------
-- Value of data LSBs required for a reset-register write to be valid.
--------------------------------------------------------------------------------
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
signal sw_reset : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
begin
----------------------------------------------------------------------------
-- Response signal generation
----------------------------------------------------------------------------
Reset2Bus_Ack <= '1' -- Always acknowledge immediately
when C_INCLUDE_SW_RST = 1 or C_INCLUDE_MIR = 1
else '0';
Reset2Bus_Error <= SW_Reset_WrCE and data_is_non_reset_match
when C_INCLUDE_SW_RST = 1
else '0';
Reset2Bus_Retry <= '0';
Reset2Bus_ToutSup <= '0';
data_is_non_reset_match <=
'0' when Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1) = RESET_MATCH
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
INCLUDE_SW_RESET_GEN : if C_INCLUDE_SW_RST = 1 generate
----------------------------------------------------------------------------
-- ToDo, sw_reset could be implemented by instantiating a LUT, muxcy,
-- orcy and two FFs.
----------------------------------------------------------------------------
sw_rst_cond <= SW_Reset_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Reset = '1') Then
sw_rst_cond_d1 <= '0';
sw_reset <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
sw_reset <= sw_rst_cond or sw_rst_cond_d1;
end if;
end if;
End process;
--
Bus2IP_Reset <= Reset or sw_reset;
end generate;
--
--
EXCLUDE_SW_RESET : if C_INCLUDE_SW_RST = 0 generate
Bus2IP_Reset <= Reset;
end generate;
--------------------------------------------------------------------------------
-- MIR
--------------------------------------------------------------------------------
EXCLUDE_MIR_GEN : if C_INCLUDE_MIR = 0 generate
Reset2Bus_Data <= (others => '0');
end generate;
--
--
INCLUDE_MIR_GEN : if C_INCLUDE_MIR = 1 generate
signal mir_value : std_logic_vector(0 to 31);
begin
----------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics
----------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_MIR_MAJOR_VERSION, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_MIR_MINOR_VERSION, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_MIR_REVISION, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_MIR_BLK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_MIR_TYPE, 8);
READ_MUX : process(SW_Reset_RdCE,mir_value)
begin
if(SW_Reset_RdCE = '1')then
Reset2Bus_Data <= mir_value;
else
Reset2Bus_Data <= (others => '0');
end if;
end process READ_MUX;
end generate;
end implementation;
| bsd-3-clause | b6c9afeab7e1fffd649e34f4e86302f2 | 0.408403 | 4.959509 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/plb_bus_wrapper.vhd | 3 | 14,698 | -------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_00_a;
use plb_v46_v1_00_a.all;
entity plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 0);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_UABus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_busLock : in std_logic_vector(0 to 0);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_MSize : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 0);
M_request : in std_logic_vector(0 to 0);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_wrBurst : in std_logic_vector(0 to 0);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 0);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 0);
PLB_MTimeout : out std_logic_vector(0 to 0);
PLB_MBusy : out std_logic_vector(0 to 0);
PLB_MRdErr : out std_logic_vector(0 to 0);
PLB_MWrErr : out std_logic_vector(0 to 0);
PLB_MRdBTerm : out std_logic_vector(0 to 0);
PLB_MRdDAck : out std_logic_vector(0 to 0);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 3);
PLB_MRearbitrate : out std_logic_vector(0 to 0);
PLB_MWrBTerm : out std_logic_vector(0 to 0);
PLB_MWrDAck : out std_logic_vector(0 to 0);
PLB_MSSize : out std_logic_vector(0 to 1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 0);
PLB_SMWrErr : out std_logic_vector(0 to 0);
PLB_SMBusy : out std_logic_vector(0 to 0);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end plb_bus_wrapper;
architecture STRUCTURE of plb_bus_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_NUM_CLK_PLB2OPB_REARB : integer;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Bus_Error_Det : out std_logic
);
end component;
begin
plb_bus : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 1,
C_PLBV46_NUM_SLAVES => 2,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 128,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 0,
C_IRQ_ACTIVE => '1',
C_NUM_CLK_PLB2OPB_REARB => 5,
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| bsd-3-clause | 699553f8987daf2b15e4a261ded0397d | 0.610763 | 3.031766 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/sr_tb.vhd | 1 | 2,890 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:41:47 11/12/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE3_final/sr_tb.vhd
-- Project Name: IDE3_final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SHIFT_REGISTER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sr_tb IS
END sr_tb;
ARCHITECTURE behavior OF sr_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SHIFT_REGISTER
PORT(
CLK : IN std_logic;
DATA : IN std_logic_vector(3 downto 0);
RESET : IN std_logic;
enable : IN std_logic;
OUTPUT : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal DATA : std_logic_vector(3 downto 0) := (others => '0');
signal RESET : std_logic := '0';
signal enable : std_logic := '0';
--Outputs
signal OUTPUT : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SHIFT_REGISTER PORT MAP (
CLK => CLK,
DATA => DATA,
RESET => RESET,
enable => enable,
OUTPUT => OUTPUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
RESET <= '1';
wait for 10 ns;
RESET<= '0';
wait for 10 ns;
DATA<= "0001";
wait for 10 ns;
enable<= '1';
wait for 10 ns;
enable<= '0';
wait for 10 ns;
DATA<= "0010";
wait for 10 ns;
enable<= '1';
wait for 10 ns;
enable<= '0';
wait for 10 ns;
DATA<= "0011";
wait for 10 ns;
enable<= '1';
wait for 10 ns;
enable<= '0';
wait for 10 ns;
DATA<= "0100";
wait for 10 ns;
enable<= '1';
wait for 10 ns;
enable<= '0';
--wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
| unlicense | f278cac42a49894c5ddc35efb338674f | 0.580969 | 3.672173 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_three_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 23,946 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal mutexAddr1, mutexAddr1_next : std_logic_vector(0 to 31);
signal condAddr1, condAddr1_next : std_logic_vector(0 to 31);
signal mutexAddr2, mutexAddr2_next : std_logic_vector(0 to 31);
signal condAddr2, condAddr2_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=FUNCTION_EXIT_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, exist) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
mutexAddr1 <= mutexAddr1_next;
condAddr1 <= condAddr1_next;
mutexAddr2 <= mutexAddr2_next;
condAddr2 <= condAddr2_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
mutexAddr1_next <= mutexAddr1;
condAddr1_next<= condAddr1;
mutexAddr2_next <= mutexAddr2;
condAddr2_next<= condAddr2;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-----------------------------------------------------
--Read size( number of tests), mutex and cond addr
-----------------------------------------------------
when STATE_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the second variable in the struct, mutex1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Read the value of xAddr
mutexAddr1_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, condAddr1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Read the value of condAddr1
condAddr1_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, mutexaddr2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- Read the value of mutexAddr1
mutexAddr2_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, condaddrr2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
condAddr2_next <= toUser_value;
next_state <= STATE_24;
new_request <= '0';
-----------------------------------------------------
--Cond_signal part;
-----------------------------------------------------
--Wait until C=1
when STATE_24 =>
-- LOAD C
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000018";
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
when STATE_25 =>
if (toUser_value =x"00000001") then
next_state <= STATE_5;
new_request <= '0';
else
next_state <= STATE_24;
new_request <= '0';
end if;
--Lock the mutex
when STATE_5 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr2;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
--signal the cond variable
when STATE_7 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condAddr2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- C=3;
when STATE_23 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000018";
thrd2intrfc_value <= x"00000003";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
--unlock the mutex
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr2;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-----------------------------------------------------
--cond_wait part
-----------------------------------------------------
--Lock the mutex
when STATE_11 =>
-- Lock the mutex, push the address of the mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr1;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
--C = 1;
when STATE_21 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000014";
thrd2intrfc_value <= x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
--Wait for (cond,mutex)
when STATE_13 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr1;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condAddr1;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- Call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_22;
next_state <= WAIT_STATE;
--C = 2;
when STATE_22 =>
index_next <= toUser_value;
-- increment index
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= structAddr + x"00000014";
thrd2intrfc_value <= x"00000002";
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
--UnLock the mutex
when STATE_16 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= mutexAddr1;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- Unlock the mutex
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-----------------------------------------------------
--Check To see if have done enough iteration?
-----------------------------------------------------
when STATE_18 =>
-- Increment count
count_next <= count + x"00000001";
-- Check to see if the index is over the size
if ( count = size ) then
next_state <=FUNCTION_EXIT_1;
new_request <= '0';
else
next_state <=STATE_24;
new_request <= '0';
end if;
-----------------------------------------------------
--Exit
-----------------------------------------------------
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= timer;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ececd0059c4cbe4d557755bc4bc2b418 | 0.535789 | 3.926217 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/wb_pkg.vhd | 1 | 72,393 | ---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : wb_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.15 $
--
-- $Log: wb_pkg.vhd,v $
-- Revision 1.15 2015/06/15 16:40:01 AGeissler
-- R1: Clearness
-- M1: Replaced tabs with spaces
--
-- Revision 1.14 2014/03/11 13:51:10 AVieira
-- R: data_mux for 16 and 1-bit are not necessary; WB bte signal unused
-- M: data_mux for 16 and 1-bit removed; WB bte signal removed from wbi_type/wbo_type
--
-- Revision 1.13 2014/03/10 16:29:54 avieira
-- R: data muxes for unconstrained array data input not supported
-- M: added new data_mux implementations and unconstrained array times for 64/32/16 bits data
--
-- Revision 1.12 2014/02/28 10:27:01 avieira
-- R: 64-bit support missing
-- M: Added 64-bit types
--
-- Revision 1.11 2009/07/29 14:05:13 FLenhardt
-- Fixed bug in SWITCH_FAB (WB slave strobe had been activated without addressing)
--
-- Revision 1.10 2007/08/24 11:15:23 FLenhardt
-- Re-added procedure SWITCH_FAB for backward compatibility
--
-- Revision 1.9 2007/08/13 16:28:35 MMiehling
-- moved switch_fab to entity switch_fab_1
--
-- Revision 1.8 2007/08/13 13:58:58 FWombacher
-- fixed typos
--
-- Revision 1.7 2007/08/13 10:14:26 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.6 2006/05/18 16:14:32 twickleder
-- added data_mux for 23 slaves
--
-- Revision 1.5 2006/05/09 11:57:29 twickleder
-- added data_mux for 21 and 22 slaves
--
-- Revision 1.4 2006/02/24 16:09:39 TWickleder
-- Added DATA_MUX procedure with 20 data inputs
--
-- Revision 1.3 2006/02/17 13:54:20 flenhardt
-- Added DATA_MUX procedure with 19 data inputs
--
-- Revision 1.2 2005/12/13 13:48:56 flenhardt
-- Added DATA_MUX procedure with 18 data inputs
--
-- Revision 1.1 2004/08/13 15:16:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:52 mmiehling
-- Initial Revision
--
-- Revision 1.6 2004/07/27 17:06:24 mmiehling
-- multifunction added
--
-- Revision 1.4 2004/05/13 14:21:25 MMiehling
-- multifunction device
--
-- Revision 1.3 2004/04/29 15:07:22 MMiehling
-- removed switch_fab from pkg, now new entity
--
-- Revision 1.2 2004/04/27 09:37:42 MMiehling
-- now correct signal names and wb-types
--
-- Revision 1.3 2004/04/14 16:54:50 MMiehling
-- now correct switch_fab io's
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
TYPE wbo_type_64 IS record
stb : std_logic;
sel : std_logic_vector(7 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type_64 IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
END record;
TYPE slv64_arr IS array (natural range <>) OF std_logic_vector(63 DOWNTO 0);
TYPE slv32_arr IS array (natural range <>) OF std_logic_vector(31 DOWNTO 0);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END wb_pkg;
PACKAGE BODY wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
| gpl-3.0 | a4e67d98996c6dee8495d8f3c40ed311 | 0.482395 | 4.049958 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hw_acc_quicksort_v1_00_a/hdl/vhdl/hw_acc_quicksort.vhd | 2 | 3,950 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_quicksort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_quicksort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_quicksort is
component quicksort is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : quicksort
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_din,
array_dOUT0 => BRAM_A_dout,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause | c58f37ef53ae1a70210d1ad981e3d7a1 | 0.560253 | 3.227124 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg2.vhd | 2 | 17,137 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| bsd-3-clause | 22cf1aa9f0c3bcef3b3e935e524df02a | 0.382039 | 4.941465 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd | 2 | 15,094 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| bsd-3-clause | 4c860a3158ed38e86ba74f539063b22a | 0.380946 | 4.976591 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_init_3.vhd | 2 | 15,641 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = _mutex_owner( mutex->num );
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b46f5d00c1d5a06a7b72711c727274a4 | 0.54127 | 3.830762 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwt_exit_v1_00_a/hdl/vhdl/hwtexit.vhd | 2 | 2,336 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity hwtexit is
port
(
clk : in std_logic;
rst : in std_logic;
HWTI2USER_READ : out std_logic;
HWTI2USER_DATA : in std_logic_vector(0 to 63);
HWTI2USER_CONTROL : in std_logic;
HWTI2USER_EXISTS : in std_logic;
USER2HWTI_WRITE : out std_logic;
USER2HWTI_DATA : out std_logic_vector(0 to 63);
USER2HWTI_CONTROL : out std_logic;
USER2HWTI_FULL : in std_logic
);
end entity hwtexit;
architecture behavioral of hwtexit is
type state is
(
IDLE,
DOEXIT
);
signal cs : state;
signal ns : state;
signal tid : std_logic_vector(0 to 7);
signal tidn : std_logic_vector(0 to 7);
signal arg : std_logic_vector(0 to 31);
signal argn : std_logic_vector(0 to 31);
begin
update : process(clk,rst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
cs <= IDLE;
tid <= (others => '0');
arg <= (others => '0');
else
cs <= ns;
tid <= tidn;
arg <= argn;
end if;
end if;
end process;
controller : process(cs,HWTI2USER_EXISTS,HWTI2USER_DATA,USER2HWTI_FULL,tid, arg) is
begin
ns <= cs;
argn <= arg;
tidn <= tid;
HWTI2USER_READ <= '0';
USER2HWTI_WRITE <= '0';
USER2HWTI_CONTROL <= '0';
USER2HWTI_DATA <= (others => '0');
case cs is
when IDLE =>
if( HWTI2USER_EXISTS = '1' ) then
hwti_wake(HWTI2USER_DATA,tidn,argn);
HWTI2USER_READ <= '1';
ns <= DOEXIT;
end if;
when DOEXIT =>
if( USER2HWTI_FULL = '0' ) then
USER2HWTI_WRITE <= '1';
USER2HWTI_DATA <= hwti_thr_exit(arg);
USER2HWTI_CONTROL <= '0';
ns <= IDLE;
end if;
end case;
end process;
end behavioral;
| bsd-3-clause | 9d7c8f3374f01b9c1ed544bb6e5c2a9e | 0.476027 | 3.588326 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/thread_store.vhd | 11 | 5,785 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity thread_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
tiaddr : in std_logic_vector(0 to C_TWIDTH-1);
tiena : in std_logic;
tiwea : in std_logic;
tinext : in std_logic_vector(0 to C_TWIDTH-1);
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end thread_store;
architecture behavioral of thread_store is
-- Calculate the number of mutexes to use
constant THREADS : integer := pow2( C_TWIDTH );
-- Constant for the last location to be reset
constant RST_END : std_logic_vector(0 to C_TWIDTH-1) := (others => '1');
-- Declare a storage area for the mutex data
type tstore is array(0 to THREADS-1) of std_logic_vector(0 to C_TWIDTH-1);
-- Declare signals for the mutex storage area
signal store : tstore;
signal tena : std_logic;
signal twea : std_logic;
signal taddr : std_logic_vector(0 to C_TWIDTH - 1);
signal tinput : std_logic_vector(0 to C_TWIDTH - 1);
signal toutput : std_logic_vector(0 to C_TWIDTH - 1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rst_cs : rststate;
signal rena : std_logic;
signal rwea : std_logic;
signal raddr : std_logic_vector(0 to C_TWIDTH - 1);
signal raddrn : std_logic_vector(0 to C_TWIDTH - 1);
signal rnext : std_logic_vector(0 to C_TWIDTH - 1);
begin
tonext <= toutput(0 to C_TWIDTH-1);
thread_mux : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
tena <= rena;
twea <= rwea;
taddr <= raddr;
tinput <= rnext;
else
tena <= tiena;
twea <= tiwea;
taddr <= tiaddr;
tinput <= tinext;
end if;
end if;
end process thread_mux;
thread_reset_controller : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process thread_reset_controller;
thread_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rnext <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process thread_reset_logic;
thread_store_controller : process (clk) is
variable output : std_logic_vector(0 to C_TWIDTH-1);
begin
if( rising_edge(clk) ) then
if( tena = '1' ) then
if( twea = '1' ) then
store( conv_integer(taddr) ) <= tinput;
end if;
toutput <= store( conv_integer(taddr) );
end if;
end if;
end process thread_store_controller;
end behavioral;
| bsd-3-clause | 1e7bb72fde6dcd8cc5122101dd504dff | 0.556093 | 4.219548 | false | false | false | false |
guilhermekrz/Pipeline-Processor | HW_Src/sevenSegment4.vhd | 1 | 5,370 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevenSegment4 is
port (
sevenSegmentVector4 : OUT std_logic_vector(27 downto 0);
numberDesired4 : IN std_logic_vector(15 downto 0);
clock, reset : IN std_logic );
end sevenSegment4;
architecture behavior of sevenSegment4 is
begin
process (clock,numberDesired4)
BEGIN
if (clock'event and clock='1') then
case numberDesired4 (3 downto 0) is
when "0000"=> sevenSegmentVector4 (6 downto 0) <="0000001";--0
when "0001"=> sevenSegmentVector4 (6 downto 0) <="1001111";--1
when "0010"=> sevenSegmentVector4 (6 downto 0) <="0010010";--2
when "0011"=> sevenSegmentVector4 (6 downto 0) <="0000110";--3
when "0100"=> sevenSegmentVector4 (6 downto 0) <="1001100";--4
when "0101"=> sevenSegmentVector4 (6 downto 0) <="0100100";--5
when "0110"=> sevenSegmentVector4 (6 downto 0) <="0100000";--6
when "0111"=> sevenSegmentVector4 (6 downto 0) <="0001111";--7
when "1000"=> sevenSegmentVector4 (6 downto 0) <="0000000";--8
when "1001"=> sevenSegmentVector4 (6 downto 0) <="0000100";--9
when "1010"=> sevenSegmentVector4 (6 downto 0) <="0001000";--A
when "1011"=> sevenSegmentVector4 (6 downto 0) <="1100000";--b
when "1100"=> sevenSegmentVector4 (6 downto 0) <="0110001";--C
when "1101"=> sevenSegmentVector4 (6 downto 0) <="1000010";--d
when "1110"=> sevenSegmentVector4 (6 downto 0) <="0110000";--E
when "1111"=> sevenSegmentVector4 (6 downto 0) <="0111000";--F
when others=> sevenSegmentVector4 (6 downto 0) <="1111111";--' '
end case;
case numberDesired4 (7 downto 4) is
when "0000"=> sevenSegmentVector4 (13 downto 7) <="0000001";--0
when "0001"=> sevenSegmentVector4 (13 downto 7) <="1001111";--1
when "0010"=> sevenSegmentVector4 (13 downto 7) <="0010010";--2
when "0011"=> sevenSegmentVector4 (13 downto 7) <="0000110";--3
when "0100"=> sevenSegmentVector4 (13 downto 7) <="1001100";--4
when "0101"=> sevenSegmentVector4 (13 downto 7) <="0100100";--5
when "0110"=> sevenSegmentVector4 (13 downto 7) <="0100000";--6
when "0111"=> sevenSegmentVector4 (13 downto 7) <="0001111";--7
when "1000"=> sevenSegmentVector4 (13 downto 7) <="0000000";--8
when "1001"=> sevenSegmentVector4 (13 downto 7) <="0000100";--9
when "1010"=> sevenSegmentVector4 (13 downto 7) <="0001000";--A
when "1011"=> sevenSegmentVector4 (13 downto 7) <="1100000";--b
when "1100"=> sevenSegmentVector4 (13 downto 7) <="0110001";--C
when "1101"=> sevenSegmentVector4 (13 downto 7) <="1000010";--d
when "1110"=> sevenSegmentVector4 (13 downto 7) <="0110000";--E
when "1111"=> sevenSegmentVector4 (13 downto 7) <="0111000";--F
when others=> sevenSegmentVector4 (13 downto 7) <="1111111";--' '
end case;
case numberDesired4 (11 downto 8) is
when "0000"=> sevenSegmentVector4 (20 downto 14) <="0000001";--0
when "0001"=> sevenSegmentVector4 (20 downto 14) <="1001111";--1
when "0010"=> sevenSegmentVector4 (20 downto 14) <="0010010";--2
when "0011"=> sevenSegmentVector4 (20 downto 14) <="0000110";--3
when "0100"=> sevenSegmentVector4 (20 downto 14) <="1001100";--4
when "0101"=> sevenSegmentVector4 (20 downto 14) <="0100100";--5
when "0110"=> sevenSegmentVector4 (20 downto 14) <="0100000";--6
when "0111"=> sevenSegmentVector4 (20 downto 14) <="0001111";--7
when "1000"=> sevenSegmentVector4 (20 downto 14) <="0000000";--8
when "1001"=> sevenSegmentVector4 (20 downto 14) <="0000100";--9
when "1010"=> sevenSegmentVector4 (20 downto 14) <="0001000";--A
when "1011"=> sevenSegmentVector4 (20 downto 14) <="1100000";--b
when "1100"=> sevenSegmentVector4 (20 downto 14) <="0110001";--C
when "1101"=> sevenSegmentVector4 (20 downto 14) <="1000010";--d
when "1110"=> sevenSegmentVector4 (20 downto 14) <="0110000";--E
when "1111"=> sevenSegmentVector4 (20 downto 14) <="0111000";--F
when others=> sevenSegmentVector4 (20 downto 14) <="1111111";--' '
end case;
case numberDesired4 (15 downto 12) is
when "0000"=> sevenSegmentVector4 (27 downto 21) <="0000001";--0
when "0001"=> sevenSegmentVector4 (27 downto 21) <="1001111";--1
when "0010"=> sevenSegmentVector4 (27 downto 21) <="0010010";--2
when "0011"=> sevenSegmentVector4 (27 downto 21) <="0000110";--3
when "0100"=> sevenSegmentVector4 (27 downto 21) <="1001100";--4
when "0101"=> sevenSegmentVector4 (27 downto 21) <="0100100";--5
when "0110"=> sevenSegmentVector4 (27 downto 21) <="0100000";--6
when "0111"=> sevenSegmentVector4 (27 downto 21) <="0001111";--7
when "1000"=> sevenSegmentVector4 (27 downto 21) <="0000000";--8
when "1001"=> sevenSegmentVector4 (27 downto 21) <="0000100";--9
when "1010"=> sevenSegmentVector4 (27 downto 21) <="0001000";--A
when "1011"=> sevenSegmentVector4 (27 downto 21) <="1100000";--b
when "1100"=> sevenSegmentVector4 (27 downto 21) <="0110001";--C
when "1101"=> sevenSegmentVector4 (27 downto 21) <="1000010";--d
when "1110"=> sevenSegmentVector4 (27 downto 21) <="0110000";--E
when "1111"=> sevenSegmentVector4 (27 downto 21) <="0111000";--F
when others=> sevenSegmentVector4 (27 downto 21) <="1111111";--' '
end case;
end if;
end process;
end behavior; | gpl-2.0 | 47c14cefeccbe8f9b7cf4090b0b67178 | 0.653073 | 3.908297 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_addr_decode.vhd | 2 | 11,405 | -------------------------------------------------------------------------------
-- $Id: xbic_addr_decode.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_decode.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_addr_decode.vhd
-- Version: v1_00_a
-- Description: Simple address decoder function for one Base Addr Pair.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from xps_bram_if_cntlr_v1_00_a library
-- -- Bypassed input address and qualifiers registering to remove
-- one clock of latency during address phase.
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Recoded to utilize behavorial address decode instead of calling
-- the pselect_f module from proc common. This reduced the timing
-- problem paths found with the pselect_f decoder in Spartan3x
-- devices.
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a library.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_type"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
-- Xilinx Primitive Library
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity xbic_addr_decode is
generic (
C_SPLB_AWIDTH : integer := 32;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF" -- IP user0 high address
);
C_FAMILY : string := "virtex5"
);
port (
-- PLB Interface signals
Address_In : in std_logic_vector(0 to
C_SPLB_AWIDTH-1);
Address_Valid : in std_logic;
-- Decode output signals
Addr_Match : out std_logic
);
end entity xbic_addr_decode;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture implementation of xbic_addr_decode is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_SPLB_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_SPLB_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_SPLB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_SPLB_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
return(C_SPLB_AWIDTH);
end function Addr_Bits;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_SPLB_AWIDTH);
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
Constant NUM_BITS_TO_DECODE : integer := DECODE_BITS(0);
constant BASE_ADDR_BITS_TO_USE : unsigned(0 to NUM_BITS_TO_DECODE-1) :=
UNSIGNED(ARD_ADDR_RANGE_ARRAY(0)(0 to NUM_BITS_TO_DECODE-1));
----------------------------------------------------------------
-- Signals
----------------------------------------------------------------
signal decode_hit : std_logic;
Signal sig_input_addr_bits_to_use : unsigned(0 to NUM_BITS_TO_DECODE-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
Addr_Match <= decode_hit;
-- rip only the bits needed for the address range decode
sig_input_addr_bits_to_use <= UNSIGNED(Address_In(0 to NUM_BITS_TO_DECODE-1));
-- Behavorial compare of input address decode bits to the Base address
-- decode bits
decode_hit <= '1'
When (sig_input_addr_bits_to_use = BASE_ADDR_BITS_TO_USE)
Else '0';
end implementation;
| bsd-3-clause | 4e4a893ec45c99a2f91bc6a65fb1f822 | 0.444893 | 4.878101 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/blk_mem_gen_wrapper.vhd | 2 | 40,186 | -------------------------------------------------------------------------------
-- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $
-------------------------------------------------------------------------------
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
-- Version: v1.00a
-- Description:
-- This wrapper file performs the direct call to Block Memory Generator
-- during design implementation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- blk_mem_gen_wrapper.vhd
-- |
-- |-- blk_mem_gen_v2_7
-- |
-- |-- blk_mem_gen_v6_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: MW
-- Revision: $Revision: 1.1.2.69 $
-- Date: $7/11/2008$
--
-- History:
-- MW 7/11/2008 Initial Version
-- MSH 2/26/2009 Add new blk_mem_gen version
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2 instance callout
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2
-- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3
-- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6.
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/27/2010 EDK 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6
-- and later build case.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated to blk_mem_gen V5.2.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated to blk_mem_gen V6.1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Regressed back to blk_mem_gen V5.2
-- ^^^^^^
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use blk_mem_gen_v6_2 for s6, v6, and later.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2
-- instance.
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
library proc_common_v3_00_a;
use proc_common_v3_00_a.coregen_comp_defs.all;
use proc_common_v3_00_a.family_support.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex5";
-- "Virtex2"
-- "Virtex4"
-- "Virtex5"
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
begin
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until clka = '1';
wait until clka = '0';
Wait until clka = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr <= '0' ; -- : out std_logic;
sbiterr <= '0' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 2.7.
-- This is for legacy cores designed and tested with FPGA
-- Families earlier than Virtex-6 and Spartan-6.
--
------------------------------------------------------------
V5_AND_EARLIER: if(FAM_IS_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for legacy BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : blk_mem_gen_v2_7
generic map
(
-- Device Family
c_family => FAMILY_TO_USE ,
c_xdevicefamily => c_xdevicefamily ,
-- Memory Specific Configurations
c_mem_type => c_mem_type ,
c_algorithm => c_algorithm ,
c_prim_type => c_prim_type ,
c_byte_size => c_byte_size ,
-- Simulation Behavior Options
c_sim_collision_check => c_sim_collision_check ,
c_common_clk => c_common_clk ,
c_disable_warn_bhv_coll => c_disable_warn_bhv_coll ,
c_disable_warn_bhv_range => c_disable_warn_bhv_range,
-- Initialization Configuration Options
c_load_init_file => c_load_init_file ,
c_init_file_name => c_init_file_name ,
c_use_default_data => c_use_default_data ,
c_default_data => c_default_data ,
-- Port A Specific Configurations
c_has_mem_output_regs_a => c_has_mem_output_regs_a ,
c_has_mux_output_regs_a => c_has_mux_output_regs_a ,
c_write_width_a => c_write_width_a ,
c_read_width_a => c_read_width_a ,
c_write_depth_a => c_write_depth_a ,
c_read_depth_a => c_read_depth_a ,
c_addra_width => c_addra_width ,
c_write_mode_a => c_write_mode_a ,
c_has_ena => c_has_ena ,
c_has_regcea => c_has_regcea ,
c_has_ssra => c_has_ssra ,
c_sinita_val => c_sinita_val ,
c_use_byte_wea => c_use_byte_wea ,
c_wea_width => c_wea_width ,
-- Port B Specific Configurations
c_has_mem_output_regs_b => c_has_mem_output_regs_b ,
c_has_mux_output_regs_b => c_has_mux_output_regs_b ,
c_write_width_b => c_write_width_b ,
c_read_width_b => c_read_width_b ,
c_write_depth_b => c_write_depth_b ,
c_read_depth_b => c_read_depth_b ,
c_addrb_width => c_addrb_width ,
c_write_mode_b => c_write_mode_b ,
c_has_enb => c_has_enb ,
c_has_regceb => c_has_regceb ,
c_has_ssrb => c_has_ssrb ,
c_sinitb_val => c_sinitb_val ,
c_use_byte_web => c_use_byte_web ,
c_web_width => c_web_width ,
-- Other Miscellaneous Configurations
c_mux_pipeline_stages => c_mux_pipeline_stages ,
c_use_ecc => c_use_ecc ,
c_use_ramb16bwer_rst_bhv => c_use_ramb16bwer_rst_bhv
-- c_corename => c_corename
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
)
port map
(
clka => clka,
ssra => ssra,
dina => dina,
addra => addra,
ena => ena,
regcea => regcea,
wea => wea,
douta => douta,
clkb => clkb,
ssrb => ssrb,
dinb => dinb,
addrb => addrb,
enb => enb,
regceb => regceb,
web => web,
doutb => doutb,
dbiterr => dbiterr,
sbiterr => sbiterr
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
V6_S6_AND_LATER: if(FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : blk_mem_gen_v7_3
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
C_RST_TYPE => "SYNC" ,
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => open , -- output
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => (others => '0') , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => (others => '0') , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => (others => '0') , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => (others => '0') , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => open , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => open , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => (others => '0') , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => (others => '0') , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => (others => '0') , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => (others => '0') , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => open , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => open , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => open , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => open -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate V6_S6_AND_LATER;
end implementation;
| bsd-3-clause | 98dbaceed62aac17ecfe3d93ed9a0a74 | 0.329742 | 5.037102 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zOutReg.vhd | 1 | 718 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity zOutReg is
generic (
port_ixd : natural := 0
);
port (
zClk : in std_logic;
port_ce : in std_logic;
port_id : in std_logic_vector(3 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end zOutReg;
architecture behave of zOutReg is
begin
RegOut : process( zClk )
begin
if zClk'event and zClk='1' then
if port_ce='1' and port_id = conv_std_logic_vector(port_ixd,4) and write_strobe = '1' then
Q <= out_port;
end if;
end if;
end process;
end behave; | gpl-2.0 | 1177fb8e0a9c0bc05701f6eb2ec5f469 | 0.626741 | 2.639706 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/brst_addr_cntr.vhd | 3 | 10,704 | -------------------------------------------------------------------------------
-- $Id: brst_addr_cntr.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- brst_addr_cntr.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: brst_addr_cntr.vhd
--
-- Description: This counter provides the addresses and byte enables during
-- burst operations. It advances based on IP2Bus_addrAck.
-------------------------------------------------------------------------------
-- Structure:
--
--
-- brst_addr_cntr.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- ALS 11/21/03
-- ~~~~~~
-- Adapted from addr_reg_cntr_brst.vhd
-- ^^^^^^
-- ALS 12/24/03
-- ^^^^^^
-- Removed BE generation from this file
-- ~~~~~~~
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity brst_addr_cntr is
generic (
C_CNTR_WIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32
);
port (
-- Inputs
Address_in : in std_logic_vector(0 to C_OPB_AWIDTH-1);
Addr_load : in std_logic;
Addr_CntEn : in std_logic;
Byte_xfer : in std_logic;
Hw_xfer : in std_logic;
Fw_xfer : in std_logic;
-- Address Outputs
Address_Out : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_Clk : in std_logic
);
end brst_addr_cntr;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
architecture implementation of brst_addr_cntr is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- Function set_cntr_width sets the counter width to generic C_CNTR_WIDTH if
-- it is >= 3, otherwise, the counter width is set to 3. This is due to the
-- fact that for OPB addresses, the counter must at least be of width 3 in order
-- to count byte, half-word, and word addresses
function set_cntr_width ( input_cntr_width : integer)
return integer is
begin
if input_cntr_width >= 3 then
return input_cntr_width;
else
return 3;
end if;
end function set_cntr_width;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CNTR_WIDTH : integer := set_cntr_width(C_CNTR_WIDTH);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal address_out_i : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal xfer_size : std_logic_vector(0 to CNTR_WIDTH-1);
signal addr_load_n : std_logic;
signal address_cnt : std_logic_vector(0 to CNTR_WIDTH-1);
-------------------------------------------------------------------------------
begin
-- Output assignments
Address_out <= address_out_i;
-----------------------------------------------------------------------
-- Determine the transfer size
ZERO_XFER_SIZE_GEN: if CNTR_WIDTH > 3 generate
xfer_size(0 to CNTR_WIDTH-4) <= (others => '0');
end generate ZERO_XFER_SIZE_GEN;
xfer_size(CNTR_WIDTH-3 to CNTR_WIDTH-1) <= Fw_xfer & Hw_xfer & Byte_xfer;
-------------------------------------------------------------------------------
-- Address Counter
--
-- Use the direct path counter so a clock delay is not incurred when the address
-- is loaded. Based on the xfer size, increment the counter by 1 ,2 , or 4
-------------------------------------------------------------------------------
addr_load_n <= not(Addr_load);
DIRECT_PATH_CNTR_I: entity opb_v20_v1_10_d.direct_path_cntr_ai
generic map (C_WIDTH => CNTR_WIDTH)
port map (
Clk => OPB_Clk,
Din => Address_in(C_OPB_AWIDTH-CNTR_WIDTH to C_OPB_AWIDTH-1),
Dout => address_cnt,
Load_n => addr_load_n,
Cnt_en => Addr_CntEn,
Delta => xfer_size
);
address_out_i <= address_in(0 to C_OPB_AWIDTH-CNTR_WIDTH-1) & address_cnt;
end implementation;
| bsd-3-clause | c511af2f598da669859cfeb876542474 | 0.413117 | 5.19864 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_5.vhd | 2 | 16,797 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_5.c
-- RETURN_VALUE 31
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- retVal = hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 4ac923d3c6116043c704ec4489ba3943 | 0.543311 | 3.810572 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/infer_bram_dual_port.vhd | 11 | 5,321 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram_dual_port.vhd
-- Date: 06/22/05
-- Purpose: File used to instantiate an inferred BRAM (dual port),
-- According to Xilinx, this will only work with 7.1 b/c of shared variables.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram_dual_port;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram_dual_port is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
| bsd-3-clause | 992eba5c2d9e2a01ec58bbd19701a907 | 0.531667 | 4.563465 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/user_logic.vhd | 10 | 26,990 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal mst_reg_write_req : std_logic;
signal mst_reg_read_req : std_logic;
signal mst_reg_write_sel : std_logic_vector(0 to 3);
signal mst_reg_read_sel : std_logic_vector(0 to 3);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_ip2bus_be : std_logic_vector(0 to 15);
signal mst_go : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the PLBv46 master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the PLBv46
-- master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Busy (User Logic Master is Busy)
-- bit 2 - Error (User Logic Master request got error response)
-- bit 3 - Tmout (User Logic Master request is timeout)
-- bit 2-7 - Spare (Spare Status Bits)
-- Addrress Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - Target Address (This 32-bit value is used to populate the
-- IP2Bus_Mst_Addr(0:31) address bus during a Read or Write
-- user logic master operation)
-- Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-15 - Master BE (This 16-bit value is used to populate the
-- IP2Bus_Mst_BE byte enable bus during a Read or Write user
-- logic master operation for single data beat transfer)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-3 - Reserved
-- bit 4-15 - Transfer Length (This 12-bit value is used to populate the
-- IP2Bus_Mst_Length(0:11) transfer length bus which specifies
-- the number of bytes (1 to 4096) to transfer during user logic
-- master Read or Write fixed length burst operations)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (Write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the target address to the address register
-- 3. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 4. write 0x0004 to the length register
-- 5. write 0x0a to the go register, this will start the master write operation
--
------------------------------------------
mst_reg_write_req <= Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
mst_reg_read_req <= Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
mst_reg_write_sel <= Bus2IP_WrCE(1 to 4);
mst_reg_read_sel <= Bus2IP_RdCE(1 to 4);
mst_write_ack <= mst_reg_write_req;
mst_read_ack <= mst_reg_read_req;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2bus_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_be <= mst_reg(8) & mst_reg(9);
mst_xfer_length <= mst_reg(12)(4 to 7) & mst_reg(13);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, mst_reg_write_req, mst_reg_write_sel ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= mst_reg_write_req and
mst_reg_write_sel(byte_index/BE_WIDTH) and
Bus2IP_BE(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH);
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_cmd_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'/'error'/'timeout'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8);
mst_reg(1)(2) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+2);
mst_reg(1)(3) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+3);
else
-- 'Done'/'error'/'timeout' from master control state machine
mst_reg(1)(0) <= mst_cmd_sm_set_done or mst_reg(1)(0);
mst_reg(1)(2) <= mst_cmd_sm_set_error or mst_reg(1)(2);
mst_reg(1)(3) <= mst_cmd_sm_set_timeout or mst_reg(1)(3);
end if;
-- byte 2 and 3 are reserved
-- address register (byte 4 to 7)
-- be register (byte 8 to 9)
-- length register (byte 12 to 13)
-- byte 10, 11 and 14 are reserved
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8 to
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_cmd_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_cmd_sm_busy = '0' and mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_sel, mst_reg ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
case mst_reg_read_sel is
when "1000" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "0100" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH+byte_index);
end loop;
when "0010" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*2+byte_index);
end loop;
when "0001" =>
for byte_index in 0 to BE_WIDTH-1 loop
if ( byte_index = BE_WIDTH-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*3+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= mst_cntl_rd_req;
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr;
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be(16-C_MST_DWIDTH/8 to 15);
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- local srl fifo for data storage
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n);
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n);
DATA_CAPTURE_FIFO_I : entity proc_common_v3_00_a.srl_fifo_f
generic map
(
C_DWIDTH => C_MST_DWIDTH,
C_DEPTH => 16
)
port map
(
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
FIFO_Write => mst_fifo_valid_write_xfer,
Data_In => Bus2IP_MstRd_d,
FIFO_Read => mst_fifo_valid_read_xfer,
Data_Out => IP2Bus_MstWr_d,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
mst_ip2bus_data when mst_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | 1c8b718dba9e5da849196bd9242dee2d | 0.513783 | 3.662641 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_thcrc_v1_00_a/hdl/vhdl/hw_thcrc.vhd | 2 | 7,960 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_thcrc is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_thcrc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_thcrc is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause | 81305f7f7804df2717418c5b8bfb16a0 | 0.472613 | 4.182869 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDEV2/netgen/translate/IDE_control_unit_translate.vhd | 1 | 10,311 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: IDE_control_unit_translate.vhd
-- /___/ /\ Timestamp: Wed Dec 16 12:53:06 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm IDE_control_unit -w -dir netgen/translate -ofmt vhdl -sim IDE_control_unit.ngd IDE_control_unit_translate.vhd
-- Device : 3s250evq100-5
-- Input file : IDE_control_unit.ngd
-- Output file : C:\Users\Bailey\Documents\IDE V2\IDEV2\netgen\translate\IDE_control_unit_translate.vhd
-- # of Entities : 1
-- Design Name : IDE_control_unit
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity IDE_control_unit is
port (
clk : in STD_LOGIC := 'X';
CS : in STD_LOGIC := 'X';
reset : in STD_LOGIC := 'X';
R : in STD_LOGIC := 'X';
W : in STD_LOGIC := 'X';
Re : out STD_LOGIC;
w_select : out STD_LOGIC;
data_select : out STD_LOGIC;
data_enable : out STD_LOGIC;
enables : out STD_LOGIC_VECTOR ( 2 downto 0 );
wr_prev : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end IDE_control_unit;
architecture Structure of IDE_control_unit is
signal R_IBUF_4 : STD_LOGIC;
signal Re_OBUF_6 : STD_LOGIC;
signal W_IBUF_8 : STD_LOGIC;
signal clk_BUFGP : STD_LOGIC;
signal cycle_counter_not0002 : STD_LOGIC;
signal data_enable_OBUF_19 : STD_LOGIC;
signal enables_0_OBUF_24 : STD_LOGIC;
signal enables_1_OBUF_25 : STD_LOGIC;
signal enables_2_OBUF_26 : STD_LOGIC;
signal i_ready_27 : STD_LOGIC;
signal i_ready_mux0000 : STD_LOGIC;
signal i_ready_not0001 : STD_LOGIC;
signal i_ready_not000112_30 : STD_LOGIC;
signal i_ready_not000120_31 : STD_LOGIC;
signal i_ready_not000130_32 : STD_LOGIC;
signal i_ready_not00019_33 : STD_LOGIC;
signal prev_R_34 : STD_LOGIC;
signal prev_W_35 : STD_LOGIC;
signal reset_IBUF_37 : STD_LOGIC;
signal w_select_OBUF_39 : STD_LOGIC;
signal wr_prev_0_42 : STD_LOGIC;
signal wr_prev_1_43 : STD_LOGIC;
signal i_ready_not00019_O : STD_LOGIC;
signal i_ready_not000120_O : STD_LOGIC;
signal clk_BUFGP_IBUFG_2 : STD_LOGIC;
signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;
signal cycle_counter : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cycle_counter_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
XST_VCC : X_ONE
port map (
O => Re_OBUF_6
);
i_ready : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => i_ready_not0001,
I => i_ready_mux0000,
O => i_ready_27,
SET => GND,
RST => GND
);
cycle_counter_0 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => cycle_counter_not0002,
RST => reset_IBUF_37,
I => cycle_counter_mux0000(2),
O => cycle_counter(0),
SET => GND
);
cycle_counter_1 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => cycle_counter_not0002,
RST => reset_IBUF_37,
I => cycle_counter_mux0000(1),
O => cycle_counter(1),
SET => GND
);
cycle_counter_2 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => cycle_counter_not0002,
RST => reset_IBUF_37,
I => cycle_counter_mux0000(0),
O => cycle_counter(2),
SET => GND
);
prev_R : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => R_IBUF_4,
O => prev_R_34,
CE => VCC,
SET => GND,
RST => GND
);
prev_W : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => W_IBUF_8,
O => prev_W_35,
CE => VCC,
SET => GND,
RST => GND
);
wr_prev_0 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => prev_R_34,
O => wr_prev_0_42,
CE => VCC,
SET => GND,
RST => GND
);
wr_prev_1 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => prev_W_35,
O => wr_prev_1_43,
CE => VCC,
SET => GND,
RST => GND
);
w_select1 : X_LUT3
generic map(
INIT => X"BF"
)
port map (
ADR0 => cycle_counter(2),
ADR1 => cycle_counter(0),
ADR2 => cycle_counter(1),
O => w_select_OBUF_39
);
enables_2_1 : X_LUT3
generic map(
INIT => X"02"
)
port map (
ADR0 => cycle_counter(1),
ADR1 => cycle_counter(0),
ADR2 => cycle_counter(2),
O => enables_2_OBUF_26
);
enables_1_1 : X_LUT3
generic map(
INIT => X"02"
)
port map (
ADR0 => cycle_counter(0),
ADR1 => cycle_counter(1),
ADR2 => cycle_counter(2),
O => enables_1_OBUF_25
);
enables_0_1 : X_LUT3
generic map(
INIT => X"01"
)
port map (
ADR0 => cycle_counter(1),
ADR1 => cycle_counter(0),
ADR2 => cycle_counter(2),
O => enables_0_OBUF_24
);
data_enable_or00001 : X_LUT4
generic map(
INIT => X"2008"
)
port map (
ADR0 => i_ready_27,
ADR1 => cycle_counter(2),
ADR2 => cycle_counter(1),
ADR3 => cycle_counter(0),
O => data_enable_OBUF_19
);
cycle_counter_mux0000_1_1 : X_LUT2
generic map(
INIT => X"6"
)
port map (
ADR0 => cycle_counter(0),
ADR1 => cycle_counter(1),
O => cycle_counter_mux0000(1)
);
cycle_counter_mux0000_2_1 : X_LUT3
generic map(
INIT => X"51"
)
port map (
ADR0 => cycle_counter(0),
ADR1 => cycle_counter(2),
ADR2 => cycle_counter(1),
O => cycle_counter_mux0000(2)
);
cycle_counter_mux0000_0_1 : X_LUT3
generic map(
INIT => X"68"
)
port map (
ADR0 => cycle_counter(0),
ADR1 => cycle_counter(1),
ADR2 => cycle_counter(2),
O => cycle_counter_mux0000(0)
);
i_ready_mux00001 : X_LUT2
generic map(
INIT => X"B"
)
port map (
ADR0 => R_IBUF_4,
ADR1 => prev_R_34,
O => i_ready_mux0000
);
i_ready_not000112 : X_LUT4
generic map(
INIT => X"8000"
)
port map (
ADR0 => cycle_counter(0),
ADR1 => cycle_counter(1),
ADR2 => R_IBUF_4,
ADR3 => i_ready_not00019_33,
O => i_ready_not000112_30
);
i_ready_not000130 : X_LUT4
generic map(
INIT => X"0200"
)
port map (
ADR0 => cycle_counter(2),
ADR1 => cycle_counter(1),
ADR2 => cycle_counter(0),
ADR3 => i_ready_not000120_31,
O => i_ready_not000130_32
);
reset_IBUF : X_BUF
port map (
I => reset,
O => reset_IBUF_37
);
R_IBUF : X_BUF
port map (
I => R,
O => R_IBUF_4
);
W_IBUF : X_BUF
port map (
I => W,
O => W_IBUF_8
);
i_ready_not000147 : X_LUT4
generic map(
INIT => X"F5C4"
)
port map (
ADR0 => prev_W_35,
ADR1 => i_ready_not000130_32,
ADR2 => W_IBUF_8,
ADR3 => i_ready_not000112_30,
O => i_ready_not0001
);
cycle_counter_not00021 : X_LUT4
generic map(
INIT => X"44F4"
)
port map (
ADR0 => R_IBUF_4,
ADR1 => prev_R_34,
ADR2 => prev_W_35,
ADR3 => W_IBUF_8,
O => cycle_counter_not0002
);
i_ready_not00019_LUT2_L_BUF : X_BUF
port map (
I => i_ready_not00019_O,
O => i_ready_not00019_33
);
i_ready_not00019 : X_LUT2
generic map(
INIT => X"1"
)
port map (
ADR0 => prev_R_34,
ADR1 => cycle_counter(2),
O => i_ready_not00019_O
);
i_ready_not000120_LUT2_L_BUF : X_BUF
port map (
I => i_ready_not000120_O,
O => i_ready_not000120_31
);
i_ready_not000120 : X_LUT2
generic map(
INIT => X"4"
)
port map (
ADR0 => R_IBUF_4,
ADR1 => prev_R_34,
O => i_ready_not000120_O
);
clk_BUFGP_BUFG : X_CKBUF
port map (
I => clk_BUFGP_IBUFG_2,
O => clk_BUFGP
);
clk_BUFGP_IBUFG : X_CKBUF
port map (
I => clk,
O => clk_BUFGP_IBUFG_2
);
Re_OBUF : X_OBUF
port map (
I => Re_OBUF_6,
O => Re
);
data_enable_OBUF : X_OBUF
port map (
I => data_enable_OBUF_19,
O => data_enable
);
data_select_OBUF : X_OBUF
port map (
I => w_select_OBUF_39,
O => data_select
);
enables_0_OBUF : X_OBUF
port map (
I => enables_0_OBUF_24,
O => enables(0)
);
enables_1_OBUF : X_OBUF
port map (
I => enables_1_OBUF_25,
O => enables(1)
);
enables_2_OBUF : X_OBUF
port map (
I => enables_2_OBUF_26,
O => enables(2)
);
w_select_OBUF : X_OBUF
port map (
I => w_select_OBUF_39,
O => w_select
);
wr_prev_0_OBUF : X_OBUF
port map (
I => wr_prev_0_42,
O => wr_prev(0)
);
wr_prev_1_OBUF : X_OBUF
port map (
I => wr_prev_1_43,
O => wr_prev(1)
);
NlwBlock_IDE_control_unit_GND : X_ZERO
port map (
O => GND
);
NlwBlock_IDE_control_unit_VCC : X_ONE
port map (
O => VCC
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| unlicense | 6c6b138d1b212010cdccf0418450dfb5 | 0.511977 | 3.108532 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/opb_ipif.vhd | 3 | 77,157 | -------------------------------------------------------------------------------
-- $Id: opb_ipif.vhd,v 1.18 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- opb_ipif.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ipif.vhd
--
-- Description: This is the top level design file for the OPB IPIF.
-- It provides a standardized interface between the
-- IP and the OPB Bus. It also provides data transfer support
-- via DMA, Scatter/Gather, and fifo buffering.
--
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- opb_ipif.vhd
-- \
-- \-- reset_control.vhd
-- \ ipif_reset.vhd
-- \
-- \
-- \-- interrupt_control.vhd
-- \
-- \-- bus2ip_amux.vhd
-- \
-- \-- ip2bus_dmux.vhd
-- \ ip2bus_dmux.vhd
-- \
-- \-- ip2bus_srmux.vhd
-- \ ip2bus_srmux.vhd
-- \
-- \-- address_decoder.vhd
-- \
-- \-- slave_attachment.vhd
-- \
-- \-- ipif_steer
-- \
-- \-- master_attachment.vhd
-- \ mst_attach.vhd
-- \
-- \ dma_sg_pkg.vhd
-- \ dma_sg_cmp.vhd
-- \-- dma_sg.vhd
-- \ dma_sg_sim.vhd
-- \ srl_fifo.vhd
-- \ ctrl_reg.vhd
-- \ ld_arith_reg.vhd
-- \
-- \-- rdfifo.vhd
-- \ rpfifo_top.vhd
-- \ ipif_control_rd.vhd
-- \ rdpfifo_dp_cntl.vhd
-- \
-- \ dp512x32_v3_2_rden_ve.edn
-- \ or
-- \ dp512x32_v3_2_rden_vii.edn
-- \
-- \
-- \-- wrfifo.vhd
-- \ wpfifo_top.vhd
-- \ ipif_control_wr.vhd
-- \ wrpfifo_dp_cntl.vhd
-- \
-- \ dp512x32_v3_2_rden_ve.edn
-- \ or
-- \ dp512x32_v3_2_rden_vii.edn
--
--
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
--
-- FPGA families qvirtex2, qrvirtex2 and virtex4 supported.
--
-- Fixed problem with Mn_BE generation for mastered reads when both DMA
-- and IP masters are present.
--
-- Fixed problem where local master write data could get driven to OPB
-- during a slave write.
--
-- Added IPIC timeout for the local read phase of locally mastered write
-- transactions.
--
-- Drive the low-order two Mn_Abus bits to match the numerically lowest
-- Mn_BE bit that is asserted.
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: <Farrell Ostler, Mike Lovejoy, and Doug Thorpe>
--
-- History:
--
-- D. Thorpe Aug-16-2001 -- Version v1.22a
--
-- DET Aug-23-2001 -- no version change
-- - corrected some file header errors
-- - corrected some generic default values
--
-- DET Aug-29-2001 -- no version change
-- - corrected the spelling of the C_VIRTEX_II parameter
--
-- FO Sep-26-2001
-- - Adapted to the wrapper-removed, generic-adjusted
-- versions of slave_attachment and addr_decode generated
-- by AS.
--
-- ALS Sep-27-2001
-- - added ipif_pkg which contains log2 function
-- - changed the address widths of SRAM, WRFIFO, and RDFIFO to
-- log2 of their size
-- - changed the data widths of SRAM, WRFIFO, and RDFIFO to
-- represent the number of bits instead of the number of bytes
-- and made these constants set to the C_IPIF_DBUS_WIDTH generic
--
-- FO Oct-15-2001
-- - Simplified address calculations for generics.
-- - Removed dependency of arithmetic into msb to get past XST.
--
-- FO Oct-16-2001
-- - Fixed assertion checking low-order zeroes for C_DEV_BASEADDR.
--
-- FO Dec-03-2001
-- - Added a commented-out chipscope ILA at the bottom.
--
-- FO Jan-02-2002
-- - General cleanup
-- - Removal of un-needed comments.
-- - Elimination Bus_Reset_i in favor of Reset.
-- - Where possible made lower-level signal same as top-level
-- signal.
-- - Elimination of C_SL_ATT_ADDR_SEL_WIDTH parameter for sa.
--
-- FO Apr-08-2002
-- - v2.00a version; has
-- - Considerable signal renaming in ipif and submodules to
-- improve naming consistency and remove some synonymous
-- names.
-- - Rework of the generics:
-- - Address Range Definition (ARD) parameters
-- implement the notion of generalized address
-- ranges and properties.
-- - DMA_SG generics now allow n channels of any of the
-- four types.
-- - Several other generic changes, also. See current
-- generic set.
-- - Bus2IP_Reg_rdCE, Bus2IP_Reg_WrCE and Bus2IP_SRAM_CE
-- signals eliminated in favor of Bus2IP_CS, Bus2IP_CE,
-- Bus2IP_RdCE and Bus2IP_WrCE, which are the decode
-- signals for generalized Address Range Definitions.
-- - Addr_decode replaced by address_decode, which handles
-- the generalized address ranges.
-- - Revised interrupt_control module instantiated, allow
-- now for level interrrupts and general edge detect
-- interrupts. Along with original pulse-detect interrupt
-- signal type and true or complement polarity for
-- each type, there are now 6 kinds of interrupt signals
-- that can be specified for the IP2Bus_IntrEvent
-- signals.
-- - ipif_steer module added to allow for multiple IPIF
-- dwidth sizes.
--
-- FO Apr-08-2002 Synplify 6.2 workaround.
-- Removal of 'length and function calls
-- in component port declarations.
--
-- FO Jun-04-2002
-- - Added generic C_ARD_DEPENDENT_PROPS_ARRAY and signal
-- IP2Bus_PostedWrInh. The function associated with
-- the signal is not yet implemented, however.
--
-- FO Jun-06-2002
-- - Corrected WFIFO2IP_Occupancy and RFIFO2IP_Vacancy
-- to adjust their vector widths to the FIFO parameters
-- passed in through C_ARD_DEPENDENT_PROPS_ARRAY.
--
-- FO Jun-07-2002
-- - Corrected the various vacancy and occupancy signals
-- to be compatible with FIFO capacity and read and
-- write width parameters.
--
-- FO Jun-24-2002
-- - Added FIFO parameters for INCLUDE_PACKET_MODE
-- and INCLUDE_VACANCY.
-- - Implemented dynamic byte-enable capability.
--
-- FO Aug-08-2002
-- - Fixed to set C_VIRTEX_II generic for FIFOs to true when
-- C_FAMILY is virtex2p.
--
-- FLO (FO) Aug-12-2002
-- - Using bits_needed_for_vac and bits_needed_for_occ now
-- for vacancy and occupancy vecter-width calculations.
--
-- FLO Aug-29-2002
-- - Up to now, the OPB_IPIF implementation has had a
-- wrapper that mapped a handful of boolean generics to
-- integers used as booleans. This was to comply with
-- some CoreGen restrictions on generics. The wrapper
-- was opb_ipif.vhd and it wrapped the implementation
-- in ipif.vhd.
--
-- Now, leaving opb_ipif.vhd as the top-level interface, the
-- extra level is removed and ipif.vhd is subsumed into
-- opb_ipif.vhd. This includes replacing the opb_ipif.vhd
-- file header--of which this is a part--with the ipif.vhd
-- file header, edited to replace "ipif" by "opb_ipif".
--
-- FLO Sep-05-2002
-- - Added default values for input ports.
-- - Added signal OPB_timeout to the port list of the
-- instantiation of the slave_attachment.
--
-- ~~~~~~
-- FLO 09/10/02
-- ^^^^^^
-- Added port signal Bus2IP_LocalMstTrans. This signal is a qualifier
-- valid during any IPIC transfer. It is asserted during an IPIC
-- transfer if and only if the transfer is taking place as part of
-- a locally initiated master transaction. Local master transactions
-- can be initiated either by an IPIF DMA[SG] engine or a IP-core
-- master, if either or both are present. If there is no IPIC
-- transfer in progress, the value of Bus2IP_LocalMstTrans may be
-- arbitrary.
-- ~~~~~~
-- FLO 09/23/02
-- ^^^^^^
-- - Substituted the port signal Bus2IP_IPMstTrans for the
-- recently added Bus2IP_LocalMstTrans. The replaced signal
-- qualified the IPIC transaction as being due to either the
-- IP-core master or the DMA master. The new signal qualifies
-- the IPIC transaction as being due to the IP-core master, only.
--
-- - Added qualification by "not(Mstr_sel_ma)" to signals
-- Bus2IP_MstRetry, Bus2IP_MstTimeOut and Bus2IP_MstLastAck.
-- ~~~~~~
-- FLO 10/30/02
-- ^^^^^^
-- - Bus2IP_RdReq signal to the read fifo is gated off for the
-- cycle following the falling edge of opb_seqaddr. This is needed
-- because Bus2IP_RdReq was generalized to handle cases where
-- the IP2Bus_RdAck signal throttles and doesn't complete a read
-- on every cycle of a burst.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added signal SA2MA_PostedWrInh, from slave_attachment to
-- master_attachment.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added generic C_MASTER_ARB_MODEL, which allows for user-parameterized
-- arbitration behavior when there are both DMA and IP masters. Supports
-- fair, DMA-priority and IP-priority modes.
-- ~~~~~~
-- FLO 05/15/03
-- ^^^^^^
-- Now passing the C_ARD_ADDR_RANGE_ARRAY generic to the slave attachment.
-- ~~~~~~
-- FLO 05/18/03
-- ^^^^^^
-- Replaced the C_DMA_ALLOW_BURST parameter by C_DMA_BURST_SIZE.
-- This parameter can be set to 1 to disable burst or to some power
-- of two to enable DMA to use bursts of that size.
-- The default is for DMA to use bursts of 16.
-- Also added parameter C_DMA_SHORT_BURST_REMAINDER, which controls
-- whether DMA remainders are transferred as a short burst or as
-- a sequence of single transactions.
-- ~~~~~~
-- FO May-22-2003
-- ^^^^^^
-- - Fixed to set C_VIRTEX_II generic for FIFOs to true when
-- C_FAMILY is spartan3.
-- ~~~~~~
-- GAB April-28-2004
-- ^^^^^^
-- - Updated C_VIRTEX_II to support VIRTEX4, QVIRTEX2, and QRVIRTEX2
-- - Added change log
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- - An IPIC read timeout function was added to the slave_attachment, its
-- use was added in the master attachment, and the connection of the
-- corresponding new signal SA2MA_TimeOut to master and slave
-- attachments is done here in opb_ipif. The timeout can detect a hung
-- IPIC read occurring as the slave attachment reads into its read
-- buffer in support of a local master write OPB transaction. When
-- SA2MA_TimeOut asserts, the master_attachment terminates the
-- local master transaction with Bus2IP_MstTimeOut. The timeout
-- function can be supressed by assertion of IP2Bus_ToutSup.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added signal MA2SA_RSRA (retained_state_retry_active).
-- Inhibit the slave attachement from reseting its count of transfers
-- left to complete a burst if in retained-state retry.
-- Fixes bug that could manifest as spurious writes in the local
-- device under a certain pattern of unrelated OPB activity.
-- ~~~~~~
-- FLO 08/20/2004
-- ^^^^^^
-- Fixed bug wherein unrelated OPB activity could cause an erroneous delay
-- in generation of the Bus2IP_DeviceSel during locally mastered write
-- transactions. An observed failure mode was the CE for a single IPIC read
-- being correspondingly delayed and, therefore, not being asserted
-- concurrently with the RdReq pulse.
-- ~~~~~~
-- FLO 08/25/2004
-- ^^^^^^
-- Changed bus2ip_rdreq_rfifo to be qualified by opb_busy. Because
-- opb_busy is only available in the slave_attachment, moved
-- generation bus2ip_rdreq_rfifo to the slave_attachment.
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added signal SA2MA_BufOccMinus1 and connected it to master and
-- slave attachments. This signal is used to help implement allowance of
-- arbitrary IPIC read retries when getting locally mastered write data
-- ready.
-- ~~~~~~
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.family.virtex2;
use proc_common_v1_00_b.family.derived;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RST;
use ipif_common_v1_00_d.ipif_pkg.IPIF_INTR;
use ipif_common_v1_00_d.ipif_pkg.IPIF_DMA_SG;
use ipif_common_v1_00_d.ipif_pkg.IPIF_WRFIFO_DATA;
use ipif_common_v1_00_d.ipif_pkg.IPIF_WRFIFO_REG;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RDFIFO_DATA;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RDFIFO_REG;
use ipif_common_v1_00_d.ipif_pkg.USER_00;
use ipif_common_v1_00_d.ipif_pkg.calc_num_ce;
use ipif_common_v1_00_d.ipif_pkg.calc_start_ce_index;
use ipif_common_v1_00_d.ipif_pkg.find_ard_id;
use ipif_common_v1_00_d.ipif_pkg.get_id_index;
use ipif_common_v1_00_d.ipif_pkg.get_min_dwidth;
use ipif_common_v1_00_d.ipif_pkg.DEPENDENT_PROPS_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.FIFO_CAPACITY_BITS;
use ipif_common_v1_00_d.ipif_pkg.WR_WIDTH_BITS;
use ipif_common_v1_00_d.ipif_pkg.RD_WIDTH_BITS;
use ipif_common_v1_00_d.ipif_pkg.EXCLUDE_PACKET_MODE;
use ipif_common_v1_00_d.ipif_pkg.EXCLUDE_VACANCY;
use ipif_common_v1_00_d.ipif_pkg.bits_needed_for_vac;
use ipif_common_v1_00_d.ipif_pkg.bits_needed_for_occ;
use ipif_common_v1_00_d.ipif_pkg.get_id_index_iboe;
use ipif_common_v1_00_d.dma_sg_pkg.all;
use ipif_common_v1_00_d.dma_sg_cmp.all;
entity opb_ipif is
generic (
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( IPIF_RST, -- 2
USER_00 -- 100
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_1100", -- USER_00
x"0000_0000_6000_11FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_RST
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 1, -- IPIF_RST
17 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= ( 0 => (others => 0),
1 => (others => 0)
);
-- Properties depending on the address range (AR) type.
--
-- AR Type Properties (use these index constants, de-
-- ------- ---------- fined in ipif_pkg, in aggregates).
--
-- IPIF_WRFIFO_DATA or FIFO_CAPACITY_BITS
-- IPIF_RDFIFO_DATA WR_WIDTH_BITS
-- RD_WIDTH_BITS
C_DEV_BLK_ID : INTEGER := 1;
-- Platform Builder Assiged Device ID number (unique
-- for each device)
C_DEV_MIR_ENABLE : integer := 0;
-- Used to Enable/Disable Module ID functions
C_DEV_BURST_ENABLE : INTEGER := 0;
-- Burst Enable for IPIF Interface
C_DEV_MAX_BURST_SIZE : INTEGER := 64;
-- Maximum burst size to be supported (in bytes)
C_INCLUDE_DEV_ISC : INTEGER := 1;
-- 'true' specifies that the full device interrupt
-- source controller structure will be included;
-- 'false' specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller
C_INCLUDE_DEV_PENCODER : integer := 0;
-- 'true' will include the Device IID in the IPIF Interrupt
-- function
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
-- One entry for each IP interrupt signal, with the
-- signal type for each signal given by the value
-- in the corresponding position. (See above.)
C_IP_MASTER_PRESENT : integer := 0;
-- 'true' specifies that the IP has Bus Master capability
C_MASTER_ARB_MODEL : integer := 0;
-- Arbitration scheme if both DMA and IP masters are present.
-- 0:FAIR 1:DMA_PRIORITY 2:IP_PRIORITY
-----------------------------------------------------------------------------
-- The parameters with names starting with 'C_DMA' need only be specified if
-- one of the address ranges is for the optional DMA[SG] controller, i.e. one
-- range of type IPIF_DMA_SG is included in C_ARD_ID_ARRAY (see above).
-- If DMA[SG] is included, then the number of channels and the
-- parameterizeable properties of each Channel are specified in the arrays,
-- below.
-----------------------------------------------------------------------------
C_DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE := (2,
3
);
-- One entry in the array for each channel, encoded as
-- 0 = simple DMA, 1 = simple sg, 2 = pkt tx SG, 3 = pkt rx SG
C_DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE := (11,
11
);
-- One entry in the array for each channel.
-- Gives the number of bits needed to specify the maximum DMA transfer
-- length, in bytes, for the channel.
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE := (x"00000000_00000000",
x"00000000_00000000"
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be "zero".
-- If the channel type is 2 or 3 (packet channel),
-- the value should give the address of the packet-length FIFO associated
-- with the channel.
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=(x"00000000_00000000",
x"00000000_00000000"
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be "zero".
-- If the channel type is 2 or 3 (packet channel),
-- the value should give the address of the packet-status FIFO associated
-- with the channel.
C_DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=(0,
0
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be 0 for the
-- channel.
-- If the channel type is 2 or 3, the channel is a packet channel and
-- the value 1 specifies that interrupt-coalescing features are
-- to be implemented for the channel. The value 0 declines the features.
C_DMA_BURST_SIZE: integer := 16; -- Must be a power of 2
-- Gives the size of burst that DMA uses to tranfer data on the bus.
-- A value of one causes DMA to use single transactions (burst disabled).
C_DMA_SHORT_BURST_REMAINDER: integer := 0;
-- When 0, any DMA data remaining that is less than a burst size will be
-- transferred as a series of single transactions.
-- When 1, remaining data is tranferred as a short burst.
C_DMA_PACKET_WAIT_UNIT_NS : INTEGER := 1000000;
-- Gives the unit for timing pack-wait bounds for all channels
-- with interrupt coalescing. (Usually left at default value.);
-- Needs to be specified only if at least one channel is of type
-- 2 or 3 with interrupt coalescing and there is a need
-- to deviate from the nominal unit of 1 ms (for example,
-- to facilitate testing by simulation).
C_OPB_AWIDTH : INTEGER := 32;
-- width of OPB Address Bus (in bits)
C_OPB_DWIDTH : INTEGER := 32;
-- Width of the OPB Data Bus (in bits)
C_OPB_CLK_PERIOD_PS : INTEGER := 10000;
-- The period of the OPB Bus clock in ps (10000 = 10ns)
C_IPIF_DWIDTH : INTEGER := 32;
-- Set this equal to C_OPB_DWIDTH
C_FAMILY : string := "virtexe"
);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1 ) := (others => '0');
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1 ) := (others => '0');
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1 );
Mn_ABus : out std_logic_vector(0 to C_OPB_AWIDTH - 1 );
IP2Bus_Addr : in std_logic_vector(0 to C_OPB_AWIDTH - 1 ) := (others => '0');
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH - 1 );
Bus2IP_Data : out std_logic_vector(0 to C_IPIF_DWIDTH - 1 );
Bus2IP_RNW : out std_logic;
Bus2IP_CS : Out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Data : in std_logic_vector(0 to C_IPIF_DWIDTH - 1 ) := (others => '0');
IP2Bus_WrAck : in std_logic := '0';
IP2Bus_RdAck : in std_logic := '0';
IP2Bus_Retry : in std_logic := '0';
IP2Bus_Error : in std_logic := '0';
IP2Bus_ToutSup : in std_logic := '0';
IP2Bus_PostedWrInh : in std_logic := '0';
IP2DMA_RxLength_Empty : in std_logic := '0';
IP2DMA_RxStatus_Empty : in std_logic := '0';
IP2DMA_TxLength_Full : in std_logic := '0';
IP2DMA_TxStatus_Empty : in std_logic := '0';
IP2IP_Addr : in std_logic_vector(0 to C_OPB_AWIDTH - 1 )
:= (others => '0');
IP2RFIFO_Data : in std_logic_vector(0 to 31 ) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
IP2Bus_MstBE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 ) := (others => '0');
IP2Bus_MstWrReq : in std_logic := '0';
IP2Bus_MstRdReq : in std_logic := '0';
IP2Bus_MstBurst : in std_logic := '0';
IP2Bus_MstBusLock : in std_logic := '0';
Bus2IP_MstWrAck : out std_logic;
Bus2IP_MstRdAck : out std_logic;
Bus2IP_MstRetry : out std_logic;
Bus2IP_MstError : out std_logic;
Bus2IP_MstTimeOut : out std_logic;
Bus2IP_MstLastAck : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
Bus2IP_WrReq : out std_logic;
Bus2IP_RdReq : out std_logic;
Bus2IP_IPMstTrans : out std_logic;
Bus2IP_Burst : out std_logic;
Mn_request : out std_logic;
Mn_busLock : out std_logic;
Mn_select : out std_logic;
Mn_RNW : out std_logic;
Mn_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
Mn_seqAddr : out std_logic;
OPB_MnGrant : in std_logic := '0';
OPB_xferAck : in std_logic := '0';
OPB_errAck : in std_logic := '0';
OPB_retry : in std_logic := '0';
OPB_timeout : in std_logic := '0';
Freeze : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out
std_logic_vector (
0 to
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA)
)
) - 1
);
RFIFO2IP_WrAck : out std_logic;
OPB_select : in std_logic := '0';
OPB_RNW : in std_logic := '0';
OPB_seqAddr : in std_logic := '0';
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 ) := (others => '0');
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
WFIFO2IP_AlmostEmpty : out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to 31 );
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out
std_logic_vector (
0 to
bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
) - 1
);
WFIFO2IP_RdAck : out std_logic;
Bus2IP_Clk : out std_logic;
Bus2IP_DMA_Ack : out std_logic;
Bus2IP_Freeze : out std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Clk : in std_logic := '0';
IP2Bus_DMA_Req : in std_logic := '0';
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1 )
:= (others => '0');
IP2INTC_Irpt : out std_logic;
OPB_Clk : in std_logic := '0';
Reset : in std_logic := '0'
);
end opb_ipif;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
architecture implementation of opb_ipif is
constant ZEROES : std_logic_vector(0 to 256) := (others => '0');
-- MIR Constants
constant IPIF_MAJOR_VERSION : INTEGER range 0 to 15 := 2;
-- set Major Version of this IPIF here (reflected in IPIF MIR)
-- Now set to Major Version 2 for v2.00d
constant IPIF_MINOR_VERSION : INTEGER range 0 to 127:= 0;
-- set Minor Version of this IPIF here (reflected in IPIF MIR)
-- Now set to 00
constant IPIF_REVISION : INTEGER := 7;
-- set Revision of this IPIF here (reflected in IPIF MIR)
-- 0 = a, 1 = b, 2 = c, etc.
constant IPIF_TYPE : INTEGER := 1;
-- set interface type for this IPIF here (reflected in IPIF MIR)
-- Always '1' for OPB ipif interface type
function num_CEs(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end num_CEs;
type SLV_OF_BUS_SIZE is array(0 to C_OPB_AWIDTH-1) of std_logic;
function base_address(ard_id: integer)
return SLV_OF_BUS_SIZE is
variable result : SLV_OF_BUS_SIZE
:= (others => '0');
variable id_included: boolean;
variable ar_index: integer;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
ar_index := 2*get_id_index(C_ARD_ID_ARRAY, ard_id);
if id_included then
result := SLV_OF_BUS_SIZE(
C_ARD_ADDR_RANGE_ARRAY(ar_index)
( C_ARD_ADDR_RANGE_ARRAY(0)'length - C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length - 1
)
)
;
end if;
return result;
end base_address;
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_OPB_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_OPB_AWIDTH-1)
:= ara(0)( ara(0)'length-C_OPB_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
-- Other constants
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
constant LOW_ADDR_DECODE_WIDTH : INTEGER
:= C_OPB_AWIDTH - K_DEV_ADDR_DECODE_WIDTH;
constant LOGIC_LOW : std_logic := '0';
constant ZERO_ADDR_PREFIX
: std_logic_vector(0 to 64 - C_OPB_AWIDTH-1)
:= (others => '0');
constant RESET_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INTERRUPT_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant WRFIFO_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_REG)
and find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
constant RDFIFO_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_REG)
and find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
constant DMA_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_DMA_SG);
constant INTERRUPT_REG_NUM : INTEGER := num_CEs(IPIF_INTR);
constant DMA_BASEADDR : std_logic_vector(0 to C_OPB_AWIDTH - 1 )
:= std_logic_vector(base_address(IPIF_DMA_SG));
constant DEV_IS_SLAVE_ONLY : BOOLEAN := not(DMA_PRESENT or
(C_IP_MASTER_PRESENT /= 0));
constant VIRTEX_II : boolean := derived(C_FAMILY, virtex2);
--constant DMA_USE_BURST : BOOLEAN := (C_DMA_ALLOW_BURST /= 0) and
-- (C_DEV_BURST_ENABLE /= 0);
function gate_burst_size(bool: boolean; posit: integer) return positive is
begin
if bool then return posit; else return 1; end if;
end gate_burst_size;
--
constant DMA_BURST_SIZE : positive := gate_burst_size(C_DEV_BURST_ENABLE=1,
C_DMA_BURST_SIZE);
constant NUM_CE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- signal used as a constant (when constant fails to be a globally
-- static expression).
signal CONST_ALL_IP_BYTES_ENABLED :
std_logic_vector(0 to C_IPIF_DWIDTH/8 -1) := (others => '1');
-- Signal declarations
signal Addr_Cntr_ClkEN : std_logic;
signal Addr_Sel : std_logic_vector(0 to 1 );
signal Bus2IP_Addr_i : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal Bus2IP_Addr_sa : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal Bus2IP_BE_sa : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_BE_amx : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_BE_i : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_Burst_i : std_logic;
signal Bus2IP_Clk_i : std_logic;
signal Bus2IP_Data_sa : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Bus2IP_Data_i : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Bus2IP_Freeze_i : std_logic;
signal Bus2IP_MstError_i : std_logic;
signal Bus2IP_MstLastAck_i : std_logic;
signal Bus2IP_MstRdAck_ma : std_logic;
signal Bus2IP_MstRetry_i : std_logic;
signal Bus2IP_MstTimeOut_i : std_logic;
signal Bus2IP_MstWrAck_ma : std_logic;
signal Bus2IP_DeviceSel : std_logic;
signal Bus2IP_RdReq_i : std_logic;
signal Bus2IP_Reset_i : std_logic;
signal Bus2IP_RNW_i : std_logic;
signal Bus2IP_WrReq_i : std_logic;
signal Bus_MnGrant : std_logic;
signal const_zero : std_logic := '0';
signal DMA2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal DMA2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal DMA2Intr_Intr : std_logic_vector(0 to 1 );
signal DMA2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal DMA2Bus_MstBE : std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
signal DMA2Bus_MstNum : STD_LOGIC_VECTOR(0 to
log2(C_DEV_MAX_BURST_SIZE/4+1)-1);
signal DMA2Bus_MstBurst : std_logic;
signal DMA2Bus_MstBusLock : std_logic;
signal DMA2Bus_MstRdReq : std_logic;
signal DMA2Bus_MstWrReq : std_logic;
signal DMA2Bus_Error : std_logic;
signal DMA2Bus_RdAck : std_logic;
signal DMA2Bus_Retry : std_logic;
signal DMA2Bus_ToutSup : std_logic;
signal DMA2Bus_WrAck : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_Error : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal Intr2Bus_Retry : std_logic;
signal Intr2Bus_ToutSup : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal IP2Bus_Data_mx : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal IP2Bus_Data_steer : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal IP2Bus_Error_mx : std_logic;
signal IP2Bus_RdAck_mx : std_logic;
signal IP2Bus_Retry_mx : std_logic;
signal IP2Bus_ToutSup_mx : std_logic;
signal IP2Bus_WrAck_mx : std_logic;
signal IPIF_Lvl_Interrupts : std_logic_vector(0 to 3 );
signal IPIF_Reg_Interrupts : std_logic_vector(0 to 1 );
signal MA2SA_Num : std_logic_vector(0 to log2(C_DEV_MAX_BURST_SIZE/4+1)-1);
signal MA2SA_Rd : std_logic;
signal MA2SA_Select : std_logic;
signal MA2SA_XferAck : std_logic;
signal MA2SA_Retry : std_logic;
signal MA2SA_RSRA : std_logic;
signal Mstr_sel_ma : std_logic;
signal RdFIFO2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal RdFIFO2Intr_DeadLock : std_logic;
signal Reset2Bus_DBus : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal RFIFO2DMA_AlmostEmpty : std_logic;
signal RFIFO2DMA_Empty : std_logic;
signal RFIFO2DMA_Occupancy :
std_logic_vector (
0 to
bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA)
)
) - 1
);
signal RFIFO_Error : std_logic;
signal RFIFO_RdAck : std_logic;
signal RFIFO_Retry : std_logic;
signal RFIFO_ToutSup : std_logic;
signal RFIFO_WrAck : std_logic;
signal Rst2Bus_Error : std_logic;
signal Rst2Bus_RdAck : std_logic;
signal Rst2Bus_Retry : std_logic;
signal Rst2Bus_ToutSup : std_logic;
signal Rst2Bus_WrAck : std_logic;
signal SA2MA_RdRdy : std_logic;
signal SA2MA_WrAck : std_ulogic;
signal SA2MA_Retry : std_logic;
signal SA2MA_Error : std_logic;
signal SA2MA_FifoRd: std_logic;
signal SA2MA_FifoWr: std_logic;
signal SA2MA_FifoBu: std_logic;
signal SA2MA_PostedWrInh: std_logic;
signal SA2MA_TimeOut: std_logic;
signal SA2MA_BufOccMinus1 : std_logic_vector(0 to 4);
signal WFIFO2DMA_AlmostFull : std_logic;
signal WFIFO2DMA_Full : std_logic;
signal WFIFO2DMA_vacancy :
std_logic_vector (
0 to
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
) - 1
);
signal WFIFO_Error : std_logic;
signal WFIFO_RdAck : std_logic;
signal WFIFO_Retry : std_logic;
signal WFIFO_ToutSup : std_logic;
signal WFIFO_WrAck : std_logic;
signal WrFIFO2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal WrFIFO2Intr_DeadLock : std_logic;
signal CS_Out : std_logic_vector(0 to (C_ARD_ADDR_RANGE_ARRAY'length)/2 - 1);
signal CE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal RdCE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal WrCE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal cs_dwidth: std_logic_vector(0 to 2);
signal bus2ip_localmsttrans: std_logic;
signal devicesel_inh_opb : std_logic;
signal devicesel_inh_mstr : std_logic;
signal bus2ip_rdreq_rfifo: std_logic;
-------------------------------------------------------------------------------
-- components
constant NUM_CE_NEEDED : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_CS_NEEDED : integer := C_ARD_ADDR_RANGE_ARRAY'LENGTH/2;
constant NUM_IP_INTR_SIGS : integer := C_IP_INTR_MODE_ARRAY'length;
-------------------------------------------------------------------------------
-- Instantiate the components
-------------------------------------------------------------------------------
begin
-- Perform consistency checks
-- synthesis translate_off
-- Any parameter consistency checks should be implemented here.
-- synthesis translate_on
------------------------------------------------------------------------------
INCLUDE_MASTER : if (DEV_IS_SLAVE_ONLY = false) generate
I_MASTER_ATTACHMENT: entity opb_ipif_v2_00_h.master_attachment
generic map (C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_DMA_ONLY => DMA_PRESENT and not (C_IP_MASTER_PRESENT /= 0),
C_IP_MSTR_ONLY => not DMA_PRESENT and (C_IP_MASTER_PRESENT /= 0),
C_MASTER_ARB_MODEL => C_MASTER_ARB_MODEL)
port map (
Reset => Reset,
--OPB ports
OPB_Clk => Bus2IP_Clk_i,
OPB_MnGrant => OPB_MnGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_timeout => OPB_timeout,
OPB_retry => OPB_retry,
--Master Attachment to OPB ports
Mn_request => Mn_request,
Mn_select => Mn_select,
Mn_RNW => Mn_RNW,
Mn_seqAddr => Mn_seqAddr,
Mn_busLock => Mn_busLock,
Mn_BE => Mn_BE,
Mn_ABus => Mn_ABus,
--Master Attachment to SA ports
Bus_MnGrant => Bus_MnGrant,
MA2SA_Select => MA2SA_Select,
MA2SA_XferAck => MA2SA_XferAck,
MA2SA_Retry => MA2SA_Retry,
MA2SA_RSRA => MA2SA_RSRA,
MA2SA_Rd => MA2SA_Rd,
MA2SA_Num => MA2SA_Num,
SA2MA_RdRdy => SA2MA_RdRdy,
SA2MA_WrAck => SA2MA_WrAck,
SA2MA_Retry => SA2MA_Retry,
SA2MA_Error => SA2MA_Error,
SA2MA_FifoRd => SA2MA_FifoRd,
SA2MA_FifoWr => SA2MA_FifoWr,
SA2MA_FifoBu => SA2MA_FifoBu,
SA2MA_PostedWrInh => SA2MA_PostedWrInh,
SA2MA_TimeOut => SA2MA_TimeOut,
SA2MA_BufOccMinus1 => SA2MA_BufOccMinus1,
--Master Attachment from IP ports
Mstr_sel_ma => Mstr_sel_ma,
--Master Attachment from IP ports
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
--Master Attachment to IP ports
Bus2IP_MstWrAck_ma => Bus2IP_MstWrAck_ma,
Bus2IP_MstRdAck_ma => Bus2IP_MstRdAck_ma,
Bus2IP_MstRetry => Bus2IP_MstRetry_i,
Bus2IP_MstError => Bus2IP_MstError_i,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut_i,
Bus2IP_MstLastAck => Bus2IP_MstLastAck_i,
--Master Attachment from DMA ports
DMA2Bus_Addr => DMA2Bus_Addr,
DMA2Bus_MstBE => DMA2Bus_MstBE,
DMA2Bus_MstWrReq => DMA2Bus_MstWrReq,
DMA2Bus_MstRdReq => DMA2Bus_MstRdReq,
DMA2Bus_MstNum => DMA2Bus_MstNum,
DMA2Bus_MstBurst => DMA2Bus_MstBurst,
DMA2Bus_MstBusLock => DMA2Bus_MstBusLock );
end generate INCLUDE_MASTER;
REMOVE_MASTER : if (DEV_IS_SLAVE_ONLY = true) generate
Bus2IP_MstError_i <= '0';
Bus2IP_MstLastAck_i <= '0';
Bus2IP_MstRdAck_ma <= '0';
Bus2IP_MstRetry_i <= '0';
Bus2IP_MstTimeOut_i <= '0';
Bus2IP_MstWrAck_ma <= '0';
Bus_MnGrant <= '0';
MA2SA_Num <= (others => '0');
MA2SA_Rd <= '0';
MA2SA_Select <= '0';
MA2SA_XferAck <= '0';
MA2SA_Retry <= '0';
MA2SA_RSRA <= '0';
Mn_ABus <= (others => '0');
Mn_BE <= (others => '0');
Mn_busLock <= '0';
Mn_request <= '0';
Mn_RNW <= '0';
Mn_select <= '0';
Mn_seqAddr <= '0';
Mstr_sel_ma <= '0';
end generate REMOVE_MASTER;
------------------------------------------------------------------------------
I_ADDRESS_DECODER: entity opb_ipif_v2_00_h.address_decoder
generic map (
C_BUS_AWIDTH => LOW_ADDR_DECODE_WIDTH,
C_USE_REG_OUTPUTS => true,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => C_ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Bus_clk => Bus2IP_Clk_i,
Bus_rst => Reset,
Address_In => Bus2IP_Addr_i( C_OPB_AWIDTH-LOW_ADDR_DECODE_WIDTH
to C_OPB_AWIDTH-1
),
Address_Valid => Bus2IP_DeviceSel,
Bus_RNW => Bus2IP_RNW_i,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
Bus2IP_Burst => Bus2IP_Burst_i,
Addr_Match => open,
CS_Out => CS_Out,
CS_Size => cs_dwidth,
CE_Out => CE_Out,
RdCE_Out => RdCE_Out,
WrCE_Out => WrCE_Out,
Devicesel_inh_opb => devicesel_inh_opb,
Devicesel_inh_mstr => devicesel_inh_mstr
);
Bus2IP_CS <= CS_Out;
Bus2IP_CE <= CE_Out;
Bus2IP_RdCE <= RdCE_Out;
Bus2IP_WrCE <= WrCE_Out;
I_IP2BUS_SRMUX: entity opb_ipif_v2_00_h.ip2bus_srmux_blk
port map (
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
DMA2Bus_WrAck => DMA2Bus_WrAck,
Intr2Bus_Error => Intr2Bus_Error,
Intr2Bus_RdAck => Intr2Bus_RdAck,
Intr2Bus_Retry => Intr2Bus_Retry,
Intr2Bus_ToutSup => Intr2Bus_ToutSup,
Intr2Bus_WrAck => Intr2Bus_WrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_ToutSup => IP2Bus_ToutSup,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
RFIFO_Error => RFIFO_Error,
RFIFO_RdAck => RFIFO_RdAck,
RFIFO_Retry => RFIFO_Retry,
RFIFO_ToutSup => RFIFO_ToutSup,
RFIFO_WrAck => RFIFO_WrAck,
Rst2Bus_Error => Rst2Bus_Error,
Rst2Bus_RdAck => Rst2Bus_RdAck,
Rst2Bus_Retry => Rst2Bus_Retry,
Rst2Bus_ToutSup => Rst2Bus_ToutSup,
Rst2Bus_WrAck => Rst2Bus_WrAck,
WFIFO_Error => WFIFO_Error,
WFIFO_RdAck => WFIFO_RdAck,
WFIFO_Retry => WFIFO_Retry,
WFIFO_ToutSup => WFIFO_ToutSup,
WFIFO_WrAck => WFIFO_WrAck);
I_BUS2IP_AMUX: entity opb_ipif_v2_00_h.bus2ip_amux
generic map (
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH)
port map (
Bus2IP_Reset_i => Reset,
Bus2IP_Clk_i => Bus2IP_Clk_i,
Mstr_sel_ma => Mstr_sel_ma,
Addr_Cntr_ClkEN => Addr_Cntr_ClkEN,
Addr_Sel => Addr_Sel,
Bus2IP_Addr_sa => Bus2IP_Addr_sa,
IP2IP_Addr => IP2IP_Addr,
DMA2IP_Addr => DMA2IP_Addr,
Bus2IP_Addr_i => Bus2IP_Addr_i,
Bus2IP_BE_sa => Bus2IP_BE_sa,
IP2IP_BE => CONST_ALL_IP_BYTES_ENABLED,
DMA2IP_BE => CONST_ALL_IP_BYTES_ENABLED,
Bus2IP_BE_i => Bus2IP_BE_amx
);
I_IP2BUS_DMUX: entity opb_ipif_v2_00_h.ip2bus_dmux_blk
generic map (C_DBUS_WIDTH => C_OPB_DWIDTH)
port map (
DMA2Bus_Data => DMA2Bus_Data(0 to C_OPB_DWIDTH - 1),
Intr2Bus_DBus => Intr2Bus_DBus(0 to C_OPB_DWIDTH - 1),
IP2Bus_Data => IP2Bus_Data(0 to C_IPIF_DWIDTH - 1),
IP2Bus_Data_mx => IP2Bus_Data_mx(0 to C_OPB_DWIDTH - 1),
Reset2Bus_Data => Reset2Bus_DBus(0 to C_OPB_DWIDTH - 1),
RFIFO2Bus_Data => RdFIFO2Bus_Data(0 to C_OPB_DWIDTH - 1),
WFIFO2Bus_Data => WrFIFO2Bus_Data(0 to C_OPB_DWIDTH - 1));
I_SLAVE_ATTACHMENT: entity opb_ipif_v2_00_h.slave_attachment
generic map (
C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_DEV_ADDR_DECODE_WIDTH => K_DEV_ADDR_DECODE_WIDTH,
C_DEV_BASEADDR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length -1
), -- Any baseaddr from array will serve to
-- supply the K_DEV_ADDR_DECODE_WIDTH
-- high-order bits.
C_DEV_BURST_ENABLE => (C_DEV_BURST_ENABLE /= 0),
C_DEV_IS_SLAVE_ONLY => DEV_IS_SLAVE_ONLY,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY
)
port map (
Reset => Reset,
OPB_Clk => Bus2IP_Clk_i,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_SeqAddr => OPB_SeqAddr,
OPB_BE => OPB_BE(0 to C_OPB_DWIDTH/8 - 1),
OPB_ABus => OPB_ABus(0 to C_OPB_AWIDTH - 1),
OPB_DBus => OPB_DBus(0 to C_OPB_DWIDTH - 1),
OPB_timeout => OPB_timeout,
Sln_DBus => Sln_DBus(0 to C_OPB_DWIDTH - 1),
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_toutSup => Sln_toutSup,
Sln_retry => Sln_retry,
Bus_MnGrant => Bus_MnGrant,
MA2SA_Select => MA2SA_Select,
MA2SA_XferAck => MA2SA_XferAck,
MA2SA_Retry => MA2SA_Retry,
MA2SA_RSRA => MA2SA_RSRA,
MA2SA_Rd => MA2SA_Rd,
MA2SA_Num => MA2SA_Num,
SA2MA_RdRdy => SA2MA_RdRdy,
SA2MA_WrAck => SA2MA_WrAck,
SA2MA_Retry => SA2MA_Retry,
SA2MA_Error => SA2MA_Error,
SA2MA_FifoRd => SA2MA_FifoRd,
SA2MA_FifoWr => SA2MA_FifoWr,
SA2MA_FifoBu => SA2MA_FifoBu,
SA2MA_PostedWrInh => SA2MA_PostedWrInh,
SA2MA_TimeOut => SA2MA_TimeOut,
SA2MA_BufOccMinus1 => SA2MA_BufOccMinus1,
Addr_Sel => Addr_Sel(0 to 1),
Addr_Cntr_ClkEn => Addr_Cntr_ClkEN,
Bus2IP_Burst => Bus2IP_Burst_i ,
Bus2IP_RNW => Bus2IP_RNW_i ,
Bus2IP_BE_sa => Bus2IP_BE_sa(0 to C_IPIF_DWIDTH/8 - 1),
Bus2IP_Addr_sa => Bus2IP_Addr_sa,
Bus2IP_Data => Bus2IP_Data_sa(0 to C_IPIF_DWIDTH - 1),
Bus2IP_DeviceSel=> Bus2IP_DeviceSel,
Bus2IP_WrReq => Bus2IP_WrReq_i,
Bus2IP_RdReq => Bus2IP_RdReq_i,
Bus2IP_RdReq_rfifo => bus2ip_rdreq_rfifo,
Bus2IP_LocalMstTrans => bus2ip_localmsttrans,
IP2Bus_Data_mx => IP2Bus_Data_steer(0 to C_IPIF_DWIDTH - 1),
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_PostedWrInh => IP2Bus_PostedWrInh,
Devicesel_inh_opb_out => devicesel_inh_opb,
Devicesel_inh_mstr_out => devicesel_inh_mstr
);
Bus2IP_IPMstTrans <= bus2ip_localmsttrans and not(Mstr_sel_ma);
I_IPIF_STEER : entity ipif_common_v1_00_d.IPIF_Steer
generic map (
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => Bus2IP_Data_sa, -- in std_logic_vector(0 to C_DWIDTH-1)
Rd_Data_In => IP2Bus_Data_mx, -- in std_logic_vector(0 to C_DWIDTH-1)
Addr => Bus2IP_Addr_i, -- in std_logic_vector(0 to C_AWIDTH-1)
BE_In => Bus2IP_BE_amx, -- in std_logic_vector(0 to C_DWIDTH/8-1)
Decode_size => cs_dwidth, -- in std_logic_vector(0 to 2)
Wr_Data_Out => Bus2IP_Data_i, -- out std_logic_vector(0 to C_DWIDTH-1)
Rd_Data_Out => IP2Bus_Data_steer, -- out std_logic_vector(0 to C_DWIDTH-1)
BE_Out => Bus2IP_BE_i -- out std_logic_vector(0 to C_DWIDTH/8-1)
);
--------------------------------------------------------------------------------
INCLUDE_RESET : if (RESET_PRESENT) generate
Constant RESET_NAME_INDEX : integer := get_id_index(
C_ARD_ID_ARRAY,
IPIF_RST
);
Constant RESET_REG_CE_INDEX : integer := calc_start_ce_index(
C_ARD_NUM_CE_ARRAY,
RESET_NAME_INDEX
);
begin
I_RESET_CONTROL: entity opb_ipif_v2_00_h.reset_control
generic map (C_IPIF_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_IPIF_TYPE => IPIF_TYPE,
C_IPIF_BLK_ID => C_DEV_BLK_ID,
C_IPIF_REVISION => IPIF_REVISION,
C_IPIF_MINOR_VERSION => IPIF_MINOR_VERSION,
C_IPIF_MAJOR_VERSION => IPIF_MAJOR_VERSION,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH)
port map (
Bus2IP_Clk_i => Bus2IP_Clk_i,
Bus_DBus => Bus2IP_Data_i(0 to C_OPB_DWIDTH - 1),
IP_Reset_RdCE => RdCE_Out(RESET_REG_CE_INDEX),
IP_Reset_WrCE => WrCE_Out(RESET_REG_CE_INDEX),
Reset => Reset,
Reset2Bus_DBus => Reset2Bus_DBus(0 to C_OPB_DWIDTH - 1),
Reset2Bus_Error => Rst2Bus_Error,
Reset2Bus_RdAck => Rst2Bus_RdAck,
Reset2Bus_Retry => Rst2Bus_Retry,
Reset2Bus_ToutSup => Rst2Bus_ToutSup,
Reset2Bus_WrAck => Rst2Bus_WrAck,
Reset2IP_Reset => bus2ip_reset_i);
end generate INCLUDE_RESET;
REMOVE_RESET : if (not RESET_PRESENT) generate
Reset2Bus_DBus <= (others => '0') ;
Rst2Bus_Error <= '0';
Rst2Bus_RdAck <= '0';
Rst2Bus_Retry <= '0';
Rst2Bus_ToutSup <= '0';
Rst2Bus_WrAck <= '0';
Bus2IP_Reset_i <= Reset; -- No sw reset capability since
-- reset_control is excluded.
end generate REMOVE_RESET;
-------------------------------------------------------------------------------
INCLUDE_INTERRUPT : if (INTERRUPT_PRESENT) generate
Constant INDEX : integer := get_id_index(C_ARD_ID_ARRAY,IPIF_INTR);
Constant CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
INDEX);
begin
I_INTERRUPT_CONTROL: entity ipif_common_v1_00_d.interrupt_control
generic map (C_INTERRUPT_REG_NUM => INTERRUPT_REG_NUM,
C_NUM_IPIF_IRPT_SRC => 4,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => (C_INCLUDE_DEV_PENCODER /= 0) and
(C_INCLUDE_DEV_ISC /= 0),
C_INCLUDE_DEV_ISC => (C_INCLUDE_DEV_ISC /= 0),
C_IRPT_DBUS_WIDTH => C_IPIF_DWIDTH)
port map (
Bus2IP_Clk_i => Bus2IP_Clk_i,
Bus2IP_Data_sa => Bus2IP_Data_i(0 to C_OPB_DWIDTH - 1),
Bus2IP_RdReq_sa => Bus2IP_RdReq_i,
Bus2IP_Reset_i => Bus2IP_Reset_i,
Bus2IP_WrReq_sa => Bus2IP_WrReq_i,
Interrupt_RdCE => RdCE_Out(CE_INDEX to CE_INDEX+INTERRUPT_REG_NUM - 1),
Interrupt_WrCE => WrCE_Out(CE_INDEX to CE_INDEX+INTERRUPT_REG_NUM - 1),
Intr2Bus_DBus => Intr2Bus_DBus(0 to C_OPB_DWIDTH - 1),
Intr2Bus_DevIntr => Intr2Bus_DevIntr,
Intr2Bus_Error => Intr2Bus_Error,
Intr2Bus_RdAck => Intr2Bus_RdAck,
Intr2Bus_Retry => Intr2Bus_Retry,
Intr2Bus_ToutSup => Intr2Bus_ToutSup,
Intr2Bus_WrAck => Intr2Bus_WrAck,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
IPIF_Lvl_Interrupts => IPIF_Lvl_Interrupts(0 to 3),
IPIF_Reg_Interrupts => IPIF_Reg_Interrupts(0 to 1));
end generate INCLUDE_INTERRUPT;
REMOVE_INTERRUPT : if (not INTERRUPT_PRESENT) generate
Intr2Bus_DBus <= (others => '0');
Intr2Bus_DevIntr <= IP2Bus_IntrEvent(0);
Intr2Bus_Error <= '0';
Intr2Bus_RdAck <= '0';
Intr2Bus_Retry <= '0';
Intr2Bus_ToutSup <= '0';
Intr2Bus_WrAck <= '0';
end generate REMOVE_INTERRUPT;
------------------------------------------------------------------------------
INCLUDE_RDFIFO : if (RDFIFO_PRESENT) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
signal opb_seqaddr_d1 : std_logic;
begin
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
OPB_SEQADDR_DN_PROC : process (Bus2IP_Clk_i) is
begin
if Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1' then
opb_seqaddr_d1 <= OPB_seqAddr;
end if;
end process;
I_RDFIFO: entity opb_ipif_v2_00_h.rdpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => Bus2IP_Reset_i,
Bus_Clk => Bus2IP_Clk_i,
Bus_RdReq => bus2ip_rdreq_rfifo,
Bus_WrReq => Bus2IP_WrReq_i,
Bus2FIFO_RdCE1 => RdCE_Out(REG_CE_INDEX),
Bus2FIFO_RdCE2 => RdCE_Out(REG_CE_INDEX+1),
Bus2FIFO_RdCE3 => RdCE_Out(DATA_CE_INDEX),
Bus2FIFO_WrCE1 => WrCE_Out(REG_CE_INDEX),
Bus2FIFO_WrCE2 => WrCE_Out(REG_CE_INDEX+1),
Bus2FIFO_WrCE3 => WrCE_Out(DATA_CE_INDEX),
Bus_DBus => Bus2IP_Data_i,
-- Inputs from the IP
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_Data => IP2RFIFO_Data,
-- Outputs to the IP
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty => RFIFO2DMA_AlmostEmpty,
RFIFO2DMA_Empty => RFIFO2DMA_Empty,
RFIFO2DMA_Occupancy => RFIFO2DMA_Occupancy,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => RdFIFO2Intr_DeadLock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => RdFIFO2Bus_Data,
FIFO2Bus_WrAck => RFIFO_WrAck,
FIFO2Bus_RdAck => RFIFO_RdAck,
FIFO2Bus_Error => RFIFO_Error,
FIFO2Bus_Retry => RFIFO_Retry,
FIFO2Bus_ToutSup => RFIFO_ToutSup
);
end generate INCLUDE_RDFIFO;
REMOVE_RDFIFO : if (not RDFIFO_PRESENT) generate
RdFIFO2Bus_Data <= (others => '0');
RdFIFO2Intr_DeadLock <= '0';
RFIFO2DMA_AlmostEmpty <= '0';
RFIFO2DMA_Empty <= '0';
RFIFO2DMA_Occupancy <= (others => '0');
RFIFO2IP_AlmostFull <= '0';
RFIFO2IP_Full <= '0';
RFIFO2IP_Vacancy <= (others => '0');
RFIFO2IP_WrAck <= '0';
RFIFO_Error <= '0';
RFIFO_RdAck <= '0';
RFIFO_Retry <= '0';
RFIFO_ToutSup <= '0';
RFIFO_WrAck <= '0';
end generate REMOVE_RDFIFO;
--------------------------------------------------------------------------------
INCLUDE_WRFIFO : if (WRFIFO_PRESENT) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
begin
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
I_WRPFIFO_TOP: entity opb_ipif_v2_00_h.wrpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => Bus2IP_Reset_i, -- In std_logic;
Bus_clk => Bus2IP_Clk_i, -- In std_logic;
Bus_RdReq => Bus2IP_RdReq_i, -- In std_logic;
Bus_WrReq => Bus2IP_WrReq_i, -- In std_logic;
Bus2FIFO_RdCE1 => RdCE_Out(REG_CE_INDEX),
Bus2FIFO_RdCE2 => RdCE_Out(REG_CE_INDEX+1),
Bus2FIFO_RdCE3 => RdCE_Out(DATA_CE_INDEX),
Bus2FIFO_WrCE1 => WrCE_Out(REG_CE_INDEX),
Bus2FIFO_WrCE2 => WrCE_Out(REG_CE_INDEX+1),
Bus2FIFO_WrCE3 => WrCE_Out(DATA_CE_INDEX),
Bus_DBus => Bus2IP_Data_i, -- In std_logic_vector(0 to C_IPIF_DWIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq => IP2WFIFO_RdReq, -- In std_logic;
IP2WFIFO_RdMark => IP2WFIFO_RdMark, -- In std_logic;
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore, -- In std_logic;
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease, -- In std_logic;
-- Outputs to the IP
WFIFO2IP_Data => WFIFO2IP_Data, -- Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck => WFIFO2IP_RdAck, -- Out std_logic;
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty, -- Out std_logic;
WFIFO2IP_Empty => WFIFO2IP_Empty, -- Out std_logic;
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull => WFIFO2DMA_AlmostFull, -- Out std_logic;
WFIFO2DMA_Full => WFIFO2DMA_Full, -- Out std_logic;
WFIFO2DMA_Vacancy => WFIFO2DMA_Vacancy,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => WrFIFO2Intr_DeadLock, -- Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => WrFIFO2Bus_Data, -- Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
FIFO2Bus_WrAck => WFIFO_WrAck, -- Out std_logic;
FIFO2Bus_RdAck => WFIFO_RdAck, -- Out std_logic;
FIFO2Bus_Error => WFIFO_Error, -- Out std_logic;
FIFO2Bus_Retry => WFIFO_Retry, -- Out std_logic;
FIFO2Bus_ToutSup => WFIFO_ToutSup -- Out std_logic
);
end generate INCLUDE_WRFIFO;
REMOVE_WRFIFO : if (not WRFIFO_PRESENT) generate
WFIFO2DMA_Full <= '0';
WFIFO2DMA_Vacancy <= (others => '0');
WFIFO2IP_AlmostEmpty <= '0';
WFIFO2IP_Data <= (others => '0');
WFIFO2IP_Empty <= '0';
WFIFO2IP_Occupancy <= (others => '0');
WFIFO2IP_RdAck <= '0';
WFIFO_Error <= '0';
WFIFO_RdAck <= '0';
WFIFO_Retry <= '0';
WFIFO_ToutSup <= '0';
WFIFO_WrAck <= '0';
WrFIFO2Bus_Data <= (others => '0');
WrFIFO2Intr_DeadLock <= '0';
end generate REMOVE_WRFIFO;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Include DMA in the IPIF
------------------------------------------------------------------------------
INCLUDE_DMA : if (DMA_PRESENT) generate
Constant DMA_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,IPIF_DMA_SG);
Constant DMA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY, DMA_INDEX);
begin
dma_sg_i1 : dma_sg
generic map (
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_CLK_PERIOD_PS => C_OPB_CLK_PERIOD_PS,
C_PACKET_WAIT_UNIT_NS => C_DMA_PACKET_WAIT_UNIT_NS,
C_DMA_CHAN_TYPE => C_DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH => C_DMA_LENGTH_WIDTH_ARRAY,
C_LEN_FIFO_ADDR => C_DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_STAT_FIFO_ADDR => C_DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_INTR_COALESCE => C_DMA_INTR_COALESCE_ARRAY,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DMA_BASEADDR => ZERO_ADDR_PREFIX & DMA_BASEADDR,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => C_DMA_SHORT_BURST_REMAINDER,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_WFIFO_VACANCY_WIDTH =>
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
)
)
port map (
DMA2Bus_Data => DMA2Bus_Data,
DMA2Bus_Addr => DMA2Bus_Addr,
DMA2Bus_MstBE => DMA2Bus_MstBE,
DMA2Bus_MstWrReq => DMA2Bus_MstWrReq,
DMA2Bus_MstRdReq => DMA2Bus_MstRdReq,
DMA2Bus_MstNum => DMA2Bus_MstNum,
DMA2Bus_MstBurst => DMA2Bus_MstBurst,
DMA2Bus_MstBusLock => DMA2Bus_MstBusLock,
DMA2IP_Addr => DMA2IP_Addr(0 to C_OPB_AWIDTH-3),
DMA2Bus_WrAck => DMA2Bus_WrAck,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
Bus2IP_MstWrAck => Bus2IP_MstWrAck_ma,
Bus2IP_MstRdAck => Bus2IP_MstRdAck_ma,
Mstr_sel_ma => Mstr_sel_ma,
Bus2IP_MstRetry => Bus2IP_MstRetry_i,
Bus2IP_MstError => Bus2IP_MstError_i,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut_i,
Bus2IP_BE => Bus2IP_BE_i,
Bus2IP_WrReq => Bus2IP_WrReq_i,
Bus2IP_RdReq => Bus2IP_RdReq_i,
Bus2IP_Clk => Bus2IP_Clk_i,
Bus2IP_Reset => Bus2IP_Reset_i,
Bus2IP_Freeze => Bus2IP_Freeze_i,
Bus2IP_Addr => Bus2IP_Addr_i(0 to C_OPB_AWIDTH-3),
Bus2IP_Data => Bus2IP_Data_i,
Bus2IP_Burst => Bus2IP_Burst_i,
WFIFO2DMA_Vacancy => WFIFO2DMA_Vacancy,
Bus2IP_MstLastAck => Bus2IP_MstLastAck_i,
DMA_RdCE => RdCE_Out(DMA_CE_INDEX),
DMA_WrCE => WrCE_Out(DMA_CE_INDEX),
IP2DMA_RxStatus_Empty => IP2DMA_RxStatus_Empty,
IP2DMA_RxLength_Empty => IP2DMA_RxLength_Empty,
IP2DMA_TxStatus_Empty => IP2DMA_TxStatus_Empty,
IP2DMA_TxLength_Full => IP2DMA_TxLength_Full,
IP2Bus_DMA_Req => IP2Bus_DMA_Req,
Bus2IP_DMA_Ack => Bus2IP_DMA_Ack,
DMA2Intr_Intr => DMA2Intr_Intr
);
DMA2IP_Addr(C_OPB_AWIDTH-2 to C_OPB_AWIDTH-1) <= (others => '0');
end generate INCLUDE_DMA;
------------------------------------------------------------------------------
-- Don't include DMA in the IPIF . Drive all outputs to zero.
------------------------------------------------------------------------------
REMOVE_DMA : if (not DMA_PRESENT) generate
Bus2IP_DMA_Ack <= '0';
DMA2Bus_Addr <= (others => '0');
DMA2Bus_Data <= (others => '0');
DMA2Intr_Intr <= (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstBE <= (others => '0');
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstBusLock <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstWrReq <= '0';
DMA2Bus_Error <= '0';
DMA2Bus_RdAck <= '0';
DMA2Bus_Retry <= '0';
DMA2Bus_ToutSup <= '0';
DMA2Bus_WrAck <= '0';
end generate REMOVE_DMA;
-------------------------------------------------------------------------------
-- Misc logic assignments
Bus2IP_Addr <= Bus2IP_Addr_i;
Bus2IP_Data <= Bus2IP_Data_i(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE <= Bus2IP_BE_i;
Bus2IP_WrReq <= Bus2IP_WrReq_i;
Bus2IP_RdReq <= Bus2IP_RdReq_i;
Bus2IP_Burst <= Bus2IP_Burst_i ;
Bus2IP_MstWrAck <= Bus2IP_MstWrAck_ma and not(Mstr_sel_ma);
Bus2IP_MstRdAck <= Bus2IP_MstRdAck_ma and not(Mstr_sel_ma);
Bus2IP_MstRetry <= Bus2IP_MstRetry_i and not(Mstr_sel_ma);
Bus2IP_MstError <= Bus2IP_MstError_i;
Bus2IP_MstTimeOut <= Bus2IP_MstTimeOut_i and not(Mstr_sel_ma);
Bus2IP_MstLastAck <= Bus2IP_MstLastAck_i and not(Mstr_sel_ma);
Bus2IP_Clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
Bus2IP_Freeze_i <= Freeze;
Bus2IP_Freeze <= Freeze;
IP2INTC_Irpt <= Intr2Bus_DevIntr;
IPIF_Lvl_Interrupts(0) <= DMA2Intr_Intr(0);
IPIF_Lvl_Interrupts(1) <= DMA2Intr_Intr(1);
IPIF_Lvl_Interrupts(2) <= RdFIFO2Intr_DeadLock;
IPIF_Lvl_Interrupts(3) <= WrFIFO2Intr_DeadLock;
IPIF_Reg_Interrupts(0) <= IP2Bus_Error_mx;
IPIF_Reg_Interrupts(1) <= const_zero;
Bus2IP_Reset <= Bus2IP_Reset_i; -- hw or sw reset; if no sw reset
-- function is included, then this
-- is set equal to the hw reset, Reset.
Bus2IP_RNW <= Bus2IP_RNW_i;
const_zero <= LOGIC_LOW;
end implementation;
| bsd-3-clause | 57c6c7b6d47f1d653c12beca1fdd481f | 0.507251 | 3.73714 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd | 2 | 12,097 | -------------------------------------------------------------------------------
-- $Id: common_types_pkg.vhd,v 1.1.4.4 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Common_Types - package and package body
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: common_types_pkg.vhd
-- Version: v1.00a
-- Description: A package with common type definition and help functions
--
--
-------------------------------------------------------------------------------
-- Structure:
-- common_types_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT (from goran's microblaze_types_pkg.vhd)
-- History:
-- BLT 6-29-2001 -- First version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 10/7/2010 v3_0_a
-- ~~~~~~
-- - Changed Get_RLOC_Name function implementation to an equivalent version
-- that addresses CR 574505.
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package Common_Types is
type RLOC_POS_TYPE is
record
X : natural;
Y : natural;
end record RLOC_POS_TYPE;
type TARGET_FAMILY_TYPE is (VIRTEX, VIRTEX2);
function log2(x : natural) return integer;
function String_To_Int(S : string) return integer;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string;
end package Common_Types;
-------------------------------------------------------------------------------
-- Package Body section
-------------------------------------------------------------------------------
package body Common_Types is
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
--itoa function converts integer to a text string
--this function is required since 'image doesn't work
--in synplicity
-- valid range for input to the function is -9999 to 9999
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end function itoa;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string is
variable Col : integer;
variable Row : integer;
variable S : integer;
begin
if Target = VIRTEX then
Row := -Y;
Col := X/2;
S := 1 - (X mod 2);
return 'R' & itoa(Row) &
'C' & itoa(Col) &
".S" & itoa(S);
else -- Target = VIRTEX2
return 'X' & itoa(X) & 'Y' & itoa(Y);
end if;
end function Get_RLOC_Name;
type POS_RECORD is
record
X : natural;
Y : natural;
end record POS_RECORD;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
-----------------------------------------------------------------------------
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end function String_To_Int;
-- function Get_RLOC ( Target : TARGET_FAMILY_TYPE;
-- Module : MODULE_TYPE;
-- Index : natural) return string is
-- begin -- function Get_RLOC
-- end function Get_RLOC;
end package body Common_Types;
| bsd-3-clause | ceff6c3bef472b2438af39192096b845 | 0.441266 | 4.71986 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/down_counter.vhd | 2 | 8,410 | -------------------------------------------------------------------------------
-- $Id: down_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
------------------------------------------------------------------------------
-- PLB Arbiter
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
------------------------------------------------------------------------------
-- Filename: down_counter.vhd
--
-- Description: Parameterizable down counter with synchronous load and
-- reset.
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi-use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/10/01 -- First version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
-- PROC_COMMON_PKG contains the RESET_ACTIVE constant
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_CNT_WIDTH -- counter width
--
-- Definition of Ports:
-- input Din -- data to be loaded into counter
-- input Load -- load control signal
-- input Cnt_en -- count enable signal
-- input Clk
-- input Rst
--
-- output Cnt_out -- counter output
-------------------------------------------------------------------------------
entity down_counter is
generic (
-- Select width of counter
C_CNT_WIDTH : INTEGER := 4
);
port (
Din : in std_logic_vector(0 to C_CNT_WIDTH-1);
Load : in std_logic;
Cnt_en : in std_logic;
Cnt_out : out std_logic_vector(0 to C_CNT_WIDTH - 1 );
Clk : in std_logic;
Rst : in std_logic
);
end down_counter;
architecture simulation of down_counter is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- internal count
signal cnt : unsigned(0 to C_CNT_WIDTH - 1 );
begin
-------------------------------------------------------------------------------
-- COUNTER_PROCESS process
-------------------------------------------------------------------------------
COUNTER_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
cnt <= (others => '0');
elsif Load = '1' then
cnt <= unsigned(Din);
elsif Cnt_en = '1' then
cnt <= cnt - 1;
else
cnt <= cnt;
end if;
end if;
end process COUNTER_PROCESS;
CNTOUT_PROCESS:process (cnt)
begin
Cnt_out <= conv_std_logic_vector(cnt, C_CNT_WIDTH);
end process CNTOUT_PROCESS;
end simulation;
| bsd-3-clause | 94d182b6e994ed35eceed052dfa368dc | 0.398335 | 5.602931 | false | false | false | false |
iocoder/graduation | hardware/cpu/pipeline.vhd | 1 | 57,480 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.cpu_pkg.all;
entity pipeline is
Port (
CLK50 : in STD_LOGIC;
CLK : in STD_LOGIC;
STALL : in STD_LOGIC;
IRQ : in STD_LOGIC;
NMI : in STD_LOGIC;
IAK : out STD_LOGIC := '0';
NAK : out STD_LOGIC := '0';
-- instruction bus
iMEME : out STD_LOGIC;
iRW : out STD_LOGIC;
iADDR : out STD_LOGIC_VECTOR (31 downto 0);
iDin : in STD_LOGIC_VECTOR (31 downto 0);
iDout : out STD_LOGIC_VECTOR (31 downto 0);
iDTYPE : out STD_LOGIC_VECTOR ( 2 downto 0);
-- data bus
dMEME : out STD_LOGIC;
dRW : out STD_LOGIC;
dADDR : out STD_LOGIC_VECTOR (31 downto 0);
dDin : in STD_LOGIC_VECTOR (31 downto 0);
dDout : out STD_LOGIC_VECTOR (31 downto 0);
dDTYPE : out STD_LOGIC_VECTOR ( 2 downto 0)
);
end entity;
architecture Behavioral of pipeline is
-- TYPES
type regfile_t is array (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
type tlb_t is array (0 to 63) of STD_LOGIC_VECTOR (40 downto 0);
-- CONTROL SIGNALS
constant REG_DEST : integer := 0;
constant ALU_SRC : integer := 1;
constant MEM_TO_REG : integer := 2;
constant REG_WRITE : integer := 3;
constant MEM_READ : integer := 4;
constant MEM_WRITE : integer := 5;
constant BRANCH : integer := 6;
constant CTRL_COUNT : integer := 7;
-- FORMATS
constant R_FORMAT : integer := 0;
constant I_FORMAT : integer := 1;
constant J_FORMAT : integer := 2;
-- ALU OPERATIONS
constant ALUOP_NOP : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
constant ALUOP_EXP : STD_LOGIC_VECTOR ( 7 downto 0) := x"01";
constant ALUOP_CPYPC : STD_LOGIC_VECTOR ( 7 downto 0) := x"02";
constant ALUOP_LUI : STD_LOGIC_VECTOR ( 7 downto 0) := x"03";
constant ALUOP_MFHI : STD_LOGIC_VECTOR ( 7 downto 0) := x"10";
constant ALUOP_MTHI : STD_LOGIC_VECTOR ( 7 downto 0) := x"11";
constant ALUOP_MFLO : STD_LOGIC_VECTOR ( 7 downto 0) := x"12";
constant ALUOP_MTLO : STD_LOGIC_VECTOR ( 7 downto 0) := x"13";
constant ALUOP_MULT : STD_LOGIC_VECTOR ( 7 downto 0) := x"14";
constant ALUOP_MULTU : STD_LOGIC_VECTOR ( 7 downto 0) := x"15";
constant ALUOP_DIV : STD_LOGIC_VECTOR ( 7 downto 0) := x"16";
constant ALUOP_DIVU : STD_LOGIC_VECTOR ( 7 downto 0) := x"17";
constant ALUOP_ADD : STD_LOGIC_VECTOR ( 7 downto 0) := x"20";
constant ALUOP_ADDU : STD_LOGIC_VECTOR ( 7 downto 0) := x"21";
constant ALUOP_SUB : STD_LOGIC_VECTOR ( 7 downto 0) := x"22";
constant ALUOP_SUBU : STD_LOGIC_VECTOR ( 7 downto 0) := x"23";
constant ALUOP_AND : STD_LOGIC_VECTOR ( 7 downto 0) := x"24";
constant ALUOP_OR : STD_LOGIC_VECTOR ( 7 downto 0) := x"25";
constant ALUOP_XOR : STD_LOGIC_VECTOR ( 7 downto 0) := x"26";
constant ALUOP_NOR : STD_LOGIC_VECTOR ( 7 downto 0) := x"27";
constant ALUOP_SLT : STD_LOGIC_VECTOR ( 7 downto 0) := x"2A";
constant ALUOP_SLTU : STD_LOGIC_VECTOR ( 7 downto 0) := x"2B";
constant ALUOP_SLL : STD_LOGIC_VECTOR ( 7 downto 0) := x"30";
constant ALUOP_SRL : STD_LOGIC_VECTOR ( 7 downto 0) := x"32";
constant ALUOP_SRA : STD_LOGIC_VECTOR ( 7 downto 0) := x"33";
constant ALUOP_SLLV : STD_LOGIC_VECTOR ( 7 downto 0) := x"34";
constant ALUOP_SRLV : STD_LOGIC_VECTOR ( 7 downto 0) := x"36";
constant ALUOP_SRAV : STD_LOGIC_VECTOR ( 7 downto 0) := x"37";
-- MEMORY OPERATIONS
constant MEMOP_BYTE : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
constant MEMOP_HALF : STD_LOGIC_VECTOR ( 7 downto 0) := x"01";
constant MEMOP_LEFT : STD_LOGIC_VECTOR ( 7 downto 0) := x"02";
constant MEMOP_WORD : STD_LOGIC_VECTOR ( 7 downto 0) := x"03";
constant MEMOP_BYTEU : STD_LOGIC_VECTOR ( 7 downto 0) := x"04";
constant MEMOP_HALFU : STD_LOGIC_VECTOR ( 7 downto 0) := x"05";
constant MEMOP_RIGHT : STD_LOGIC_VECTOR ( 7 downto 0) := x"06";
-- PC SOURCE
constant PCSRC_PC4 : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
constant PCSRC_BRANCH : STD_LOGIC_VECTOR ( 7 downto 0) := x"01";
constant PCSRC_JMP : STD_LOGIC_VECTOR ( 7 downto 0) := x"02";
constant PCSRC_JR : STD_LOGIC_VECTOR ( 7 downto 0) := x"03";
constant PCSRC_EXP : STD_LOGIC_VECTOR ( 7 downto 0) := x"04";
-- EXCEPTION HANDLER
signal exception : STD_LOGIC := '0';
-- IF
signal if_pc : STD_LOGIC_VECTOR (31 downto 0) := x"BFBFFFFC";
signal if_pc4 : STD_LOGIC_VECTOR (31 downto 0) := x"BFC00000";
signal if_instr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal if_badvaddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal if_exphndl : STD_LOGIC := '0';
signal if_exception : STD_LOGIC := '0';
signal if_exception2 : STD_LOGIC := '0';
-- ID
signal id_instr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_opcode : STD_LOGIC_VECTOR ( 5 downto 0) := "000000";
signal id_rs : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal id_rt : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal id_rd : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal id_ropcode : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal id_shamt : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal id_funct : STD_LOGIC_VECTOR ( 5 downto 0) := "000000";
signal id_is_jr : STD_LOGIC := '0';
signal id_is_jalr : STD_LOGIC := '0';
signal id_is_bltz : STD_LOGIC := '0';
signal id_is_bgez : STD_LOGIC := '0';
signal id_is_blzal : STD_LOGIC := '0';
signal id_is_bgzal : STD_LOGIC := '0';
signal id_is_j : STD_LOGIC := '0';
signal id_is_jal : STD_LOGIC := '0';
signal id_is_beq : STD_LOGIC := '0';
signal id_is_bne : STD_LOGIC := '0';
signal id_is_blez : STD_LOGIC := '0';
signal id_is_bgtz : STD_LOGIC := '0';
signal id_is_branch : STD_LOGIC := '0';
signal id_pc : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_pc4 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_imm32 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_shl : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_val_of_rs : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_val_of_rt : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_cop0_regrd : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_val1 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_val2 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_braddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_jmpaddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_jraddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal id_is_equal : STD_LOGIC := '0';
signal id_is_zero : STD_LOGIC := '0';
signal id_is_lez : STD_LOGIC := '0';
signal id_is_gtz : STD_LOGIC := '0';
signal id_is_mfc0 : STD_LOGIC := '0';
signal id_is_mtc0 : STD_LOGIC := '0';
signal id_is_rfe : STD_LOGIC := '0';
signal id_is_tlbr : STD_LOGIC := '0';
signal id_is_tlbwi : STD_LOGIC := '0';
signal id_is_cop0 : STD_LOGIC := '0';
signal id_pc_src : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal id_if_flush : STD_LOGIC := '0';
signal id_ctrlsig_in : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal id_aluop : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal id_memop : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal id_ctrlsig : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal id_stall : STD_LOGIC := '0';
signal id_ifclk : STD_LOGIC := '1';
signal id_pcclk : STD_LOGIC := '1';
signal id_exception : STD_LOGIC := '0';
signal id_regfile_p1 : STD_LOGIC := '0';
signal id_regfile_p2 : STD_LOGIC := '0';
signal id_regfile : regfile_t := (others => x"00000000");
signal id_regfile1 : regfile_t := (others => x"00000000");
signal id_regfile2 : regfile_t := (others => x"00000000");
attribute ram_style: string;
attribute ram_style of id_regfile : signal is "block";
attribute ram_style of id_regfile1 : signal is "block";
attribute ram_style of id_regfile2 : signal is "block";
-- EX
signal ex_hi : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_lo : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_op1 : STD_LOGIC_VECTOR (31 downto 0);
signal ex_op2 : STD_LOGIC_VECTOR (31 downto 0);
signal ex_mulres : STD_LOGIC_VECTOR (63 downto 0);
signal ex_busy : integer := 0;
signal ex_phase : integer := 0;
signal ex_instr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_rs : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal ex_rt : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal ex_rd : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal ex_shamt : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal ex_pc4 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_aluop : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal ex_memop : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal ex_ctrlsig : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal ex_val_of_rs : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_val_of_rt : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_imm32 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_fu_mux1 : STD_LOGIC_VECTOR ( 1 downto 0) := "00";
signal ex_fu_mux2 : STD_LOGIC_VECTOR ( 1 downto 0) := "00";
signal ex_muxop1 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_muxop2 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_alu1 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_alu2 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_alu_output : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal ex_rk : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal ex_is_mfc0 : STD_LOGIC := '0';
signal ex_is_mtc0 : STD_LOGIC := '0';
signal ex_exception : STD_LOGIC := '0';
-- MEM
signal mem_busy : boolean := false;
signal mem_phase : integer := 0;
signal mem_instr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_pc4 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_memop : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal mem_ctrlsig : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal mem_addr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_data_in : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_data_out : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_tmp : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_tmp2 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_pagemiss : STD_LOGIC := '0';
signal mem_cached : STD_LOGIC := '0';
signal mem_rk : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal mem_is_mfc0 : STD_LOGIC := '0';
signal mem_is_mtc0 : STD_LOGIC := '0';
signal mem_exception : STD_LOGIC := '0';
-- WB
signal wb_instr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal wb_pc4 : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal wb_ctrlsig : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal wb_mem_out : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal wb_alu_out : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal wb_value_of_rk : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal wb_rk : STD_LOGIC_VECTOR ( 4 downto 0) := "00000";
signal wb_is_mfc0 : STD_LOGIC := '0';
signal wb_is_mtc0 : STD_LOGIC := '0';
signal wb_exception : STD_LOGIC := '0';
-- TLB
signal instr_paddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal instr_miss : boolean := false;
signal data_vaddr : STD_LOGIC_VECTOR (31 downto 0);
signal data_paddr : STD_LOGIC_VECTOR (31 downto 0);
signal data_miss : boolean := false;
signal tlb_entrylo : STD_LOGIC_VECTOR (31 downto 0);
signal tlb_entryhi : STD_LOGIC_VECTOR (31 downto 0);
signal tlb : tlb_t := (others => "0" & x"0000000000");
attribute ram_style of tlb : signal is "block";
-- coprocessor registers:
constant IEc : integer := 0;
constant KUc : integer := 1;
constant IEp : integer := 2;
constant KUp : integer := 3;
constant IEo : integer := 4;
constant KUo : integer := 5;
constant IR : STD_LOGIC_VECTOR (4 downto 0) := "00000";
signal Index : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 0
signal Random : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 1
signal EntryLo : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 2
signal BadVaddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 8
signal EntryHi : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 10
signal SR : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 12
signal CAUSE : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 13
signal EPC : STD_LOGIC_VECTOR (31 downto 0) := x"00000000"; -- 14
signal CAUSE_tmp : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal EPC_tmp : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal mem_badvaddr : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal got_rising : std_logic := '0';
signal got_falling : std_logic := '0';
signal int_busy : boolean := false;
signal int_busy2 : boolean := false;
signal exp_busy : boolean := false;
signal iSTALL : STD_LOGIC;
begin
-- _ _ _ _ _
-- CLK _| |_| |_| |_| |_| |
-- ^ ^ ^ ^ ^ Rising : CPU starts new cycle.
-- + + + + + Falling: exception handling, register transfers.
-- TLB has translated address and cache
-- has moved to phase 1
iSTALL <= '1' when STALL='1' or
ex_busy = 1 or
int_busy or
int_busy2 or
mem_busy or
exp_busy
else '0';
--------------------------------------------------------------------------------
-- TLB --
--------------------------------------------------------------------------------
process(CLK50)
variable data_entry : std_logic_vector(40 downto 0);
variable read_entry : std_logic_vector(40 downto 0);
variable write_entry : std_logic_vector(40 downto 0);
begin
if (CLK50 = '0' and CLK50'event) then
if (id_is_tlbwi='1' and (ex_instr = x"00000000" or
mem_instr = x"00000000" or
wb_instr = x"00000000")) then
write_entry(19 downto 0) := EntryLo(31 downto 12);
write_entry(39 downto 20) := EntryHi(31 downto 12);
write_entry(40) := EntryLo(9);
tlb(conv_integer(Index)) <= write_entry;
end if;
if (id_is_tlbr='1') then
read_entry := tlb(conv_integer(Index));
tlb_entrylo(31 downto 12) <= read_entry(19 downto 0);
tlb_entryhi(31 downto 12) <= read_entry(39 downto 20);
tlb_entrylo(9) <= read_entry(40);
end if;
-- instrution access
-- data access
data_entry := tlb(conv_integer(data_vaddr(16 downto 12)&"0"));
if (data_vaddr(31) = '0' or data_vaddr(30) = '1') then
-- 0x00000000-0x7FFFFFFF
-- 0xC0000000-0xFFFFFFFF
if (data_entry(39 downto 20) = data_vaddr(31 downto 12) and
data_entry(40) = '1') then
data_miss <=false;
data_paddr<=data_entry(19 downto 0)&data_vaddr(11 downto 0);
else
data_miss <=true;
end if;
elsif (data_vaddr(29) = '0') then
-- 0x80000000-0x9FFFFFFF
data_paddr <= "000" & data_vaddr(28 downto 0);
data_miss <= false;
else
-- 0xA0000000-0xBFFFFFFF
data_paddr <= "000" & data_vaddr(28 downto 0);
data_miss <= false;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- EXCEPTIONS --
--------------------------------------------------------------------------------
-- exception handler
process(CLK)
begin
if (CLK = '1' and CLK'event and iSTALL='0') then
got_rising <= not got_rising;
end if;
if (CLK = '0' and CLK'event) then
if (got_falling /= got_rising or int_busy or
int_busy2 or exp_busy) then
-- if exception conditions are satisfied, next cycle is
-- an exception fetch, and all stages before and including the
-- exception-source stage shall be flushed.
if ((mem_exception='1' or if_exception2='1') and not exp_busy) then
exp_busy <= true;
elsif (mem_exception='1') then
exp_busy <= false;
CAUSE <= x"00000004"; -- TLB miss
EPC <= alu_add(mem_pc4,x"FFFFFFFC");
elsif (if_exception2='1') then
exp_busy <= false;
CAUSE <= x"00000004"; -- TLB miss
EPC <= alu_add(if_pc4,x"FFFFFFFC");
elsif (int_busy) then
int_busy <= false;
int_busy2 <= true;
elsif (int_busy2) then
int_busy2 <= false;
-- store EPC and CAUSE
if (id_is_jr='1' or id_is_jalr='1' or
is_branchregimm(id_opcode) or
is_jmp(id_opcode) or
is_branch(id_opcode)) then
-- branch instruction in ID stage
EPC <= id_pc;
CAUSE <= x"80000000";
else
EPC <= if_pc;
CAUSE <= x"00000000";
end if;
elsif (if_exphndl = '1') then
-- exception served
if_exception <= '0';
IAK <= '1';
exception <= '1';
elsif (exception='1') then
-- deactivate interrupt ack
IAK <= '0';
exception <= '0';
elsif (IRQ = '1' and SR(IEc) = '1' and if_exception='0') then
-- IRQ happened!
if_exception <= '1';
int_busy <= true;
end if;
got_falling <= got_rising;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- IF STAGE --
--------------------------------------------------------------------------------
-- register transfer
process(CLK)
variable handle_exception : boolean := false;
begin
if (CLK = '1' and CLK'event and iSTALL = '0') then
handle_exception := false;
if (if_exphndl= '0' and
(if_exception='1' or if_exception2='1') and
id_instr=x"00000000" and
ex_instr=x"00000000" and
mem_instr=x"00000000") then
-- IF STAGE EXCEPTION
handle_exception := true;
elsif (if_exphndl= '0' and
id_exception='1' and
ex_instr=x"00000000" and
mem_instr=x"00000000") then
-- ID EXCEPTION
handle_exception := true;
elsif (if_exphndl= '0' and
ex_exception='1' and
mem_instr=x"00000000") then
-- EX EXCEPTION
handle_exception := true;
elsif (if_exphndl= '0' and mem_exception='1') then
-- MEM EXCEPTION
handle_exception := true;
end if;
if (handle_exception) then
if_pc <= x"BFC00180";
if_exphndl <= '1';
elsif (if_exception='1' or if_exception2='1') then
-- Don't Move (Phantogram)
else
-- normal operation
if (id_pcclk = '1') then
if (id_pc_src = PCSRC_PC4 or if_exphndl = '1') then
if_pc <= if_pc4;
elsif (id_pc_src = PCSRC_BRANCH) then
if_pc <= id_braddr;
elsif (id_pc_src = PCSRC_JMP) then
if_pc <= id_jmpaddr;
elsif (id_pc_src = PCSRC_JR) then
if_pc <= id_jraddr;
end if;
end if;
if_exphndl <= '0';
end if;
end if;
end process;
-- add 4 to pc
if_pc4 <= alu_add(if_pc, x"00000004");
process(if_pc)
variable instr_vaddr : std_logic_vector(31 downto 0) := x"00000000";
variable instr_entry : std_logic_vector(40 downto 0);
begin
instr_vaddr := if_pc;
instr_entry := tlb(conv_integer(instr_vaddr(16 downto 12)&"1"));
-- solve instr_vaddr
if (instr_vaddr(31) = '0' or instr_vaddr(30) = '1') then
-- 0x00000000-0x7FFFFFFF
-- 0xC0000000-0xFFFFFFFF
if (instr_entry(39 downto 20) = instr_vaddr(31 downto 12) and
instr_entry(40) = '1') then
instr_miss <=false;
instr_paddr<=instr_entry(19 downto 0)&instr_vaddr(11 downto 0);
if_exception2 <= '0';
else
instr_miss <=true;
-- if_exception2 <= '1';
if_badvaddr <= instr_vaddr;
end if;
elsif (instr_vaddr(29) = '0') then
-- 0x80000000-0x9FFFFFFF
instr_paddr <= "000" & instr_vaddr(28 downto 0);
instr_miss <= false;
if_exception2 <= '0';
else
-- 0xA0000000-0xBFFFFFFF
instr_paddr <= "000" & instr_vaddr(28 downto 0);
instr_miss <= false;
if_exception2 <= '0';
end if;
end process;
-- interface iMEM component
iMEME <= '1';
iRW <= '0';
iADDR <= instr_paddr;
iDTYPE <= "100";
if_instr <= iDin;
iDout <= x"00000000";
--------------------------------------------------------------------------------
-- ID STAGE --
--------------------------------------------------------------------------------
-- register transfer
process(CLK)
variable id_next_instr : STD_LOGIC_VECTOR (31 downto 0);
variable id_next_opcode : STD_LOGIC_VECTOR ( 5 downto 0);
variable id_next_funct : STD_LOGIC_VECTOR ( 5 downto 0);
begin
if (CLK = '1' and CLK'event and iSTALL = '0') then
if (id_exception='1') then
-- don't move
id_next_instr := id_instr;
elsif (if_exception='1' or
if_exception2='1' or
ex_exception='1' or
mem_exception = '1') then
-- flush ID
id_instr <= x"00000000";
id_next_instr := x"00000000";
id_pc <= if_pc;
id_pc4 <= if_pc4;
else
-- normal operation
if (id_ifclk = '1') then
id_instr <= if_instr;
id_next_instr := if_instr;
id_pc <= if_pc;
id_pc4 <= if_pc4;
else
id_next_instr := id_instr;
end if;
end if;
id_next_opcode := id_next_instr(31 downto 26);
id_next_funct := id_next_instr( 5 downto 0);
if ((id_next_opcode="000000" and id_next_funct="001000") or
(id_next_opcode="000000" and id_next_funct="001001") or
is_branchregimm(id_next_opcode) or
is_jmp(id_next_opcode) or
is_branch(id_next_opcode)) then
id_is_branch <= '1';
else
id_is_branch <= '0';
end if;
end if;
end process;
-- register file operation
process(CLK)
-- vals of rs & rt registers extracted from regfile (or by forwarding)
variable val_of_rs : STD_LOGIC_VECTOR(31 downto 0);
variable val_of_rt : STD_LOGIC_VECTOR(31 downto 0);
impure function read_cop0_reg(indx : in STD_LOGIC_VECTOR (4 downto 0))
return STD_LOGIC_VECTOR is
variable retval : STD_LOGIC_VECTOR(31 downto 0);
begin
case indx is
when "00000" => retval := x"0000"&"00"&Index(5 downto 0)&x"00";
when "00010" => retval := EntryLo;
when "01000" => retval := BadVaddr;
when "01010" => retval := EntryHi;
when "01100" => retval := SR;
when "01101" => retval := CAUSE;
when "01110" => retval := EPC;
when others =>
end case;
return retval;
end read_cop0_reg;
procedure write_cop0_reg(indx : in STD_LOGIC_VECTOR (4 downto 0);
val : in STD_LOGIC_VECTOR (31 downto 0)) is
begin
case indx is
when "00000" => Index(5 downto 0) <= val(13 downto 8);
when "00010" => EntryLo <= val;
when "01010" => EntryHi <= val;
when "01100" => SR <= val;
when others =>
end case;
end write_cop0_reg;
begin
if (CLK50 = '0' and CLK50'event) then
if (id_regfile_p1 = '0') then
-- write to regfile
if (wb_ctrlsig(REG_WRITE) = '1' and wb_rk /= "00000") then
id_regfile1(conv_integer(wb_rk)) <= wb_value_of_rk;
id_regfile2(conv_integer(wb_rk)) <= wb_value_of_rk;
end if;
id_regfile_p1 <= '1';
else
-- read from regfile
id_val1 <= id_regfile1(conv_integer(id_rs));
id_val2 <= id_regfile2(conv_integer(id_rt));
id_regfile_p1 <= '0';
end if;
end if;
if (CLK = '0' and CLK'event) then
if (if_exphndl='1' and got_falling /= got_rising) then
-- disable interrupts
SR(5 downto 0) <= SR(3 downto 0) & "00";
-- set badvaddr
if (mem_exception='1') then
BadVaddr <= mem_badvaddr;
elsif (if_exception2='1') then
BadVaddr <= if_badvaddr;
end if;
elsif (id_is_rfe='1' and
ex_instr=x"00000000" and
mem_instr=x"00000000" and
wb_instr=x"00000000" and
got_rising /= got_falling) then
SR(3 downto 0) <= SR(5 downto 2);
elsif (wb_is_mtc0='1') then
-- write to coprocessor registers
write_cop0_reg(wb_rk, wb_value_of_rk);
elsif (id_is_tlbr='1') then
-- read TLB entry
EntryLo <= tlb_entrylo;
EntryHi <= tlb_entryhi;
else
-- read from coprocessor registers
id_cop0_regrd <= read_cop0_reg(id_rd);
end if;
end if;
end process;
-- combinational logic
id_opcode <= id_instr(31 downto 26);
id_rs <= id_instr(25 downto 21);
id_rt <= id_instr(20 downto 16);
id_rd <= id_instr(15 downto 11) when id_opcode /= "000011" else "11111";
id_ropcode <= id_instr(20 downto 16);
id_shamt <= id_instr(10 downto 6);
id_funct <= id_instr( 5 downto 0);
id_is_jr <= '1' when id_opcode="000000" and id_funct="001000" else '0';
id_is_jalr <= '1' when id_opcode="000000" and id_funct="001001" else '0';
id_is_bltz <= '1' when id_opcode="000001" and id_ropcode = "00000" else '0';
id_is_bgez <= '1' when id_opcode="000001" and id_ropcode = "00001" else '0';
id_is_blzal <= '1' when id_opcode="000001" and id_ropcode = "10000" else '0';
id_is_bgzal <= '1' when id_opcode="000001" and id_ropcode = "10001" else '0';
id_is_j <= '1' when id_opcode="000010" else '0';
id_is_jal <= '1' when id_opcode="000011" else '0';
id_is_beq <= '1' when id_opcode="000100" else '0';
id_is_bne <= '1' when id_opcode="000101" else '0';
id_is_blez <= '1' when id_opcode="000110" else '0';
id_is_bgtz <= '1' when id_opcode="000111" else '0';
id_imm32 <= alu_add(id_pc4, x"00000004") when (
id_opcode = "000011" or
(id_opcode = "000000" and id_funct = "001001") or
(id_opcode = "000001" and id_ropcode = "10000") or
(id_opcode = "000001" and id_ropcode = "10001")) else
unsiext2(id_instr(15 downto 0)) when (
id_opcode = "001100" or
id_opcode = "001101" or
id_opcode = "001110") else
signext2(id_instr(15 downto 0));
id_shl <= id_imm32(29 downto 0) & "00";
id_braddr <= alu_add(id_pc4, id_shl);
id_jmpaddr <= id_pc4(31 downto 28) & id_instr(25 downto 0) & "00";
id_jraddr <= id_val_of_rs;
id_is_equal <= '1' when id_val_of_rs = id_val_of_rt else '0';
id_is_zero <= '1' when id_val_of_rs = x"00000000" else '0';
id_is_lez <= alu_lts(id_val_of_rs, x"00000000")(0) OR id_is_zero;
id_is_gtz <= NOT id_is_lez;
id_is_mfc0 <= '1' when is_cop0(id_opcode) and id_rs = "00000" else '0';
id_is_mtc0 <= '1' when is_cop0(id_opcode) and id_rs = "00100" else '0';
id_is_rfe <= '1' when is_cop0(id_opcode) and id_rs = "10000"
and id_funct = "010000" else '0';
id_is_tlbr <= '1' when is_cop0(id_opcode) and id_rs = "10000"
and id_funct = "000001" else '0';
id_is_tlbwi <= '1' when is_cop0(id_opcode) and id_rs = "10000"
and id_funct = "000010" else '0';
id_is_cop0 <= '1' when is_cop0(id_opcode) else '0';
-- register file outputs
id_val_of_rs <= id_val1 when id_is_cop0='0' else
id_cop0_regrd when id_is_mfc0='1' else
x"00000000";
id_val_of_rt <= id_val2 when (id_is_cop0='0' or id_is_mtc0='1') else
x"00000000";
-- generate control signals
id_ctrlsig_in(REG_DEST) <=
'1' when is_alureg (id_opcode) else
'1' when is_branchregimm(id_opcode) else
'1' when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'0' when is_aluimm (id_opcode) else
'0' when is_memload (id_opcode) else
'0' when is_memstore (id_opcode) else
id_is_mtc0 when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(ALU_SRC) <=
id_is_jr or id_is_jalr when is_alureg (id_opcode) else
'1' when is_branchregimm(id_opcode) else
'1' when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'1' when is_aluimm (id_opcode) else
'1' when is_memload (id_opcode) else
'1' when is_memstore (id_opcode) else
'0' when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(MEM_TO_REG) <=
'0' when is_alureg (id_opcode) else
'0' when is_branchregimm(id_opcode) else
'0' when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'0' when is_aluimm (id_opcode) else
'1' when is_memload (id_opcode) else
'0' when is_memstore (id_opcode) else
'0' when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(REG_WRITE) <=
'1' when is_alureg (id_opcode) else
id_is_blzal or id_is_bgzal when is_branchregimm(id_opcode) else
id_is_jal when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'1' when is_aluimm (id_opcode) else
'1' when is_memload (id_opcode) else
'0' when is_memstore (id_opcode) else
id_is_mfc0 when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(MEM_READ) <=
'0' when is_alureg (id_opcode) else
'0' when is_branchregimm(id_opcode) else
'0' when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'0' when is_aluimm (id_opcode) else
'1' when is_memload (id_opcode) else
'0' when is_memstore (id_opcode) else
'0' when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(MEM_WRITE) <=
'0' when is_alureg (id_opcode) else
'0' when is_branchregimm(id_opcode) else
'0' when is_jmp (id_opcode) else
'0' when is_branch (id_opcode) else
'0' when is_aluimm (id_opcode) else
'0' when is_memload (id_opcode) else
'1' when is_memstore (id_opcode) else
'0' when is_cop0 (id_opcode) else
'0';
id_ctrlsig_in(BRANCH) <=
id_is_jr or id_is_jalr when is_alureg (id_opcode) else
'1' when is_branchregimm(id_opcode) else
'1' when is_jmp (id_opcode) else
'1' when is_branch (id_opcode) else
'0' when is_aluimm (id_opcode) else
'0' when is_memload (id_opcode) else
'0' when is_memstore (id_opcode) else
'0' when is_cop0 (id_opcode) else
'0';
-- decoding
id_aluop <= ALUOP_SLL when is_alureg(id_opcode) and id_funct = "000000" else
ALUOP_SRL when is_alureg(id_opcode) and id_funct = "000010" else
ALUOP_SRA when is_alureg(id_opcode) and id_funct = "000011" else
ALUOP_SLLV when is_alureg(id_opcode) and id_funct = "000100" else
ALUOP_SRLV when is_alureg(id_opcode) and id_funct = "000110" else
ALUOP_SRAV when is_alureg(id_opcode) and id_funct = "000111" else
ALUOP_CPYPC when is_alureg(id_opcode) and id_funct = "001000" else
ALUOP_CPYPC when is_alureg(id_opcode) and id_funct = "001001" else
ALUOP_EXP when is_alureg(id_opcode) and id_funct = "001100" else
ALUOP_EXP when is_alureg(id_opcode) and id_funct = "001101" else
ALUOP_MFHI when is_alureg(id_opcode) and id_funct = "010000" else
ALUOP_MTHI when is_alureg(id_opcode) and id_funct = "010001" else
ALUOP_MFLO when is_alureg(id_opcode) and id_funct = "010010" else
ALUOP_MTLO when is_alureg(id_opcode) and id_funct = "010011" else
ALUOP_MULT when is_alureg(id_opcode) and id_funct = "011000" else
ALUOP_MULTU when is_alureg(id_opcode) and id_funct = "011001" else
ALUOP_DIV when is_alureg(id_opcode) and id_funct = "011010" else
ALUOP_DIVU when is_alureg(id_opcode) and id_funct = "011011" else
ALUOP_ADD when is_alureg(id_opcode) and id_funct = "100000" else
ALUOP_ADDU when is_alureg(id_opcode) and id_funct = "100001" else
ALUOP_SUB when is_alureg(id_opcode) and id_funct = "100010" else
ALUOP_SUBU when is_alureg(id_opcode) and id_funct = "100011" else
ALUOP_AND when is_alureg(id_opcode) and id_funct = "100100" else
ALUOP_OR when is_alureg(id_opcode) and id_funct = "100101" else
ALUOP_XOR when is_alureg(id_opcode) and id_funct = "100110" else
ALUOP_NOR when is_alureg(id_opcode) and id_funct = "100111" else
ALUOP_SLT when is_alureg(id_opcode) and id_funct = "101010" else
ALUOP_SLTU when is_alureg(id_opcode) and id_funct = "101011" else
ALUOP_ADD when is_aluimm(id_opcode) and id_opcode= "001000" else
ALUOP_ADDU when is_aluimm(id_opcode) and id_opcode= "001001" else
ALUOP_SLT when is_aluimm(id_opcode) and id_opcode= "001010" else
ALUOP_SLTU when is_aluimm(id_opcode) and id_opcode= "001011" else
ALUOP_AND when is_aluimm(id_opcode) and id_opcode= "001100" else
ALUOP_OR when is_aluimm(id_opcode) and id_opcode= "001101" else
ALUOP_XOR when is_aluimm(id_opcode) and id_opcode= "001110" else
ALUOP_LUI when is_aluimm(id_opcode) and id_opcode= "001111" else
ALUOP_CPYPC when is_jmp(id_opcode) else
ALUOP_ADD when is_memload(id_opcode) else
ALUOP_ADD when is_memstore(id_opcode) else
ALUOP_ADD when id_is_mfc0='1' else
ALUOP_ADD when id_is_mtc0='1' else
ALUOP_NOP;
id_memop <= "00000" & id_opcode(2 downto 0);
-- hazard detection unit
id_stall <= '1' when
-- LW followed immediately by instruction that needs its value
(ex_ctrlsig(MEM_READ) = '1' and ex_rk /= "00000" and
((ex_rk=id_rs) or ((ex_rk=id_rt) and (id_ctrlsig_in(MEM_READ)='0')))) or
-- branch/jmpreg instruction that needs values in EX and MEM stages
(id_ctrlsig_in(BRANCH) = '1' and (NOT is_jmp(id_opcode)) and
((ex_ctrlsig(REG_WRITE) = '1' and ex_rk /= "00000" and
(ex_rk = id_rs or (id_opcode /= "000001" and ex_rk = id_rt))) or
(mem_ctrlsig(REG_WRITE) = '1' and mem_rk /= "00000" and
(mem_rk = id_rs or (id_opcode /= "000001" and mem_rk = id_rt))))) or
-- mtc0 instruction that needs values in EX and MEM stages
(id_is_mtc0 = '1' and (
(ex_ctrlsig(REG_WRITE) ='1' and ex_rk /="00000" and ex_rk =id_rt) or
(mem_ctrlsig(REG_WRITE)='1' and mem_rk/="00000" and mem_rk=id_rt))) or
-- mfc0/mtc0 need to introduce 3 bubbles in the pipeline
((id_is_cop0 = '1') and
(ex_instr /= x"00000000" or mem_instr /= x"00000000" or
wb_instr /= x"00000000"))
-- any other case shouldn't need a stall
else '0';
id_ifclk <= NOT id_stall;
id_pcclk <= NOT id_stall;
-- control signals mux
with id_stall select id_ctrlsig <= id_ctrlsig_in when '0', x"00" when others;
-- pc source selection
id_pc_src <=
PCSRC_JR when id_is_jr ='1' else
PCSRC_JR when id_is_jalr ='1' else
PCSRC_BRANCH when id_is_bltz ='1' and (id_is_lez='1' and id_is_zero='0') else
PCSRC_BRANCH when id_is_bgez ='1' and (id_is_gtz='1' or id_is_zero='1') else
PCSRC_BRANCH when id_is_blzal='1' and (id_is_lez='1' and id_is_zero='0') else
PCSRC_BRANCH when id_is_bgzal='1' and (id_is_gtz='1' or id_is_zero='1') else
PCSRC_JMP when id_is_j ='1' else
PCSRC_JMP when id_is_jal ='1' else
PCSRC_BRANCH when id_is_beq ='1' and id_is_equal='1' else
PCSRC_BRANCH when id_is_bne ='1' and id_is_equal='0' else
PCSRC_BRANCH when id_is_blez ='1' and id_is_lez ='1' else
PCSRC_BRANCH when id_is_bgtz ='1' and id_is_gtz ='1' else
PCSRC_PC4;
--------------------------------------------------------------------------------
-- EX STAGE --
--------------------------------------------------------------------------------
-- register transfer
process(CLK)
begin
if (CLK = '1' and CLK'event and iSTALL = '0') then
if (ex_exception='1') then
-- don't move
elsif (id_exception='1' or mem_exception='1' or id_ifclk = '0') then
-- introduce a bubble in EX
ex_instr <= x"00000000";
ex_pc4 <= x"00000000";
ex_rs <= "00000";
ex_rt <= "00000";
ex_rd <= "00000";
ex_shamt <= "00000";
ex_aluop <= x"00";
ex_memop <= x"00";
ex_ctrlsig <= x"00";
ex_val_of_rs <= x"00000000";
ex_val_of_rt <= x"00000000";
ex_imm32 <= x"00000000";
ex_is_mfc0 <= '0';
ex_is_mtc0 <= '0';
else
-- normal operation
ex_instr <= id_instr;
ex_pc4 <= id_pc4;
ex_rs <= id_rs;
ex_rt <= id_rt;
ex_rd <= id_rd;
ex_shamt <= id_shamt;
ex_aluop <= id_aluop;
ex_memop <= id_memop;
ex_ctrlsig <= id_ctrlsig;
ex_val_of_rs <= id_val_of_rs;
ex_val_of_rt <= id_val_of_rt;
ex_imm32 <= id_imm32;
ex_is_mfc0 <= id_is_mfc0;
ex_is_mtc0 <= id_is_mtc0;
end if;
end if;
end process;
-- forwarding unit
ex_fu_mux1 <= "10" when (mem_ctrlsig(REG_WRITE) = '1' and
mem_rk /= "00000" and
mem_rk = ex_rs) else
"01" when (wb_ctrlsig(REG_WRITE) = '1' and
wb_rk /= "00000" and
wb_rk = ex_rs) else
"00";
ex_fu_mux2 <= "10" when (mem_ctrlsig(REG_WRITE) = '1' and
mem_rk /= "00000" and
mem_rk = ex_rt) else
"01" when (wb_ctrlsig(REG_WRITE) = '1' and
wb_rk /= "00000" and
wb_rk = ex_rt) else
"00";
-- MUX components
with ex_fu_mux1
select ex_muxop1 <= ex_val_of_rs when "00",
wb_value_of_rk when "01",
mem_addr when "10",
x"00000000" when others;
with ex_fu_mux2
select ex_muxop2 <= ex_val_of_rt when "00",
wb_value_of_rk when "01",
mem_addr when "10",
x"00000000" when others;
with ex_aluop
select ex_alu1 <= x"00000010" when ALUOP_LUI,
x"000000" & "000" & ex_shamt when ALUOP_SLL,
x"000000" & "000" & ex_shamt when ALUOP_SRL,
x"000000" & "000" & ex_shamt when ALUOP_SRA,
ex_muxop1 when others;
with ex_ctrlsig(ALU_SRC)
select ex_alu2 <= ex_muxop2 when '0',
ex_imm32 when others;
with ex_ctrlsig(REG_DEST)
select ex_rk <= ex_rt when '0',
ex_rd when others;
-- ALU
with ex_aluop
select ex_alu_output <= alu_cpy(ex_alu1, ex_alu2) when ALUOP_CPYPC,
alu_sll(ex_alu1, ex_alu2) when ALUOP_LUI,
alu_add(ex_alu1, ex_alu2) when ALUOP_ADD,
alu_add(ex_alu1, ex_alu2) when ALUOP_ADDU,
alu_sub(ex_alu1, ex_alu2) when ALUOP_SUB,
alu_sub(ex_alu1, ex_alu2) when ALUOP_SUBU,
alu_and(ex_alu1, ex_alu2) when ALUOP_AND,
alu_ior(ex_alu1, ex_alu2) when ALUOP_OR,
alu_xor(ex_alu1, ex_alu2) when ALUOP_XOR,
alu_nor(ex_alu1, ex_alu2) when ALUOP_NOR,
alu_lts(ex_alu1, ex_alu2) when ALUOP_SLT,
alu_ltu(ex_alu1, ex_alu2) when ALUOP_SLTU,
alu_sll(ex_alu1, ex_alu2) when ALUOP_SLL,
alu_srl(ex_alu1, ex_alu2) when ALUOP_SRL,
alu_sra(ex_alu1, ex_alu2) when ALUOP_SRA,
alu_sll(ex_alu1, ex_alu2) when ALUOP_SLLV,
alu_srl(ex_alu1, ex_alu2) when ALUOP_SRLV,
alu_sra(ex_alu1, ex_alu2) when ALUOP_SRAV,
ex_hi when ALUOP_MFHI,
ex_lo when ALUOP_MFLO,
x"00000000" when others;
process(CLK)
variable N : unsigned(31 downto 0);
variable D : unsigned(31 downto 0);
variable Q : unsigned(31 downto 0);
variable R : unsigned(31 downto 0);
begin
if (CLK = '0' and CLK'event ) then
if (ex_busy = 0) then
if (ex_aluop = ALUOP_MULT or
ex_aluop = ALUOP_MULTU or
ex_aluop = ALUOP_DIV or
ex_aluop = ALUOP_DIVU) then
-- start multiplication/division FSM
ex_op1 <= ex_alu1;
ex_op2 <= ex_alu2;
ex_mulres <= x"0000000000000000";
N := unsigned(ex_alu1);
D := unsigned(ex_alu2);
Q := x"00000000";
R := x"00000000";
ex_busy <= 1;
elsif (ex_aluop = ALUOP_MTLO) then
ex_lo <= ex_alu1;
elsif (ex_aluop = ALUOP_MTHI) then
ex_hi <= ex_alu1;
end if;
ex_phase <= 0;
elsif (ex_aluop = ALUOP_MULT or ex_aluop = ALUOP_MULTU) then
-- multiplication
if (ex_phase = 0) then
if (ex_aluop = ALUOP_MULT) then
ex_mulres <= alu_mul(ex_op1, ex_op2);
else
ex_mulres <= alu_mulu(ex_op1, ex_op2);
end if;
elsif (ex_phase = 1) then
ex_lo <= ex_mulres(31 downto 0);
ex_hi <= ex_mulres(63 downto 32);
ex_busy <= 0;
end if;
ex_phase <= ex_phase + 1;
elsif (ex_aluop = ALUOP_DIV or ex_aluop = ALUOP_DIVU) then
-- division
if (ex_phase < 32) then
R := R(30 downto 0) & N(31-ex_phase);
if R >= D then
R := R - D;
Q(31-ex_phase) := '1';
end if;
elsif (ex_phase = 32) then
ex_lo <= std_logic_vector(Q);
ex_hi <= std_logic_vector(R);
ex_busy <= 0;
end if;
ex_phase <= ex_phase + 1;
end if;
end if;
end process;
-- precalculation for physical address
data_vaddr <= ex_alu_output;
--------------------------------------------------------------------------------
-- MEM STAGE --
--------------------------------------------------------------------------------
-- register transfer
process(CLK)
begin
if ( CLK = '1' and CLK'event ) then
if (iSTALL = '0') then
if (mem_exception='1') then
if (if_exphndl = '1') then
mem_exception <= '0';
end if;
elsif ((not mem_busy) and (ex_exception='1' or
((ex_ctrlsig(MEM_READ)='1' OR
ex_ctrlsig(MEM_WRITE)='1') and data_miss))) then
-- introduce a bubble in MEM
mem_instr <= x"00000000";
mem_memop <= x"00";
mem_ctrlsig <= x"00";
mem_addr <= x"00000000";
mem_data_in <= x"00000000";
mem_rk <= "00000";
mem_is_mfc0 <= '0';
mem_is_mtc0 <= '0';
if (((ex_ctrlsig(MEM_READ)='1' OR
ex_ctrlsig(MEM_WRITE)='1') and data_miss)) then
-- TLB data miss, throw exception
mem_pagemiss <= '1';
mem_exception <= '1';
mem_badvaddr <= ex_alu_output;
mem_pc4 <= ex_pc4;
else
mem_pagemiss <= '0';
mem_exception <= '0';
mem_pc4 <= x"00000000";
end if;
else
-- normal operation
mem_instr <= ex_instr;
mem_pc4 <= ex_pc4;
mem_memop <= ex_memop;
mem_ctrlsig <= ex_ctrlsig;
mem_rk <= ex_rk;
mem_is_mfc0 <= ex_is_mfc0;
mem_is_mtc0 <= ex_is_mtc0;
mem_pagemiss <= '0';
mem_exception <= '0';
if (ex_ctrlsig(MEM_READ)='1' OR
ex_ctrlsig(MEM_WRITE)='1') then
if (ex_memop = MEMOP_LEFT) then
-- first cycle
mem_pagemiss <= '0';
mem_busy <= true;
mem_addr <= data_paddr(31 downto 2) & "00";
mem_phase <= conv_integer(data_paddr(1 downto 0));
mem_tmp <= ex_muxop2;
mem_tmp2 <= ex_muxop2;
if (data_paddr(1 downto 0) = "00") then
mem_data_in <= x"000000" & ex_muxop2(31 downto 24);
elsif (data_paddr(1 downto 0) = "01") then
mem_data_in <= x"000000" & ex_muxop2(23 downto 16);
elsif (data_paddr(1 downto 0) = "10") then
mem_data_in <= x"000000" & ex_muxop2(15 downto 8);
else
mem_data_in <= x"000000" & ex_muxop2( 7 downto 0);
end if;
elsif (ex_memop = MEMOP_RIGHT) then
-- first cycle
mem_pagemiss <= '0';
mem_busy <= true;
mem_addr <= data_paddr(31 downto 2) & "11";
mem_phase <= conv_integer(data_paddr(1 downto 0));
mem_tmp <= ex_muxop2;
mem_tmp2 <= ex_muxop2;
if (data_paddr(1 downto 0) = "00") then
mem_data_in <= x"000000" & ex_muxop2(31 downto 24);
elsif (data_paddr(1 downto 0) = "01") then
mem_data_in <= x"000000" & ex_muxop2(23 downto 16);
elsif (data_paddr(1 downto 0) = "10") then
mem_data_in <= x"000000" & ex_muxop2(15 downto 8);
else
mem_data_in <= x"000000" & ex_muxop2( 7 downto 0);
end if;
else
-- normal load/store instruction
mem_pagemiss <= '0';
mem_busy <= false;
mem_data_in <= ex_muxop2;
mem_addr <= data_paddr;
end if;
else
mem_busy <= false;
mem_data_in <= ex_muxop2;
mem_addr <= ex_alu_output;
end if;
end if;
elsif (STALL='0') then
-- new cache cycle
if (mem_busy) then
-- lwl, lwr, swl, swr...
if (mem_phase = 0) then
mem_tmp(31 downto 24) <= dDin(7 downto 0);
elsif (mem_phase = 1) then
mem_tmp(23 downto 16) <= dDin(7 downto 0);
elsif (mem_phase = 2) then
mem_tmp(15 downto 8) <= dDin(7 downto 0);
elsif (mem_phase = 3) then
mem_tmp( 7 downto 0) <= dDin(7 downto 0);
end if;
-- update address and phase
if (mem_memop = MEMOP_LEFT) then
if (mem_phase = 1) then
-- next phase = 0
mem_data_in <= x"000000" & mem_tmp2(31 downto 24);
elsif (mem_phase = 2) then
-- next phase = 1
mem_data_in <= x"000000" & mem_tmp2(23 downto 16);
elsif (mem_phase = 3) then
-- next phase = 2
mem_data_in <= x"000000" & mem_tmp2(15 downto 8);
end if;
if (mem_phase = 0) then
-- done
mem_busy <= false;
else
-- next step
mem_addr <= alu_add(mem_addr, x"00000001");
mem_phase <= mem_phase - 1;
end if;
elsif (mem_memop = MEMOP_RIGHT) then
if (mem_phase = 0) then
-- next phase = 1
mem_data_in <= x"000000" & mem_tmp2(23 downto 16);
elsif (mem_phase = 1) then
-- next phase = 2
mem_data_in <= x"000000" & mem_tmp2(15 downto 8);
elsif (mem_phase = 2) then
-- next phase = 3
mem_data_in <= x"000000" & mem_tmp2( 7 downto 0);
end if;
if (mem_phase = 3) then
-- done
mem_busy <= false;
else
-- next step
mem_addr <= alu_sub(mem_addr, x"00000001");
mem_phase <= mem_phase + 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- interfacing dMEM component
dMEME <= mem_ctrlsig(MEM_READ) OR mem_ctrlsig(MEM_WRITE);
dRW <= mem_ctrlsig(MEM_WRITE);
dADDR <= mem_addr(31 downto 0) ;
dDout <= mem_data_in;
-- specify type
dDTYPE(0) <= '1' when (mem_memop = MEMOP_BYTE or
mem_memop = MEMOP_BYTEU or
mem_memop = MEMOP_LEFT or
mem_memop = MEMOP_RIGHT) else '0';
dDTYPE(1) <= '1' when (mem_memop = MEMOP_HALF or
mem_memop = MEMOP_HALFU) else '0';
dDTYPE(2) <= '1' when (mem_memop = MEMOP_WORD) else '0';
-- sign extension for memory data
mem_data_out <= signext1(dDin( 7 downto 0)) when mem_memop = MEMOP_BYTE else
unsiext1(dDin( 7 downto 0)) when mem_memop = MEMOP_BYTEU else
signext2(dDin(15 downto 0)) when mem_memop = MEMOP_HALF else
unsiext2(dDin(15 downto 0)) when mem_memop = MEMOP_HALFU else
dDin(31 downto 0) when mem_memop = MEMOP_WORD else
mem_tmp when mem_memop = MEMOP_LEFT else
mem_tmp when mem_memop = MEMOP_RIGHT;
--------------------------------------------------------------------------------
-- WB STAGE --
--------------------------------------------------------------------------------
-- register transfer
process(CLK)
begin
if ( CLK = '1' and CLK'event and iSTALL = '0') then
if (mem_exception='1') then
-- introduce a bubble in WB
wb_instr <= x"00000000";
wb_pc4 <= x"00000000";
wb_ctrlsig <= x"00";
wb_mem_out <= x"00000000";
wb_alu_out <= x"00000000";
wb_rk <= "00000";
wb_is_mfc0 <= '0';
wb_is_mtc0 <= '0';
else
-- normal operation
wb_instr <= mem_instr;
wb_pc4 <= mem_pc4;
wb_ctrlsig <= mem_ctrlsig;
wb_mem_out <= mem_data_out;
wb_alu_out <= mem_addr;
wb_rk <= mem_rk;
wb_is_mfc0 <= mem_is_mfc0;
wb_is_mtc0 <= mem_is_mtc0;
end if;
end if;
end process;
-- the mux
wb_value_of_rk <= wb_mem_out when wb_ctrlsig(MEM_TO_REG) = '1'
else wb_alu_out;
end Behavioral;
| gpl-3.0 | badde60b314659fadd670961f7a2f715 | 0.472477 | 3.628559 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_mergesort_v1_00_a/hdl/vhdl/hw_acc_mergesort.vhd | 2 | 5,386 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_mergesort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_mergesort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_mergesort is
component mergesort is
port
(
array0_addr0 : out std_logic_vector(0 to (32 - 1));
array0_dIN0 : out std_logic_vector(0 to (32 - 1));
array0_dOUT0 : in std_logic_vector(0 to (32 - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
array1_addr0 : out std_logic_vector(0 to (32 - 1));
array1_dIN0 : out std_logic_vector(0 to (32 - 1));
array1_dOUT0 : in std_logic_vector(0 to (32 - 1));
array1_rENA0 : out std_logic;
array1_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
signal in_BRAM_A_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_A_wEN : std_logic;
signal in_BRAM_B_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_B_wEN : std_logic;
signal in_BRAM_C_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_C_wEN : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
BRAM_A_addr <= in_BRAM_A_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_A_wEN <= in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN;
BRAM_B_addr <= in_BRAM_B_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_B_wEN <= in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN;
BRAM_C_addr <= in_BRAM_C_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_C_wEN <= in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN;
uut : mergesort
port map (
array0_addr0 => in_BRAM_A_addr,
array0_dIN0 => BRAM_A_dout,
array0_dOUT0 => BRAM_A_din,
array0_rENA0 => BRAM_A_en,
array0_wENA0 => in_BRAM_A_wen,
array1_addr0 => in_BRAM_B_addr,
array1_dIN0 => BRAM_B_dout,
array1_dOUT0 => BRAM_B_din,
array1_rENA0 => BRAM_B_en,
array1_wENA0 => in_BRAM_B_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | 4471ff442d0ea644da21614a750ed7f9 | 0.567026 | 2.920824 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder_bit.vhd | 3 | 7,451 | -------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder_bit.vhd
--
-- Description: Implements 1 bit of the pf_adder
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:26 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2001-09-25
-- - Added generic to allow selection of a registered output
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean := true
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic; -- A operand
Bin : in std_logic; -- B operand
Add_sub_n : in std_logic; -- Function ('1' = add, '0' = A - B)
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_adder_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal lutout_AddSub : std_logic;
signal addsub_result : std_logic;
signal addsub_result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"0069"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lutout_AddSub,
--- xst wrk around I0 => Bin,
--- xst wrk around I1 => Ain,
--- xst wrk around I2 => Add_sub_n,
--- xst wrk around I3 => '0');
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"0069"
)
port map (
O => lutout_AddSub,
I0 => Bin,
I1 => Ain,
I2 => Add_sub_n,
I3 => '0');
MUXCY_I : MUXCY_L
port map (
DI => Ain,
CI => Carry_In,
S => lutout_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => lutout_AddSub,
CI => Carry_In,
O => addsub_result);
FDRE_I: FDRE
port map (
Q => addsub_result_Reg,
C => Clk,
CE => Clock_Enable,
D => addsub_result,
R => Rst
);
USE_REGISTERED_RESULT : if (C_REGISTERED_RESULT = true) generate
Result <= addsub_result_Reg; -- registered version
end generate USE_REGISTERED_RESULT;
USE_COMBINATIONAL_RESULT : if (C_REGISTERED_RESULT = false) generate
Result <= addsub_result; -- combinational version
end generate USE_COMBINATIONAL_RESULT;
end implementation;
| bsd-3-clause | dd75e4ff2bb983af3ab2c650655fba81 | 0.386794 | 4.630827 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/user_logic.vhd | 8 | 29,499 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_c;
use fsl_v20_v2_11_c.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 810968abf292fe5f7d9201cff40b8dd6 | 0.518289 | 3.540446 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/equal_1.vhd | 2 | 15,082 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- equal_1.c
-- FIRST_THREAD 5
-- SECOND_THREAD 5
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- if ( hthread_self( FIRST_THREAD, SECOND_THREAD ) != 0 ) retVal = SUCCESS;
-- else retVal = FAILURE;
when FUNCTION_START =>
-- Push FIRST_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push SECOND_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_equal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EQUAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
case intrfc2thrd_value is
when x"00000000" =>
retVal_next <= x"00000001";
when others =>
retVal_next <= Z32;
end case;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 2a2ab1fd945ce7f872769eaf3e0a04f1 | 0.536666 | 3.868171 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_init_3.vhd | 2 | 18,377 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: attr_init_3.c
-- NUM_THREADS 5
-- reg1 = i
-- reg2 = * attr
-- reg3 = * function
-- reg4 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_attr_init( data->attr );
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_5 =>
reg1_next <= Z32;
next_state <= STATE_6;
when STATE_6 =>
case reg1 is
when x"00000000" => next_state <= STATE_7;
when x"00000001" => next_state <= STATE_7;
when x"00000002" => next_state <= STATE_7;
when x"00000003" => next_state <= STATE_7;
when x"00000004" => next_state <= STATE_7;
when others => next_state <= STATE_12;
end case;
-- hthread_create( &data->thread[i], &data->attr, data->function, NULL );
when STATE_7 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push &data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_12 =>
reg1_next <= Z32;
next_state <= STATE_13;
when STATE_13 =>
case reg1 is
when x"00000000" => next_state <= STATE_14;
when x"00000001" => next_state <= STATE_14;
when x"00000002" => next_state <= STATE_14;
when x"00000003" => next_state <= STATE_14;
when x"00000004" => next_state <= STATE_14;
when others => next_state <= STATE_18;
end case;
-- retVal = hthread_join( data->thread[i], NULL );
when STATE_14 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
reg1_next <= reg1 + 1;
when STATE_18 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 9619f7c08e60240f96027f64e69cf3f0 | 0.551124 | 3.676871 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/fsl_v20.vhd | 2 | 17,211 | -------------------------------------------------------------------------------
-- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- fsl_v20.vhd - Entity and architecture
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: fsl_v20.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2003-02-13 First Version
-- satish 2004-03-03 New Version
-- rolandp 2006-08-20 BRAM in asynch mode
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library fsl_v20_v2_11_f;
use fsl_v20_v2_11_f.sync_fifo;
use fsl_v20_v2_11_f.async_fifo;
entity fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer := 1;
C_ASYNC_CLKS : integer := 0;
C_IMPL_STYLE : integer := 0;
C_USE_CONTROL : integer := 1;
C_FSL_DWIDTH : integer := 32;
C_FSL_DEPTH : integer := 16;
C_READ_CLOCK_PERIOD : integer := 0
);
port (
-- Clock and reset signals
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
-- FSL master signals
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
-- FSL slave signals
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
-- FIFO status signals
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end entity fsl_v20;
architecture IMP of fsl_v20 is
component Sync_FIFO is
generic (
C_IMPL_STYLE : Integer;
WordSize : Integer;
MemSize : Integer);
port (
Reset : in Std_Logic;
Clk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Sync_FIFO;
component Async_FIFO is
generic (
WordSize : Integer;
MemSize : Integer;
Protect : Boolean);
port (
Reset : in Std_Logic;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Async_FIFO;
component Async_FIFO_BRAM is
generic (
WordSize : Integer;
MemSize : Integer;
Protect : Boolean);
port (
Reset : in Std_Logic;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Async_FIFO_BRAM;
signal sys_rst_i : std_logic;
signal srl_time_out : std_logic;
signal fsl_rst_i : std_logic;
signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
signal fifo_full : std_logic;
-- signal fifo_half_full : std_logic;
-- signal fifo_half_empty : std_logic;
signal fifo_has_data : std_logic;
signal fsl_s_control_i : std_logic;
signal srl_clk : std_logic;
begin -- architecture IMP
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_i <= not SYS_Rst;
else
sys_rst_i <= SYS_Rst;
end if;
end process SYS_RST_PROC;
Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
srl_clk <= FSL_M_Clk;
end generate Rst_Delay_Async;
Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
srl_clk <= FSL_Clk;
end generate Rst_Delay_Sync;
POR_SRL_I : SRL16
generic map (
INIT => X"FFFF")
port map (
D => '0',
CLK => srl_Clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
POR_FF_I : FDS
port map (
Q => fsl_rst_i,
D => srl_time_out,
C => srl_Clk,
S => sys_rst_i);
FSL_Rst <= fsl_rst_i;
-----------------------------------------------------------------------------
-- Width is 1, so implement a registers
-----------------------------------------------------------------------------
Only_Register : if (C_FSL_DEPTH = 1) generate
signal fsl_s_exists_i : std_logic;
signal fsl_m_full_i : std_logic;
begin
-- FSL_S_Clk and FSL_M_Clk are the same
Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
FIFO : process (FSL_Clk) is
variable fifo_full : std_logic;
begin -- process FIFO
if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
if fsl_rst_i = '1' then -- synchronous reset (active high)
fifo_full := '0';
Fsl_m_full_i <= '1';
Fsl_s_exists_i <= '0';
else
if (fifo_full = '0') then -- Empty
if (FSL_M_Write = '1') then
fifo_full := '1';
FSL_S_Data <= FSL_M_Data;
fsl_s_control_i <= FSL_M_Control;
end if;
end if;
if (fifo_full = '1') then -- Has data
if (FSL_S_Read = '1') then
fifo_full := '0';
end if;
end if;
Fsl_m_full_i <= fifo_full;
Fsl_s_exists_i <= fifo_full;
end if;
end if;
end process FIFO;
end generate Sync_Clocks;
FSL_S_Exists <= fsl_s_exists_i;
FSL_Has_Data <= fsl_s_exists_i;
FSL_M_Full <= fsl_m_full_i;
FSL_Full <= fsl_m_full_i;
FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
end generate Only_Register;
Using_FIFO: if (C_FSL_DEPTH > 1) generate
begin
-- Map Master Data/Control signal
Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
-- Map Slave Data/Control signal
FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
-- SRL FIFO BASED IMPLEMENTATION
Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
Use_Control: if (C_USE_CONTROL /= 0) generate
Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
Sync_FIFO_I1 : Sync_FIFO
generic map (
C_IMPL_STYLE => C_IMPL_STYLE,
WordSize => C_FSL_DWIDTH + 1,
MemSize => C_FSL_DEPTH)
port map (
Reset => fsl_rst_i,
Clk => FSL_Clk,
WE => FSL_M_Write,
DataIn => Data_In,
Full => fifo_full,
RD => FSL_S_Read,
DataOut => Data_Out,
Exists => fifo_has_data);
end generate Use_Control;
Use_Data: if (C_USE_CONTROL = 0) generate
fsl_s_control_i <= '0';
Sync_FIFO_I1 : Sync_FIFO
generic map (
C_IMPL_STYLE => C_IMPL_STYLE,
WordSize => C_FSL_DWIDTH,
MemSize => C_FSL_DEPTH)
port map (
Reset => fsl_rst_i,
Clk => FSL_Clk,
WE => FSL_M_Write,
DataIn => Data_In(0 to C_FSL_DWIDTH-1),
Full => fifo_full,
RD => FSL_S_Read,
DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
Exists => fifo_has_data);
end generate Use_Data;
end generate Sync_FIFO_Gen;
Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
Use_Control: if (C_USE_CONTROL /= 0) generate
Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
-- LUT RAM implementation
Async_FIFO_I1: Async_FIFO
generic map (
WordSize => C_FSL_DWIDTH + 1, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_DPRAM1;
Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
-- BRAM implementation
Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
generic map (
WordSize => C_FSL_DWIDTH + 1, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_BRAM1;
end generate Use_Control;
Use_Data: if (C_USE_CONTROL = 0) generate
fsl_s_control_i <= '0';
Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
-- LUT RAM implementation
Async_FIFO_I1 : Async_FIFO
generic map (
WordSize => C_FSL_DWIDTH, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_DPRAM0;
Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
-- BRAM implementation
Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
generic map (
WordSize => C_FSL_DWIDTH, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_BRAM0;
end generate Use_Data;
end generate Async_FIFO_Gen;
FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
-- forcing full to '1'
FSL_S_Exists <= fifo_has_data;
FSL_Full <= fifo_full;
FSL_Has_Data <= fifo_has_data;
FSL_S_Control <= fsl_s_control_i;
FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
end generate Using_FIFO;
end architecture IMP;
| bsd-3-clause | c590cb9fdfca4499aa2d1f62235d3bfa | 0.501772 | 3.730169 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/rx_module.vhd | 1 | 15,702 | --------------------------------------------------------------------------------
-- Title : RX module v2
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_module.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-23
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines modules rx_get_data.vhd, rx_ctrl.vhd and 2 FIFO's
-- to calculate valid values for RX_FIFO_DEPTH refer to ug_fifo.pdf page 9
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- * rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_module is
generic(
DEVICE_FAMILY : string := "unused";
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
rst : in std_logic;
-- IP Core
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
-- FIFO
rx_fifo_c_rd_enable : in std_logic;
rx_fifo_wr_rd_enable : in std_logic;
rx_fifo_c_empty : out std_logic;
rx_fifo_wr_empty : out std_logic;
rx_fifo_c_out : out std_logic_vector(31 downto 0);
rx_fifo_wr_out : out std_logic_vector(31 downto 0);
-- Tx Module
rx_tag_nbr : out std_logic_vector(7 downto 0);
rx_tag_rcvd : out std_logic;
-- error
rx_type_fmt_err : out std_logic_vector(1 downto 0);
rx_ecrc_err : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end entity rx_module;
architecture rx_module_arch of rx_module is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component rx_ctrl
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
sop_q_i : in std_logic;
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end component;
component rx_get_data
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- rx_ctrl and rx_get_data connection signals
signal int_len_cntr_val : std_logic_vector(9 downto 0);
signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_wrusedw_c : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_c_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_c_usedw : std_logic_vector(9 downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_wrusedw_wr : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_wr_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_wr_usedw : std_logic_vector(9 downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
-- signals for signal management process
signal int_ready : std_logic;
signal int_sop : std_logic;
signal int_err : std_logic;
signal int_sop_q : std_logic;
signal int_tlp_type : std_logic_vector(4 downto 0);
signal int_tlp_fmt : std_logic_vector(2 downto 0);
-- define some aliases for easier handling
alias rx_data0_type is rx_st_data0(28 downto 24);
alias rx_data0_fmt is rx_st_data0(31 downto 29);
-- debug signals: none
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
rx_st_mask0 <= '0';
rx_st_ready0 <= int_ready;
int_rx_wrusedw_c_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_c)),10));
int_rx_wrusedw_wr_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_wr)),10));
int_rx_fifo_c_usedw <= int_rx_wrusedw_c_temp;
int_rx_fifo_wr_usedw <= int_rx_wrusedw_wr_temp;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
-- registers to remembe the type and fmt for the last received TLP
process(rst, clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_type <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_type <= rx_data0_type;
end if;
end if;
end process;
process(rst, clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_fmt <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_fmt <= rx_data0_fmt;
end if;
end if;
end process;
rx_sig_manage : process(rst, clk)
begin
if rst = '1' then
int_ready <= '0';
int_sop <= '0';
int_err <= '0';
int_sop_q <= '0';
elsif clk'event and clk = '1' then
------------------------------
-- manage registered signals
------------------------------
int_sop_q <= rx_st_sop0;
--------------------------------------
-- signal ECRC error to error module
--------------------------------------
if rx_st_err0 = '1' and int_err = '0' then
rx_ecrc_err <= '1';
else
rx_ecrc_err <= '0';
end if;
-------------------------------------------------------
-- if an error state occured reset ready signal
-- until rx_ctrl has finished processing the error
-- if the FIFOs are not full assert ready
-- else deassert it until the FIFOs are not full
-------------------------------------------------------
if ((int_err = '1' or rx_st_err0 = '1') and rx_st_eop0 = '1' and rx_st_valid0 = '1') or
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw >= FIFO_MAX_USEDW) or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw >= FIFO_MAX_USEDW) then
int_ready <= '0';
elsif int_err = '0' and (
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw < FIFO_MAX_USEDW and int_c_wr_full = '0') or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw < FIFO_MAX_USEDW and int_wr_wr_full = '0')
) then
int_ready <= '1';
end if;
-----------------------------------------------------------------
-- reset error flag if rx_ctrl has finished working on the fifo
-- set error flag if error ocurs during transmission
-- otherwise keep error flag value
-----------------------------------------------------------------
if int_fifo_action_done = '1' then
int_err <= '0';
elsif rx_st_err0 = '1' and rx_st_valid0 = '1' then
int_err <= '1';
else
int_err <= int_err;
end if;
if rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_sop <= '0';
elsif rx_st_valid0 = '1' and rx_st_sop0 = '1' then
int_sop <= '1';
else
int_sop <= int_sop;
end if;
end if;
end process rx_sig_manage;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
rx_ctrl_comp : rx_ctrl
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_err0 => rx_st_err0,
rx_st_valid0 => rx_st_valid0,
rx_st_sop0 => rx_st_sop0,
rx_st_eop0 => rx_st_eop0,
rx_st_be0 => rx_st_be0,
tlp_type_i => rx_data0_type,
tlp_fmt_i => rx_data0_fmt,
-- FIFO
rx_fifo_c_enable_o => int_c_wr_enable,
rx_fifo_wr_enable_o => int_wr_wr_enable,
-- rx_sig_manage
sop_q_i => int_sop_q,
fifo_action_done_o => int_fifo_action_done,
-- rx_get_data
len_cntr_val_i => int_len_cntr_val
);
rx_get_data_comp : rx_get_data
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_valid0 => rx_st_valid0,
rx_st_data0 => rx_st_data0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_sop0 => rx_st_sop0,
-- FIFO
rx_fifo_in_o => int_rx_fifo_data,
-- tx_ctrl
tag_nbr_o => rx_tag_nbr,
tag_rcvd_o => rx_tag_rcvd,
-- rx_ctrl
len_cntr_val_o => int_len_cntr_val,
-- error
type_fmt_err_o => rx_type_fmt_err,
-- rx_sig_manage
sop_q_i => int_sop_q
);
c_fifo_comp : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "ON")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_c_rd_enable,
wrclk => clk,
wrreq => int_c_wr_enable,
q => rx_fifo_c_out,
rdempty => rx_fifo_c_empty,
wrfull => int_c_wr_full,
wrusedw => int_rx_wrusedw_c);
wr_fifo_comp : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "OFF")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_wr_rd_enable,
wrclk => clk,
wrreq => int_wr_wr_enable,
q => rx_fifo_wr_out,
rdempty => rx_fifo_wr_empty,
wrfull => int_wr_wr_full,
wrusedw => int_rx_wrusedw_wr);
-------------------------
-- manage debug signals
-------------------------
rx_debug_out <= (others => '0');
-------------------------------------------------------------------------------
end architecture rx_module_arch;
| gpl-3.0 | 2a86c61403b4cdfc7b9539005faa3e09 | 0.447905 | 3.736792 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_5.vhd | 2 | 17,299 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_5.c
-- ARGUMENT_VALUE 31
-- reg6 = * function
-- reg7 = thread
-- reg4 = childVal
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, (void *) ARGUMENT_VALUE );
when STATE_3 =>
-- push ARGUMENT_VALUE
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"0000001F";
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, &data->childVal );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push &data->childVal
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- if (data->childVal == ARGUMENT_VALUE ) retVal = SUCCESS;
-- else retVal = FAILURE;
when STATE_12 =>
-- Load the value of data->childThread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
if ( intrfc2thrd_value = x"0000001F" ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | d84926204a1cc5795cfd2048600c0523 | 0.54506 | 3.807836 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/m_eth.vhd | 1 | 24,129 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity m_eth is
generic(
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
----------------------------------------------
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
progIO_id : out std_logic_vector(3 downto 0);
progIO_reset : out std_logic;
progIO_wren : out std_logic;
progIO_addr : out std_logic_vector(9 downto 0);
progIO_wdata : out std_logic_vector(15 downto 0);
progIO_rdata : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(15 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of m_eth is
component ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(15 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
component macAddrConfig
port (
ethtx_port_id : in std_logic_vector(7 downto 0);
ethrx_port_id : in std_logic_vector(7 downto 0);
db_port_id : in std_logic_vector(7 downto 0);
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0);
ethtx_in_port : out std_logic_vector(7 downto 0);
ethrx_in_port : out std_logic_vector(7 downto 0);
db_in_port : out std_logic_vector(7 downto 0)
);
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal txen_buf : std_logic;
signal db_ce : std_logic_vector(15 downto 0);
signal ethtx_ce : std_logic_vector(15 downto 0);
signal ethrx_ce : std_logic_vector(15 downto 0);
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
u_rx : ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
-- db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
-- eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
-- eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
db_rx_ce <= db_ce(conv_integer(PORTS_DB_RX));
eth_rx_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX));
eth_rxdma_ce <= ethrx_ce(conv_integer(PORTS_ETH_RXDMA));
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethrx_port_id( 7 downto 4),
ce => ethrx_ce
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
-- ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
ethrx_task_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX_TASK));
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
-- ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
u_tx : ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
txen <= txen_buf;
-- db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
-- eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
db_tx_ce <= db_ce(conv_integer(PORTS_DB_TX));
eth_tx_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX));
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethtx_port_id( 7 downto 4),
ce => ethtx_ce
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
-- ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_task_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX_TASK));
-- ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
-- local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
u_db_zcpsm_ce : zcpsmDecode
port map(
port_id_H => db_port_id( 7 downto 4),
ce => db_ce
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
-- db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
db_debug_ce <= db_ce(conv_integer(PORTS_DB_DEBUG));
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
-- db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
-- local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
-- (others => 'Z');
u_macAddr : macAddrConfig
port map(
ethtx_port_id => ethtx_port_id,
ethrx_port_id => ethrx_port_id,
db_port_id => db_port_id,
local_id_MAC0_Req => local_id_MAC0_Req,
local_id_MAC0_A => local_id_MAC0_A,
local_id_MAC0_B => local_id_MAC0_B,
local_id => local_id,
ethtx_in_port => ethtx_in_port,
ethrx_in_port => ethrx_in_port,
db_in_port => db_in_port
);
end arch_eth;
| gpl-2.0 | 6eb0ce1888eb76d7a5905439e29543bf | 0.579759 | 2.689967 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/testbench.vhd | 3 | 27,888 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library plb_v34_v1_02_a;
library opb_v20_v1_10_c;
library plb2opb_bridge_v1_01_a;
entity testbench is
end entity;
architecture behavioral of testbench is
constant PLB_NUM_MASTERS : integer := 1;
constant PLB_NUM_SLAVES : integer := 1;
constant PLB_AWIDTH : integer := 32;
constant PLB_DWIDTH : integer := 64;
constant OPB_NUM_MASTERS : integer := 1;
constant OPB_NUM_SLAVES : integer := 1;
constant OPB_AWIDTH : integer := 32;
constant OPB_DWIDTH : integer := 32;
constant DCR_AWIDTH : integer := 10;
constant DCR_DWIDTH : integer := 32;
constant PLB_MID_WIDTH : integer := 2;
constant PLB_TAWIDTH : integer := PLB_NUM_MASTERS*PLB_AWIDTH;
constant PLB_TDWIDTH : integer := PLB_NUM_MASTERS*PLB_DWIDTH;
constant PLB_SAWIDTH : integer := PLB_NUM_SLAVES*PLB_AWIDTH;
constant PLB_SDWIDTH : integer := PLB_NUM_SLAVES*PLB_DWIDTH;
constant PLB_SLVMST : integer := PLB_NUM_SLAVES*PLB_NUM_MASTERS;
constant HWTI_SLV : integer := 0;
constant HWTI_MST : integer := 0;
-- Signals for the PLB bus
signal PLB_SaddrAck : std_logic;
signal PLB2OPB_rearb : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal DCR_ABus : std_logic_vector(0 to DCR_AWIDTH-1);
signal DCR_DBus : std_logic_vector(0 to DCR_DWIDTH-1);
signal DCR_Read : std_logic;
signal DCR_Write : std_logic;
signal PLB_dcrAck : std_logic;
signal PLB_dcrDBus : std_logic_vector(0 to DCR_DWIDTH-1);
signal M_ABus : std_logic_vector(0 to PLB_TAWIDTH-1);
signal M_BE : std_logic_vector(0 to PLB_TDWIDTH/8-1);
signal M_RNW : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_abort : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_busLock : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_compress : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_guarded : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_lockErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_MSize : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal M_ordered : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_priority : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal M_rdBurst : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_request : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_size : std_logic_vector(0 to PLB_NUM_MASTERS*4-1);
signal M_type : std_logic_vector(0 to PLB_NUM_MASTERS*3-1);
signal M_wrBurst : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_wrDBus : std_logic_vector(0 to PLB_TDWIDTH-1);
signal PLB_ABus : std_logic_vector(0 to PLB_AWIDTH-1);
signal PLB_BE : std_logic_vector(0 to PLB_DWIDTH/8-1);
signal PLB_MAddrAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MBusy : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdBTerm : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdDAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdDBus : std_logic_vector(0 to PLB_TDWIDTH-1);
signal PLB_MRdWdAddr : std_logic_vector(0 to PLB_NUM_MASTERS*4-1);
signal PLB_MRearbitrate : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MWrBTerm : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MWrDAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MSSize : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal PLB_PAValid : std_logic;
signal PLB_RNW : std_logic;
signal PLB_SAValid : std_logic;
signal PLB_abort : std_logic;
signal PLB_busLock : std_logic;
signal PLB_compress : std_logic;
signal PLB_guarded : std_logic;
signal PLB_lockErr : std_logic;
signal PLB_masterID : std_logic_vector(0 to PLB_MID_WIDTH-1);
signal PLB_MSize : std_logic_vector(0 to 1);
signal PLB_ordered : std_logic;
signal PLB_pendPri : std_logic_vector(0 to 1);
signal PLB_pendReq : std_logic;
signal PLB_rdBurst : std_logic;
signal PLB_rdPrim : std_logic;
signal PLB_reqPri : std_logic_vector(0 to 1);
signal PLB_size : std_logic_vector(0 to 3);
signal PLB_type : std_logic_vector(0 to 2);
signal PLB_wrBurst : std_logic;
signal PLB_wrDBus : std_logic_vector(0 to PLB_DWIDTH-1);
signal PLB_wrPrim : std_logic;
signal Sl_addrAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_MErr : std_logic_vector(0 to PLB_SLVMST-1);
signal Sl_MBusy : std_logic_vector(0 to PLB_SLVMST-1);
signal Sl_rdBTerm : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdComp : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdDAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdDBus : std_logic_vector(0 to PLB_SDWIDTH-1);
signal Sl_rdWdAddr : std_logic_vector(0 to PLB_NUM_SLAVES*4-1);
signal Sl_rearbitrate : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_SSize : std_logic_vector(0 to PLB_NUM_SLAVES*2-1);
signal Sl_wait : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrBTerm : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrComp : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrDAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal PLB_SMErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_SMBusy : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_SrdBTerm : std_logic;
signal PLB_SrdComp : std_logic;
signal PLB_SrdDAck : std_logic;
signal PLB_SrdDBus : std_logic_vector(0 to PLB_DWIDTH-1);
signal PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal PLB_Srearbitrate : std_logic;
signal PLB_Sssize : std_logic_vector(0 to 1);
signal PLB_Swait : std_logic;
signal PLB_SwrBTerm : std_logic;
signal PLB_SwrComp : std_logic;
signal PLB_SwrDAck : std_logic;
signal ArbAddrVldReg : std_logic;
signal SYS_Rst : std_logic;
signal Bus_Error_Det : std_logic;
signal PLB_Rst : std_logic;
signal PLB_Clk : std_logic;
-- Signals for the OPB bus
signal Debug_SYS_Rst : std_logic;
signal WDT_Rst : std_logic;
signal OPB_Clk : std_logic;
signal OPB_Rst : std_logic;
signal OM_ABus : std_logic_vector(0 to OPB_AWIDTH*OPB_NUM_MASTERS-1);
signal OM_BE : std_logic_vector(0 to (OPB_DWIDTH+7)/8*OPB_NUM_MASTERS-1);
signal OM_beXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_busLock : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_DBus : std_logic_vector(0 to OPB_DWIDTH*OPB_NUM_MASTERS-1);
signal OM_DBusEn : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_DBusEn32_63 : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_dwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_fwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_hwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_request : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_RNW : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_select : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_seqAddr : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OSl_beAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_DBus : std_logic_vector(0 to OPB_DWIDTH*OPB_NUM_SLAVES-1);
signal OSl_DBusEn : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_DBusEn32_63 : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_errAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_dwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_fwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_hwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_retry : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_toutSup : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_xferAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OPB_MRequest : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_ABus : std_logic_vector(0 to OPB_AWIDTH-1);
signal OPB_BE : std_logic_vector(0 to (OPB_DWIDTH+7)/8-1);
signal OPB_beXfer : std_logic;
signal OPB_beAck : std_logic;
signal OPB_busLock : std_logic;
signal OPB_rdDBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_wrDBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_DBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_errAck : std_logic;
signal OPB_dwAck : std_logic;
signal OPB_dwXfer : std_logic;
signal OPB_fwAck : std_logic;
signal OPB_fwXfer : std_logic;
signal OPB_hwAck : std_logic;
signal OPB_hwXfer : std_logic;
signal OPB_MGrant : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_pendReq : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_retry : std_logic;
signal OPB_RNW : std_logic;
signal OPB_select : std_logic;
signal OPB_seqAddr : std_logic;
signal OPB_timeout : std_logic;
signal OPB_toutSup : std_logic;
signal OPB_xferAck : std_logic;
-- Signals for the PLB2OPB bridge
PLB_Rst : std_logic; -- unused input
PLB_Clk : std_logic;
OPB_Rst : std_logic;
OPB_Clk : std_logic;
Bus_Error_Det : std_logic;
BGI_Trans_Abort : std_logic;
PLB_abort : std_logic;
PLB_ABus : std_logic_vector (0 to C_PLB_AWIDTH-1);
PLB_BE : std_logic_vector (0 to C_PLB_DWIDTH/8-1);
PLB_busLock : std_logic;
PLB_compress : std_logic;
PLB_guarded : std_logic;
PLB_lockErr : std_logic;
PLB_masterID : std_logic_vector (0 to C_PLB_MID_WIDTH-1);
PLB_MSize : std_logic_vector (0 to 1);
PLB_ordered : std_logic;
PLB_PAValid : std_logic;
PLB_RNW : std_logic;
PLB_size : std_logic_vector (0 to 3);
PLB_type : std_logic_vector (0 to 2);
BGO_addrAck : std_logic;
BGO_MBusy : std_logic_vector (0 to C_PLB_NUM_MASTERS-1);
BGO_MErr : std_logic_vector (0 to C_PLB_NUM_MASTERS-1);
BGO_rearbitrate : std_logic;
BGO_SSize : std_logic_vector (0 to 1);
BGO_wait : std_logic;
PLB_rdPrim : std_logic;
PLB_SAValid : std_logic;
PLB_wrPrim : std_logic;
PLB_wrBurst : std_logic;
PLB_wrDBus : std_logic_vector (0 to C_PLB_DWIDTH-1);
BGO_wrBTerm : std_logic;
BGO_wrComp : std_logic;
BGO_wrDAck : std_logic;
PLB_rdBurst : std_logic;
BGO_rdBTerm : std_logic;
BGO_rdComp : std_logic;
BGO_rdDAck : std_logic;
BGO_rdDBus : std_logic_vector (0 to C_PLB_DWIDTH-1);
BGO_rdWdAddr : std_logic_vector (0 to 3) ;
OPB_DBus : std_logic_vector (0 to C_OPB_DWIDTH-1);
OPB_errAck : std_logic;
OPB_MnGrant : std_logic;
OPB_retry : std_logic;
OPB_timeout : std_logic;
OPB_xferAck : std_logic;
BGO_ABus : std_logic_vector (0 to C_OPB_AWIDTH-1);
BGO_BE : std_logic_vector (0 to C_OPB_DWIDTH/8-1) ;
BGO_busLock : std_logic;
BGO_DBus : std_logic_vector (0 to C_OPB_DWIDTH-1);
BGO_request : std_logic;
BGO_RNW : std_logic;
BGO_select : std_logic;
BGO_seqAddr : std_logic;
DCR_ABus : std_logic_vector (0 to C_DCR_AWIDTH-1);
DCR_DBus : std_logic_vector (0 to C_DCR_DWIDTH-1);
DCR_Read : std_logic;
DCR_Write : std_logic;
BGO_dcrAck : std_logic;
BGO_dcrDBus : std_logic_vector (0 to C_DCR_DWIDTH-1);
PLB2OPB_rearb : std_logic
-- Signals for the HWTI
signal tid : std_logic_vector(0 to 7);
signal arg : std_logic_vector(0 to 31);
signal opgo : std_logic;
signal opcode : std_logic_vector(0 to 7);
signal oparg : std_logic_vector(0 to 31);
signal opack : std_logic;
signal operr : std_logic;
signal opres : std_logic_vector(0 to 31);
begin
ihwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
C_MANAG_BASEADDR => x"00000000",
C_SCHED_BASEADDR => x"00000000",
C_MUTEX_BASEADDR => x"00000000",
C_CONDV_BASEADDR => x"00000000",
C_BASEADDR => X"FFFFFFFF",
C_HIGHADDR => X"00000000",
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => PLB_MID_WIDTH
)
port map
(
tid => tid,
arg => arg,
opgo => opgo,
opcode => opcode,
oparg => oparg,
opack => opack,
operr => operr,
opres => opres,
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck(0),
Sl_MBusy => Sl_MBusy(0*PLB_NUM_MASTERS to 1*PLB_NUM_MASTERS-1),
Sl_MErr => Sl_MErr(0*PLB_NUM_MASTERS to 1*PLB_NUM_MASTERS-1),
Sl_rdBTerm => Sl_rdBTerm(0),
Sl_rdComp => Sl_rdComp(0),
Sl_rdDAck => Sl_rdDAck(0),
Sl_rdDBus => Sl_rdDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
Sl_rdWdAddr => Sl_rdWdAddr(0*4 to 1*4-1),
Sl_rearbitrate => Sl_rearbitrate(0),
Sl_SSize => Sl_SSize(0*2 to 1*2-1),
Sl_wait => Sl_wait(0),
Sl_wrBTerm => Sl_wrBTerm(0),
Sl_wrComp => Sl_wrComp(0),
Sl_wrDAck => SL_wrDAck(0),
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort(0),
M_ABus => M_ABus(0*PLB_AWIDTH to 1*PLB_AWIDTH-1),
M_BE => M_BE(0*(PLB_DWIDTH/8) to 1*(PLB_DWIDTH/8)-1),
M_busLock => M_busLock(0),
M_compress => M_compress(0),
M_guarded => M_guarded(0),
M_lockErr => M_lockErr(0),
M_MSize => M_MSize(0*2 to 1*2-1),
M_ordered => M_ordered(0),
M_priority => M_priority(0*2 to 1*2-1),
M_rdBurst => M_rdBurst(0),
M_request => M_request(0),
M_RNW => M_RNW(0),
M_size => M_size(0*4 to 1*4-1),
M_type => M_type(0*3 to 1*3-1),
M_wrBurst => M_wrBurst(0),
M_wrDBus => M_wrDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
PLB_MBusy => PLB_MBusy(0),
PLB_MErr => PLB_MErr(0),
PLB_MWrBTerm => PLB_MWrBTerm(0),
PLB_MWrDAck => PLB_MWrDAck(0),
PLB_MAddrAck => PLB_MAddrAck(0),
PLB_MRdBTerm => PLB_MRdBTerm(0),
PLB_MRdDAck => PLB_MRdDAck(0),
PLB_MRdDBus => PLB_MRdDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
PLB_MRdWdAddr => PLB_MRdWdAddr(0*4 to 1*4-1),
PLB_MRearbitrate => PLB_MRearbitrate(0),
PLB_MSSize => PLB_MSSize(0*2 to 1*2-1)
);
iplb : entity plb_v34_v1_02_a.plb_v34
generic map
(
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_NUM_SLAVES => PLB_NUM_SLAVES,
C_PLB_MID_WIDTH => PLB_MID_WIDTH,
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_DCR_INTFCE => 0,
C_BASEADDR => "1111111111",
C_HIGHADDR => "0000000000",
C_DCR_AWIDTH => DCR_AWIDTH,
C_DCR_DWIDTH => DCR_DWIDTH,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_NUM_OPBCLK_PLB2OPB_REARB => 25
)
port map
(
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
M_ABus => M_ABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
Sl_addrAck => Sl_addrAck,
Sl_MErr => Sl_MErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMErr => PLB_SMErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
ArbAddrVldReg => ArbAddrVldReg,
SYS_Rst => SYS_Rst,
Bus_Error_Det => Bus_Error_Det,
PLB_Rst => PLB_Rst,
PLB_Clk => PLB_Clk
);
iopb : entity opb_v20_v1_10_c.opb_v20
generic map
(
C_OPB_AWIDTH => OPB_AWIDTH,
C_OPB_DWIDTH => OPB_DWIDTH,
C_NUM_MASTERS => OPB_NUM_MASTERS,
C_NUM_SLAVES => OPB_NUM_SLAVES,
C_USE_LUT_OR => 0,
C_EXT_RESET_HIGH => 1,
C_BASEADDR => x"10000000",
C_HIGHADDR => x"100001FF",
C_DYNAM_PRIORITY => 1,
C_PARK => 1,
C_PROC_INTRFCE => 1,
C_REG_GRANTS => 1,
C_DEV_BLK_ID => 0,
C_DEV_MIR_ENABLE => 0
)
port map
(
SYS_Rst => SYS_Rst,
Debug_SYS_Rst => Debug_SYS_Rst,
WDT_Rst => WDT_Rst,
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
M_ABus => OM_ABus,
M_BE => OM_BE,
M_beXfer => OM_beXfer,
M_busLock => OM_busLock,
M_DBus => OM_DBus,
M_DBusEn => OM_DBusEn,
M_DBusEn32_63 => OM_DBusEn32_63,
M_dwXfer => OM_dwXfer,
M_fwXfer => OM_fwXfer,
M_hwXfer => OM_hwXfer,
M_request => OM_request,
M_RNW => OM_RNW,
M_select => OM_select,
M_seqAddr => OM_seqAddr,
Sl_beAck => OSl_beAck,
Sl_DBus => OSl_DBus,
Sl_DBusEn => OSl_DBusEn,
Sl_DBusEn32_63 => OSl_DBusEn32_63,
Sl_errAck => OSl_errAck,
Sl_dwAck => OSl_dwAck,
Sl_fwAck => OSl_fwAck,
Sl_hwAck => OSl_hwAck,
Sl_retry => OSl_retry,
Sl_toutSup => OSl_toutSup,
Sl_xferAck => OSl_xferAck,
OPB_MRequest => OPB_MRequest,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_beXfer => OPB_beXfer,
OPB_beAck => OPB_beAck,
OPB_busLock => OPB_busLock,
OPB_rdDBus => OPB_rdDBus,
OPB_wrDBus => OPB_wrDBus,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_dwAck => OPB_dwAck,
OPB_dwXfer => OPB_dwXfer,
OPB_fwAck => OPB_fwAck,
OPB_fwXfer => OPB_fwXfer,
OPB_hwAck => OPB_hwAck,
OPB_hwXfer => OPB_hwXfer,
OPB_MGrant => OPB_MGrant,
OPB_pendReq => OPB_pendReq,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck
);
iplb2opb : entity plb2opb_bridge_v1_01_a.plb2opb_bridge
generic map
(
C_NO_PLB_BURST => 0,
C_DCR_INTFCE => 0,
C_NUM_ADDR_RNG => 1,
C_RNG0_BASEADDR => x"00000000";
C_RNG0_HIGHADDR => x"0003FFFF";
C_RNG1_BASEADDR => x"00000000";
C_RNG1_HIGHADDR => x"00000000";
C_RNG2_BASEADDR => x"00000000";
C_RNG2_HIGHADDR => x"00000000";
C_RNG3_BASEADDR => x"00000000";
C_RNG3_HIGHADDR => x"00000000";
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => PLB_MID_WIDTH,
C_OPB_AWIDTH => OPB_AWIDTH,
C_OPB_DWIDTH => OPB_DWIDTH,
C_DCR_BASEADDR => "0000000000",
C_DCR_HIGHADDR => "0000000111",
C_DCR_AWIDTH => DCR_AWIDTH,
C_DCR_DWIDTH => DCR_DWIDTH
)
port map
(
PLB_Rst => PLB_Rst,
PLB_Clk => PLB_Clk,
OPB_Rst => OPB_Rst,
OPB_Clk => OPB_Clk,
Bus_Error_Det => Bus_Error_Det,
BGI_Trans_Abort => BGI_Trans_Abort,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_size => PLB_size,
PLB_type => PLB_type,
BGO_addrAck => BGO_addrAck,
BGO_MBusy => BGO_MBusy,
BGO_MErr => BGO_MErr,
BGO_rearbitrate => BGO_rearbitrate,
BGO_SSize => BGO_SSize,
BGO_wait => BGO_wait,
PLB_rdPrim => PLB_rdPrim,
PLB_SAValid => PLB_SAValid,
PLB_wrPrim => PLB_wrPrim,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
BGO_wrBTerm => BGO_wrBTerm,
BGO_wrComp => BGO_wrComp,
BGO_wrDAck => BGO_wrDAck,
PLB_rdBurst => PLB_rdBurst,
BGO_rdBTerm => BGO_rdBTerm,
BGO_rdComp => BGO_rdComp,
BGO_rdDAck => BGO_rdDAck,
BGO_rdDBus => BGO_rdDBus,
BGO_rdWdAddr => BGO_rdWdAddr,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_MnGrant => OPB_MnGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
BGO_ABus => BGO_ABus,
BGO_BE => BGO_BE,
BGO_busLock => BGO_busLock,
BGO_DBus => BGO_DBus,
BGO_request => BGO_request,
BGO_RNW => BGO_RNW,
BGO_select => BGO_select,
BGO_seqAddr => BGO_seqAddr,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
BGO_dcrAck => BGO_dcrAck,
BGO_dcrDBus => BGO_dcrDBus,
PLB2OPB_rearb => PLB2OPB_rearb
);
end behavioral;
| bsd-3-clause | 0d0cd6712297f9b2a0383e62baff4d19 | 0.509968 | 3.460479 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmProgRam.vhd | 1 | 2,370 | ---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmProgRam
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity zcpsmProgRam is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
reset: in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 );
soft_rst : out std_logic;
prog_we : in std_logic;
prog_clk: in std_logic;
prog_addr : in std_logic_vector( AWIDTH-1 downto 0 );
prog_din : in std_logic_vector( 17 downto 0 )
);
end zcpsmProgRam;
architecture syn of zcpsmProgRam is
type RamType is array( 0 to (2**AWIDTH-1) ) of bit_vector( 17 downto 0 );
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile(PROG);
signal soft_rst_i : std_logic;
signal ones : std_logic_vector( 31 downto 0 );
begin
soft_rst <= soft_rst_i;
ones <= ( others=>'0' );
process( clk, reset )
begin
if reset='1' then
dout <= ( others=>'0' );
elsif clk'event and clk = '1' then
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
program : process (prog_clk)
begin
if prog_clk'event and prog_clk = '1' then
if prog_we = '1' then
RAM(conv_integer(prog_addr)) <= to_bitvector(prog_din);
end if;
end if;
end process;
soft_reset : process( prog_clk, reset )
begin
if reset='1' then
soft_rst_i <= '0';
elsif prog_clk'event and prog_clk = '1' then
if prog_we = '1' and prog_addr = ones( AWIDTH-1 downto 0 ) then
soft_rst_i <= prog_din(0);
end if;
end if;
end process;
end syn;
| gpl-2.0 | a69cf970f28dcfc0275c66bb8db9ccd3 | 0.539241 | 3.419913 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/control_register_logic.vhd | 3 | 16,975 | -------------------------------------------------------------------------------
-- $Id: control_register_logic.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- control_register_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: control_register_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the control register. The bits of this
-- register determine whether dynamic priority is enabled and
-- how parking (if enabled) is accomplished. This register is
-- written from the OPB. The bit definitions are as follows:
--
-- BIT DESCRIPTION RESET VALUE
-- ---- --------------------- -------------------
-- 0 Dynamic Priority Enable 0 (DYNAM_PRIORITY=false)
-- 1 (DYNAM_PRIORITY=true)
-- 1 Dynamic Priority R/W access 0 (DYNAM_PRIORITY=false)
-- 1 (DYNAM_PRIORITY=true)
-- 2 Park Enable 0 (PARK=false)
-- 1 (PARK=true)
-- 3 Park Enable R/W access 0 (PARK=false)
-- 1 (PARK=true)
-- 4 Park Master Not Last 0
-- 5 Priority Registers Valid 1
-- 6:C_NUM_MID_BITS Reserved
-- C_NUM_MID_BITS:C_OPBDATA_WIDTH-1 Park MasterID Master 0 ID
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
--Package file that contains constant definition for RESET_ACTIVE
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OPBDATA_WIDTH -- width of OPB data bus
-- C_NUM_MID_BITS -- number of bits required to encode master ids
-- C_DYNAM_PRIORITY -- indicates if dynamic priority is supported
-- C_PARK -- indicates if bus parking is supported
-- C_PROC_INTRFCE -- indicates if there is a processor intrfce
--
-- Definition of Ports:
--
-- -- OPB Interface
-- input Ctrlreg_wrce -- Control register write clock enable
-- input Bus2ip_data -- data to be written in the control register
--
-- output Ctrl_reg -- Control register data
--
-- -- Clock and Reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity control_register_logic is
generic ( C_OPBDATA_WIDTH : integer := 32;
C_NUM_MID_BITS : integer := 2;
C_DYNAM_PRIORITY : boolean := true;
C_PARK : boolean := true;
C_PROC_INTRFCE : boolean := true
);
port (
Ctrlreg_wrce : in std_logic;
Bus2Ip_Data : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Ctrl_reg : out std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Clk : in std_logic;
Rst : in std_logic
);
end control_register_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of control_register_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- set starting bit location for Park Master ID
constant PMID_START_LOC : integer := C_OPBDATA_WIDTH-C_NUM_MID_BITS;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- internal version of output signal
signal ctrl_reg_i : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- CONTROL_REGISTER_PROCESS
-------------------------------------------------------------------------------
-- This process loads data from the OPB when there is a write request and this
-- register is enabled. Certain bits are dependant on parameters, set these
-- according to the parameter values.
-------------------------------------------------------------------------------
-- If dynamic priority is supported, set DPEN and DPENRW to 1 and allow these
-- bits to be written if there is a processor interface
-- If there is no processor interface, set DPEN to 1 and DPENRW to 0
DYNAM_CTRL_GEN: if C_DYNAM_PRIORITY generate
DYNAM_PI_GEN: if C_PROC_INTRFCE generate
DYNAM_BITS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
ctrl_reg_i(DPEN_LOC) <= '1';
elsif Ctrlreg_wrce = '1' then
-- Load Control Register with OPB data if there is a write request
-- and the control register is enabled
ctrl_reg_i(DPEN_LOC) <= Bus2Ip_Data(DPEN_LOC);
else
ctrl_reg_i(DPEN_LOC) <= ctrl_reg_i(DPEN_LOC);
end if;
end if;
end process DYNAM_BITS_PROCESS;
ctrl_reg_i(DPENRW_LOC) <= '1';
end generate DYNAM_PI_GEN;
DYNAM_NOPI_GEN: if not(C_PROC_INTRFCE) generate
ctrl_reg_i(DPEN_LOC) <= '1';
ctrl_reg_i(DPENRW_LOC) <= '0';
end generate DYNAM_NOPI_GEN;
end generate DYNAM_CTRL_GEN;
-- If dynamic priority is not supported, DPEN and DPENRW are constants
FIXED_CTRL_GEN: if not(C_DYNAM_PRIORITY) generate
ctrl_reg_i(DPEN_LOC) <= '0';
ctrl_reg_i(DPENRW_LOC) <= '0';
end generate FIXED_CTRL_GEN;
-- If bus parking is supported, set PEN and PENRW to 1, PMN and PMID to 0
-- Allow these bits to be written if there is a processor interface
-- If there is no processor interface, set PEN to 1, PENRW, PMN and PMID to 0
PARK_CTRL_GEN: if C_PARK generate
PARK_PI_GEN: if C_PROC_INTRFCE generate
PARK_BITS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
ctrl_reg_i(PEN_LOC) <= '1';
ctrl_reg_i(PMN_LOC) <= '0'; -- default to park on last master
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1) <= (others => '0');
elsif Ctrlreg_wrce = '1' then
-- Load Control Register with OPB data if there is a write request
-- and the control register is enabled
ctrl_reg_i(PEN_LOC) <= Bus2Ip_Data(PEN_LOC);
ctrl_reg_i(PMN_LOC) <= Bus2Ip_Data(PMN_LOC);
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1) <=
Bus2IP_Data(PMID_START_LOC to C_OPBDATA_WIDTH-1);
else
ctrl_reg_i(PEN_LOC) <= ctrl_reg_i(PEN_LOC);
ctrl_reg_i(PMN_LOC) <= ctrl_reg_i(PMN_LOC);
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1) <=
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1);
end if;
end if;
end process PARK_BITS_PROCESS;
ctrl_reg_i(PENRW_LOC) <= '1';
end generate PARK_PI_GEN;
PARK_NOPI_GEN: if not(C_PROC_INTRFCE) generate
ctrl_reg_i(PEN_LOC) <= '1';
ctrl_reg_i(PENRW_LOC) <= '0';
ctrl_reg_i(PMN_LOC) <= '0';
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1) <= (others => '0');
end generate PARK_NOPI_GEN;
end generate PARK_CTRL_GEN;
-- If bus parking is not supported, PEN, PENRW, PMN, and PMID are constants
NOPARK_CTRL_GEN: if not(C_PARK) generate
ctrl_reg_i(PEN_LOC) <= '0';
ctrl_reg_i(PENRW_LOC) <= '0';
ctrl_reg_i(PMN_LOC) <= '0';
ctrl_reg_i(PMID_START_LOC to C_OPBDATA_WIDTH-1) <= (others => '0');
end generate NOPARK_CTRL_GEN;
-- If there is a processor interface, generate the PRV bit, otherwise
-- set it to '1'.
PRV_PI_GEN: if C_PROC_INTRFCE generate
PRV_BIT_PROCESS:process (Clk, Rst, Ctrlreg_wrce,
Bus2Ip_Data, ctrl_reg_i)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
ctrl_reg_i(PRV_LOC) <= '1'; -- default to priority registers valid
elsif Ctrlreg_wrce = '1' then
-- Load Control Register with OPB data if there is a write request
-- and the control register is enabled
ctrl_reg_i(PRV_LOC) <= Bus2Ip_Data(PRV_LOC);
else
ctrl_reg_i(PRV_LOC) <= ctrl_reg_i(PRV_LOC);
end if;
end if;
end process PRV_BIT_PROCESS;
end generate PRV_PI_GEN;
PRV_NOPI_GEN: if not(C_PROC_INTRFCE) generate
ctrl_reg_i(PRV_LOC) <= '1';
end generate PRV_NOPI_GEN;
-- Set unused bits of the control register to 0
ctrl_reg_i(CTRL_FIELD+1 to PMID_START_LOC-1) <= (others => '0');
-- Set output port to internal signal
Ctrl_reg <= ctrl_reg_i;
end implementation;
| bsd-3-clause | 0bff71e039d905177fc39056317b756d | 0.450368 | 4.617791 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/common/fifo_async.vhd | 1 | 9,775 | -- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector(DWIDTH - 1 downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector(DWIDTH - 1 downto 0); -- dob delay = 2 clk compared with rdb
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector(AWIDTH -1 downto 0)
);
end fifo_async;
architecture fast_read of fifo_async is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal wea_sync : std_logic := '0';
signal wp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clka)
begin
if reset = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
wp <= (others => '0');
elsif full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ASYNCWRITE_wea_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clka,
sync_clk => clkb,
async_wren => wea,
trigger => '1',
sync_wren => wea_sync,
over => open,
flag => open
);
WritePointorCtrl_sync : process(reset,clkb)
begin
if reset = '1' then
wp_sync <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
wp_sync <= (others => '0');
elsif full_flag = '0' and wea_sync = '1' then
wp_sync <= wp_sync + 1;
end if;
end if;
end process;
ReadPointorCtrl : process(reset,clkb)
begin
if reset = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
rp <= (others => '0');
elsif empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clkb)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clkb) then
if clr = '1' then
empty_flag <= '1';
elsif (wp_sync = rp) and (wea_sync = '1') then
empty_flag <= '0';
elsif (wp_sync = rp + 1) and (rdb = '1'and wea_sync = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clkb)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clkb) then
if clr = '1' then
full_flag <= '0';
elsif (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
full_flag <= '1';
elsif (wp_sync = rp) and (rdb = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp_sync - rp;
end fast_read;
---------------------------------------------------------------------------------
architecture fast_write of fifo_async is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal rdb_sync : std_logic := '0';
signal rp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clka)
begin
if reset = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
wp <= (others => '0');
elsif full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ReadPointorCtrl : process(reset,clkb)
begin
if reset = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
rp <= (others => '0');
elsif empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
ASYNCWRITE_rdb_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clkb,
sync_clk => clka,
async_wren => rdb,
trigger => '1',
sync_wren => rdb_sync,
over => open,
flag => open
);
ReadPointorCtrl_sync : process(reset,clka)
begin
if reset = '1' then
rp_sync <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
rp_sync <= (others => '0');
elsif empty_flag = '0' and rdb_sync = '1' then
rp_sync <= rp_sync + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clka)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clka) then
if clr = '1' then
empty_flag <= '1';
elsif (wp = rp_sync) and (wea = '1') then
empty_flag <= '0';
elsif (wp = rp_sync + 1) and (rdb_sync = '1'and wea = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clka)
begin
if reset = '1' then
full_flag <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
if clr = '1' then
full_flag <= '0';
elsif (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
full_flag <= '1';
elsif (wp = rp_sync) and (rdb_sync = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp - rp_sync;
end fast_write;
| gpl-2.0 | 0a6cda531e05551107cb823983fd6b49 | 0.55376 | 2.75974 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/join_1.vhd | 2 | 21,015 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_1_stress
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * function
-- reg4 = thread
-- reg5 = i
-- reg6 = joinReturn
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
--joinValue = SUCCESS
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
reg5_next <= Z32;
reg6_next <= Z32;
next_state <= STATE_6;
when STATE_6 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_7;
else
next_state <= STATE_13;
end if;
when STATE_7 =>
next_state <= STATE_8;
-- createReturn == hthread_create( &(data->threads[i]), NULL, data->function, NULL );
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &( data->threads[i] )
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- increment i
reg5_next <= reg5 + "x00000001";
-- END OF FOR LOOP
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_13 =>
reg5_next <= Z32;
next_state <= STATE_14;
when STATE_14 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_15;
else
next_state <= STATE_;
end if;
-- hthread_join( data->thread[i], NULL );
when STATE_15 =>
-- read the value of data->thread[i]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- push thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
when STATE_15 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
reg5_next <= reg5 + x"00000001";
when STATE_16 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- for( i=0; i< *(data->numberOfTestsCompleted); i++ );
when STATE_17 =>
-- set i to 0
reg5_next <= Z32;
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_18 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_19;
when STATE_19 =>
-- compare i and numberOfTestsComplted
if ( reg5 < reg6 ) then
next_state <= STATE_20;
else
next_state <=FUNCTION_EXIT;
end if;
when STATE_24 =>
reg5_next <= reg5 + x"00000001";
next_state <= STATE_19;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 15265f4e373b2a61128bf2522eb12498 | 0.547799 | 3.687489 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 29,499 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_f;
use fsl_v20_v2_11_f.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- DEQ: begin
----------------------------
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 82d0b1819fb0e7c7a7baaacb705137b1 | 0.518289 | 3.540446 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/ethrx_zcpsm/ethrx_zcpsm.vhd | 1 | 1,950 | ---------------------------------------------------------------------------------------------------
--
-- Title : ethrx_zcpsm
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethrx_zcpsm is
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end ethrx_zcpsm;
--}} End of automatically maintained section
architecture behavior of ethrx_zcpsm is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component ethrxrom_romonly
port(
addrb : in std_logic_vector(11 downto 0);
clkb : in std_logic;
dob : out std_logic_vector(17 downto 0));
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
begin
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rx_rom : ethrxrom_romonly
port map(
addrb => address,
clkb => clk,
dob => instruction
);
end behavior;
| gpl-2.0 | 5761ec7a3887e6540309fb496f552feb | 0.547179 | 3.110048 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_v20_wrap.vhd | 3 | 16,958 | -- $Id: opb_v20_wrap.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- opb_v20_wrap.vhd
-- Generated by wrapgen, v1.01j Sep 22,2004 4:16:33
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- entity
-------------------------------------------------------------------------------
entity opb_v20_wrap is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20_wrap;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of opb_v20_wrap is
component opb_v20 is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end component opb_v20;
begin ------------------------------------------------------------------------
OPB_V20_I : opb_v20
generic map
(
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_SLAVES => C_NUM_SLAVES,
C_USE_LUT_OR => C_USE_LUT_OR,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_REG_GRANTS => C_REG_GRANTS,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE
)
port map
(
SYS_Rst => SYS_Rst,
Debug_SYS_Rst => Debug_SYS_Rst,
WDT_Rst => WDT_Rst,
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
M_ABus => M_ABus,
M_BE => M_BE,
M_beXfer => M_beXfer,
M_busLock => M_busLock,
M_DBus => M_DBus,
M_DBusEn => M_DBusEn,
M_DBusEn32_63 => M_DBusEn32_63,
M_dwXfer => M_dwXfer,
M_fwXfer => M_fwXfer,
M_hwXfer => M_hwXfer,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
Sl_beAck => Sl_beAck,
Sl_DBus => Sl_DBus,
Sl_DBusEn => Sl_DBusEn,
Sl_DBusEn32_63 => Sl_DBusEn32_63,
Sl_errAck => Sl_errAck,
Sl_dwAck => Sl_dwAck,
Sl_fwAck => Sl_fwAck,
Sl_hwAck => Sl_hwAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_MRequest => OPB_MRequest,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_beXfer => OPB_beXfer,
OPB_beAck => OPB_beAck,
OPB_busLock => OPB_busLock,
OPB_rdDBus => OPB_rdDBus,
OPB_wrDBus => OPB_wrDBus,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_dwAck => OPB_dwAck,
OPB_dwXfer => OPB_dwXfer,
OPB_fwAck => OPB_fwAck,
OPB_fwXfer => OPB_fwXfer,
OPB_hwAck => OPB_hwAck,
OPB_hwXfer => OPB_hwXfer,
OPB_MGrant => OPB_MGrant,
OPB_pendReq => OPB_pendReq,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck
);
end architecture imp;
| bsd-3-clause | 1a9a0cb89cf57204205306561fdbb320 | 0.45536 | 3.681719 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_6.vhd | 2 | 20,507 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_6.c
-- ARGUMENT_VALUE = 31
-- reg3 = childVal1
-- reg4 = childVal2
-- reg5 = * function1
-- reg6 = * function2
-- reg7 = thread1
-- reg8 = thread2
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread1, NULL, data->function1, ARGUMENT_VALUE );
when STATE_3 =>
reg6_next <= intrfc2thrd_value;
-- push ARGUMENT_VALUE
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"0000001F";
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread2, NULL, data->function2, ARGUMENT_VALUE );
when STATE_8 =>
-- push ARGUMENT_VALUE
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"0000001F";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &data->thread2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
-- hthread_join( data->thread1, (void *) &data->childVal1 );
when STATE_13 =>
-- Load the value of data->thread1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
reg7_next <= intrfc2thrd_value;
-- push &data->childVal1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- push data->thread1
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_join( data->thread2, (void *) &data->childVal2 );
when STATE_17 =>
-- Load the value of data->thread2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
reg8_next <= intrfc2thrd_value;
-- push &data->childVal2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- push data->thread2
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg8;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
when STATE_21 =>
-- Load the value of childVal1
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000010";
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
reg3_next <= intrfc2thrd_value;
-- Load the value of childVal2
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_23;
when STATE_23 =>
reg4_next <= intrfc2thrd_value;
next_state <= STATE_24;
when STATE_24 =>
if ( reg3 = reg4 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 28934f7252f63786480c1249e8896307 | 0.549666 | 3.738742 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_dly1_mux.vhd | 3 | 9,364 | -------------------------------------------------------------------------------
-- $Id: pf_dly1_mux.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_dly1_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dly1_mux.vhd
--
-- Description: Implements a multiplexer and register combo that allows
-- selection of a registered or non-registered version of
-- the input signal for output.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dly1_mux.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
--
-- DET 4/2/2004 IPIF to v2_02_a
-- ~~~~~~
-- - Updated proc common library reference to v2_00_a
-- ^^^^^^
--
--
-- DET 4/12/2004 IPIF to V1_00_f
-- ~~~~~~
-- - Updated unisim library reference to unisim.vcomponents.all.
-- - Commented out Xilinx primitive component declarations
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-- Xilinx primitive library
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_dly1_mux is
Generic (C_MUX_WIDTH : Integer := 12
);
port (
Clk : in std_logic;
Rst : In std_logic;
dly_sel1 : in std_logic;
dly_sel2 : in std_logic;
Inputs : in std_logic_vector(0 to C_MUX_WIDTH-1);
Y_out : out std_logic_vector(0 to C_MUX_WIDTH-1)
);
end pf_dly1_mux;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_dly1_mux is
signal lut_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal reg_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
MAKE_DLY_MUX : for i in 0 to C_MUX_WIDTH-1 generate
--- xst wrk around I_SEL_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"FE10"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lut_out(i),
--- xst wrk around I0 => dly_sel1,
--- xst wrk around I1 => dly_sel2,
--- xst wrk around I2 => Inputs(i),
--- xst wrk around I3 => reg_out(i)
--- xst wrk around );
I_SEL_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"FE10"
)
port map (
O => lut_out(i),
I0 => dly_sel1,
I1 => dly_sel2,
I2 => Inputs(i),
I3 => reg_out(i)
);
FDRE_I: FDRE
port map (
Q => reg_out(i),
C => Clk,
CE => '1',
D => Inputs(i),
R => Rst
);
End generate MAKE_DLY_MUX;
Y_out <= lut_out;
end implementation;
| bsd-3-clause | af2f9496becaf045b584264ebdc92488 | 0.418625 | 4.894929 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/src_utils_pkg.vhd | 1 | 4,852 | --------------------------------------------------------------------------------
-- Title : Utilities package
-- Project :
--------------------------------------------------------------------------------
-- File : src_utils_pkg.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 02.06.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- utilities to foster source code programming
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package src_utils_pkg is
constant TYPE_IS_MEMORY : std_logic_vector(4 downto 0) := "00000";
constant TYPE_IS_IO : std_logic_vector(4 downto 0) := "00010";
constant TYPE_IS_CPL : std_logic_vector(4 downto 0) := "01010";
constant FMT_IS_READ : std_logic_vector(2 downto 0) := "000";
constant FMT_IS_WRITE : std_logic_vector(2 downto 0) := "010";
constant ZERO_02B : std_logic_vector(1 downto 0) := "00";
constant ZERO_03B : std_logic_vector(2 downto 0) := "000";
constant ZERO_04B : std_logic_vector(3 downto 0) := x"0";
constant ZERO_10B : std_logic_vector(9 downto 0) := "0000000000";
constant ZERO_11B : std_logic_vector(10 downto 0) := "00000000000";
constant ZERO_12B : std_logic_vector(11 downto 0) := x"000";
constant ZERO_20B : std_logic_vector(19 downto 0) := x"00000";
constant ONE_02B : std_logic_vector(1 downto 0) := "01";
constant ONE_03B : std_logic_vector(2 downto 0) := "001";
constant ONE_04B : std_logic_vector(3 downto 0) := x"1";
constant ONE_05B : std_logic_vector(4 downto 0) := "00001";
constant ONE_10B : std_logic_vector(9 downto 0) := "0000000001";
constant ONE_11B : std_logic_vector(10 downto 0) := "00000000001";
constant ONE_12B : std_logic_vector(11 downto 0) := x"001";
constant TWO_02B : std_logic_vector(1 downto 0) := "10";
constant TWO_03B : std_logic_vector(2 downto 0) := "010";
constant TWO_04B : std_logic_vector(3 downto 0) := x"2";
constant TWO_10B : std_logic_vector(9 downto 0) := "0000000010";
constant TWO_11B : std_logic_vector(10 downto 0) := "00000000010";
constant TWO_12B : std_logic_vector(11 downto 0) := x"002";
constant THREE_02B : std_logic_vector(1 downto 0) := "11";
constant THREE_03B : std_logic_vector(2 downto 0) := "011";
constant THREE_04B : std_logic_vector(3 downto 0) := x"3";
constant THREE_10B : std_logic_vector(9 downto 0) := "0000000011";
constant THREE_12B : std_logic_vector(11 downto 0) := x"003";
constant FOUR_03B : std_logic_vector(2 downto 0) := "100";
constant FOUR_04B : std_logic_vector(3 downto 0) := x"4";
constant FOUR_12B : std_logic_vector(11 downto 0) := x"004";
constant FOUR_32B : std_logic_vector(31 downto 0) := x"00000004";
constant FIVE_12B : std_logic_vector(11 downto 0) := x"005";
constant SIX_04B : std_logic_vector(3 downto 0) := x"6";
constant SIX_12B : std_logic_vector(11 downto 0) := x"006";
constant EIGHT_04B : std_logic_vector(3 downto 0) := x"8";
constant EIGHT_32B : std_logic_vector(31 downto 0) := x"00000008";
constant C_04B : std_logic_vector(3 downto 0) := x"C";
constant FULL_03B : std_logic_vector(2 downto 0) := "111";
constant FULL_10B : std_logic_vector(9 downto 0) := "1111111111";
constant X_400_11B : std_logic_vector(10 downto 0) := "10000000000";
end src_utils_pkg;
| gpl-3.0 | d15e6953dde6a9e8c1c75fd8cdcd37d9 | 0.550082 | 3.681335 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_destroy_3.vhd | 2 | 15,295 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-- attr_destroy_3.c
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
-- retVal = hthread_attr_destroy( attr );
when STATE_3 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 5fe571bb0048bdb63e081d84086e838e | 0.546061 | 3.804726 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/reg_tb.vhd | 1 | 2,773 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:05:00 11/11/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE3_final/reg_tb.vhd
-- Project Name: IDE3_final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Reg_addr
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY reg_tb IS
END reg_tb;
ARCHITECTURE behavior OF reg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Reg_addr
PORT(
Re_clk : IN std_logic;
Re_rst : IN std_logic;
Re_ld : IN std_logic;
Re_reg_in : IN std_logic_vector(4 downto 0);
Re_reg_out : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal Re_clk : std_logic := '0';
signal Re_rst : std_logic := '0';
signal Re_ld : std_logic := '0';
signal Re_reg_in : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal Re_reg_out : std_logic_vector(4 downto 0);
-- Clock period definitions
constant Re_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Reg_addr PORT MAP (
Re_clk => Re_clk,
Re_rst => Re_rst,
Re_ld => Re_ld,
Re_reg_in => Re_reg_in,
Re_reg_out => Re_reg_out
);
-- Clock process definitions
Re_clk_process :process
begin
Re_clk <= '0';
wait for Re_clk_period/2;
Re_clk <= '1';
wait for Re_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
Re_rst <= '1';
wait for 10 ns;
Re_rst <= '0';
wait for 10 ns;
Re_reg_in <= "00110";
wait for 10 ns;
Re_ld <= '1';
wait for 10 ns;
Re_ld <= '0';
wait for 5 ns;
Re_ld <= '1';
wait for 5 ns;
Re_reg_in <= "11111";
wait for 10 ns;
-- wait for Re_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| unlicense | 69d8654840c2a86b75ffa40ecff85557 | 0.56978 | 3.427689 | false | false | false | false |
iocoder/graduation | hardware/kbd/kbdctl.vhd | 1 | 3,107 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity kbdctl is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Output:
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- System bus interface:
EN : in STD_LOGIC;
RW : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0) := x"00";
RDY : out STD_LOGIC := '0';
-- Interrupt Logic:
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC
);
end entity;
architecture Behavioral of kbdctl is
component debouncer is
Port (
CLK : in STD_LOGIC;
Din : in STD_LOGIC;
Dout : out STD_LOGIC := '0'
);
end component;
component ps2 is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Outputs
SENSE : out STD_LOGIC;
PACKET : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal PS2CLKD : STD_LOGIC;
signal SENSE : STD_LOGIC := '0';
signal LASTSENSE : STD_LOGIC := '0';
signal LASTEN : STD_LOGIC := '0';
signal PACKET : STD_LOGIC_VECTOR (7 downto 0) := x"00";
type kbdbuf_t is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
signal kbdbuf : kbdbuf_t := (others => x"00");
signal buf_front : integer range 0 to 100 := 0;
signal buf_back : integer range 0 to 100 := 0;
attribute ram_style: string;
attribute ram_style of kbdbuf : signal is "distributed";
begin
D: debouncer port map (CLK, PS2CLK, PS2CLKD);
K: ps2 port map (CLK, PS2CLKD, PS2DATA, SENSE, PACKET);
LED <= PACKET;
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (SENSE = '1') then
LASTSENSE <= '1';
else
LASTSENSE <= '0';
end if;
if (EN = '1') then
LASTEN <= '1';
else
LASTEN <= '0';
end if;
if (IAK='1' and not (SENSE = '1' and LASTSENSE = '0')) then
INT <= '0';
end if;
if (SENSE = '1' and LASTSENSE = '0') then
-- a scancode has arrived
kbdbuf(buf_front) <= PACKET;
if (buf_front = 15) then
buf_front <= 0;
else
buf_front <= buf_front + 1;
end if;
INT <= '1';
end if;
if (EN = '1' and LASTEN = '0') then
-- data cycle started
if (buf_back = buf_front) then
DATA <= x"00";
else
DATA <= kbdbuf(buf_back);
if (buf_back = 15) then
buf_back <= 0;
else
buf_back <= buf_back + 1;
end if;
end if;
elsif (EN = '0' and LASTEN = '1') then
-- data cycle ended
DATA <= x"00";
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 3de5f5dea802ef952768b95d8daddc91 | 0.490183 | 3.459911 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/self_1.vhd | 2 | 10,556 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
-----------------------------------------------------------------------
-- Testcase: hthread_stress_1
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
next_state <= STATE_1;
-- hthread_exit( (void *) hthread_self() )
when STATE_1 =>
-- call self
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_2;
next_state <= WAIT_STATE;
when STATE_2 =>
-- push hthread_self
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
-- call hthread_exit
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 847c27b3be1f77109c14ccc07066d959 | 0.556556 | 4.063125 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_pkg.vhd | 3 | 52,825 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-- Moved to proc_common_v2_00_a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
| bsd-3-clause | 40f5baf74e9a9562279066f72303179d | 0.498268 | 4.776221 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_plbv46_bridge_v1_01_a/hdl/vhdl/bridge.vhd | 3 | 15,821 | -------------------------------------------------------------------------------
-- $Id: bridge.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: bridge.vhd
--
-- Description: This block maintains state about the current status of
-- plbv46 write operations, the state of plbv46 read
-- operations and the availability of prefetch data in the
-- LocalLink read buffer. It also provides a transaction
-- timeout timer in the event that read data is never claimed
-- or write data can't make it onto the PLBv46 bus.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
-------------------------------------------------------------------------------
ENTITY bridge IS
GENERIC (
-- BRIDGE CONFIGURATION
C_PREFETCH_TIMEOUT : integer RANGE 1 TO 32 := 10; -- prefetch timeout counter size (bits)
-- System wide Specification
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-- PLBV46 Master Burst Interface
IP2Bus_MstRd_Req : OUT std_logic; -- User Logic Read Request
IP2Bus_MstWr_Req : OUT std_logic; -- User Logic Write Request
IP2Bus_Mst_Addr : OUT std_logic_vector(0 TO 32-1); -- User Logic Request Address
IP2Bus_Mst_BE : OUT std_logic_vector(0 TO (32/8)-1); -- User Logic Request Byte Enables (only used during single data beat requests)
IP2Bus_Mst_Length : OUT std_logic_vector(0 TO 11);
IP2Bus_Mst_Type : OUT std_logic; -- User Logic Request Type Indicator
IP2Bus_Mst_Lock : OUT std_logic; -- User Logic Bus Lock Request
IP2Bus_Mst_Reset : OUT std_logic; -- Optional User Logic Reset Request.
Bus2IP_Mst_CmdAck : IN std_logic; -- Command Acknowledge Status
Bus2IP_Mst_Cmplt : IN std_logic; -- Command Complete Status
Bus2IP_Mst_Error : IN std_logic; -- Command Error Status
Bus2IP_Mst_Rearbitrate : IN std_logic; -- Command Rearbitrate Status
Bus2IP_Mst_Cmd_Timeout : IN std_logic; -- Command Timeout Status
-- opb_slave Interface
opbs_prefetch_req : IN std_logic; -- opb slave prefetch request
opbs_type : IN std_logic; -- opb slave transaction request type
opbs_prefetch_clr : IN std_logic; -- opb slave prefetch clear
opbs_postedwr_clr : IN std_logic; -- opb slave posted write clear
opbs_length : IN std_logic_vector(0 TO 11); -- opb slave transaction length
opbs_postedwrt_req : IN std_logic; -- opb slave posted write request
opbs_trans_addr : IN std_logic_vector(0 TO 31); -- opb slave transaction address
opbs_be : IN std_logic_vector(0 TO 3); -- opb slave byte enable
brdg_block : OUT std_logic; -- bridge block
brdg_prefetch_cmplt : OUT std_logic; -- bridge prefetch complete
brdg_prefetch_status : OUT std_logic; -- bridge prefetch status
-- Buffer Interface
brdg_wr_bf_rst : OUT std_logic; -- bridge write buffer reset
brdg_rd_bf_rst : OUT std_logic; -- bridge read buffer reset
-- System
MPLB_rst : IN std_logic; -- plb reset
MPLB_clk : IN std_logic -- plb clock
);
END ENTITY bridge;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
ARCHITECTURE syn OF bridge IS
--CONSTANT timeout_value : unsigned(0 TO C_PREFETCH_TIMEOUT) := ( 1 TO C_PREFETCH_TIMEOUT => '1', others => '0');
SIGNAL timer_ns, timer_cs : unsigned(0 TO C_PREFETCH_TIMEOUT);
SIGNAL trigger_ns, trigger_cs : std_logic;
SIGNAL transaction_timeout : std_logic;
TYPE bridge_sm_type IS (REQ, CMD, WR, RD, FUFILL);
SIGNAL bridge_cs, bridge_ns : bridge_sm_type;
SIGNAL IP2Bus_MstWr_Req_ns, IP2Bus_MstWr_Req_cs : std_logic;
SIGNAL IP2Bus_MstRd_Req_ns, IP2Bus_MstRd_Req_cs : std_logic;
SIGNAL brdg_wr_bf_rst_ns, brdg_wr_bf_rst_cs : std_logic;
SIGNAL brdg_rd_bf_rst_ns, brdg_rd_bf_rst_cs : std_logic;
SIGNAL brdg_block_ns, brdg_block_cs : std_logic;
SIGNAL brdg_prefetch_status_ns , brdg_prefetch_status_cs : std_logic;
SIGNAL brdg_prefetch_cmplt_ns , brdg_prefetch_cmplt_cs : std_logic;
BEGIN
s1 : IP2Bus_Mst_Lock <= '0';
s2 : IP2Bus_Mst_Reset <= '0';
s3: IP2Bus_Mst_BE(0 TO 3) <= opbs_be;
s4: IP2Bus_Mst_Addr <= opbs_trans_addr;
capture : PROCESS (MPLB_clk, MPLB_rst) IS
BEGIN
IF (MPLB_rst = '1') THEN
IP2Bus_Mst_Length <= (others => '0');
IP2Bus_Mst_Type <= '0';
ELSIF (rising_edge(MPLB_clk)) THEN
IF (opbs_postedwrt_req OR opbs_prefetch_req) = '1' THEN
-- These qualifier must be held until the request is cmd_ack'd by
-- the master burst block. The address and byte enables will NOT
-- change by design of the opb_slave
IP2Bus_Mst_Length <= opbs_length;
IP2Bus_Mst_Type <= opbs_type;
END IF;
END IF;
END PROCESS capture;
-- Transaction timeout
-- This timer protects against an OPB master that never returns to claim the
-- prefetch data. If the data isn't claimed then the bridge state machine
-- can clear out the buffers and unlock the opb slave. This timer is in the
-- OPB clock domain so it will count half the number of clocks if the
-- plbv46:opb clock period ratio is 1:2!!!
s8 : timer_ns <= timer_cs - 1;
timeout : PROCESS (MPLB_clk, MPLB_rst) IS
BEGIN
IF (MPLB_rst = '1') THEN
timer_cs <= (OTHERS => '0');
ELSIF (rising_edge(MPLB_clk)) THEN
IF (trigger_cs = '1') THEN
timer_cs(0) <= '0';
timer_cs(1 TO C_PREFETCH_TIMEOUT) <= (OTHERS => '1');
ELSE
timer_cs <= timer_ns;
END IF;
END IF;
END PROCESS timeout;
s9 : transaction_timeout <= timer_cs(0);
bridge_sm : PROCESS (
Bus2IP_Mst_CmdAck, Bus2IP_Mst_Cmplt, Bus2IP_Mst_Error,
IP2Bus_MstRd_Req_cs, IP2Bus_MstWr_Req_cs,
brdg_block_cs, brdg_prefetch_cmplt_cs,
brdg_prefetch_status_cs, bridge_cs, opbs_postedwrt_req,
opbs_prefetch_clr, opbs_prefetch_req,
transaction_timeout
) IS
BEGIN
-- Hold current state by default
bridge_ns <= bridge_cs;
-- SM output signal defaults
brdg_wr_bf_rst_ns <= '0';
brdg_rd_bf_rst_ns <= '0';
brdg_block_ns <= brdg_block_cs;
IP2Bus_MstRd_Req_ns <= IP2Bus_MstRd_Req_cs;
IP2Bus_MstWr_Req_ns <= IP2Bus_MstWr_Req_cs;
brdg_prefetch_status_ns <= brdg_prefetch_status_cs;
brdg_prefetch_cmplt_ns <= brdg_prefetch_cmplt_cs;
trigger_ns <= '1';
CASE bridge_cs IS
WHEN REQ =>
IF (opbs_postedwrt_req OR opbs_prefetch_req) = '1' THEN
IP2Bus_MstWr_Req_ns <= opbs_postedwrt_req;
IP2Bus_MstRd_Req_ns <= opbs_prefetch_req;
brdg_prefetch_cmplt_ns <= '0';
brdg_prefetch_status_ns <= '0';
brdg_block_ns <= '1';
brdg_rd_bf_rst_ns <= '1';
bridge_ns <= CMD;
END IF;
WHEN CMD =>
IF (Bus2IP_Mst_Cmplt = '1') THEN
IF (IP2Bus_MstWr_Req_cs) = '1' THEN
-- The write transaction timed out or errored out when the
-- master attempted to acquire the PLB. Clean out the posted
-- write data buffer as the contents are now stale.
IP2Bus_MstWr_Req_ns <= '0';
brdg_block_ns <= '0';
brdg_wr_bf_rst_ns <= '1';
bridge_ns <= REQ;
ELSE
-- Had to be a read request since the requests are mutually
-- exclusive. But it is a read prefetch error so the OPB_slave
-- needs notification of a prefetch complete but with a status
-- of error. It switches to status FUFILL because the OPB slave
-- must wait until it gets a read request that claims the buffer
-- so that it can spew error acks to the OPB master who wanted
-- the data. That means brdg_block must remain asserted
IP2Bus_MstRd_Req_ns <= '0';
brdg_block_ns <= '1';
brdg_prefetch_status_ns <= '1'; -- error status
brdg_prefetch_cmplt_ns <= '1';
bridge_ns <= FUFILL;
END IF; -- (IP2Bus_MstWr_Req_cs) = '1'
ELSE
IF (Bus2IP_Mst_CmdAck = '1') THEN
-- PLBv46 master is done acquiring the PLB and transaction
-- can commence.
IF (IP2Bus_MstWr_Req_cs) = '1' THEN
IP2Bus_MstWr_Req_ns <= '0';
bridge_ns <= WR;
ELSE
IP2Bus_MstRd_Req_ns <= '0';
bridge_ns <= RD;
END IF; -- (IP2Bus_MstWr_Req_cs) = '1'
END IF; --(Bus2IP_Mst_CmdAck='1')
END IF; -- (Bus2IP_Mst_Cmplt = '1')
WHEN WR =>
IF (Bus2IP_Mst_Cmplt) = '1' THEN
brdg_block_ns <= '0';
brdg_wr_bf_rst_ns <= '1';
bridge_ns <= REQ;
END IF;
WHEN RD =>
IF (Bus2IP_Mst_Cmplt = '1') THEN
brdg_block_ns <= '1';
brdg_wr_bf_rst_ns <= '1';
brdg_prefetch_status_ns <= Bus2IP_Mst_Error;
brdg_prefetch_cmplt_ns <= '1';
bridge_ns <= FUFILL;
END IF;
WHEN FUFILL =>
trigger_ns <= '0';
IF ((transaction_timeout OR opbs_prefetch_clr) = '1') THEN
brdg_rd_bf_rst_ns <= '1';
brdg_block_ns <= '0';
brdg_prefetch_cmplt_ns <= '0';
brdg_prefetch_status_ns <= '0';
bridge_ns <= REQ;
END IF;
END CASE;
END PROCESS bridge_sm;
bridge_reg : PROCESS(MPLB_clk, MPLB_rst)
BEGIN
IF (MPLB_rst = '1') THEN
bridge_cs <= REQ;
IP2Bus_MstRd_req_cs <= '0';
IP2Bus_MstWr_req_cs <= '0';
brdg_prefetch_cmplt_cs <= '0';
brdg_prefetch_status_cs <= '0';
brdg_block_cs <= '0';
brdg_rd_bf_rst_cs <= '1';
brdg_wr_bf_rst_cs <= '1';
trigger_cs <= '1';
ELSIF (rising_edge(MPLB_clk)) THEN
bridge_cs <= bridge_ns;
IP2Bus_MstRd_req_cs <= IP2Bus_MstRd_req_ns;
IP2Bus_MstWr_req_cs <= IP2Bus_MstWr_req_ns;
brdg_prefetch_cmplt_cs <= brdg_prefetch_cmplt_ns;
brdg_prefetch_status_cs <= brdg_prefetch_status_ns;
brdg_block_cs <= brdg_block_ns;
brdg_rd_bf_rst_cs <= brdg_rd_bf_rst_ns;
brdg_wr_bf_rst_cs <= brdg_wr_bf_rst_ns OR opbs_postedwr_clr;
trigger_cs <= trigger_ns;
END IF;
END PROCESS bridge_reg;
s10 : IP2Bus_MstRd_req <= IP2Bus_MstRd_req_cs;
s11 : IP2Bus_MstWr_req <= IP2Bus_MstWr_req_cs;
s12 : brdg_prefetch_cmplt <= brdg_prefetch_cmplt_cs;
s13 : brdg_prefetch_status <= brdg_prefetch_status_cs;
s14 : brdg_block <= brdg_block_cs;
s15 : brdg_rd_bf_rst <= brdg_rd_bf_rst_cs;
s16 : brdg_wr_bf_rst <= brdg_wr_bf_rst_cs;
END ARCHITECTURE syn;
| bsd-3-clause | 9ab1bd4f98ea9572eac60a9f6ea0d2c4 | 0.529107 | 3.946371 | false | false | false | false |
xdsopl/vhdl | debouncer.vhd | 1 | 1,180 | -- debouncer - switch debouncer logic written in vhdl
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity debouncer is
generic (
CLOCK_RATE_HZ : positive := 50000000;
SETTLING_TIME_MS : positive := 10
);
port (
clock : in std_logic;
input : in std_logic;
output : out std_logic := '0'
);
end debouncer;
architecture rtl of debouncer is
constant max : integer := (CLOCK_RATE_HZ * SETTLING_TIME_MS) / 1000;
signal cnt : integer range 0 to max := 0;
signal last : std_logic;
begin
process (clock)
begin
if rising_edge(clock) then
last <= input;
if input = last then
if cnt = max then
output <= input;
else
cnt <= cnt + 1;
end if;
else
cnt <= 0;
end if;
end if;
end process;
end rtl;
| cc0-1.0 | 03941d2cfdcdef2f9977065612a9d2d1 | 0.69322 | 3.440233 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_monitor_wrapper.vhd | 3 | 16,448 | -------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MIRQ : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 2,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
| bsd-3-clause | d625cd7af34f1a68a9b955c46c03675b | 0.607855 | 2.91115 | false | false | false | false |
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