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masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_exit.vhd | 2 | 11,732 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Push a return value that is not the default return value
thrd2intrfc_value <= x"ABCDEF01";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 0181d56a427ba4512ea257d6a4f370cf | 0.583021 | 4.256894 | false | false | false | false |
QuickJack/logi-hard | test_bench/async_serial_tb.vhd | 2 | 5,330 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:49 03/22/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/async_serial_tb.vhd
-- Project Name: test_ugv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: async_serial
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library work ;
use work.logi_utils_pack.all ;
ENTITY async_serial_tb IS
END async_serial_tb;
ARCHITECTURE behavior OF async_serial_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT async_serial
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200) ;
PORT(
clk : IN std_logic;
reset : IN std_logic;
rx : IN std_logic;
tx : OUT std_logic;
data_out : OUT std_logic_vector(7 downto 0);
data_in : IN std_logic_vector(7 downto 0);
data_ready : OUT std_logic;
data_send : IN std_logic;
available : out std_logic
);
END COMPONENT;
component nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal rx : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_send : std_logic := '0';
--Outputs
signal tx : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_ready : std_logic;
signal available : std_logic ;
signal new_byte_out : std_logic ;
signal nmea_byte_out : std_logic_vector(7 downto 0) ;
signal frame_size : std_logic_vector(7 downto 0) ;
signal end_of_frame : std_logic ;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant baud_period : time := 8680 ns;
constant data_serial : std_logic_vector(7 downto 0) := X"5A";
constant gps_string : STRING (1 to 27):="$GPRMC,0,0,0,1,0,0,0,0,0*56";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: async_serial
GENERIC MAP(CLK_FREQ => 100_000_000)
PORT MAP (
clk => clk,
reset => reset,
rx => rx,
tx => tx,
data_out => data_out,
data_in => data_in,
data_ready => data_ready,
data_send => data_send,
available => available
);
nmea_filter : nmea_frame_extractor
generic map(nmea_header => "$GPRMC")
port map(
clk => clk,
reset => reset,
nmea_byte_in => data_out,
new_byte_in => data_ready,
nmea_byte_out => nmea_byte_out,
new_byte_out => new_byte_out,
frame_size => frame_size,
end_of_frame => end_of_frame
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1' ;
-- rx <= '1' ;
wait for 100 ns;
reset <= '0' ;
-- wait for clk_period*10;
-- rx <= '1' ;
-- wait for baud_period*10;
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_0 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '1' ;
-- wait for baud_period*10;
--
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_1 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '0' ;
-- wait for baud_period;
-- rx <= '1' ;
-- wait for baud_period*10;
-- -- insert stimulus here
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_2 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '1' ;
-- wait for baud_period*10 ;
-- rx <= tx ;
for i in 1 to gps_string'length loop
data_in <= std_logic_vector(to_unsigned(character'pos(gps_string(i)), 8));
data_send <= '1' ;
wait until available = '0' ;
data_send <= '0' ;
wait until data_ready = '1' ;
end loop ;
for i in 0 to 8 loop
data_in <= X"0D";
data_send <= '1' ;
wait until available = '0' ;
data_send <= '0' ;
wait until data_ready = '1' ;
end loop ;
wait;
end process;
rx <= tx ;
END;
| lgpl-3.0 | 9afca92d1b83218b354b1c526848743c | 0.583677 | 3.088065 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_broadcast_4.vhd | 2 | 15,002 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_broadcast_4.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_cond_broadcast( cond );
when STATE_1 =>
-- Push the argument to hthread_cond_broadcast
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_cond_broadcast
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 3391a7c388b9cf410bcdcae898cc4257 | 0.538595 | 3.863508 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/user_logic_tb.vhd | 2 | 7,548 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:18 06/17/2009
-- Design Name:
-- Module Name: /home/jagron/uark_research/uark_ht_trunk/src/hardware/MyRepository/pcores/plb_cond_vars_v1_00_a/hdl/vhdl//user_logic_tb.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: user_logic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY user_logic_tb IS
END user_logic_tb;
ARCHITECTURE behavior OF user_logic_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT user_logic
PORT(
Soft_Reset : IN std_logic;
Reset_Done : OUT std_logic;
interrupts_in : in std_logic_vector(0 to 3);
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
Bus2IP_Addr : IN std_logic_vector(0 to 31);
Bus2IP_Data : IN std_logic_vector(0 to 31);
Bus2IP_BE : IN std_logic_vector(0 to 3);
Bus2IP_RdCE : IN std_logic_vector(0 to 4);
Bus2IP_WrCE : IN std_logic_vector(0 to 4);
IP2Bus_Data : OUT std_logic_vector(0 to 31);
IP2Bus_RdAck : OUT std_logic;
IP2Bus_WrAck : OUT std_logic;
IP2Bus_Error : OUT std_logic;
IP2Bus_MstRd_Req : OUT std_logic;
IP2Bus_MstWr_Req : OUT std_logic;
IP2Bus_Mst_Addr : OUT std_logic_vector(0 to 31);
IP2Bus_Mst_BE : OUT std_logic_vector(0 to 3);
IP2Bus_Mst_Lock : OUT std_logic;
IP2Bus_Mst_Reset : OUT std_logic;
Bus2IP_Mst_CmdAck : IN std_logic;
Bus2IP_Mst_Cmplt : IN std_logic;
Bus2IP_Mst_Error : IN std_logic;
Bus2IP_Mst_Rearbitrate : IN std_logic;
Bus2IP_Mst_Cmd_Timeout : IN std_logic;
Bus2IP_MstRd_d : IN std_logic_vector(0 to 31);
Bus2IP_MstRd_src_rdy_n : IN std_logic;
IP2Bus_MstWr_d : OUT std_logic_vector(0 to 31);
Bus2IP_MstWr_dst_rdy_n : IN std_logic
);
END COMPONENT;
--Inputs
signal Soft_Reset : std_logic := '0';
signal interrupts_in : std_logic_vector(0 to 3) := (others => '0');
signal Bus2IP_Clk : std_logic := '0';
signal Bus2IP_Reset : std_logic := '0';
signal Bus2IP_Addr : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_Data : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_BE : std_logic_vector(0 to 3) := (others => '0');
signal Bus2IP_RdCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_WrCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_Mst_CmdAck : std_logic := '0';
signal Bus2IP_Mst_Cmplt : std_logic := '0';
signal Bus2IP_Mst_Error : std_logic := '0';
signal Bus2IP_Mst_Rearbitrate : std_logic := '0';
signal Bus2IP_Mst_Cmd_Timeout : std_logic := '0';
signal Bus2IP_MstRd_d : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_MstRd_src_rdy_n : std_logic := '0';
signal Bus2IP_MstWr_dst_rdy_n : std_logic := '0';
--Outputs
signal Reset_Done : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal IP2Bus_RdAck : std_logic;
signal IP2Bus_WrAck : std_logic;
signal IP2Bus_Error : std_logic;
signal IP2Bus_MstRd_Req : std_logic;
signal IP2Bus_MstWr_Req : std_logic;
signal IP2Bus_Mst_Addr : std_logic_vector(0 to 31);
signal IP2Bus_Mst_BE : std_logic_vector(0 to 3);
signal IP2Bus_Mst_Lock : std_logic;
signal IP2Bus_Mst_Reset : std_logic;
signal IP2Bus_MstWr_d : std_logic_vector(0 to 31);
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: user_logic PORT MAP (
Soft_Reset => Soft_Reset,
Reset_Done => Reset_Done,
interrupts_in => interrupts_in,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n
);
Bus2IP_Clk_process :process
begin
Bus2IP_Clk <= '0';
wait for clock_period/2;
Bus2IP_Clk <= '1';
wait for clock_period/2;
end process;
ACK_proc : process
begin
wait until IP2Bus_MstRd_Req = '1';
Bus2IP_Mst_Cmplt <= '1';
Bus2IP_Mst_CmdAck <= '1';
wait until IP2Bus_MstRd_Req = '0';
Bus2IP_Mst_Cmplt <= '0';
Bus2IP_Mst_CmdAck <= '0';
wait for 5*clock_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clock_period*10;
-- Reset the core
Soft_Reset <= '1';
wait until Reset_Done = '1';
wait for clock_period*5;
Soft_Reset <= '0';
wait for 5*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010300";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010440";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010580";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"110109C0";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Cause interrupts
interrupts_in <= x"8";
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait;
end process;
END;
| bsd-3-clause | 800393829367a907e2026d3c5f8906e1 | 0.598702 | 2.926716 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/basic_sfifo_fg.vhd | 2 | 44,796 | -------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
use proc_common_v3_00_a.coregen_comp_defs.all;
-- synopsys translate_off
library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : fifo_generator_v8_2
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => CLK, -- uses this one
RST => '0',
SRST => SRST, -- uses this one
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => DIN, -- uses this one
WR_EN => WR_EN, -- uses this one
RD_EN => RD_EN, -- uses this one
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DOUT => DOUT, -- uses this one
FULL => FULL, -- uses this one
ALMOST_FULL => open,
WR_ACK => open,
OVERFLOW => open,
EMPTY => EMPTY, -- uses this one
ALMOST_EMPTY => open,
VALID => open,
UNDERFLOW => open,
DATA_COUNT => DATA_COUNT, -- uses this one
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open -- : OUT std_logic
);
end implementation;
| bsd-3-clause | 0260885c9df3012987e390c6f39589c9 | 0.398138 | 3.78121 | false | false | false | false |
guilhermekrz/Pipeline-Processor | HW_Src/sevenSegment.vhd | 1 | 1,425 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevenSegment is
port (
numberDesired : in std_logic_vector(3 downto 0);
sevenSegmentVector : out std_logic_vector(6 downto 0);
clock, reset : in std_logic
);
end sevenSegment;
architecture behavior of sevenSegment is
begin
process (clock,numberDesired)
BEGIN
if (clock'event and clock='1') then
case numberDesired is
when "0000"=> sevenSegmentVector <="0000001";--0
when "0001"=> sevenSegmentVector <="1001111";--1
when "0010"=> sevenSegmentVector <="0010010";--2
when "0011"=> sevenSegmentVector <="0000110";--3
when "0100"=> sevenSegmentVector <="1001100";--4
when "0101"=> sevenSegmentVector <="0100100";--5
when "0110"=> sevenSegmentVector <="0100000";--6
when "0111"=> sevenSegmentVector <="0001111";--7
when "1000"=> sevenSegmentVector <="0000000";--8
when "1001"=> sevenSegmentVector <="0000100";--9
when "1010"=> sevenSegmentVector <="0001000";--A
when "1011"=> sevenSegmentVector <="1100000";--b
when "1100"=> sevenSegmentVector <="0110001";--C
when "1101"=> sevenSegmentVector <="0000011";--d
when "1110"=> sevenSegmentVector <="0110000";--E
when "1111"=> sevenSegmentVector <="0111000";--F
when others=> sevenSegmentVector <="1111111";--' '
end case;
end if;
end process;
end behavior; | gpl-2.0 | 6d3555079a965544f408eff0faba5f4c | 0.665263 | 4.241071 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethrx_input.vhd | 1 | 13,530 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Eth_TestSig_Cfg.all;
entity ethrx_input is
generic(
HEAD_AWIDTH : natural := 5; -- ½ÓÊÕ¶ÓÁеØÖ·¿í¶È 2^5 = 32 ×Ö½Ú
BUFF_AWIDTH : natural := 16 -- BUFF16λµØÖ·Ïß
);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic; -- FPGAʱÖÓ
reset : in std_logic;
rxclk : in std_logic; -- MIIÊä³öʱÖÓ
rxd : in std_logic_vector(3 downto 0); -- ²¢¿ÚÊäÈëÊý¾Ý£¬4bitΪµ¥Î»£¨nipple£©
rxdv : in std_logic; -- ÔÚRXDV='1'µÄÇé¿öϼì²âµ½"5..5D"£¬±íʾһ¸öÒÔÌ«°üµÄ¿ªÊ¼
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0); --ÿһ¸ö°ü´Ó0¿ªÊ¼µÝÔö¼ÆÊý
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic; -- ָʾCRC½á¹û£¬'1'±íʾÕýÈ·£¬'0'±íʾ²»ÕýÈ·
buff_wren : out std_logic;
buff_waddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_wdata : out std_logic_vector(7 downto 0) -- ÒÔÌ«°üÊý¾Ý°´×Ö½Úд³ö£¬Ð´µØÖ·´ÓÉÏ´ÎдµØÖ·µÄĩβµÝÔö£¬°üº¬ÒÔÌ«°üÍ·
);
end ethrx_input;
architecture arch_ethrx_input of ethrx_input is
component fifo_async
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async use entity WORK.fifo_async(fast_read);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
component crcrom
port(
addr : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
constant INFO_LENGTH : natural := 4;
constant HEAD_LENGTH : natural := 2 ** HEAD_AWIDTH - INFO_LENGTH;
signal rxdv_buf : std_logic;
signal rxd_buf : std_logic_vector(3 downto 0);
signal d_ext : std_logic_vector(4 downto 0);
signal rxdv_int : std_logic;
signal rxd_int : std_logic_vector(3 downto 0);
signal d_int : std_logic_vector(4 downto 0);
signal ce : std_logic;
signal rd_ena : std_logic;
signal empty : std_logic;
signal rx_state : std_logic_vector(1 downto 0);
signal nibble_cnt : std_logic_vector(11 downto 0);
signal rxd_int_d1 : std_logic_vector(3 downto 0);
signal rxd_int_d2 : std_logic_vector(3 downto 0);
signal byte_data : std_logic_vector(7 downto 0);
signal buff_wren_buf : std_logic;
signal buff_waddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(3 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(3 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal crc_flag : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_ena : std_logic;
signal start_addr : std_logic_vector(15 downto 0);
signal length : std_logic_vector(15 downto 0);
signal head_wren_buf : std_logic;
signal head_waddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wr_block_buf: std_logic;
signal rxclk_temp : std_logic;
signal localtime_locked_reg: std_logic;
begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if info_ena = '1' then
-- test_crc(0) <= crc_flag;
-- test_crc(1) <= crc_reg(2);
-- test_crc(2) <= crc_reg(4);
-- test_crc(3) <= crc_reg(8);
-- end if;
-- end if;
-- end process;
p_mii_din : process(rxclk) -- MII->ETH-RX ÊäÈëÊý¾Ý»º´æ
begin
if rising_edge(rxclk) then
-- if falling_edge(rxclk) then
rxdv_buf <= rxdv;
rxd_buf <= rxd;
end if;
end process;
-- rxclk_temp <= not rxclk;
u_din_sync : fifo_async
generic map(
DEPTH => 4,
AWIDTH => 2,
DWIDTH => 5,
RAM_TYPE => "DIS_RAM")
port map(
reset => reset,
clr => '0',
clka => rxclk,
-- clka => rxclk_temp,
wea => '1',
dia => d_ext,
clkb => clk,
rdb => rd_ena,
dob => d_int,
empty => empty,
full => open,
dn => open
);
d_ext <= rxdv_buf & rxd_buf;
rxdv_int <= d_int(4);
rxd_int <= d_int(3 downto 0);
rd_ena <= not empty;
p_ce : process(clk)
begin
if rising_edge(clk) then
ce <= rd_ena;
end if;
end process;
------------------------------------------------------------------------------
p_state_machine : process(clk, reset)
begin
if reset = '1' then
rx_state <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
case rx_state is
when "00" =>
if rxdv_int = '1' and rxd_int = "0101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
when "01" =>
if rxdv_int = '1' then
if rxd_int = "1101" then
rx_state <= "10";
elsif rxd_int = "0101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
else
rx_state <= "00";
end if;
when "10" =>
if rxdv_int = '1' then
rx_state <= "11";
end if;
when "11" =>
if rxdv_int = '0' then
rx_state <= "00";
end if;
when others =>
NULL;
end case;
end if;
end if;
end process;
p_nibble_cnt : process(clk, reset) -- nibble count
begin
if reset = '1' then
nibble_cnt <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "00" then
nibble_cnt <= (others => '0');
elsif rx_state = "11" then
nibble_cnt <= nibble_cnt + 1;
end if;
end if;
end if;
end process;
p_s2p : process(clk, reset)
begin
if reset = '1' then
rxd_int_d1 <= (others => '0');
rxd_int_d2 <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
rxd_int_d1 <= rxd_int;
rxd_int_d2 <= rxd_int_d1;
end if;
end if;
end process;
byte_data <= rxd_int_d1 & rxd_int_d2;
------------------------------------------------------------------------------
p_recvtime : process(clk, reset)
begin
if reset = '1' then
recvtime(31 downto 0) <= (others => '0');
recvtime_valid <= '0';
elsif rising_edge(clk) then
if ce = '1' then
case nibble_cnt is
when X"01B" => recvtime(27 downto 24) <= rxd_int;
when X"01c" => recvtime(31 downto 28) <= rxd_int;
when X"01d" => recvtime(19 downto 16) <= rxd_int;
when X"01e" => recvtime(23 downto 20) <= rxd_int;
when X"01f" => recvtime(11 downto 8) <= rxd_int;
when X"020" => recvtime(15 downto 12) <= rxd_int;
when X"021" => recvtime(3 downto 0) <= rxd_int;
when X"022" => recvtime(7 downto 4) <= rxd_int;
when X"023" => recvtime_valid <= '1';
when others => recvtime_valid <= '0';
end case;
end if;
end if;
end process;
p_localtime_locked : process(clk, reset)
begin
if reset = '1' then
localtime_locked_reg <= '0';
elsif rising_edge(clk) then
if ce = '1' and rx_state = "10" and localtime_locked_reg = '0' then
localtime_locked_reg <= '1';
elsif localtime_locked_reg = '1' then
localtime_locked_reg <= '0';
end if;
end if;
end process;
localtime_locked <= localtime_locked_reg;
------------------------------------------------------------------------------
p_buff_wren : process(clk, reset)
begin
if reset = '1' then
buff_wren_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if nibble_cnt(0) = '1' and rx_state = "11" then -- 2nibbleдʹÄÜ£¿
buff_wren_buf <= '1';
else
buff_wren_buf <= '0';
end if;
end if;
end if;
end process;
p_buff_waddr : process(clk, reset)
begin
if reset = '1' then
buff_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if buff_wren_buf = '1' then
buff_waddr_buf <= buff_waddr_buf + 1; -- buffer address ++
end if;
end if;
end if;
end process;
p_buff_wdata : process(clk, reset)
begin
if reset = '1' then
buff_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
buff_wdata <= byte_data;
end if;
end if;
end process;
buff_wren <= buff_wren_buf and ce;
buff_waddr <= buff_waddr_buf;
------------------------------------------------------------------------------
u_crc_rom : CRCRom
port map(
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 28);
p_calc_crc : process(clk, reset)
begin
if reset = '1' then
crc_din <= (others => '0');
crc_reg <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if nibble_cnt < 7 then
crc_din <= not (rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3));
else
crc_din <= rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3);
end if;
if rx_state = "10" then
crc_reg <= (others => '0');
elsif rx_state = "11" then
crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
end if;
end if;
end if;
end process;
p_crc_flag : process(clk, reset)
begin
if reset = '1' then
crc_flag <= '0';
g_Test_EthRec_CRCFlag <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "00" and crc_reg = X"FFFFFFFF" then
crc_flag <= '1';
elsif rx_state = "10" then
crc_flag <= '0';
end if;
end if;
g_Test_EthRec_CRCFlag <= crc_flag;
end if;
end process;
------------------------------------------------------------------------------
p_start_addr : process(clk, reset)
begin
if reset = '1' then
start_addr <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "10" then
start_addr <= EXT(buff_waddr_buf, 16); -- °üÀ¨CRCµØÖ·
end if;
end if;
end if;
end process;
p_length : process(clk, reset)
begin
if reset = '1' then
length <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "11" and rxdv_int = '0' then
length <= "00000" & nibble_cnt(11 downto 1) - 3; -- Êý¾Ý³¤¶È£¬³ýµô4Bytes CRCУÑé
end if;
end if;
end if;
end process;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "11" and rxdv_int = '0' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
p_head_wren : process(clk, reset)
begin
if reset = '1' then
head_wren_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if (nibble_cnt(0) = '1' and rx_state = "11" and rxdv_int = '1' and nibble_cnt(11 downto 1) < HEAD_LENGTH) or info_ena = '1' then -- Ç°32¸ö×Ö½Úдʱ£¬ÒÔ¼°×îºóдµØÖ·Ó볤¶È4×Ö½ÚʱΪ1
head_wren_buf <= '1';
else
head_wren_buf <= '0';
end if;
end if;
end if;
end process;
p_head_waddr : process(clk, reset)
begin
if reset = '1' then
head_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if rx_state = "10" then
head_waddr_buf <= conv_std_logic_vector(INFO_LENGTH, HEAD_AWIDTH);
elsif rx_state = "11" and rxdv_int = '0' then
head_waddr_buf <= conv_std_logic_vector(0, HEAD_AWIDTH);
elsif head_wren_buf = '1' then
head_waddr_buf <= head_waddr_buf + 1;
end if;
end if;
end if;
end process;
p_head_wdata : process(clk, reset)
begin
if reset = '1' then
head_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 => head_wdata <= length(7 downto 0);
when 1 => head_wdata <= length(15 downto 8);
when 2 => head_wdata <= start_addr(7 downto 0);
when 3 => head_wdata <= start_addr(15 downto 8);
when others => null;
end case;
else
head_wdata <= byte_data;
end if;
end if;
end if;
end process;
head_wren <= head_wren_buf and ce;
head_waddr <= head_waddr_buf;
p_head_wr_block : process(clk, reset)
begin
if reset = '1' then
head_wr_block_buf <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if info_cnt = INFO_LENGTH and crc_flag = '1' then -- crcУÑéÕýÈ·
head_wr_block_buf <= '1';
else
head_wr_block_buf <= '0';
end if;
end if;
end if;
end process;
head_wr_block <= head_wr_block_buf and ce; -- crcУÑéÖ¸Õë
end arch_ethrx_input;
| gpl-2.0 | 38d1704240c134f06e32a533411ba632 | 0.539098 | 2.689861 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_top.vhd | 3 | 18,412 | -------------------------------------------------------------------------------
-- $Id: wrpfifo_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Write Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
-- wrpfifo_top.vhd
-- |
-- |---> ipif_control_wr.vhd
-- |
-- |---> wrpfifo_dp_cntl.vhd
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | | |
-- | | |-- pf_adder_bit.vhd
-- | |
-- | |
-- | |-- pf_dly1_mux.vhd
-- |
-- |---> pf_dpram.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET Apr-24-01
-- - Change the dual port configuration name to wdport_512x32
-- from dport_512x32.
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- Commented out the rpfifo_lib declarations.
--
-- DET MAY-24-01
-- - v0.00B Incorporated the V0.00c dual port controller module
--
-- DET June-25-01
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
-- - Changed to V1.00b of the IPIF write Control module.
-- - Changed to the V1.00d version of the DP control module.
-- - Added input Generics for MIR enable and Block ID
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
-- - Added additional parameters (generics)
--
-- DET Oct. 02, 2001 (part of v1.02a version)
-- - added the optimization changes
--
--
-- DET Oct. 8, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ipif_control_wr;
use opb_ipif_v2_00_h.wrpfifo_dp_cntl;
use opb_ipif_v2_00_h.pf_dpram_select;
use opb_ipif_v2_00_h.srl16_fifo;
-------------------------------------------------------------------------------
entity wrpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq : In std_logic;
IP2WFIFO_RdMark : In std_logic;
IP2WFIFO_RdRestore : In std_logic;
IP2WFIFO_RdRelease : In std_logic;
-- Outputs to the IP
WFIFO2IP_Data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck : Out std_logic;
WFIFO2IP_AlmostEmpty : Out std_logic;
WFIFO2IP_Empty : Out std_logic;
WFIFO2IP_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull : Out std_logic;
WFIFO2DMA_Full : Out std_logic;
WFIFO2DMA_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end wrpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_top is
-- COMPONENTS
-- The IPIF Local Bus Interface Block
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the WrPFIFO design
-- (0 = engineering release,
-- 1 = major release 1, etc.)
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the WrPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter of the WrPFIFO design
-- (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
-- IPIF block protocol Type (Read Packet FIFO = 2, Write PFIFO = 3)
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 3;
----------------------------------------------------------------------------
-- General Use Constants
----------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_fifo_wrack: std_logic;
Signal sig_fifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_wr_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_mem_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
-------------------------------------------------------------------------------
------------------------------- start processes -------------------------------
begin
-- connect I/O signals to internals
WFIFO2IP_RdAck <= sig_fifo_rdack;
WFIFO2IP_Empty <= sig_fifo_empty;
WFIFO2IP_AlmostEmpty <= sig_fifo_almost_empty;
WFIFO2IP_Occupancy <= sig_fifo_occupancy;
WFIFO2DMA_AlmostFull <= sig_fifo_almost_full;
WFIFO2DMA_Full <= sig_fifo_full ;
WFIFO2DMA_Vacancy <= sig_fifo_vacancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_rdreq <= IP2WFIFO_RdReq;
WFIFO2IP_Data <= sig_mem_rd_data;
I_IPIF_INTERFACE_BLOCK : entity opb_ipif_v2_00_h.ipif_control_wr
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_clk => Bus_clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => Bus_DBus ,
-- Inputs from the FIFO Interface Logic
Fifo_WrAck => sig_fifo_wrack,
Vacancy => sig_fifo_vacancy,
AlmostFull => sig_fifo_almost_full,
Full => sig_fifo_full,
Deadlock => sig_fifo_deadlock,
-- Outputs to the FIFO
Fifo_wr_data => sig_mem_wr_data,
Fifo_Reset => sig_fifo_logic_reset,
Fifo_WrReq => sig_mem_wrreq,
Fifo_burst_wr_xfer => sig_burst_wr_xfer,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
-- The Dual Port Control Block
begin
-- Connect the Dual Port Address Controller the VHDL wrapper
I_DP_CONTROLLER: entity opb_ipif_v2_00_h.wrpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_clk,
Rdreq => sig_mem_rdreq,
Wrreq => sig_mem_wrreq,
Burst_wr_xfer => sig_burst_wr_xfer,
Mark => IP2WFIFO_RdMark,
Restore => IP2WFIFO_RdRestore,
Release => IP2WFIFO_RdRelease,
-- Outputs
WrAck => sig_fifo_wrack,
RdAck => sig_fifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_ipif_v2_00_h.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_fifo_rdack <= sig_mem_rdreq and not(sig_fifo_empty);
sig_fifo_wrack <= sig_mem_wrreq and not(sig_fifo_full);
I_SRL_MEM : entity opb_ipif_v2_00_h.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_mem_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
| bsd-3-clause | 58683f4771c570f718409d6550f5e4b6 | 0.451662 | 3.941768 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_adder.vhd | 2 | 10,249 | -------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
component pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic;
Bin : in std_logic;
Add_sub_n : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end component pf_adder_bit;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
--
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
-- carry_active_high <= alu_cy(0) xor not(Add_sub_n);
--
--
--
-- I_CARRY_OUT: FDRE
-- port map (
-- Q => Carry_Out, -- [out]
-- C => Clk, -- [in]
-- CE => count_clock_en, -- [in]
-- D => carry_active_high, -- [in]
-- R => Rst -- [in]
-- );
result_out <= iresult_out;
end architecture implementation;
| bsd-3-clause | ff5f4a1ddc1f2469744f57b2495c4742 | 0.39155 | 5.043799 | false | false | false | false |
jevinskie/aes-over-pcie | source/experiment/lfsr.vhd | 1 | 1,289 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr is
port (
clk : in std_logic;
clr : in std_logic;
count : out unsigned(3 downto 0);
top : out std_logic
);
end lfsr;
architecture behav of lfsr is
signal cnt, next_cnt : unsigned(3 downto 0);
signal near,near2 : std_logic;
signal g, next_g : unsigned(3 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
cnt <= next_cnt;
g <= next_g;
end if;
end process;
process(cnt, clr, near, g)
begin
if (clr='1') then
next_cnt <= (others => '1');
next_g <= (others => '1');
else
-- next_cnt <= cnt rol 1;
--next_cnt(3) <= cnt(2) xor cnt(0) xor near;
--next_cnt(2) <= cnt(1) xor cnt(0);
next_cnt <= cnt ror 1;
next_cnt(3) <= cnt(3) xor cnt(0) xor near;
next_g(3) <= g(0);
next_g(2) <= g(0) xor g(3);
next_g(1 downto 0) <= g(2 downto 1);
end if;
end process;
near <= '1' when (cnt(3)='0' and cnt(2)='0' and cnt(1)='0') else '0';
near2 <= '1' when (g(3)='0' and g(2)='0' and g(1)='0') else '0';
count <= cnt;
top <= '1' when cnt = x"e" else '0';
end behav;
| bsd-3-clause | a8460df55f014a2dd19e212312471832 | 0.494182 | 2.997674 | false | false | false | false |
meteorcloudy/CPU_verilog | shit_tester.vhd | 1 | 2,503 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:19 03/28/2014
-- Design Name:
-- Module Name: D:/XilinxProject/CPU/shit_tester.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shift
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY shit_tester IS
END shit_tester;
ARCHITECTURE behavior OF shit_tester IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shift
PORT(
d : IN std_logic_vector(31 downto 0);
sa : IN std_logic_vector(4 downto 0);
right : IN std_logic;
arith : IN std_logic;
sh : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal d : std_logic_vector(31 downto 0) := (others => '0');
signal sa : std_logic_vector(4 downto 0) := (others => '0');
signal right : std_logic := '0';
signal arith : std_logic := '0';
--Outputs
signal sh : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shift PORT MAP (
d => d,
sa => sa,
right => right,
arith => arith,
sh => sh
);
-- Clock process definitions
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | ea4ea2473aeb428e913909e186fc0ef0 | 0.582101 | 3.941732 | false | true | false | false |
xdsopl/vhdl | asynchronous_quadrature_decoder.vhd | 1 | 1,199 | -- asynchronous_quadrature_decoder - quadrature decoder without synchronizing clock input
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
-- prior debouncing of rotary input is unnecessary
entity asynchronous_quadrature_decoder is
port (
rotary : in std_logic_vector (1 downto 0);
direction : out std_logic;
pulse : out std_logic
);
end asynchronous_quadrature_decoder;
architecture gate_level of asynchronous_quadrature_decoder is
signal a, b, c, d, e, f : std_logic;
signal pul, pul_n, dir, dir_n : std_logic;
begin
a <= rotary(0);
b <= rotary(1);
c <= a and b;
d <= a nor b;
e <= a and not b;
f <= b and not a;
dir <= dir_n nor e;
dir_n <= dir nor f;
pul <= pul_n nor d;
pul_n <= pul nor c;
pulse <= pul;
direction <= dir;
end gate_level;
| cc0-1.0 | aa6909262c7b0360e023eb766e490a2f | 0.718098 | 3.396601 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/sync_fifo.vhd | 2 | 14,999 | -------------------------------------------------------------------------------
-- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- sync_fifo.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2004-03-24 New Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
library fsl_v20_v2_11_f;
use fsl_v20_v2_11_f.all;
entity Sync_FIFO is
generic (
C_IMPL_STYLE : integer := 0;
WordSize : integer := 8;
MemSize : integer := 16
);
port (
Reset : in std_logic;
Clk : in std_logic;
WE : in std_logic;
DataIn : in std_logic_vector(WordSize-1 downto 0);
Full : out std_logic;
RD : in std_logic;
DataOut : out std_logic_vector(WordSize-1 downto 0);
Exists : out std_logic
);
end Sync_FIFO;
architecture VHDL_RTL of Sync_FIFO is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
-- coverage off
if x = 0 then return 0;
-- coverage on
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant AddrWidth : integer := log2(MemSize);
signal Read_Address : std_logic_vector(0 to AddrWidth-1);
signal Write_Address : std_logic_vector(0 to AddrWidth-1);
component SRL_FIFO is
generic (
C_DATA_BITS : integer;
C_DEPTH : integer);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
-- FIFO_Half_Full : out std_logic;
-- FIFO_Half_Empty : out std_logic;
Data_Exists : out std_logic);
end component SRL_FIFO;
component Sync_DPRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component;
component Sync_BRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
-- Write port
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
-- Read port
dpra_en : in std_logic;
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component;
signal read_bram_enable : std_logic;
signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
begin
FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
signal full_i : std_logic;
signal exists_i : std_logic;
signal read_addr_incr : std_logic;
signal first_write_on_empty_fifo : std_logic;
signal last_word : std_logic;
signal fifo_length : natural range 0 to MemSize;
begin
-- FIFO length handling
Fifo_Length_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_length <= 0;
else
-- write and no read => increment length
-- don't increment length when FULL
if (WE = '1' and RD = '0' and full_i = '0') then
fifo_length <= fifo_length + 1;
-- read and no write => decrement length
-- don't decrement length when EMPTY
elsif (WE = '0' and RD = '1' and exists_i = '1') then
fifo_length <= fifo_length - 1;
end if;
end if;
end if;
end process Fifo_Length_Handle;
---------------------------------------------------------------------------
-- Need special handling for BRAM based fifo since there is one extra delay
-- reading out data from it.
-- We are pipelining the reading by making read_addr be one read ahead and
-- are holding the data on the BRAM output by enabling/disabling the BRAM
-- enable signal
---------------------------------------------------------------------------
Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
signal use_fall_through : std_logic;
begin
-------------------------------------------------------------------------
-- Need to detect when writing into an empty FIFO,
-------------------------------------------------------------------------
First_Write : process (Clk) is
begin -- process First_Write
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
first_write_on_empty_fifo <= '0';
else
first_write_on_empty_fifo <= WE and not exists_i;
end if;
end if;
end process First_Write;
-------------------------------------------------------------------------
-- Read out BRAM contents on the first word written in an empty FIFO and
-- all other FIFO read except when the last word is read since the "real"
-- FIFO is actually empty at this time since the last word is on the
-- output of the BRAM
-------------------------------------------------------------------------
last_word <= '1' when (fifo_length = 1) else '0';
read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
read_addr_incr <= read_bram_enable;
-------------------------------------------------------------------------
-- The exists flag is now if the BRAM output has valid data and not the
-- content of the FIFO
-------------------------------------------------------------------------
FIFO_Exists_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
Exists <= '0';
else
if (first_write_on_empty_fifo = '1') then
Exists <= '1';
elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
Exists <= '0';
end if;
end if;
end if;
end process FIFO_Exists_DFF;
-------------------------------------------------------------------------
-- Data output with fallthrough
-------------------------------------------------------------------------
use_fall_through_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
use_fall_through <= '0';
elsif (RD and not last_word) = '1' then
use_fall_through <= '0';
elsif (RD = '1') then
-- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
use_fall_through <= '1';
end if;
end if;
end process use_fall_through_DFF;
fall_through_data_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (RD and WE and last_word) = '1' then
fall_through_data <= DataIn;
end if;
end if;
end process fall_through_data_DFF;
DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
end generate Rd_Delay_For_Bram;
Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
read_addr_incr <= RD;
Exists <= exists_i;
end generate Rd_No_Delay;
-- Set Full and empty flags
full_i <= '1' when (fifo_length = MemSize) else '0';
exists_i <= '1' when (fifo_length /= 0) else '0';
Full <= full_i;
-- Increment Read Address Pointer
Read_Addr_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
read_addr_ptr <= 0;
elsif (read_addr_incr = '1') then
read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
end if;
end if;
end process Read_Addr_Handle;
-- Increment Write Address Pointer
Write_Addr_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
write_addr_ptr <= 0;
elsif (WE = '1') then
write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
end if;
end if;
end process Write_Addr_Handle;
Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
end generate FSL_Flag_Handle;
Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
srl_fifo_i : if (MemSize <= 16) generate
FSL_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => WordSize,
C_DEPTH => MemSize)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => WE, -- Master Write Signal
Data_In => DataIn, -- Master Data
FIFO_Read => RD, -- Slave Read Signal
Data_Out => DataOut, -- Slave Data
FIFO_Full => Full, -- FIFO full signal
-- FIFO_Half_Full => open,
-- FIFO_Half_Empty => open,
Data_Exists => Exists); -- Slave Data exists
end generate srl_fifo_i;
dpram_fifo_i : if (MemSize > 16) generate
DPRAM_FIFO : SYNC_DPRAM
generic map (
C_DWIDTH => WordSize,
C_AWIDTH => AddrWidth)
port map (
clk => Clk,
we => WE,
a => Write_Address,
dpra => Read_Address,
di => DataIn,
dpo => DataOut);
end generate dpram_fifo_i;
end generate Sync_FIFO_I;
Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
Sync_BRAM_I1 : Sync_BRAM
generic map (
C_DWIDTH => WordSize, -- [integer]
C_AWIDTH => AddrWidth) -- [integer]
port map (
clk => Clk, -- [in std_logic]
-- Write port
we => WE, -- [in std_logic]
a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
-- Read port
dpra_en => read_bram_enable, -- [in std_logic]
dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
end generate Sync_BRAM_FIFO;
end VHDL_RTL;
| bsd-3-clause | 5c09cc2f161aa941936e316fed3adab5 | 0.517768 | 4.10594 | false | false | false | false |
QuickJack/logi-hard | hdl/utils/generic_rs_latch.vhd | 2 | 1,323 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 17:17:17 06/18/2012
-- Design Name:
-- Module Name: generic_rs_latch - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity generic_rs_latch is
port(clk, resetn : in std_logic ;
s, r : in std_logic ;
q : out std_logic );
end generic_rs_latch;
architecture Behavioral of generic_rs_latch is
signal Qp : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= '0' ;
elsif clk'event and clk = '1' then
if s = '1' then
Qp <= '1' ;
elsif r = '1' then
Qp <= '0' ;
end if ;
end if ;
end process ;
q <= Qp ;
end Behavioral;
| lgpl-3.0 | 7c5b6acb43d92e7d0153e92eb43f8aad | 0.585034 | 3.537433 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/stackP.vhd | 1 | 886 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity StackP is
generic (
width : integer
);
port(
reset: in std_logic;
en: in std_logic;
clk: in std_logic;
pop_push: in std_logic;
addr: out std_logic_vector(width-1 downto 0)
);
end StackP;
architecture behavior of StackP is
signal count : std_logic_vector( width-1 downto 0 ):=(others=>'0');
signal updown : std_logic_vector( width-1 downto 0 ):=(others=>'0');
begin
updown<=count+1 when pop_push='1' else count-1;
addr<=updown when pop_push='1' else count;
process(clk,reset)
begin
if reset = '1' then
count <= (others=>'0');
elsif rising_edge(clk) then
if en='1' then
count<=updown;
end if;
end if;
end process;
end behavior;
| gpl-2.0 | 29dd7be8abf46c5df6ad8526e01e926f | 0.65237 | 2.812698 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/srl_fifo3.vhd | 3 | 13,894 | -------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
-- als 01/19/04 added FIFO_AlmostEmpty output from the not of next_data_exists
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
FIFO_AlmostEmpty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
FIFO_AlmostEmpty <= not(next_Data_Exists);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| bsd-3-clause | 514a05f37ca42104f76c9617a9b945ec | 0.448467 | 4.673394 | false | false | false | false |
jevinskie/aes-over-pcie | source/numeric_std_textio.vhd | 1 | 2,834 | --
-- Package: numerric_std_textio
-- Author: n0702078
-- Created On: 02/02/01 at 13:16
--
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
package numeric_std_textio is
--synopsys synthesis_off
-- Read and Write procedures for SIGNED and UNSIGNED
procedure READ(L:inout LINE; VALUE:out SIGNED);
procedure READ(L:inout LINE; VALUE:out SIGNED; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out UNSIGNED);
procedure READ(L:inout LINE; VALUE:out UNSIGNED; GOOD: out BOOLEAN);
procedure HREAD(L:inout LINE; VALUE:out UNSIGNED);
procedure HREAD(L:inout LINE; VALUE:out UNSIGNED; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in SIGNED;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in UNSIGNED;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end numeric_std_textio;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
package body numeric_std_textio is
--synopsys synthesis_off
-- Read and Write procedures for SIGNED and UNSIGNED
procedure READ(L:inout LINE; VALUE:out SIGNED; GOOD: out BOOLEAN) is
variable slv_value : std_logic_vector(value'range);
begin
read(L, slv_value, good);
value:= signed(slv_value);
end;
procedure READ(L:inout LINE; VALUE:out SIGNED) is
variable good : boolean;
begin
read(l, value, good);
assert good
report "numeric_std_textio: read(line,signed) failed"
severity error;
end;
procedure READ(L:inout LINE; VALUE:out UNSIGNED; GOOD: out BOOLEAN) is
variable slv_value : std_logic_vector(value'range);
begin
read(L, slv_value, good);
value:= unsigned(slv_value);
end;
procedure READ(L:inout LINE; VALUE:out UNSIGNED) is
variable good : boolean;
begin
read(l, value, good);
assert good
report "numeric_std_textio: read(line,unsigned) failed"
severity error;
end;
procedure HREAD(L:inout LINE; VALUE:out UNSIGNED; GOOD: out BOOLEAN) is
variable slv_value : std_logic_vector(value'range);
begin
hread(L, slv_value, good);
value:= unsigned(slv_value);
end;
procedure HREAD(L:inout LINE; VALUE:out UNSIGNED) is
variable good : boolean;
begin
hread(l, value, good);
assert good
report "numeric_std_textio: hread(line,unsigned) failed"
severity error;
end;
procedure WRITE(L:inout LINE; VALUE:in SIGNED;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, std_logic_vector(value), justified, field);
end;
procedure WRITE(L:inout LINE; VALUE:in UNSIGNED;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, std_logic_vector(value), justified, field);
end;
--synopsys synthesis_on
end;
| bsd-3-clause | e5fc8bb08f3c69f4c56b60e1ff90a349 | 0.686309 | 3.511772 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/ipif_data_steer.vhd | 3 | 10,250 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_data_steer.vhd
-- Version: v1.10.a
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_data_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
-- BLT 5-13-2002 -- Added capability for peripherals larger
-- than bus, new optimizations
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH_BUS : integer := width of host databus attached to the IPIF
-- C_DWIDTH_IP : integer := width of IP databus attached to the IPIF
-- C_SMALLEST_MASTER : integer := width of smallest master (not access size)
-- attached to the IPIF
-- C_SMALLEST_IP : integer := width of smallest IP device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Data_Steer is
generic (
C_DWIDTH_BUS : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_IP : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_MASTER : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IP : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH_BUS-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH_IP-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_BUS/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH_IP-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH_BUS-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_IP/8-1)
);
end entity IPIF_Data_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Data_Steer is
component Steer_Module_Write is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end component Steer_Module_Write;
component Steer_Module_Read is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end component Steer_Module_Read;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
WRITE_I: Steer_Module_Write
generic map (
C_DWIDTH_IN => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Wr_Data_In, --[in]
BE_In => BE_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Wr_Data_Out, --[out]
BE_Out => BE_Out --[out]
);
READ_I: Steer_Module_Read
generic map (
C_DWIDTH_IN => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT => C_SMALLEST_MASTER, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Rd_Data_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Rd_Data_Out --[out]
);
end architecture IMP;
| bsd-3-clause | 8c85d03c641021e647c088bd59664fa3 | 0.420683 | 4.059406 | false | false | false | false |
michaelmiehling/A25_VME | Source/z091_01_wb_adr_dec.vhd | 1 | 5,824 | --------------------------------------------------------------------------------
-- Title : 16z091-01 specific Wishbone bus
-- Project :
-------------------------------------------------------------------------------
-- File : z091_01_wb_adr_dec.vhd
-- Author : Susanne Reinfelder
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2012-12-19
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- +-------------------------------+-----+----------+----------+-----+
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
entity z091_01_wb_adr_dec is
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port(
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end z091_01_wb_adr_dec;
-------------------------------------------------------------------------
-- sim_test_arch implements a sample pcie address decoder to enable
-- the simulation iram models
-------------------------------------------------------------------------
architecture a25_arch of z091_01_wb_adr_dec is
begin
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 DOWNTO 0);
CONSTANT zero : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0):=(OTHERS => '0');
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 5) = "0000000010000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "01" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF or_reduce(pci_cyc_i) = '1' AND wbm_cyc_o_int = zero THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
end a25_arch;
| gpl-3.0 | b12a1e09c32f36813a1c88126e32c085 | 0.445742 | 3.429918 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ipif_reset.vhd | 3 | 16,423 | -------------------------------------------------------------------------------
-- $Id: ipif_reset.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
--ipif_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_reset.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Ethernet IPIF Reset support block.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.01a (initial release)
--
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all; -- need 'conv_std_logic_vector' conversion function
----------------------------------------------------------------------
entity ipif_reset is
Generic (
--C_RESET_PRESENT : Boolean := True; -- specifies if interrupt function is used
C_DBUS_WIDTH : Integer := 32; -- Data bus width (in bits)
C_IPIF_MIR_ENABLE : Boolean := False;-- Allows inclusion of the IPIF MIR
C_IPIF_TYPE : Integer := 1; -- used if MIR is enabled
C_IPIF_BLK_ID : Integer := 1; -- used if MIR is enabled
C_IPIF_REVISION : Integer := 1; -- used if MIR is enabled
C_IPIF_MINOR_VERSION : Integer := 0; -- used if MIR is enabled
C_IPIF_MAJOR_VERSION : Integer := 0 -- used if MIR is enabled
);
port (
-- Inputs From the IPIF Bus
Reset : In std_logic; -- Master Reset from the IPIF reset block
Bus2IP_Clk_i : In std_logic; -- Master timing clock from the IPIF
IP_Reset_WrCE : In std_logic;
IP_Reset_RdCE : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_DBUS_WIDTH-1);
-- Final Device Reset Output
Reset2IP_Reset : Out std_logic; -- Device interrupt output to the Master Interrupt Controller
-- Status Reply Outputs to the Bus
Reset2Bus_DBus : Out std_logic_vector(0 to C_DBUS_WIDTH-1);
Reset2Bus_WrAck : Out std_logic;
Reset2Bus_RdAck : Out std_logic;
Reset2Bus_Error : Out std_logic;
Reset2Bus_Retry : Out std_logic;
Reset2Bus_ToutSup : Out std_logic
);
end ipif_reset ;
-------------------------------------------------------------------------------
architecture implementation of ipif_reset is
--TYPES
type sw_reset_state_types is (idle, wait_for_bus, reset_1, reset_2);
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010"; -- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Generic to constant mapping
--Constant IPIF_BUS_WIDTH : Integer range 0 to 31 := C_DBUS_WIDTH - 1;
--INTERNAL SIGNALS
Signal sw_reset_state : sw_reset_state_types;
Signal strt_sm_reset : std_logic;
Signal sm_reset : std_logic;
Signal sm_wrack : std_logic;
Signal error_reply : std_logic;
Signal MIR_RdAck : std_logic;
Signal Reset_WrAck : std_logic;
Signal Reset_Error : std_logic;
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start architecture logic -------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= Reset_WrAck;
Reset2Bus_RdAck <= MIR_RdAck;
Reset2Bus_Error <= Reset_Error;
Reset2Bus_Retry <= '0';
Reset2Bus_ToutSup <= '0';
Reset_WrAck <= (sm_wrack or error_reply) and IP_Reset_WrCE;
Reset_Error <= error_reply and IP_Reset_WrCE;
Reset2IP_Reset <= Reset or sm_reset;
-----------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-----------------------------------------------------------------------
DETECT_SW_RESET : process (Reset, Bus2IP_Clk_i)
Begin
If (Reset = '1') Then
strt_sm_reset <= '0';
error_reply <= '0';
Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (IP_Reset_WrCE = '1' and Bus_DBus(C_DBUS_WIDTH-4 to C_DBUS_WIDTH-1) = RESET_MATCH) Then
strt_sm_reset <= '1';
error_reply <= '0';
elsif (IP_Reset_WrCE = '1') then
strt_sm_reset <= '0';
error_reply <= '1';
else
strt_sm_reset <= '0';
error_reply <= '0';
End if;
Else
null;
End if;
End process; -- DETECT_SW_RESET
-----------------------------------------------------------------------
-- The S/W reset state machine causes a 2 clock wide reset pulse that
-- occurs after the initiating bus cycle completes.
-----------------------------------------------------------------------
RESET_STATE_MACHINE : process (Reset, Bus2IP_Clk_i)
Begin
If (Reset = '1') Then
sw_reset_state <= idle;
sm_reset <= '0';
sm_wrack <= '0';
Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
sm_reset <= '0'; -- default value
sm_wrack <= '0'; -- default value
Case sw_reset_state Is
When idle =>
If (strt_sm_reset = '1') Then
sw_reset_state <= wait_for_bus;
sm_wrack <= '1'; -- issue the write ack to the ipif bus
else
sw_reset_state <= idle;
End if;
When wait_for_bus =>
If (IP_Reset_WrCE = '1') Then -- wait until bus cycle completes
sw_reset_state <= wait_for_bus;
sm_wrack <= '1'; -- issue the write ack to the ipif bus
else
sw_reset_state <= reset_1;
sm_reset <= '1';
End if;
When reset_1 =>
sw_reset_state <= reset_2;
sm_reset <= '1';
When reset_2 =>
sw_reset_state <= idle;
When others =>
sw_reset_state <= idle;
End case;
Else
null;
End if;
End process; -- RESET_STATE_MACHINE
--------------------------------------------------------------------------------------
-- MIR function stuff
--------------------------------------------------------------------------------------
DELETE_MIR : if (C_IPIF_MIR_ENABLE = False) generate
Reset2Bus_DBus <= (others => '0'); -- always zeroes
-- Status Reply Outputs always low
MIR_RdAck <= '0'; -- no RdAck
end generate DELETE_MIR;
INCLUDE_MIR : if (C_IPIF_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
signal Reg_IP_Reset_RdCE : std_logic;
begin -- generate
----------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics
----------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_IPIF_MAJOR_VERSION, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_IPIF_MINOR_VERSION, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_IPIF_REVISION, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_IPIF_BLK_ID, 8); -- conversion to std_logic_vector required
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_IPIF_TYPE, 8);
REG_RDCE : process (Reset, Bus2IP_Clk_i)
Begin
If (Reset = '1') Then
Reg_IP_Reset_RdCE <= '0';
Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
Reg_IP_Reset_RdCE <= IP_Reset_RdCE;
Else
null;
End if;
End process; -- REG_RDCE
OUTPUT_MIR : process (IP_Reset_RdCE, Reg_IP_Reset_RdCE, mir_value)
Begin
If (IP_Reset_RdCE = '1') Then
for i in 0 to C_DBUS_WIDTH-1 loop
Reset2Bus_DBus(i) <= mir_value(i);
End loop; --forloop_n2
-- Status Reply is RdCE delayed 1 clock
MIR_RdAck <= Reg_IP_Reset_RdCE; -- no RdAck
else
Reset2Bus_DBus <= (others => '0'); -- always zeroes
-- Status Reply Outputs always low
MIR_RdAck <= '0'; -- no RdAck
End if;
End process; -- OUTPUT_MIR
end generate INCLUDE_MIR;
-- --------------------------------------------------------------------------------------
-- -- Reset function stuff
-- --------------------------------------------------------------------------------------
--
-- DELETE_RESET : if (C_RESET_PRESENT = False) generate
--
-- -- Final Device Reset Output
-- Reset2IP_Reset <= Reset; -- Just pass the Reset signal through
-- -- to the output
--
-- -- Status Reply Outputs always low
-- Reset_WrAck <= '0';
-- Reset_Error <= '0'; -- tie to zero
--
-- end generate DELETE_RESET;
--
-- INCLUDE_RESET : if (C_RESET_PRESENT = True) generate
--
-- --TYPES
--
-- type sw_reset_state_types is (idle, wait_for_bus, reset_1, reset_2);
--
-- -- CONSTANTS
--
--
-- -- Module Software Reset screen value for write data
-- Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010"; -- This requires a Hex 'A' to be written
-- -- to ativate the S/W reset port
--
-- -- general use constants
-- Constant LOGIC_LOW : std_logic := '0';
-- Constant LOGIC_HIGH : std_logic := '1';
--
--
--
-- -- Generic to constant mapping
-- --Constant IPIF_BUS_WIDTH : Integer range 0 to 31 := C_DBUS_WIDTH - 1;
--
--
--
--
-- --INTERNAL SIGNALS
--
-- Signal sw_reset_state : sw_reset_state_types;
-- Signal strt_sm_reset : std_logic;
-- Signal sm_reset : std_logic;
-- Signal sm_wrack : std_logic;
-- Signal error_reply : std_logic;
--
--
--
--
-- begin -- generate
--
-- -- Misc I/O and Signal assignments
--
-- Reset_WrAck <= (sm_wrack or error_reply) and IP_Reset_WrCE;
-- Reset_Error <= error_reply and IP_Reset_WrCE;
--
--
-- Reset2IP_Reset <= Reset or sm_reset;
--
--
--
-- -----------------------------------------------------------------------
-- -- Start the S/W reset state machine as a result of an IPIF Bus write to
-- -- the Reset port and the data on the DBus inputs matching the Reset
-- -- match value. If the value on the data bus input does not match the
-- -- designated reset key, an error acknowledge is generated.
-- -----------------------------------------------------------------------
-- DETECT_SW_RESET : process (Reset, Bus2IP_Clk_i)
-- Begin
-- If (Reset = '1') Then
-- strt_sm_reset <= '0';
-- error_reply <= '0';
-- Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
-- If (IP_Reset_WrCE = '1' and Bus_DBus(C_DBUS_WIDTH-4 to C_DBUS_WIDTH-1) = RESET_MATCH) Then
-- strt_sm_reset <= '1';
-- error_reply <= '0';
-- elsif (IP_Reset_WrCE = '1') then
-- strt_sm_reset <= '0';
-- error_reply <= '1';
-- else
-- strt_sm_reset <= '0';
-- error_reply <= '0';
-- End if;
-- Else
-- null;
-- End if;
-- End process; -- DETECT_SW_RESET
--
--
--
--
-- -----------------------------------------------------------------------
-- -- The S/W reset state machine causes a 2 clock wide reset pulse that
-- -- occurs after the initiating bus cycle completes.
-- -----------------------------------------------------------------------
-- RESET_STATE_MACHINE : process (Reset, Bus2IP_Clk_i)
-- Begin
-- If (Reset = '1') Then
-- sw_reset_state <= idle;
-- sm_reset <= '0';
-- sm_wrack <= '0';
--
-- Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
--
-- sm_reset <= '0'; -- default value
-- sm_wrack <= '0'; -- default value
--
-- Case sw_reset_state Is
--
-- When idle =>
-- If (strt_sm_reset = '1') Then
-- sw_reset_state <= wait_for_bus;
-- sm_wrack <= '1'; -- issue the write ack to the ipif bus
-- else
-- sw_reset_state <= idle;
-- End if;
--
-- When wait_for_bus =>
--
-- If (IP_Reset_WrCE = '1') Then -- wait until bus cycle completes
-- sw_reset_state <= wait_for_bus;
-- sm_wrack <= '1'; -- issue the write ack to the ipif bus
-- else
-- sw_reset_state <= reset_1;
-- sm_reset <= '1';
-- End if;
--
-- When reset_1 =>
-- sw_reset_state <= reset_2;
-- sm_reset <= '1';
--
-- When reset_2 =>
-- sw_reset_state <= idle;
--
-- When others =>
-- sw_reset_state <= idle;
-- End case;
--
-- Else
-- null;
-- End if;
--
-- End process; -- RESET_STATE_MACHINE
--
--
--
-- end generate INCLUDE_RESET;
end implementation;
| bsd-3-clause | 2b4e3f8f3886252a48cb49fe1200d04c | 0.415332 | 4.19061 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd | 11 | 407,201 | --------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, qartix7l
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package family_support;
package body family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5fx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6cx => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
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kintex7l => (
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artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when qartix7l => return "qartix7l" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7l" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body family_support;
| bsd-3-clause | eb5fc46737d10b6fce39f3f1bfb573e8 | 0.322696 | 2.583189 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/exit_1.vhd | 2 | 16,784 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: exit_1.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- retVal = SUCCESS
when STATE_12 =>
retVal_next <= Z32;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 5930969ebb7505a428e210f2c42559e5 | 0.5426 | 3.813679 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/gen_srlfifo.vhd | 2 | 8,380 | -------------------------------------------------------------------------------
-- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd - Entity and architecture
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : integer := 8;
C_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
-- FIFO_Half_Full : out std_logic;
-- FIFO_Half_Empty : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
architecture IMP of SRL_FIFO is
signal Addr : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 3);
signal buffer_full_early : std_logic;
begin -- architecture IMP
-- buffer_Full <= '1' when (Addr = "1111") else '0';
buffer_full_early <= '1' when (sum_A = "1111") else '0';
FDRE_I1: FDRE
port map (
Q => buffer_Full, -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => buffer_full_early, -- [in std_logic]
R => Reset); -- [in std_logic]
FIFO_Full <= buffer_Full;
-- FIFO_Half_Full <= Addr(3);
-- FIFO_Half_Empty <= not Addr(3);
buffer_Empty <= '1' when (Addr = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(4) is not used anywhere
Used_MuxCY: if I < 3 generate
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
generic map (
INIT => x"0000")
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
end architecture IMP;
| bsd-3-clause | 3a01d26b335535516cd476c52552582a | 0.514797 | 3.954696 | false | false | false | false |
a4a881d4/zcpsm | src/example/Q7Led/vhd/ARM_wrapper.vhd | 1 | 4,477 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
--Date : Sun Mar 01 22:41:07 2015
--Host : dodo-PC running 64-bit Service Pack 1 (build 7601)
--Command : generate_target ARM_wrapper.bd
--Design : ARM_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ARM_wrapper is
port (
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end ARM_wrapper;
architecture STRUCTURE of ARM_wrapper is
component ARM is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component ARM;
begin
ARM_i: component ARM
port map (
BRAM_PORTA_addr(12 downto 0) => BRAM_PORTA_addr(12 downto 0),
BRAM_PORTA_clk => BRAM_PORTA_clk,
BRAM_PORTA_din(31 downto 0) => BRAM_PORTA_din(31 downto 0),
BRAM_PORTA_dout(31 downto 0) => BRAM_PORTA_dout(31 downto 0),
BRAM_PORTA_en => BRAM_PORTA_en,
BRAM_PORTA_rst => BRAM_PORTA_rst,
BRAM_PORTA_we(3 downto 0) => BRAM_PORTA_we(3 downto 0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| gpl-2.0 | aa8dc6c2ec524e86f5d9717e343f1f8e | 0.597052 | 3.081211 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xps_bram_if_cntlr.vhd | 2 | 34,698 | -------------------------------------------------------------------------------
-- $Id: xps_bram_if_cntlr.vhd,v 1.2.2.2 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xps_bram_if_cntlr.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xps_bram_if_cntlr.vhd
-- Version: v1.00a (Initial release support for PLBV46)
-- Description: This is the top-level design file for the XPS BRAM
-- Interface Controller supporting the IBM CoreConnect
-- PLB V4.6 specification. This module provides the
-- interface between the PLB and the actual FPGA BRAM
-- resources that are instantiated by the EDK tools.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 10-19-2006 -- V1_00_a initial version
-- ~~~~~~
-- - Incorporated use of plbv46_slave_single for use in non-burst
-- application and 32-bit only applications
-- - Incorporated PLBV46 Slave burst for single data beats wider than
-- 32-bits, cacheline support, and Fixed Length Burst support.
--
-- ^^^^^^
--
-- DET 2/27/2007 v1_00_a
-- ~~~~~~
-- - Revamped design to remove 2 clocks of latency. IPIFs replaced with
-- custom design.
-- - Point to Point Mode removes Address Decode function only. No latency
-- reduction realized.
--
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Various redesign changes for the Performance Mode HDL to improve
-- Fmax results in Spartan devices.
-- ^^^^^^
--
-- DET 6/5/2007 jm.10
-- ~~~~~~
-- - Changed default value of C_SPLB_SUPPORT_BURSTS from 0 to 1.
-- ^^^^^^
--
-- DET 8/25/2008 V1_00_b
-- ~~~~~~
-- - Updated to proc_common_v3_00_a library.
-- - Updated this core's library reference to V1_00_b.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 11/25/2008 v1_00_b
-- ~~~~~~
-- - Removed imbedded Changelog from file header.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
--
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
--
library Unisim;
use Unisim.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family.all;
use proc_common_v3_00_a.all;
library xps_bram_if_cntlr_v1_00_b;
use xps_bram_if_cntlr_v1_00_b.xbic_slave_attach_sngl;
use xps_bram_if_cntlr_v1_00_b.xbic_slave_attach_burst;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- Generics set by the User
-- C_BASEADDR
-- BRAM memory base address (width must match C_SPLB_AWIDTH)
-- C_HIGHADDR
-- BRAM memory high address (width must match C_SPLB_AWIDTH)
-- C_SPLB_NATIVE_DWIDTH
-- Desired Data Bit Width of the BRAM (32,64 or 128)
-- Generics auto-calculated/set by the EDK XPS tools
-- C_SPLB_AWIDTH
-- PLBV46 interface address width
-- C_SPLB_DWIDTH
-- PLBV46 interface data width
-- C_SPLB_NUM_MASTERS
-- number of PLB masters on the PLBV46 interconnect
-- C_SPLB_MID_WIDTH
-- log2(C_SPLB_NUM_MASTERS)
-- C_SPLB_SUPPORT_BURSTS
-- 0 = Resource optimized mode for Bursts and Cacheline transfers
-- 1 = Performance optimized mode for Bursts and Cacheline transfers
-- C_SPLB_P2P
-- Designates the interconnect topology of the attached
-- PLBV46 interface
-- 0 = Shared bus
-- 1 = Point to Point (no address decoding and low latency)
-- C_SPLB_SMALLEST_MASTER
-- Used to specify the data width of the
-- smallest master that could access this BRAM
-- interface controller (needed for ipif resource
-- optimization opportunity)
-- C_FAMILY
-- Indicates the target device architecture
-- Definition of Ports:
-- -- PLB input ports
-- SPLB_Clk -- PLB system clock
-- SPLB_Rst -- PLB system Reset
-- PLB_abort -- PLB abort bus request indicator
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper (extended) address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master indicator
-- PLB_abort -- PLB abort indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending request
-- PLB_rdPendReq -- PLB read pending request
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB request priority
-- PLB_TAttribute -- PLB Tranfer Attribute qualifier bus
-- -- Slave Reply ports (to PLB)
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus sizer
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave rearbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator (one bit per PLB mstr)
-- Sl_MWrMErr -- Slave write error indicator (one bit per PLB mstr)
-- Sl_MRdMErr -- Slave read error indicator (one bit per PLB mstr)
-- Sl_MIRQ -- Slave interrupt indicator (one bit per PLB mstr)
-- BRAM Block output ports (to BRAM Block)
-- BRAM_Rst -- BRAM Block reset control
-- BRAM_CLK -- BRAM Block clock
-- BRAM_EN -- BRAM Block enable
-- BRAM_WEN -- BRAM Block write enable
-- BRAM_Addr -- BRAM Block address
-- BRAM_Dout -- BRAM Block write data
--
-- BRAM Block input port (from BRAM Block)
-- BRAM_Din -- BRAM Block read data
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------
entity xps_bram_if_cntlr is
generic (
-- User configured Generics
--- Note: Base/High Addresses must be C_SPLB_AWIDTH bits wide
C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector := X"0000_0000";
C_SPLB_NATIVE_DWIDTH : Integer range 32 to 128 := 32;
-- Generics auto-calculated/set by the EDK XPS tools
C_SPLB_AWIDTH : integer range 32 to 36 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 2;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 1;
C_SPLB_SUPPORT_BURSTS : integer range 0 to 1 := 1;
C_SPLB_P2P : Integer range 0 to 1 := 0;
C_SPLB_SMALLEST_MASTER : Integer range 32 to 128 := 32;
C_FAMILY : String := "virtex5"
);
port (
-- System Port Declarations *****************************************
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
-- PLB Port Declarations ********************************************
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to
C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to
(C_SPLB_DWIDTH /8) - 1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to
C_SPLB_DWIDTH -1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
-- Slave Response Signals
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to
C_SPLB_DWIDTH -1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to
C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to
C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to
C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to
C_SPLB_NUM_MASTERS-1);
-- User BRAM Ports
BRAM_Rst : out std_logic;
BRAM_Clk : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to
(C_SPLB_NATIVE_DWIDTH/8)-1);
BRAM_Addr : out std_logic_vector(0 to
C_SPLB_AWIDTH-1);
BRAM_Din : in std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to
C_SPLB_NATIVE_DWIDTH-1)
);
-- fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of SPLB_Clk : signal is "10000";
attribute MAX_FANOUT of SPLB_Rst : signal is "10000";
-- PSFUtil attributes (for Auto_generation of MPD file)
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_BASEADDR : constant is "0x04000";
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SPECIAL : string;
attribute SPECIAL of xps_bram_if_cntlr : entity is "BRAM_CNTLR";
end xps_bram_if_cntlr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of xps_bram_if_cntlr is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant PLBV46_AWIDTH : integer := C_SPLB_AWIDTH;
Constant BASEADDR_SIZE : integer := C_BASEADDR'length;
Constant HIGHADDR_SIZE : integer := C_HIGHADDR'length;
constant ZERO_BADDR_PAD : std_logic_vector(0 to
(64-BASEADDR_SIZE)-1) :=
(others => '0');
constant ZERO_HADDR_PAD : std_logic_vector(0 to
(64-HIGHADDR_SIZE)-1) :=
(others => '0');
-- BRAM Constants
constant BRAM : integer := USER_00;
constant NUM_BRAM_CS : integer := 1;
constant NUM_BRAM_CE : integer := 1;
constant NUM_BRAM_BE : integer := C_SPLB_NATIVE_DWIDTH/8;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sig_bus2ip_reset : std_logic;
signal sig_bus2ip_clk : std_logic;
signal sig_bus2ip_cs : std_logic;
signal sig_bus2ip_wrce : std_logic_vector(0 to NUM_BRAM_CE-1);
signal sig_bus2ip_rdce : std_logic_vector(0 to NUM_BRAM_CE-1);
signal sig_bus2ip_addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal sig_bus2ip_be : std_logic_vector(0 to NUM_BRAM_BE-1);
signal sig_bus2ip_rnw : std_logic;
signal sig_bus2ip_wrreq : std_logic;
signal sig_bus2ip_rdreq : std_logic;
signal sig_bus2ip_data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal sig_ip2bus_rdack : std_logic;
signal sig_ip2bus_data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal sig_ip2bus_wrack : std_logic;
signal sig_bus2ip_burst : std_logic;
Signal sig_bram_wr_enable : std_logic_vector(0 to NUM_BRAM_BE-1);
Signal sig_bram_rd_enable : std_logic;
begin -- architecture IMP
----------------------------------------------------------------
-- Assign the BRAM backend interface ports --------------------
----------------------------------------------------------------
Sl_MIRQ <= (others => '0');
-- Connect BRAM output Ports
BRAM_Rst <= SPLB_Rst ;
BRAM_Clk <= SPLB_Clk ;
BRAM_EN <= sig_bus2ip_cs ;
BRAM_WEN <= sig_bram_wr_enable ;
BRAM_Addr <= sig_bus2ip_addr ;
BRAM_Dout <= sig_bus2ip_data ;
-- Connect BRAM input Data Port
sig_ip2bus_data <= BRAM_Din ;
------------------------------------------------------------
-- If Generate
--
-- Label: SINGLES_ONLY_SUPPORT
--
-- If Generate Description:
-- This IfGen instantiates a custom Slave Attachment which
-- has been optimized for size and single data beats. It
-- also requires the Native DWIDTH of the core to be 32-bits.
--
------------------------------------------------------------
SINGLES_ONLY_SUPPORT : if (C_SPLB_SUPPORT_BURSTS = 0 and
C_SPLB_NATIVE_DWIDTH = 32) generate
-- Local Constants
Constant STEER_ADDR_SIZE : integer := 5;
-- local signals
signal sig_bus2ip_wrreq_dly1 : std_logic;
signal sig_bus2ip_wrreq_dly2 : std_logic;
signal sig_bus2ip_rdreq_dly1 : std_logic;
signal sig_bus2ip_rdreq_dly2 : std_logic;
Signal sig_write_enable : std_logic;
------------------------------------------------------------
begin
sig_bram_rd_enable <= sig_bus2ip_cs;
sig_ip2bus_rdack <= sig_bus2ip_rdreq_dly1 and
not(sig_bus2ip_rdreq_dly2);
sig_ip2bus_wrack <= sig_bus2ip_wrreq and
not(sig_bus2ip_wrreq_dly1);
sig_write_enable <= sig_bus2ip_wrreq_dly1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_WR_REQ1
--
-- Process Description:
-- This process registers the Write Request signal.
--
-------------------------------------------------------------
REG_WR_REQ1 : process (SPLB_Clk)
begin
if (SPLB_Clk'event and SPLB_Clk = '1') then
if (SPLB_Rst = '1' or
sig_bus2ip_wrreq = '0' or
sig_bus2ip_wrreq_dly1 = '1') then
sig_bus2ip_wrreq_dly1 <= '0';
else
sig_bus2ip_wrreq_dly1 <= sig_bus2ip_wrreq;
end if;
end if;
end process REG_WR_REQ1;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GEN_WR_ENABLES
--
-- Process Description:
-- This process generates the BRAM write enable controls
-- based on the number of byte enables available.
--
-------------------------------------------------------------
GEN_WR_ENABLES : process (sig_bus2ip_be,
sig_write_enable)
begin
for be_index in 0 to NUM_BRAM_BE-1 loop
sig_bram_wr_enable(be_index) <= sig_bus2ip_be(be_index) and
sig_write_enable;
end loop;
end process GEN_WR_ENABLES;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RD_REQ1
--
-- Process Description:
-- This process registers the Read Request signal for
-- one high pulse only.
--
-------------------------------------------------------------
REG_RD_REQ : process (SPLB_Clk)
begin
if (SPLB_Clk'event and SPLB_Clk = '1') then
if (SPLB_Rst = '1' or
sig_bus2ip_rdreq = '0' or
sig_bus2ip_rdreq_dly1 = '1' or
sig_bus2ip_rdreq_dly2 = '1') then
sig_bus2ip_rdreq_dly1 <= '0';
else
sig_bus2ip_rdreq_dly1 <= sig_bus2ip_rdreq;
end if;
end if;
end process REG_RD_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RD_REQ2
--
-- Process Description:
-- This process samples and holds the delayed Read
-- Request signal when it goes high.
--
-------------------------------------------------------------
REG_RD_REQ2 : process (SPLB_Clk)
begin
if (SPLB_Clk'event and SPLB_Clk = '1') then
if (SPLB_Rst = '1' or
sig_bus2ip_rdreq = '0') then
sig_bus2ip_rdreq_dly2 <= '0';
else
sig_bus2ip_rdreq_dly2 <= sig_bus2ip_rdreq_dly1;
end if;
end if;
end process REG_RD_REQ2;
sig_bus2ip_burst <= '0';
sig_bus2ip_rnw <= '0';
I_SLAVE_SINGLE_ATTACH : entity xps_bram_if_cntlr_v1_00_b.xbic_slave_attach_sngl
generic map (
C_STEER_ADDR_SIZE => STEER_ADDR_SIZE,
C_ARD_ADDR_RANGE_ARRAY => (ZERO_BADDR_PAD & C_BASEADDR,
ZERO_HADDR_PAD & C_HIGHADDR),
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS ,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH ,
C_SPLB_P2P => C_SPLB_P2P ,
C_SPLB_AWIDTH => C_SPLB_AWIDTH ,
C_SPLB_DWIDTH => C_SPLB_DWIDTH ,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH ,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER
)
port map (
--System signals
Bus_Rst => SPLB_Rst ,
Bus_Clk => SPLB_Clk ,
-- PLB Bus signals
PLB_ABus => PLB_ABus ,
PLB_UABus => PLB_UABus ,
PLB_PAValid => PLB_PAValid ,
PLB_masterID => PLB_masterID ,
PLB_RNW => PLB_RNW ,
PLB_BE => PLB_BE ,
PLB_Msize => PLB_MSize ,
PLB_size => PLB_size ,
PLB_type => PLB_type ,
PLB_wrDBus => PLB_wrDBus ,
PLB_wrBurst => PLB_wrBurst ,
PLB_rdBurst => PLB_rdBurst ,
Sl_SSize => Sl_SSize ,
Sl_addrAck => Sl_addrAck ,
Sl_wait => Sl_wait ,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck ,
Sl_wrComp => Sl_wrComp ,
Sl_wrBTerm => Sl_wrBTerm ,
Sl_rdDBus => Sl_rdDBus ,
Sl_rdWdAddr => Sl_rdWdAddr ,
Sl_rdDAck => Sl_rdDAck ,
Sl_rdComp => Sl_rdComp ,
Sl_rdBTerm => Sl_rdBTerm ,
Sl_MBusy => Sl_MBusy ,
Sl_MRdErr => Sl_MRdErr ,
Sl_MWrErr => Sl_MWrErr ,
-- Controls to the IP/IPIF modules
Bus2Bram_CS => sig_bus2ip_cs ,
Bus2Bram_WrReq => sig_bus2ip_wrreq ,
Bus2Bram_RdReq => sig_bus2ip_rdreq ,
Bus2Bram_Addr => sig_bus2ip_addr ,
Bus2Bram_BE => sig_bus2ip_be ,
Bus2Bram_WrData => sig_bus2ip_data ,
-- Inputs from the BRAM interface logic
Bram2Bus_RdData => sig_ip2bus_data ,
Bram2Bus_WrAck => sig_ip2bus_wrack ,
Bram2Bus_RdAck => sig_ip2bus_rdack
);
end generate SINGLES_ONLY_SUPPORT;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_BURST_SUPPORT
--
-- If Generate Description:
-- This IfGen instantiates a PLBV46 Slave Attachment
-- which incorporates singles, fixed length bursts, and
-- cacheline transfers. It may also have a Native DWIDTH of
-- 32, 64, and 128 bits.
--
--
------------------------------------------------------------
INCLUDE_BURST_SUPPORT : if (C_SPLB_SUPPORT_BURSTS = 1 or
C_SPLB_NATIVE_DWIDTH > 32) generate
-- Local Constants
-- PLBV46 Slave Standard IPIF ARD Array overloads --------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_BADDR_PAD & C_BASEADDR , -- BRAM Base Address
ZERO_HADDR_PAD & C_HIGHADDR -- BRAM High Address
);
-- Cacheline read address mode
Constant CACHLINE_ADDR_MODE : integer := 0; -- Legacy mode
-- Selects the addressing mode to use for Cacheline Read
-- operations.
-- 0 = Legacy Read mode (target word first)
-- 1 = Realign target word address to Cacheline aligned and
-- then do a linear incrementing addressing from start
-- to end of the Cacheline (PCI Bridge enhancement).
Constant STEER_ADDR_SIZE : integer := 5;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GEN_WR_ENABLES
--
-- Process Description:
-- This process generates the BRAM write enable controls
-- based on the number of byte enables available.
--
-------------------------------------------------------------
GEN_WR_ENABLES : process (sig_bus2ip_be,
sig_bus2ip_wrreq)
begin
for be_index in 0 to NUM_BRAM_BE-1 loop
sig_bram_wr_enable(be_index) <= sig_bus2ip_be(be_index) and
sig_bus2ip_wrreq;
end loop;
end process GEN_WR_ENABLES;
-- Instantiate the Slave Burst Attachnebt using direct entity instantiation
I_SLAVE_BURST_ATTACH : entity xps_bram_if_cntlr_v1_00_b.xbic_slave_attach_burst
generic map (
--C_STEER_ADDR_SIZE => STEER_ADDR_SIZE,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_CACHLINE_ADDR_MODE => CACHLINE_ADDR_MODE,
C_FAMILY => C_FAMILY
)
port map (
-- System signals ------------------------------------------------
Bus_Rst => SPLB_Rst ,
Bus_Clk => SPLB_Clk ,
-- PLBV46 Slave input signals ------------------------------------
PLB_ABus => PLB_ABus ,
PLB_UABus => PLB_UABus ,
PLB_PAValid => PLB_PAValid ,
PLB_masterID => PLB_masterID ,
PLB_RNW => PLB_RNW ,
PLB_BE => PLB_BE ,
PLB_MSize => PLB_MSize ,
PLB_size => PLB_size ,
PLB_type => PLB_type ,
PLB_wrDBus => PLB_wrDBus ,
PLB_wrBurst => PLB_wrBurst ,
PLB_rdBurst => PLB_rdBurst ,
-- PLBV46 Slave reply signals
Sl_SSize => Sl_SSize ,
Sl_addrAck => Sl_addrAck ,
Sl_wait => Sl_wait ,
Sl_rearbitrate => Sl_rearbitrate ,
Sl_wrDAck => Sl_wrDAck ,
Sl_wrComp => Sl_wrComp ,
Sl_wrBTerm => Sl_wrBTerm ,
Sl_rdDBus => Sl_rdDBus ,
Sl_rdWdAddr => Sl_rdWdAddr ,
Sl_rdDAck => Sl_rdDAck ,
Sl_rdComp => Sl_rdComp ,
Sl_rdBTerm => Sl_rdBTerm ,
Sl_MBusy => Sl_MBusy ,
Sl_MWrErr => Sl_MWrErr ,
Sl_MRdErr => Sl_MRdErr ,
-- BRAM Interconnect port signals ---------------------------
-- Controls to the IP/IPIF modules
Bus2Bram_CS => sig_bus2ip_cs ,
Bus2Bram_WrReq => sig_bus2ip_wrreq ,
Bus2Bram_RdReq => sig_bus2ip_rdreq ,
Bus2Bram_Addr => sig_bus2ip_addr ,
Bus2Bram_BE => sig_bus2ip_be ,
Bus2Bram_WrData => sig_bus2ip_data ,
-- Inputs from the BRAM interface logic
Bram2Bus_RdData => sig_ip2bus_data ,
Bram2Bus_WrAck => '0', -- unused
Bram2Bus_RdAck => '0' -- unused
);
end generate INCLUDE_BURST_SUPPORT;
end implementation; | bsd-3-clause | fa9f9d1a857b4a687189b5a71037c9cd | 0.442648 | 4.495724 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_wr.vhd | 3 | 36,376 | -------------------------------------------------------------------------------
-- $Id: ipif_control_wr.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
--ipif_control_wr.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_wr.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Write Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-- ipif_control_wr.vhd
--
--
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 5, 2001 -- V1.00a
--
-- DET June 25, 2001 V1.00b
-- - eliminated redundant logic warnings during synthesis
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Sept. 4, 2001
-- - Optimization changes and clean up
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_wr is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 9;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 99;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 25 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates write burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_WrAck : In std_logic;
Vacancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostFull : In std_logic;
Full : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_wr_data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
Fifo_Reset : Out std_logic;
Fifo_WrReq : Out std_logic;
Fifo_burst_wr_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_wr ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_wr is
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset key value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to activate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
--signal mir_value : std_logic_vector(0 to 31);
Signal sw_reset_error : std_logic;
signal reg_vacancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostfull : std_logic;
Signal reg_full : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce1 : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_rdce3 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_wrce2 : std_logic;
Signal reg_wrce3 : std_logic;
Signal reg_wrreq : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_wr_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal reg_write_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_wr_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
--------------------- start architecture logic --------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_Retry <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_WrAck <= write_ack and write_req;
-- Connect the write acknowledge (drive only if a
-- request is present)
FIFO2Bus_RdAck <= read_ack and read_req;
-- Connect the read acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
Fifo_WrReq <= Bus2FIFO_WrCE3 and Bus_WrReq;
-- Write Request to FIFO read controller
Fifo_burst_wr_xfer <= burst_wr_xfer;
-- Burst detect signal to FIFO read controller
sig_fifo_wr_data <= Bus_DBus;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
for j in 0 to C_FIFO_WIDTH-1 loop
fifo_wr_data(j) <= sig_fifo_wr_data(C_IPIF_DBUS_WIDTH-
C_FIFO_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
fifo_wr_data <= sig_fifo_wr_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
fifo_wr_data <= (others => '0'); --default bus state
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
fifo_wr_data(C_FIFO_WIDTH-C_IPIF_DBUS_WIDTH+j)
<= sig_fifo_wr_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_rdce1 <= '0';
reg_rdce2 <= '0';
reg_rdce3 <= '0';
reg_wrce1 <= '0';
reg_wrce2 <= '0';
reg_wrce3 <= '0';
reg_rdreq <= '0';
reg_wrreq <= '0';
reg_read_req <= '0';
reg_write_req <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
reg_rdce1 <= Bus2FIFO_RdCE1;
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_rdce3 <= Bus2FIFO_RdCE3;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_wrce2 <= Bus2FIFO_WrCE2;
reg_wrce3 <= Bus2FIFO_WrCE3;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
reg_wrreq <= Bus_WrReq;
reg_write_req <= write_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
-------------------------------------------------------------------------------
-- Detect a Burst Write Condition (used for reading the FIFO Data)
-------------------------------------------------------------------------------
BURST_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
burst_wr_xfer <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_wrreq = '1' and Bus_WrReq = '1') Then
burst_wr_xfer <= '1';
Elsif (burst_wr_xfer = '1' and Bus_WrReq = '0') Then
burst_wr_xfer <= '0';
else
burst_wr_xfer <= '0';
End if;
else
null;
End if;
End process; -- BURST_DETECT
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_vacancy <= (others => '0');
reg_deadlock <= '0';
reg_almostfull <= '0';
reg_full <= '1';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during read
-- operation.
null;
else -- register new status every clock
reg_vacancy <= Vacancy ;
reg_deadlock <= Deadlock ;
reg_almostfull <= AlmostFull ;
reg_full <= Full ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
FIFO_Reset <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
FIFO_Reset <= '1';
sw_reset_error <= '0';
When "01" =>
FIFO_Reset <= '0';
sw_reset_error <= '1';
When others =>
FIFO_Reset <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
-------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- conversion to std_logic_vector required
-------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
-------------------------------------------------------------------------
-- If the IPIF read data bus width is less than or equal to the MIR value
-- size (32bits), then populate the LS MIR bits that will fit. Truncate
-- those that will not fit.
-------------------------------------------------------------------------
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to (C_IPIF_DBUS_WIDTH-1) loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
-------------------------------------------------------------------------
-- If the IPIF read data bus width is greater than the MIR value size
-- (32bits), then populate the MIR bits into the LSBits of the bus
-- and zero the remaining MSBits
-------------------------------------------------------------------------
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
-- data through the data write
rd_access_error <= '1'; -- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-- Synthesis for MIR occlusion ------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- If the IPIF DBUS is larger than 32 bits in width, place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- If the IPIF DBUS is less than or equal to 32 bits wide and is of sufficient
-- width to contain the complete status informatio, then.....
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1' ;
-- occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the two read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When others =>
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read the MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
rd_access_error <= '1'; -- data through the data write
-- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack or rd_access_error;
write_ack <= reg_wrce1 or -- used for reset port write
wr_access_error or -- used for error ack on invalid
-- write ops
Fifo_WrAck ; -- The FIFO accepted the write data
-------------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data write
-- cycle during a burst write. An error ack is generated only if a data
-- write is initiated at the same time as the FIFO is FUll.
-------------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1' ) Then
If (Bus2FIFO_WrCE3 = '1' and Fifo_WrAck = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_WrCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
-------------------------------------------------------------------------------
-- Generate the Error Acknowledge Reply to the Bus when
-- an attempted access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE3 = '1' and
Full = '1' and
fifo_errack_inhibit = '0') Then -- Initiating a fifo write during a
wr_access_error <= '1'; -- full condition, this is an error.
Elsif (Bus2FIFO_WrCE2 = '1') Then -- Attempting to write to the staus
-- register
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause | ebf1a25e5f5b7d036fcd42f91e56faeb | 0.394353 | 4.89451 | false | false | false | false |
iocoder/graduation | hardware/tlc_sim.vhdl | 1 | 6,791 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tlc_sim is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- VGA Connector
R0 : out STD_LOGIC;
R1 : out STD_LOGIC;
R2 : out STD_LOGIC;
G0 : out STD_LOGIC;
G1 : out STD_LOGIC;
G2 : out STD_LOGIC;
B0 : out STD_LOGIC;
B1 : out STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR0 : out STD_LOGIC;
ADDR1 : out STD_LOGIC;
ADDR2 : out STD_LOGIC;
ADDR3 : out STD_LOGIC;
ADDR4 : out STD_LOGIC;
ADDR5 : out STD_LOGIC;
ADDR6 : out STD_LOGIC;
ADDR7 : out STD_LOGIC;
ADDR8 : out STD_LOGIC;
ADDR9 : out STD_LOGIC;
ADDR10 : out STD_LOGIC;
ADDR11 : out STD_LOGIC;
ADDR12 : out STD_LOGIC;
ADDR13 : out STD_LOGIC;
ADDR14 : out STD_LOGIC;
ADDR15 : out STD_LOGIC;
ADDR16 : out STD_LOGIC;
ADDR17 : out STD_LOGIC;
ADDR18 : out STD_LOGIC;
ADDR19 : out STD_LOGIC;
ADDR20 : out STD_LOGIC;
ADDR21 : out STD_LOGIC;
ADDR22 : out STD_LOGIC;
ADDR23 : out STD_LOGIC;
DataIn0 : in STD_LOGIC;
DataIn1 : in STD_LOGIC;
DataIn2 : in STD_LOGIC;
DataIn3 : in STD_LOGIC;
DataIn4 : in STD_LOGIC;
DataIn5 : in STD_LOGIC;
DataIn6 : in STD_LOGIC;
DataIn7 : in STD_LOGIC;
DataIn8 : in STD_LOGIC;
DataIn9 : in STD_LOGIC;
DataIn10 : in STD_LOGIC;
DataIn11 : in STD_LOGIC;
DataIn12 : in STD_LOGIC;
DataIn13 : in STD_LOGIC;
DataIn14 : in STD_LOGIC;
DataIn15 : in STD_LOGIC;
DataOut0 : out STD_LOGIC;
DataOut1 : out STD_LOGIC;
DataOut2 : out STD_LOGIC;
DataOut3 : out STD_LOGIC;
DataOut4 : out STD_LOGIC;
DataOut5 : out STD_LOGIC;
DataOut6 : out STD_LOGIC;
DataOut7 : out STD_LOGIC;
DataOut8 : out STD_LOGIC;
DataOut9 : out STD_LOGIC;
DataOut10 : out STD_LOGIC;
DataOut11 : out STD_LOGIC;
DataOut12 : out STD_LOGIC;
DataOut13 : out STD_LOGIC;
DataOut14 : out STD_LOGIC;
DataOut15 : out STD_LOGIC;
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC
);
end entity;
architecture Structural of tlc_sim is
component TLC is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- LED:
LED : out STD_LOGIC_VECTOR ( 7 downto 0);
-- VGA Connector
R : out STD_LOGIC_VECTOR ( 2 downto 0);
G : out STD_LOGIC_VECTOR ( 2 downto 0);
B : out STD_LOGIC_VECTOR ( 1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC
);
end component;
signal LED : STD_LOGIC_VECTOR ( 7 downto 0);
signal R : STD_LOGIC_VECTOR ( 2 downto 0);
signal G : STD_LOGIC_VECTOR ( 2 downto 0);
signal B : STD_LOGIC_VECTOR ( 1 downto 0);
signal ADDR : STD_LOGIC_VECTOR (23 downto 0);
signal DATA : STD_LOGIC_VECTOR (15 downto 0);
signal DataIn : STD_LOGIC_VECTOR (15 downto 0);
signal DataOut : STD_LOGIC_VECTOR (15 downto 0);
signal myCLK : STD_LOGIC;
begin
-- array work around
R0 <= R(0);
R1 <= R(1);
R2 <= R(2);
G0 <= G(0);
G1 <= G(1);
G2 <= G(2);
B0 <= B(0);
B1 <= B(1);
ADDR0 <= ADDR( 0);
ADDR1 <= ADDR( 1);
ADDR2 <= ADDR( 2);
ADDR3 <= ADDR( 3);
ADDR4 <= ADDR( 4);
ADDR5 <= ADDR( 5);
ADDR6 <= ADDR( 6);
ADDR7 <= ADDR( 7);
ADDR8 <= ADDR( 8);
ADDR9 <= ADDR( 9);
ADDR10 <= ADDR(10);
ADDR11 <= ADDR(11);
ADDR12 <= ADDR(12);
ADDR13 <= ADDR(13);
ADDR14 <= ADDR(14);
ADDR15 <= ADDR(15);
ADDR16 <= ADDR(16);
ADDR17 <= ADDR(17);
ADDR18 <= ADDR(18);
ADDR19 <= ADDR(19);
ADDR20 <= ADDR(20);
ADDR21 <= ADDR(21);
ADDR22 <= ADDR(22);
ADDR23 <= ADDR(23);
DataIn( 0) <= DataIn0;
DataIn( 1) <= DataIn1;
DataIn( 2) <= DataIn2;
DataIn( 3) <= DataIn3;
DataIn( 4) <= DataIn4;
DataIn( 5) <= DataIn5;
DataIn( 6) <= DataIn6;
DataIn( 7) <= DataIn7;
DataIn( 8) <= DataIn8;
DataIn( 9) <= DataIn9;
DataIn(10) <= DataIn10;
DataIn(11) <= DataIn11;
DataIn(12) <= DataIn12;
DataIn(13) <= DataIn13;
DataIn(14) <= DataIn14;
DataIn(15) <= DataIn15;
DataOut0 <= DataOut( 0);
DataOut1 <= DataOut( 1);
DataOut2 <= DataOut( 2);
DataOut3 <= DataOut( 3);
DataOut4 <= DataOut( 4);
DataOut5 <= DataOut( 5);
DataOut6 <= DataOut( 6);
DataOut7 <= DataOut( 7);
DataOut8 <= DataOut( 8);
DataOut9 <= DataOut( 9);
DataOut10 <= DataOut(10);
DataOut11 <= DataOut(11);
DataOut12 <= DataOut(12);
DataOut13 <= DataOut(13);
DataOut14 <= DataOut(14);
DataOut15 <= DataOut(15);
-- memory data bus
DATA <= DataIn;
DataOut <= DATA;
U: TLC port map (myCLK, LED, R, G, B, HS, VS,
ADDR, DATA, OE, WE,
MT_ADV, MT_CLK, MT_UB, MT_LB, MT_CE, MT_CRE, MT_WAIT,
ST_STS, RP, ST_CE,
PS2CLK, PS2DATA);
process
begin
while true loop
myCLK <= '1';
wait for 10 ns;
myCLK <= '0';
wait for 10 ns;
end loop;
end process;
end architecture;
| gpl-3.0 | 48b58a7887c3f194b87a539fd4644f4a | 0.492711 | 3.086818 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_2.vhd | 2 | 16,783 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_2.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- retVal = hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 71af677e2df10d02ec44cf03bf8c64ae | 0.543109 | 3.813451 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_12.vhd | 2 | 16,784 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_12.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- retVal = hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
retVal_next <= intrfc2thrd_value;
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 3fed3c6d3764fb5b35ad0d910bf79ae0 | 0.543136 | 3.813679 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_lock_2.vhd | 2 | 20,566 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: mutex_lock_2.c
-- reg1 = i
-- reg2 = * mutex
-- reg4 = owner
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_mutex_lock( data->mutex );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread, NULL, data->function, (void *) data );
when STATE_5 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- for( i=0; i<1024; i++ ) hthread_yield();
when STATE_10 =>
-- set i to 0
reg1_next <= Z32;
next_state <= STATE_11;
when STATE_11 =>
case reg1 is
when x"00000400" => next_state <= STATE_13;
when others => next_state <= STATE_12;
end case;
when STATE_12 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- hthread_mutex_unlock( data->mutex );
when STATE_13 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_15 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- if ( data->owner == data->thread ) retVal = SUCCESS
-- else retVal = FAILURE
when STATE_19 =>
-- Load the value of data->owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
if ( intrfc2thrd_value = reg7 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | dec93f47663be98ade1c8255743fd4bb | 0.543178 | 3.728426 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_adder_bit.vhd | 3 | 10,202 | -------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder_bit.vhd
--
-- Description: Implements 1 bit of the pf_adder
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2001-09-25
-- - Added generic to allow selection of a registered output
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - CHanged the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common_v2_00_a library.
-- ^^^^^^
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean := true
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic; -- A operand
Bin : in std_logic; -- B operand
Add_sub_n : in std_logic; -- Function ('1' = add, '0' = A - B)
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_adder_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
signal lutout_AddSub : std_logic;
signal addsub_result : std_logic;
signal addsub_result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"0069"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lutout_AddSub,
--- xst wrk around I0 => Bin,
--- xst wrk around I1 => Ain,
--- xst wrk around I2 => Add_sub_n,
--- xst wrk around I3 => '0');
I_ALU_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"0069"
)
port map (
O => lutout_AddSub,
I0 => Bin,
I1 => Ain,
I2 => Add_sub_n,
I3 => '0');
MUXCY_I : MUXCY
port map (
DI => Ain,
CI => Carry_In,
S => lutout_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => lutout_AddSub,
CI => Carry_In,
O => addsub_result);
FDRE_I: FDRE
port map (
Q => addsub_result_Reg,
C => Clk,
CE => Clock_Enable,
D => addsub_result,
R => Rst
);
USE_REGISTERED_RESULT : if (C_REGISTERED_RESULT = true) generate
Result <= addsub_result_Reg; -- registered version
end generate USE_REGISTERED_RESULT;
USE_COMBINATIONAL_RESULT : if (C_REGISTERED_RESULT = false) generate
Result <= addsub_result; -- combinational version
end generate USE_COMBINATIONAL_RESULT;
end implementation;
| bsd-3-clause | bad2795cbfec5edbae3e790e5b945fb6 | 0.438345 | 4.738504 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_au.vhd | 1 | 17,905 | --------------------------------------------------------------------------------
-- Title : DMA adress unit
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_au.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module provides the adresses and byte enables for the
-- dma operation.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_au
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_dma_au.vhd,v $
-- Revision 1.3 2013/09/12 08:45:28 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.2 2012/08/27 12:57:18 MMiehling
-- removed dma_size_counter instance and implemented as common source code
-- adopted tga logic
--
-- Revision 1.1 2012/03/29 10:14:45 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:02:20 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:23 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:19:38 mmiehling
-- improved timing
-- fixed boundary errors
-- changed dma_size_cnt to lpm
--
-- Revision 1.3 2004/08/13 15:41:10 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:20 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:48 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY vme_dma_au IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_signals
adr_o : OUT std_logic_vector(31 DOWNTO 0); -- adress for wb-bus
sel_o : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for wb_bus
we_o : OUT std_logic; -- write/read
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
cyc_o_sram : OUT std_logic; -- chip select for sram
cyc_o_pci : OUT std_logic; -- chip select for pci
cyc_o_vme : OUT std_logic; -- chip select for vme
stb_o : IN std_logic; -- request signal for cyc switching
-- fifo
fifo_empty : in std_logic;
fifo_full : in std_logic;
-- vme_dma_mstr
sour_dest : IN std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : IN std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : IN std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : OUT std_logic; -- if all data from one bd was read and stored in the fifo
load_cnt : IN std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : OUT std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : out std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : out std_logic; -- if all data from one bd was read and stored in the fifo
clr_dma_act_bd : IN std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
dma_act_bd : OUT std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
dma_dest_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : IN std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : IN std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : IN std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : IN std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0) -- size of data package
);
END vme_dma_au;
ARCHITECTURE vme_dma_au_arch OF vme_dma_au IS
CONSTANT dma_size_cnt_val : std_logic_vector(15 DOWNTO 0):= x"0001";
SIGNAL dma_act_bd_int : std_logic_vector(7 DOWNTO 2);
SIGNAL blk_int : std_logic;
SIGNAL dma_size_int : std_logic_vector(15 DOWNTO 0);
SIGNAL dma_sour_adr_int : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_dest_adr_int : std_logic_vector(31 DOWNTO 2);
signal dma_sour_adr_blt : std_logic_vector(31 downto 2);
signal dma_dest_adr_blt : std_logic_vector(31 downto 2);
SIGNAL cyc_o_sram_int : std_logic;
SIGNAL cyc_o_pci_int : std_logic;
SIGNAL cyc_o_vme_int : std_logic;
SIGNAL adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL reached_size_int : std_logic;
SIGNAL almost_reached_size_int : std_logic;
SIGNAL boundary_blt : std_logic;
SIGNAL boundary_blt_d1 : std_logic;
SIGNAL boundary_mblt : std_logic;
SIGNAL almost_boundary_blt : std_logic;
SIGNAL almost_boundary_mblt : std_logic;
SIGNAL dma_size_en : std_logic;
signal tga_int : std_logic_vector(8 DOWNTO 0);
signal dma_vme_am_conv : std_logic_vector(1 DOWNTO 0);
signal trans_blt_src : std_logic;
signal trans_blt_dst : std_logic;
signal fifo_empty_d1 : std_logic;
signal fifo_full_d1 : std_logic;
signal boundary_blt_edge : std_logic;
signal fifo_empty_edge : std_logic;
signal fifo_full_edge : std_logic;
BEGIN
cyc_o_sram <= cyc_o_sram_int WHEN stb_o = '1' ELSE '0';
cyc_o_pci <= cyc_o_pci_int WHEN stb_o = '1' ELSE '0';
cyc_o_vme <= cyc_o_vme_int WHEN stb_o = '1' ELSE '0';
-- perform VME block transfer when
-- 1. block transfer configured and access to source selected and source address shall be incremented
-- 2. block transfer configured and access to destination selected and destination address shall be incremented
-- 3. else single transfer
blk_int <= '1' when blk_sgl = '0' and sour_dest = '0' and inc_sour = '0' else
'1' when blk_sgl = '0' and sour_dest = '1' and inc_dest = '0' else
'0';
dma_act_bd <= dma_act_bd_int;
reached_size_int <= '1' WHEN dma_size_int = dma_size ELSE '0';
almost_reached_size_int <= '1' WHEN (dma_size_int + 1) = dma_size ELSE '0';
adr_o_int(31 DOWNTO 2) <= x"000f_f9" & dma_act_bd_int WHEN get_bd = '1' ELSE -- switch iram adress [10:2] to adr_o
dma_sour_adr when (sour_dest = '1' and inc_sour = '1') else -- keep src address from the descriptor
dma_sour_adr_blt when (sour_dest = '1' and inc_sour = '0' and trans_blt_src = '1') else
dma_sour_adr_int when (sour_dest = '1' and inc_sour = '0') else -- switch source adress to adr_o & dma_access & swap
dma_dest_adr when (sour_dest = '0' and inc_dest = '1') else -- keep dst address from the descriptor
dma_dest_adr_blt when (sour_dest = '0' and inc_sour = '0' and trans_blt_dst = '1') else
dma_dest_adr_int ; -- switch destination adress to adr_o & dma_access & swap
adr_o_int(1 DOWNTO 0) <= "00";
boundary <= boundary_blt OR boundary_mblt;
almost_boundary <= almost_boundary_blt OR almost_boundary_mblt;
-- rising edge pulses
boundary_blt_edge <= boundary_blt and (not boundary_blt_d1);
fifo_empty_edge <= fifo_empty and (not fifo_empty_d1);
fifo_full_edge <= fifo_full and (not fifo_full_d1);
sel_o <= (OTHERS => '1'); -- always longword accessess
dma_vme_am_conv <= "10" when dma_vme_am(1 DOWNTO 0) = "01" else -- A32
"01" when dma_vme_am(1 DOWNTO 0) = "10" else -- A16
"00"; -- A24
-- (1:0) : 00=A24, 01=A32, 10=A16
-- (3:2) : 00=D16, 01=D32, 10=D64
-- (4) : if increment enabled the burst else single
-- (5) : swapped(1) or non swapped (0)
-- (6) : =0 always VME bus access (no register access)
-- (7) : =1 indicates access to vme_ctrl by DMA
-- (8) : 0= non-privileged 1= supervisory
tga_int <= dma_vme_am(4) & "10" & NOT dma_vme_am(0) & blk_int & dma_vme_am(3 DOWNTO 2) & dma_vme_am_conv;
-- A32D32 BLT transfer
trans_blt_src <= '1' when (dma_sour_device(1) = '1' and dma_vme_am(3 downto 2) = "01" and blk_int = '1') else
'0';
trans_blt_dst <= '1' when (dma_dest_device(1) = '1' and dma_vme_am(3 downto 2) = "01" and blk_int = '1') else
'0';
adr_o_proc : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
adr_o <= (OTHERS => '0');
dma_sour_adr_int <= (OTHERS => '0');
dma_dest_adr_int <= (OTHERS => '0');
dma_act_bd_int <= (OTHERS => '0');
cyc_o_sram_int <= '0';
cyc_o_pci_int <= '0';
cyc_o_vme_int <= '0';
we_o <= '0';
reached_size <= '0';
almost_reached_size <= '0';
tga_o <= (OTHERS => '0');
boundary_blt <= '0';
boundary_blt_d1 <= '0';
boundary_mblt <= '0';
almost_boundary_blt <= '0';
almost_boundary_mblt <= '0';
dma_sour_adr_blt <= (others=>'0');
dma_dest_adr_blt <= (others=>'0');
ELSIF clk'EVENT AND clk = '1' THEN
-- rule of vmebus: do not cross 256 byte boundaries (0x100)
IF dma_vme_am(3) = '0' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "000000" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "000000" AND sour_dest = '1')) THEN
boundary_blt <= '1';
ELSE
boundary_blt <= '0';
END IF;
IF dma_vme_am(3) = '0' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "111111" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "111111" AND sour_dest = '1')) THEN
almost_boundary_blt <= '1';
ELSE
almost_boundary_blt <= '0';
END IF;
-- for mblt-d64: do not cross 2k byte boundaries (0x800)
IF dma_vme_am(3) = '1' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(7 DOWNTO 2) = "000000" AND dma_dest_adr_int(10 DOWNTO 8) = "000" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(7 DOWNTO 2) = "000000" AND dma_sour_adr_int(10 DOWNTO 8) = "000" AND sour_dest = '1')) THEN
boundary_mblt <= '1';
ELSE
boundary_mblt <= '0';
END IF;
IF dma_vme_am(3) = '1' AND ((dma_dest_device(1) = '1' AND dma_dest_adr_int(10 DOWNTO 2) = "111111111" AND sour_dest = '0') OR
(dma_sour_device(1) = '1' AND dma_sour_adr_int(10 DOWNTO 2) = "111111111" AND sour_dest = '1')) THEN
almost_boundary_mblt <= '1';
ELSE
almost_boundary_mblt <= '0';
END IF;
IF inc_adr = '1' OR get_bd = '1' THEN
adr_o <= adr_o_int;
END IF;
IF load_cnt = '1' THEN
reached_size <= '0';
if dma_size = conv_std_logic_vector(0, 16) then -- if just one longword shall be transfered, indicate almost reached
almost_reached_size <= '1';
else
almost_reached_size <= '0';
end if;
ELSIF inc_adr = '1' AND sour_dest = '1' THEN
reached_size <= reached_size_int;
almost_reached_size <= almost_reached_size_int;
END IF;
IF get_bd = '1' THEN
cyc_o_sram_int <= '1';
cyc_o_pci_int <= '0';
cyc_o_vme_int <= '0';
we_o <= '0'; -- only reading from sram
tga_o <= (OTHERS => '0');
ELSIF sour_dest = '1' THEN -- SOURCE
cyc_o_sram_int <= dma_sour_device(0);
cyc_o_vme_int <= dma_sour_device(1);
cyc_o_pci_int <= dma_sour_device(2);
we_o <= '0'; -- read from source
if dma_sour_device(1) = '1' then -- if access to vme range, use tga for space selection
tga_o <= tga_int;
else -- if access to SRAM or PCI => no special tga setting
tga_o <= (OTHERS => '0');
end if;
ELSE -- DESTINATION
cyc_o_sram_int <= dma_dest_device(0);
cyc_o_vme_int <= dma_dest_device(1);
cyc_o_pci_int <= dma_dest_device(2);
we_o <= '1'; -- write to destination
if dma_dest_device(1) = '1' then -- if access to vme range, use tga for space selection
tga_o <= tga_int;
else -- if access to SRAM or PCI => no special tga setting
tga_o <= (OTHERS => '0');
end if;
END IF;
IF load_cnt = '1' THEN
dma_sour_adr_int <= dma_sour_adr;
ELSIF get_bd = '0' AND sour_dest = '1' AND inc_adr = '1' THEN
dma_sour_adr_int <= dma_sour_adr_int + 1;
END IF;
IF load_cnt = '1' THEN
dma_dest_adr_int <= dma_dest_adr;
ELSIF get_bd = '0' AND sour_dest = '0' AND inc_adr = '1' THEN
dma_dest_adr_int <= dma_dest_adr_int + 1;
END IF;
boundary_blt_d1 <= boundary_blt;
fifo_empty_d1 <= fifo_empty;
fifo_full_d1 <= fifo_full;
-- address regiters for BLT
if load_cnt = '1' then
dma_sour_adr_blt <= dma_sour_adr;
elsif sour_dest = '1' and (boundary_blt_edge = '1' or fifo_full_edge = '1') then
-- remember address value for new BLT transfer
dma_sour_adr_blt <= dma_sour_adr_int;
end if;
if load_cnt = '1' then
dma_dest_adr_blt <= dma_dest_adr;
elsif sour_dest = '0' and (boundary_blt_edge = '1' or fifo_empty_edge = '1') then
-- remember address value for new BLT transfer
dma_dest_adr_blt <= dma_dest_adr_int;
end if;
IF start_dma = '1' OR clr_dma_act_bd = '1' THEN
dma_act_bd_int <= (OTHERS => '0');
ELSIF get_bd = '1' AND inc_adr = '1' THEN
dma_act_bd_int <= dma_act_bd_int + 1;
END IF;
END IF;
END PROCESS adr_o_proc;
dma_size_en <= '1' WHEN sour_dest = '1' AND inc_adr = '1' ELSE '0';
size_cnt: PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
dma_size_int <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF load_cnt = '1' THEN
dma_size_int <= (OTHERS => '0');
ELSIF dma_size_en = '1' THEN
dma_size_int <= dma_size_int + 1;
END IF;
END IF;
END PROCESS size_cnt;
END vme_dma_au_arch;
| gpl-3.0 | 56d06145b892d17e96b666666670ea50 | 0.495895 | 3.709343 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/dma/zcpsm2dma.vhd | 1 | 4,262 | library ieee;
use ieee.std_logic_1164.all;
entity zcpsm2dma is
generic (
RAM_AWIDTH : natural
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
lastframe_flag : out std_logic;
start : out std_logic;
length : out std_logic_vector(15 downto 0);
start_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
start_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : out std_logic_vector(7 downto 0);
rstep : out std_logic_vector(7 downto 0);
busy : in std_logic
);
end entity;
architecture behave of zcpsm2dma is
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
constant PORT_DMA_START : std_logic_vector(3 downto 0) := X"0";
constant PORT_DMA_LENGTH_0 : std_logic_vector(3 downto 0) := X"1";
constant PORT_DMA_LENGTH_1 : std_logic_vector(3 downto 0) := X"2";
constant PORT_DMA_RADDR_0 : std_logic_vector(3 downto 0) := X"3";
constant PORT_DMA_RADDR_1 : std_logic_vector(3 downto 0) := X"4";
constant PORT_DMA_RADDR_2 : std_logic_vector(3 downto 0) := X"5";
constant PORT_DMA_RADDR_3 : std_logic_vector(3 downto 0) := X"6";
constant PORT_DMA_WADDR_0 : std_logic_vector(3 downto 0) := X"7";
constant PORT_DMA_WADDR_1 : std_logic_vector(3 downto 0) := X"8";
constant PORT_DMA_WADDR_2 : std_logic_vector(3 downto 0) := X"9";
constant PORT_DMA_WADDR_3 : std_logic_vector(3 downto 0) := X"A";
constant PORT_DMA_RSTEP : std_logic_vector(3 downto 0) := X"B";
constant PORT_DMA_WSTEP : std_logic_vector(3 downto 0) := X"C";
constant PORT_DMA_BUSY : std_logic_vector(3 downto 0) := X"D";
constant PORT_RX_LAST_FRAME : std_logic_vector(3 downto 0) := X"E";
signal zcpsm_we : std_logic;
signal zcpsm_re : std_logic;
signal zcpsm_addr : std_logic_vector(3 downto 0);
signal start_en : std_logic;
begin
zcpsm_we <= zcpsm_ce and zcpsm_write_strobe;
zcpsm_re <= zcpsm_ce and zcpsm_read_strobe;
zcpsm_addr <= zcpsm_port_id(3 downto 0);
zcpsm_in_port <= "0000000" & busy when zcpsm_ce = '1' and zcpsm_addr = PORT_DMA_BUSY else (others => 'Z');
WriteIO : process(zcpsm_clk, reset)
begin
if reset = '1' then
wstep <= X"01";
rstep <= X"01";
length <= (others => '0');
start_raddr <= (others => '0');
start_waddr <= (others => '0');
elsif rising_edge(zcpsm_clk) then
if zcpsm_we = '1' then
case zcpsm_addr is
when PORT_DMA_LENGTH_0 => length(7 downto 0) <= zcpsm_out_port;
when PORT_DMA_LENGTH_1 => length(15 downto 8) <= zcpsm_out_port;
when PORT_DMA_RADDR_0 => start_raddr(7 downto 0) <= zcpsm_out_port;
when PORT_DMA_RADDR_1 => start_raddr(15 downto 8) <= zcpsm_out_port;
when PORT_DMA_RADDR_2 => start_raddr(23 downto 16) <= zcpsm_out_port;
when PORT_DMA_RADDR_3 => start_raddr(31 downto 24) <= zcpsm_out_port;
when PORT_DMA_WADDR_0 => start_waddr(7 downto 0) <= zcpsm_out_port;
when PORT_DMA_WADDR_1 => start_waddr(15 downto 8) <= zcpsm_out_port;
when PORT_DMA_WADDR_2 => start_waddr(23 downto 16) <= zcpsm_out_port;
when PORT_DMA_WADDR_3 => start_waddr(31 downto 24) <= zcpsm_out_port;
when PORT_DMA_RSTEP => rstep <= zcpsm_out_port;
when PORT_DMA_WSTEP => wstep <= zcpsm_out_port;
when others => null;
end case;
end if;
end if;
end process;
u_start : asyncwrite
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => start_en,
trigger => '1',
sync_wren => start,
over => open,
flag => open
);
start_en <= '1' when zcpsm_we = '1' and zcpsm_addr = PORT_DMA_START else '0';
lastframe_flag <= '1' when zcpsm_we = '1' and zcpsm_addr = PORT_RX_LAST_FRAME else '0';
end behave;
| gpl-2.0 | 4d398ff63df21d73351bd7bcc445a6f8 | 0.622947 | 2.581466 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_counter.vhd | 3 | 9,250 | -------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_v20_v1_10_d.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
| bsd-3-clause | 470433bc8fe38f6b37afff28ca416ca7 | 0.405081 | 5.029908 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_thread_manager_smp_v1_00_a/hdl/vhdl/plb_thread_manager_smp.vhd | 2 | 24,408 | ------------------------------------------------------------------------------
-- plb_thread_manager_smp.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager_smp.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 15:01:53 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_thread_manager_smp_v1_00_a;
use plb_thread_manager_smp_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_thread_manager_smp is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_NUM_CPUS : integer := 2;
C_RESET_TIMEOUT : natural := 4096;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
-- current_thread for CPU 0 = tm2sch_cpu_thread_id(0 to 7)
-- current_thread for CPU 1 = tm2sch_cpu_thread_id(8 to 15)
-- current_thread for CPU N = tm2sch_cpu_thread_id(8*(N-1) to 8*N-1)
tm2sch_cpu_thread_id : out std_logic_vector(0 to (8 * C_NUM_CPUS) - 1);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
end entity plb_thread_manager_smp;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_thread_manager_smp is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_thread_manager_smp_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_NUM_CPUS => C_NUM_CPUS,
C_RESET_TIMEOUT => C_RESET_TIMEOUT,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause | 1a423d03aa8b86ced69c8a6adddb6c3e | 0.456531 | 4.296427 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmRom.vhd | 1 | 2,577 | ---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmRom
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity zcpsmRom is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port(
reset : in std_logic;
clk : in std_logic;
port_ce : out std_logic_vector(15 downto 0);
port_id : out std_logic_vector(3 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end zcpsmRom;
--}} End of automatically maintained section
architecture behavior of zcpsmRom is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component zcpsmProgRom
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 )
);
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id_i : std_logic_vector(7 downto 0);
begin
port_id <= port_id_i( 3 downto 0 );
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id_i,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rom : zcpsmProgRom
generic map(
AWIDTH => 10,
PROG => PROG
)
port map(
clk => clk,
addr => address( AWIDTH-1 downto 0 ),
dout => instruction
);
u_decode : zcpsmDecode
port map(
port_id_H => port_id_i( 7 downto 4 ),
ce => port_ce
);
end behavior;
| gpl-2.0 | 9f0e0fbaf56920c6b374476eacfbfca5 | 0.549864 | 3.010514 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_destroy_3.vhd | 2 | 15,509 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- condattr_destroy_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * cond = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_condattr_init( condattr );
when STATE_2 =>
-- Push condattr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_condattr_destroy( condattr );
when STATE_4 =>
-- Push the argument to hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 462e1214cd92555ffc011214e2eb9dc2 | 0.541557 | 3.844571 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutexattr_destroy_1.vhd | 2 | 15,927 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutexattr_destroy_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutexattr_init( mutexattr );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_mutexattr_destroy( mutexattr );
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutexattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_mutexattr_init( mutexattr );
when STATE_6 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
when STATE_8 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | c795c7af1f9afd76663f2f074e184998 | 0.544233 | 3.829526 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/or_gate.vhd | 3 | 10,171 | -------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.02e
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-----------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
-- C_USE_LUT_OR -- Implement OR function in LUTs or MUXCY
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity opb_v20_v1_10_d.or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp; | bsd-3-clause | f67c27da183c691fc0592f2338ff20f9 | 0.41343 | 4.990677 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_unlock_1.vhd | 2 | 16,349 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_unlock_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- if( _mutex_owner( mutex->num ) != hthread_self() )
when STATE_6 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
reg1_next <= intrfc2thrd_value;
-- Call hthread_self();
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
next_state <= WAIT_STATE;
when STATE_9 =>
if ( intrfc2thrd_value = reg1 ) then
retVal_next <= x"00000001";
else
retVal_next <= Z32;
end if;
next_state <= STATE_10;
when STATE_10 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | c0380808b444190469e1ae2422ab00ff | 0.54462 | 3.793271 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_counter.vhd | 2 | 9,218 | -------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v3_00_a.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
| bsd-3-clause | 3b46cb5b4ec0022aaeacbc69b62d09c1 | 0.404101 | 5.109756 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/tx_put_data.vhd | 1 | 18,302 | --------------------------------------------------------------------------------
-- Title : tx_put_data
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_put_data.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- data handling module for tx path, controlled by tx_ctrl.vhd;
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- * tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_put_data is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end entity tx_put_data;
-- ****************************************************************************
architecture tx_put_data_arch of tx_put_data is
-- internal signals: ----------------------------------------------------------
signal aligned_int : std_logic;
signal data_in_q : std_logic_vector(63 downto 0);
signal data_q : std_logic_vector(63 downto 0);
signal data_qq : std_logic_vector(63 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal lower_addr_int : std_logic_vector(6 downto 0);
signal first_DW_int : std_logic_vector(3 downto 0);
signal last_DW_int : std_logic_vector(3 downto 0);
signal wr_rd_int : std_logic; -- =0: wr, =1: rd
signal mem_io_int : std_logic; -- =0: mem, =1: I/O
signal io_write_int : std_logic;
-------------------------------------------------------------------------------
begin
io_write <= io_write_int;
data_path : process(rst, clk)
begin
if(rst = '1') then
-- ports:
tx_st_data0 <= (others => '0');
data_length <= (others => '0');
aligned <= '0';
wr_rd <= '0';
posted <= '0';
byte_count <= (others => '0');
orig_addr <= (others => '0');
-- signals:
aligned_int <= '0';
data_in_q <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
req_id_int <= (others => '0');
tag_id_int <= (others => '0');
lower_addr_int <= (others => '0');
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
wr_rd_int <= '0';
mem_io_int <= '0';
io_write_int <= '0';
else
if(clk'event and clk = '1') then
-- capture data length from appropriate FIFO packet
if(get_header = '1' and c_wrrd = '0') then
data_length <= tx_c_head_out(9 downto 0);
elsif(get_header = '1' and c_wrrd = '1') then
data_length <= tx_wr_head_out(9 downto 0);
end if;
-- store alignment information for both completion and write/read transmissions
if(get_header = '1' and c_wrrd = '0') then
case tx_c_head_out(34) is
when '0' => -- check bit 2 of address for alignment
aligned_int <= '1' ;
aligned <= '1' ;
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
elsif(get_header = '1' and c_wrrd = '1') then
case tx_wr_head_out(34) is
when '0' =>
aligned_int <= '1';
aligned <= '1';
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
end if;
-- capture information if transmission is write or read
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(31) = '1') then
wr_rd <= '0';
wr_rd_int <= '0';
else
wr_rd <= '1';
wr_rd_int <= '1';
end if;
----------------------------------------------------------------------------------------
-- wr_rd is not reset if c_wrrd = 0 and if previous transfer is read it's stuck at '1'
-- which causes errors during transfer
-- thus added elsif
----------------------------------------------------------------------------------------
elsif get_header = '1' and c_wrrd = '0' then
wr_rd <= '0';
wr_rd_int <= '0';
end if;
-- define if transfer is posted or not
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(30) = '1') then -- posted
posted <= '1';
else -- non-posted
posted <= '0';
end if;
end if;
-- define wether transfer is of type memory or I/O
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(29) = '1') then
mem_io_int <= '0'; -- memory
else
mem_io_int <= '1'; -- I/O
end if;
end if;
-- store information on first/last byte enables
if(get_header = '1' and c_wrrd = '1') then
first_DW_int <= tx_wr_head_out(17 downto 14); -- first DW
last_DW_int <= tx_wr_head_out(13 downto 10); -- last DW
end if;
-- register header packet
if(get_header = '1' and c_wrrd = '0') then
data_in_q <= tx_c_head_out;
end if;
-- store requester ID
if(get_next_header = '1' and c_wrrd = '0') then
req_id_int <= tx_c_head_out(15 downto 0);
end if;
-- store tag ID
if(get_header = '1' and c_wrrd = '0') then
tag_id_int <= tx_c_head_out(25 downto 18);
end if;
-- store byte count
if(get_next_header = '1' and c_wrrd = '0') then
byte_count <= tx_c_head_out(27 downto 16);
end if;
-- store I/O write flag
if(get_next_header = '1' and c_wrrd = '0') then
io_write_int <= tx_c_head_out(28);
elsif c_wrrd = '1' then
io_write_int <= '0';
end if;
-- store original transfer address
if(get_header = '1' and c_wrrd = '0') then
orig_addr <= tx_c_head_out(63 downto 32);
elsif(get_header = '1' and c_wrrd = '1') then
orig_addr <= tx_wr_head_out(63 downto 32);
end if;
-- calculate lower address for completions
if(get_header = '1' and c_wrrd = '0') then
if(tx_c_head_out(17 downto 14) = "0000" or tx_c_head_out(14) = '1') then
lower_addr_int <= tx_c_head_out(38 downto 34) & "00"; -- calculate from first DW
elsif(tx_c_head_out(15 downto 14) = "10") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "01";
elsif(tx_c_head_out(16 downto 14) = "100") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "10";
elsif(tx_c_head_out(17 downto 14) = "1000") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "11";
-- coverage off
else
-- synthesis translate_off
report "wrong encoding of tx_c_head_out(17 downto 14)" severity error;
-- synthesis translate_on
-- coverage on
end if;
end if;
-- assebmle packets for transmission
-- c_wrrd controls whether completion or write/read transfer is needed
-- R := reserved according to PCIe base specification, thus set to '0' here
if(make_header = '1' and c_wrrd = '0') then
if(abort_compl = '1' or io_write_int = '1') then
data_qq(31 downto 24) <= "00001010"; -- fmt & type -> completion without data
else
data_qq(31 downto 24) <= "01001010"; -- fmt & type -> completion with data
end if;
data_qq(23) <= '0'; -- R
data_qq(22 downto 20) <= data_in_q(28 downto 26); -- TC
data_qq(19) <= '0'; -- R
data_qq(18) <= data_in_q(31); -- Attr(2)
data_qq(17 downto 14) <= '0' & '0' & '0' & '0'; -- R & TH & TD & EP
data_qq(13 downto 12) <= data_in_q(30 downto 29); -- Attr(1:0)
data_qq(11 downto 10) <= "00"; -- AT
data_qq(9 downto 0) <= data_in_q(9 downto 0); -- length
data_qq(63 downto 48) <= completer_id;
if(abort_compl = '1') then
data_qq(47 downto 45) <= "100"; -- completion status = completer abort
else
data_qq(47 downto 45) <= "000"; -- completion status = successful completion
end if;
data_qq(44) <= '0'; -- bcm
data_qq(43 downto 32) <= tx_c_head_out(27 downto 16); -- byte count
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 16) <= req_id_int; -- requester ID
data_q(15 downto 8) <= tag_id_int; -- tag ID
data_q(7 downto 0) <= '0' & lower_addr_int; -- R & lower address
elsif(make_header = '1' and c_wrrd = '1') then
if(mem_io_int = '0' and wr_rd_int = '0') then -- memory write
data_qq(31 downto 24) <= "01000000";
elsif(mem_io_int = '1' and wr_rd_int = '0') then -- I/O write
data_qq(31 downto 24) <= "01000010";
elsif(mem_io_int = '0' and wr_rd_int = '1') then -- memory read
data_qq(31 downto 24) <= "00000000";
else -- I/O read
data_qq(31 downto 24) <= "00000010";
end if;
-- R & TC(2:0) & R & Attr(2) & R & TH & TD & EP & Attr(1:0) & AT
data_qq(23 downto 10) <= '0' & "000" & '0' & '0' & '0' & '0' & '0' & '0' & "00" & "00";
data_qq(9 downto 0) <= send_len; -- length
data_qq(63 downto 48) <= req_id;
data_qq(47 downto 40) <= tag_nbr;
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 0) <= send_addr; -- address
-- do payload loop, that means: one request was transmitted from Wishbone but the length is too big
-- thus split up in order to obey PCIe max_payload_size or max_read_size, which means
-- to send several packets with the same header info except address and length
-- CAUTION:
-- if the last packet to be sent has length =1 then last_DW must be =0
-- and the original setting for last_DW must be inserted for first_DW
if(payload_loop = '0') then
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "01") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "10") then
if send_len = "0000000001" then
data_qq(39 downto 36) <= x"0";
data_qq(35 downto 32) <= last_DW_int;
else
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= x"F";
end if;
elsif(payload_loop = '1' and first_last_full = "11") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= x"F";
end if;
end if;
-- manage registration of data retrieved from FIFO's
if(data_enable = '1' and aligned_int = '0' and c_wrrd = '0') then
data_q(31 downto 0) <= tx_c_data_out(63 downto 32);
data_qq <= tx_c_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '0' and c_wrrd = '1') then
data_q(31 downto 0) <= tx_wr_data_out(63 downto 32);
data_qq <= tx_wr_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '0') then
data_q <= tx_c_data_out;
data_qq <= data_q;
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '1') then
data_q <= tx_wr_data_out;
data_qq <= data_q;
end if;
-- output registered data to Avalon ST data bus
if(data_enable = '1') then
tx_st_data0 <= data_qq;
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture tx_put_data_arch;
| gpl-3.0 | 7ccb21188ab196c3d322042ae565fd0c | 0.41001 | 4.183314 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_ethtx.vhd | 1 | 11,498 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g_ethtx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RD_CYCLE : natural := 1;
RD_DELAY : natural := 1;
RAM_AWIDTH : natural := 32
);
port (
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
-- ram_raddr : out std_logic_vector(23 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- ram_rdata : in std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- local time --
localtime : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch_ethtx of g_ethtx is
component g_ethtx_output
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_rdata : in std_logic_vector(31 downto 0);
dma_start : out std_logic;
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
-- local time --
localtime: in std_logic_vector(31 downto 0)
);
end component;
component Tx_queue
generic(
HEAD_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RAM_TYPE : STRING := "DIS_RAM");
port(
clk : in std_logic;
reset : in std_logic;
queue_empty : out std_logic;
head_raddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component disdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
A : in std_logic_vector((Awidth-1) downto 0);
CLK : in std_logic;
D : in std_logic_vector((Dwidth-1) downto 0);
WE : in std_logic;
DPRA : in std_logic_vector((Awidth-1) downto 0);
DPO : out std_logic_vector((Dwidth-1) downto 0);
QDPO : out std_logic_vector((Dwidth-1) downto 0));
end component;
component dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((DWIDTH-1) downto 0));
end component;
signal tx_queue_empty : std_logic;
signal tx_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal tx_head_rdata : std_logic_vector(7 downto 0);
signal tx_head_rd_block : std_logic;
signal db_queue_empty : std_logic;
signal db_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal db_head_rdata : std_logic_vector(7 downto 0);
signal db_head_rd_block : std_logic;
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(31 downto 0);
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(31 downto 0);
signal dma_length_byte : std_logic_vector(15 downto 0);
signal dma_length_dword : std_logic_vector(15 downto 0);
-- signal dma_start_raddr : std_logic_vector(23 downto 0);
signal dma_start_raddr_word : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_raddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
-- signal dma_raddr : std_logic_vector(23 downto 0);
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_rdata : std_logic_vector(7 downto 0);
signal dma_rdata : std_logic_vector(31 downto 0);
signal dma_wdata_dword : std_logic_vector(31 downto 0);
signal dma_waddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wren_dword : std_logic;
signal flag : std_logic;
signal buff_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal buff_wdata_reg : std_logic_vector(31 downto 0);
signal dma_wren_reg : std_logic;
-- signal dma_wren : std_logic;
-- signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_wdata : std_logic_vector(7 downto 0);
signal dma_ena : std_logic;
signal buff_wr_diff : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
begin
u_output : g_ethtx_output
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen,
tx_queue_empty => tx_queue_empty,
tx_head_raddr => tx_head_raddr,
tx_head_rdata => tx_head_rdata,
tx_head_rd_block => tx_head_rd_block,
db_queue_empty => db_queue_empty,
db_head_raddr => db_head_raddr,
db_head_rdata => db_head_rdata,
db_head_rd_block => db_head_rd_block,
buff_raddr => buff_raddr,
buff_rdata => buff_rdata,
dma_start => dma_start,
dma_start_addr => dma_start_raddr_word,
dma_length => dma_length_byte,
dma_step => dma_rstep,
-- local time
localtime => localtime
);
u_db_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 0,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => db_queue_empty,
head_raddr => db_head_raddr,
head_rdata => db_head_rdata,
head_rd_block => db_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_tx_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => tx_queue_empty,
head_raddr => tx_head_raddr,
head_rdata => tx_head_rdata,
head_rd_block => tx_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_tx_buffer : disdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 32
)
port map(
A => buff_waddr(BUFF_AWIDTH - 1 downto 0),
CLK => clk,
D => buff_wdata,
WE => buff_wren,
DPRA => buff_raddr(BUFF_AWIDTH - 1 downto 0),
DPO => buff_rdata,
QDPO => open
);
u_dma : dma_ctrl
generic map(
DWIDTH => 32,
RD_CYCLE => RD_CYCLE,
RD_DELAY => RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => dma_ena,
start => dma_start,
length => dma_length_dword,
start_waddr => (others => '0'),
start_raddr => dma_start_raddr_dword,
wstep => X"01",
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren_dword,
waddr => dma_waddr_dword,
wdata => dma_wdata_dword
);
----------
dma_length_dword <= "00" & dma_length_byte(15 downto 2);
dma_start_raddr_dword <= '0' & dma_start_raddr_word(RAM_AWIDTH-1 downto 1);
--- process(reset, clk)
---- begin
-- if reset = '1' then
--- wren_byte <= '0';
-- elsif rising_edge(clk) then
-- if dma_wren_byte = '1' then
-- wren_byte <= dma_wren_byte;
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'0';
-- buff_wdata <= dma_wdata_byte(7 downto 0);
-- elsif flag = '1' then
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'1';
-- buff_wdata <= dma_wdata_byte(15 downto 8);
-- end if;
-- end if;
-- end process;
process(reset, clk)
begin
if reset = '1' then
buff_waddr_reg <= (others => '0');
buff_wdata_reg <= (others => '0');
dma_wren_reg <= '0';
elsif rising_edge(clk) then
if dma_wren_dword = '1' then
buff_waddr_reg <= dma_waddr_dword;
buff_wdata_reg <= dma_wdata_dword;
end if;
dma_wren_reg <= dma_wren_dword;
end if;
end process;
-- buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'0' when dma_wren_reg = '1' else
-- buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'1' ;
--
-- buff_wdata <= buff_wdata_reg(7 downto 0) when dma_wren_reg = '1' else
-- buff_wdata_reg(15 downto 8);
buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 1 downto 0);
buff_wdata <= buff_wdata_reg;
process(reset, clk)
begin
if reset = '1' then
flag <= '0';
elsif rising_edge(clk) then
-- if wren_byte = '1' then
flag <= dma_wren_reg;
-- end if;
end if;
end process;
buff_wren <= flag or dma_wren_reg;
ram_raddr <= dma_raddr;
dma_rdata <= ram_rdata;
-- buff_wren <= dma_wren;
-- buff_waddr <= dma_waddr(BUFF_AWIDTH - 1 downto 0);
-- buff_wdata <= dma_wdata;
buff_wr_diff <= buff_waddr - buff_raddr;
p_dma_ena : process(clk, reset)
begin
if reset = '1' then
dma_ena <= '1';
elsif rising_edge(clk) then
if buff_wr_diff >= 2 ** BUFF_AWIDTH - RD_CYCLE - RD_DELAY - 4 then
dma_ena <= '0';
elsif buff_wr_diff <= RD_CYCLE + RD_DELAY + 2 then
dma_ena <= '1';
end if;
end if;
end process;
end arch_ethtx;
| gpl-2.0 | 9cedb2b572d5c8afa10e865745dcd8c2 | 0.614803 | 2.668988 | false | false | false | false |
iocoder/graduation | hardware/vga/clkgen.vhd | 1 | 3,555 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clkgen is
Port (CLK : in STD_LOGIC;
CLK_56MHz : out STD_LOGIC;
CLK_50MHz : out STD_LOGIC;
CLK_28MHz : out STD_LOGIC;
CLK_25MHz : out STD_LOGIC;
CLK_12MHz : out STD_LOGIC);
end clkgen;
architecture Behavioral of clkgen is
component DCM
generic (CLKFX_MULTIPLY : integer := 27;
CLKFX_DIVIDE : integer := 24);
port (CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector(7 downto 0));
end component;
component BUFG
port (I : in std_logic;
O : out std_logic);
end component;
signal RST : STD_LOGIC := '0';
signal GND : STD_LOGIC := '0';
signal CLKFX : STD_LOGIC := '0';
signal oCLK_56MHz : STD_LOGIC := '0';
signal oCLK_50MHz : STD_LOGIC := '0';
signal oCLK_28MHz : STD_LOGIC := '0';
signal oCLK_25MHz : STD_LOGIC := '0';
signal oCLK_12MHz : STD_LOGIC := '0';
signal bCLK_12MHz : STD_LOGIC := '0';
signal HALF : STD_LOGIC := '0';
attribute clock_signal : string;
attribute clock_signal of oCLK_50MHz : signal is "yes";
attribute clock_signal of oCLK_25MHz : signal is "yes";
attribute clock_signal of oCLK_12MHz : signal is "yes";
attribute clock_signal of oCLK_56MHz : signal is "yes";
attribute clock_signal of oCLK_28MHz : signal is "yes";
signal reset : integer := 2;
begin
-- generate 50MHz clock
oCLK_50MHz <= CLK;
-- generate 25MHz clock
process(oCLK_50MHz)
begin
if (oCLK_50MHz = '1' and oCLK_50MHz'event ) then
oCLK_25MHz <= NOT oCLK_25MHz;
end if;
end process;
-- generate 12MHz clock
process(oCLK_25MHz)
begin
if (oCLK_25MHz = '1' and oCLK_25MHz'event ) then
oCLK_12MHz <= NOT oCLK_12MHz;
end if;
end process;
buf12: BUFG port map (oCLK_12MHz, bCLK_12MHz);
-- generate 56MHz clock
U0: DCM port map (CLKIN => oCLK_50MHz,
CLKFB => GND,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => GND,
CLKFX => CLKFX);
U1: BUFG port map (CLKFX, oCLK_56MHz);
-- generate 28MHz clock
process(oCLK_56MHz)
begin
if (oCLK_56MHz = '1' and oCLK_56MHz'event ) then
oCLK_28MHz <= NOT oCLK_28MHz;
end if;
end process;
-- connect generated clock frequencies to outputs
CLK_56MHz <= oCLK_56MHz;
CLK_50MHz <= oCLK_50MHz;
CLK_28MHz <= oCLK_28MHz;
CLK_25MHz <= oCLK_25MHz;
CLK_12MHz <= bCLK_12MHz;
end Behavioral;
| gpl-3.0 | ae06ddc1ac7729becbca10c971fb52a2 | 0.52602 | 3.609137 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_vector_v1_00_a/hdl/vhdl/hw_acc_vector.vhd | 2 | 8,997 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_vector is
port
(
--chipscope_icon_control : in std_logic_vector(35 downto 0);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_vector;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_vector is
component vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
component chipscope_ila
PORT (
CONTROL : in STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TRIG6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TRIG7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
TRIG8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
TRIG9 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG10 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG11 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG12 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG13 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG14 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG15 : IN STD_LOGIC_VECTOR(0 TO 0));
end component;
component chipscope_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal sBRAM_A_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_en : std_logic_vector(0 to 0) ;
signal sBRAM_A_wEN : std_logic_vector(0 to (32/8) -1);
signal sBRAM_B_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_en : std_logic_vector(0 to 0) ;
signal sBRAM_B_wEN : std_logic_vector(0 to (32/8) -1);
signal sBRAM_C_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_en : std_logic_vector(0 to 0) ;
signal sBRAM_C_wEN : std_logic_vector(0 to (32/8) -1);
signal sFSL0_S_Read : std_logic_vector(0 to 0);
signal sFSL0_S_Data : std_logic_vector(0 to 31);
signal sFSL0_S_Exists : std_logic_vector(0 to 0);
------------------------------------------------------
signal sFSL0_M_Write : std_logic_vector(0 to 0);
signal sFSL0_M_Data : std_logic_vector(0 to 31);
signal sFSL0_M_Full : std_logic_vector(0 to 0);
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
sBRAM_A_dIN <= BRAM_A_din;
BRAM_A_addr <= sBRAM_A_addr;
BRAM_A_dOUT <= sBRAM_A_dout;
BRAM_A_en <= sBRAM_A_en(0);
BRAM_A_wEN <= sBRAM_A_wen;
sBRAM_B_dIN <= BRAM_B_din ;
BRAM_B_addr <= sBRAM_B_addr ;
BRAM_B_dOUT <= sBRAM_B_dout ;
BRAM_B_en <= sBRAM_B_en(0) ;
BRAM_B_wEN <= sBRAM_B_wen ;
sBRAM_C_dIN <= BRAM_C_din ;
BRAM_C_addr <= sBRAM_C_addr ;
BRAM_C_dOUT <= sBRAM_C_dout ;
BRAM_C_en <= sBRAM_C_en(0) ;
BRAM_C_wEN <= sBRAM_C_wen ;
FSL0_S_Read<= sFSL0_S_Read(0);
sFSL0_S_Data<= FSL0_S_data;
sFSL0_S_Exists(0) <= FSL0_S_exists;
------------------------------------------------------
FSL0_M_Write <= sFSL0_M_Write(0);
FSL0_M_Data <= sFSL0_M_data;
sFSL0_M_Full(0) <= FSL0_M_full;
--icon_uut : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
-- ila_uut : chipscope_ila
-- port map (
-- CONTROL => chipscope_icon_control,
-- CLK => clk,
-- TRIG0 => sBRAM_C_addr,
-- TRIG1 => sBRAM_C_din,
-- TRIG2 => sBRAM_C_dout,
-- TRIG3 => sFSL0_M_Data,
-- TRIG4 => sFSL0_S_Data,
-- TRIG5 => X"0000" ,
-- TRIG6 => X"00" ,
-- TRIG7 => X"0",
-- TRIG8 => sBRAM_c_wen,
-- TRIG9 => sBRAM_C_en(0 to 0),
-- TRIG10 => sFSL0_S_Exists(0 to 0),
-- TRIG11 => sFSL0_S_Read(0 to 0),
-- TRIG12 => sFSL0_M_Write(0 to 0),
-- TRIG13 => sFSL0_M_Write(0 to 0),
-- TRIG14 => sFSL0_M_Write(0 to 0),
-- TRIG15 => sFSL0_M_Write(0 to 0));
uut : vector_chan
port map (
Vector_A_addr0 => sBRAM_A_addr,
Vector_A_dIN0 => sBRAM_A_dout,
Vector_A_dOUT0 => sBRAM_A_din,
Vector_A_rENA0 => sBRAM_A_en(0),
Vector_A_wENA0 => sBRAM_A_wen,
Vector_B_addr0 => sBRAM_B_addr,
Vector_B_dIN0 => sBRAM_B_dout,
Vector_B_dOUT0 => sBRAM_B_din,
Vector_B_rENA0 => sBRAM_B_en(0),
Vector_B_wENA0 => sBRAM_B_wen,
Vector_C_addr0 => sBRAM_C_addr,
Vector_C_dIN0 => sBRAM_C_dout,
Vector_C_dOUT0 => sBRAM_C_din,
Vector_C_rENA0 => sBRAM_C_en(0),
Vector_C_wENA0 => sBRAM_C_wen,
chan1_channelDataIn => sFSL0_M_Data,
chan1_channelDataOut => sFSL0_S_Data,
chan1_exists => sFSL0_S_Exists(0),
chan1_full => sFSL0_M_Full(0),
chan1_channelRead => sFSL0_S_Read(0),
chan1_channelWrite => sFSL0_M_Write(0),
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | 283d215fa1ae1f6d8941d6a36b8a0498 | 0.573747 | 2.696134 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_lock_3.vhd | 2 | 15,473 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_lock_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- retVal = hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= STATE_5;
-- hthread_mutex_unlock( mutex );
when STATE_5 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 9b802153a7bab1f8984283cde33d6152 | 0.539585 | 3.832797 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/plb_thread_manager.vhd | 9 | 24,206 | ------------------------------------------------------------------------------
-- plb_thread_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 15:01:53 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_thread_manager_v1_00_a;
use plb_thread_manager_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_thread_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_RESET_TIMEOUT : natural := 4096
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_thread_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_thread_manager is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_thread_manager_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_RESET_TIMEOUT => C_RESET_TIMEOUT
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause | 2596f7877d5f04854b01f2e225ee63bb | 0.456003 | 4.336439 | false | false | false | false |
jevinskie/aes-over-pcie | source/experiment/cntr.vhd | 1 | 684 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntr is
port (
clk : in std_logic;
clr : in std_logic;
count : out unsigned(3 downto 0);
top : out std_logic
);
end cntr;
architecture behav of cntr is
signal cnt, next_cnt : unsigned(3 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
cnt <= next_cnt;
end if;
end process;
process(cnt, clr)
begin
if (clr='1') then
next_cnt <= (others => '0');
else
next_cnt <= cnt + "1";
end if;
end process;
count <= cnt;
top <= '1' when cnt = x"f" else '0';
end behav;
| bsd-3-clause | 400e5af17c78b0c0e8f947b5fc914e56 | 0.53655 | 3.320388 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_key_scheduler.vhd | 1 | 2,389 | -- File name: tb_key_scheduler.vhd
-- Created: 2009-04-06
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 2.0 Revamped Test Bench with external test vectors!
use work.aes.all;
use work.aes_textio.all;
use work.numeric_std_textio.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_key_scheduler is
generic (
clk_per : time := 4 ns
);
end entity tb_key_scheduler;
architecture test of tb_key_scheduler is
signal clk : std_logic := '0';
signal nrst : std_logic := '1';
signal round : round_type;
signal key_data : byte;
signal key_load : std_logic;
signal key_index : g_index;
signal round_key : key_type;
signal go : std_logic := '0';
signal done : std_logic;
-- clock only runs when stop isnt asserted
signal stop : std_logic := '1';
begin
dut : entity work.key_scheduler(behavioral) port map (
clk => clk, nrst => nrst, round => round,
round_key => round_key, key_data => key_data,
key_load => key_load, key_index => key_index,
go => go, done => done
);
clk <= not clk and not stop after clk_per/2;
process
file data : text open read_mode is "test_vectors/tb_key_scheduler.dat";
variable sample : line;
variable gold_encryption_key : key_type;
variable gold_round_key : key_type;
begin
stop <= '0';
nrst <= '0';
wait for clk_per;
nrst <= '1';
wait for clk_per;
-- leda DCVHDL_165 off
while not endfile(data) loop
readline(data, sample);
hread(sample, gold_encryption_key);
key_load <= '1';
for i in g_index loop
key_data <= gold_encryption_key(i mod 4, i / 4);
key_index <= i;
wait for clk_per;
end loop;
key_load <= '0';
wait for clk_per;
for i in 0 to 10 loop
go <= '1';
round <= i;
wait for clk_per;
go <= '0';
wait until done = '1';
wait for 2*clk_per;
hread(sample, gold_round_key);
assert gold_round_key = round_key;
end loop;
end loop;
-- leda DCVHDL_165 on
stop <= '1';
wait;
end process;
end architecture test;
| bsd-3-clause | 68a8eba0d5dc86687ec5d4d23107b5a5 | 0.545416 | 3.513235 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_init_2.vhd | 2 | 16,069 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_2.c
-- arg = * data
-- reg1 = * mutex
-- reg2 = * mutex_attr
-- The return value should be the mutexattr->num set by either the
-- software main thread, or the bfl in case of simulation.
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the value of mutex
thrd2intrfc_address <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Read the value of mutex_attr
thrd2intrfc_address <= arg + 4;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_mutex_init( data->mutex, data->mutex_attr );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- Push data->mutex_attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = data->mutex->num;
when STATE_6 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | c10304557bc80018c2c0f3ad3a1c129d | 0.543407 | 3.825952 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/my_core_wrapper.vhd | 3 | 10,380 | -------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_scheduler_tb_v1_00_a;
use plb_scheduler_tb_v1_00_a.all;
entity my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component plb_scheduler_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : integer;
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer;
C_SPLB_NATIVE_DWIDTH : integer;
C_SPLB_P2P : integer;
C_SPLB_SUPPORT_BURSTS : integer;
C_SPLB_SMALLEST_MASTER : integer;
C_SPLB_CLK_PERIOD_PS : integer;
C_INCLUDE_DPHASE_TIMER : integer;
C_FAMILY : string;
C_MPLB_AWIDTH : integer;
C_MPLB_DWIDTH : integer;
C_MPLB_NATIVE_DWIDTH : integer;
C_MPLB_P2P : integer;
C_MPLB_SMALLEST_SLAVE : integer;
C_MPLB_CLK_PERIOD_PS : integer
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to (31));
PLB_UABus : in std_logic_vector(0 to (31));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to (1));
PLB_rdPendPri : in std_logic_vector(0 to (1));
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_TAttribute : in std_logic_vector(0 to (15));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8-1));
M_MSize : out std_logic_vector(0 to (1));
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_TAttribute : out std_logic_vector(0 to (15));
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to (31));
M_ABus : out std_logic_vector(0 to (31));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_MPLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : plb_scheduler_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_SMALLEST_MASTER => 32,
C_SPLB_CLK_PERIOD_PS => 10000,
C_INCLUDE_DPHASE_TIMER => 0,
C_FAMILY => "virtex5",
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 128,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_P2P => 0,
C_MPLB_SMALLEST_SLAVE => 32,
C_MPLB_CLK_PERIOD_PS => 10000
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
| bsd-3-clause | 5db00ce65cf5d9cfc8234b57e7eed9b0 | 0.582755 | 3.174312 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE_READ/mux_out.vhd | 1 | 1,516 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:44 11/12/2015
-- Design Name:
-- Module Name: mux_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_out is
port( mux_in: in std_logic_vector(15 downto 0); -- data read from hard drive
mux_enable: in std_logic_vector (2 downto 0);
mux_out: out std_logic_vector(3 downto 0) -- data to cpu
);
end mux_out;
architecture Behavioral of mux_out is
begin
process(mux_in, mux_enable)
begin
case mux_enable is
when "001" => mux_out <= mux_in (15 downto 12);
when "010" => mux_out <= mux_in (11 downto 8); --when Re_ld "0010";
when "011" => mux_out <= mux_in (7 downto 4); --when Re_ld "0011";
when "100" => mux_out <= mux_in (3 downto 0); --when Re_ld "0100";
when others => mux_out <= "ZZZZ";
end case;
end process;
end Behavioral;
| unlicense | 79d7b04ac3f5b9698b50a6b8f80060e7 | 0.5719 | 3.525581 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_be_reset_gen.vhd | 2 | 10,315 | -------------------------------------------------------------------------------
-- $Id: xbic_be_reset_gen.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_be_reset_gen - entity / architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_be_reset_gen.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Author: GAB
--
-- History:
--
-- DET Feb-5-07
-- ~~~~~~
-- -- Special version for the XPS BRAM IF Cntlr that is adapted
-- from plbv46_slave_burst_V1_00_a library
-- ^^^^^^
--
-- DET 3/6/2007 Reduced latency revision
-- ~~~~~~
-- - Added missing 64-bit case for when C_SMALLEST = 32 and C_NATIVE_DWIDTH=128.
-- this cause bus2ip_be to be driven incorrectly for address offets 0x4,
-- 0x5, 0x6,and 0x7.
-- ^^^^^^
--
-- DET 5/24/2007 Jm
-- ~~~~~~
-- - Changed the design to output active low BE reset mask.
-- - Modifed output Mask width to be the full width of the BE bus.
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity xbic_be_reset_gen is
generic (
C_NATIVE_DWIDTH : integer := 32;
C_SMALLEST : integer := 32
);
port(
Addr : in std_logic_vector(0 to 1);
MSize : in std_logic_vector(0 to 1);
BE_Sngl_Mask : out std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1)
);
end entity xbic_be_reset_gen;
architecture implementation of xbic_be_reset_gen is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal reset_be_extended : std_logic_vector(0 to (C_NATIVE_DWIDTH/8) - 1);
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
BE_Sngl_Mask <= not(reset_be_extended);
GEN_FOR_SAME : if C_NATIVE_DWIDTH <= C_SMALLEST generate
reset_be_extended <= (others => '0');
end generate GEN_FOR_SAME;
---------------------
-- 64 Bit Support --
---------------------
GEN_BE_64_32: if C_NATIVE_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(1); --a29
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "00001111";
when others => null;
end case;
when '1' =>
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "11110000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_BE_128_32: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr; -- 24 25 26 27 | 28 29 30 31
reset_be_extended <= (others => '0');
case addr_bits is
when "00" => --0
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "0000111111111111";
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "01" => --4
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111000011111111";
when "01" => -- 64-Bit Master -- GAB 12/22/06
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when "10" => --8
case MSize is
when "00" => -- 32-Bit Master
reset_be_extended <= "1111111100001111";
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when "11" => --C
case MSize is
when "00" => --32-Bit Master
reset_be_extended <= "1111111111110000";
when "01" => --64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_32;
GEN_BE_128_64: if C_NATIVE_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,MSize)
begin
addr_bits <= Addr(0);
reset_be_extended <= (others => '0');
case addr_bits is
when '0' =>
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "0000000011111111";
when others => null;
end case;
when '1' => --8
case MSize is
when "01" => -- 64-Bit Master
reset_be_extended <= "1111111100000000";
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_BE_128_64;
end implementation; -- (architecture)
| bsd-3-clause | 55ede4361951b837e56ff9d0438f8794 | 0.464566 | 4.564159 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_occ_counter.vhd | 3 | 10,830 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity opb_v20_v1_10_d.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity opb_v20_v1_10_d.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| bsd-3-clause | a45f59ef64cb1ecb92237962188bf305 | 0.437488 | 4.563843 | false | false | false | false |
jevinskie/aes-over-pcie | source/aes_top.vhd | 1 | 5,560 | -- File name: aes_top.vhd
-- Created: 2009-04-04
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES top level
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aes_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte;
got_key : in std_logic;
got_pt : in std_logic;
send_ct : in std_logic;
aes_done : out std_logic;
tx_data : out byte
);
end entity aes_top;
architecture structural of aes_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal num_shifts : index;
signal filtered : slice;
signal round_num : round_type;
signal round_key : key_type;
signal sub_bytes_out : byte;
signal shift_rows_out : row;
signal mix_columns_out : col;
signal add_round_key_out : byte;
signal filtered_key : byte;
signal start_key : std_logic;
signal key_done : std_logic;
signal ks_sbox_lookup : byte;
signal key_load : std_logic;
signal ks_sbox_return : byte;
begin
state_b : entity work.state(dataflow) port map (
clk => clk, state_d => state_d, state_q => state_q
);
state_filter_in_b : entity work.state_filter_in(behavioral) port map (
s => state_q, subblock => subblock, i => i, d_out => filtered,
filtered_key => filtered_key, round_key => round_key
);
state_filter_out_b : entity work.state_filter_out(mux) port map (
current_state => state_q, sub_bytes_out => sub_bytes_out,
shift_rows_out => shift_rows_out, mix_columns_out => mix_columns_out,
add_round_key_out => add_round_key_out, load_out => rx_data,
subblock => subblock, i => i, next_state => state_d
);
sub_bytes_b : entity work.sbox(dataflow) port map (
clk => clk, a => filtered(0), b => sub_bytes_out
);
num_shifts <= i mod 4;
shift_rows_b : entity work.shift_rows(dataflow) port map (
data_in => filtered, num_shifts => num_shifts,
data_out => shift_rows_out
);
mix_columns_b : entity work.mix_columns(behavioral) port map (
d_in => filtered, d_out => mix_columns_out
);
add_round_key_b : entity work.add_round_key(dataflow) port map (
data_in => filtered(0), key_in => filtered_key,
data_out => add_round_key_out
);
aes_rcu_b : entity work.aes_rcu(behavioral) port map (
clk => clk, nrst => nrst, p => i, subblock => subblock,
current_round => round_num, start_key => start_key,
key_done => key_done, key_load => key_load,
got_key => got_key, got_pt => got_pt, aes_done => aes_done,
send_ct => send_ct
);
key_scheduler_b : entity work.key_scheduler(behavioral) port map (
clk => clk, nrst => nrst, round => round_num,
round_key => round_key, go => start_key, done => key_done,
key_data => rx_data, key_index => i, key_load => key_load
);
tx_data <= filtered(0);
end architecture structural;
architecture structural_p of aes_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal round_num : round_type;
signal round_key : key_type;
signal sub_bytes_out : state_type;
signal shift_rows_out : state_type;
signal mix_columns_out : state_type;
signal add_round_key_out : state_type;
signal start_key : std_logic;
signal key_done : std_logic;
signal ks_sbox_lookup : byte;
signal key_load : std_logic;
signal ks_sbox_return : byte;
begin
state_b : entity work.state(dataflow) port map (
clk => clk, state_d => state_d, state_q => state_q
);
state_filter_out_p_b : entity work.state_filter_out_p(mux) port map (
current_state => state_q, sub_bytes_out => sub_bytes_out,
shift_rows_out => shift_rows_out, mix_columns_out => mix_columns_out,
add_round_key_out => add_round_key_out, load_out => rx_data,
subblock => subblock, i => i, next_state => state_d
);
sub_bytes_p_b : entity work.sub_bytes_p(structural) port map (
d_in => state_q, d_out => sub_bytes_out
);
shift_rows_p_b : entity work.shift_rows_p(behavioral) port map (
d_in => state_q, d_out => shift_rows_out
);
mix_columns_p_b : entity work.mix_columns_p(behavioral) port map (
d_in => state_q, d_out => mix_columns_out
);
add_round_key_p_b : entity work.add_round_key_p(dataflow) port map (
data_in => state_q, key_in => round_key,
data_out => add_round_key_out
);
aes_rcu_b : entity work.aes_rcu(behavioral_p) port map (
clk => clk, nrst => nrst, p => i, subblock => subblock,
current_round => round_num, start_key => start_key,
key_done => key_done, key_load => key_load,
got_key => got_key, got_pt => got_pt, aes_done => aes_done,
send_ct => send_ct
);
key_scheduler_p_b : entity work.key_scheduler(behavioral_p) port map (
clk => clk, nrst => nrst, round => round_num,
round_key => round_key, go => start_key, done => key_done,
key_data => rx_data, key_index => i, key_load => key_load
);
tx_data <= state_q(i mod 4, i / 4);
end architecture structural_p;
| bsd-3-clause | 3a234a9221ae68cbfe9c24d78265229e | 0.577878 | 3.243874 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/kind_fsm.vhd | 11 | 6,373 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity kind_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end kind_fsm;
architecture behavioral of kind_fsm is
-- A type for the states in the kind fsm
type kind_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the kind register fsm
signal kind_cs : kind_state;
signal kind_ns : kind_state;
-- Alias the kind input and output bits
alias kidata : std_logic_vector(0 to 1) is datain(C_DWIDTH-2 to C_DWIDTH-1);
alias kodata : std_logic_vector(0 to 1) is data(C_DWIDTH-2 to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
kind_update : process (clk,rst,sysrst,kind_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
kind_cs <= IDLE;
else
kind_cs <= kind_ns;
end if;
end if;
end process kind_update;
kind_controller : process (kind_cs,start,mutex,miowner,micount,mikind,milast,minext,rnw,datain) is
begin
kind_ns <= kind_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case kind_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
mowea <= '0';
moena <= '1';
kind_ns <= READ;
end if;
when READ =>
kind_ns <= DONE;
when DONE =>
if( rnw = '0' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mokind <= kidata;
mocount <= micount;
monext <= minext;
molast <= milast;
finish <= '1';
kind_ns <= IDLE;
else
finish <= '1';
kodata <= mikind;
kind_ns <= IDLE;
end if;
end case;
end process kind_controller;
end behavioral;
| bsd-3-clause | ab8a84462c7567c8a904f2b6b9a389b4 | 0.517182 | 4.187254 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hvm_control_interface_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 11,414 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Apr 16 16:10:38 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
go : out std_logic;
my_rst : out std_logic;
mode : out std_logic_vector(0 to 1);
done : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 3);
signal slv_reg_read_select : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 3);
slv_reg_read_select <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
-- slv_reg3 <= (others => '0');
else
case slv_reg_write_select is
when "1000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0001" =>
-- for byte_index in 0 to (C_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
INCOMING_PROC : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg3 <= (others => '0');
else
slv_reg3 <= x"0000000" & "000" & done;
end if;
end if;
end process INCOMING_PROC;
go <= slv_reg0(31);
mode <= slv_reg1(30 to 31);
my_rst <= slv_reg2(31);
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_select is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
| bsd-3-clause | 6ef7084e173243f1a94d983ca9d2a821 | 0.468285 | 4.155078 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_ethrx_input.vhd | 1 | 22,602 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Eth_TestSig_Cfg.all;
entity g_ethrx_input is
generic(
HEAD_AWIDTH : natural := 5; -- ½ÓÊÕ¶ÓÁеØÖ·¿í¶È 2^5 = 32 ×Ö½Ú
BUFF_AWIDTH : natural := 16 -- BUFF16λµØÖ·Ïß
);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic; -- FPGAʱÖÓ
reset : in std_logic;
rxclk : in std_logic; -- GMIIÊä³öʱÖÓ
rxd : in std_logic_vector(7 downto 0); -- ²¢¿ÚÊäÈëÊý¾Ý£¬8bitΪµ¥Î»£¨byte£©
rxdv : in std_logic; -- ÔÚRXDV='1'µÄÇé¿öϼì²âµ½"5..5D"£¬±íʾһ¸öÒÔÌ«°üµÄ¿ªÊ¼
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0); --ÿһ¸ö°ü´Ó0¿ªÊ¼µÝÔö¼ÆÊý
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic; -- ָʾCRC½á¹û£¬'1'±íʾÕýÈ·£¬'0'±íʾ²»ÕýÈ·
buff_wren : out std_logic;
buff_waddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_wdata : out std_logic_vector(31 downto 0) -- ÒÔÌ«°üÊý¾Ý°´×Ö½Úд³ö£¬Ð´µØÖ·´ÓÉÏ´ÎдµØÖ·µÄĩβµÝÔö£¬°üº¬ÒÔÌ«°üÍ·
);
end g_ethrx_input;
architecture arch_ethrx_input of g_ethrx_input is
component fifo_async_almost_full
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
almost_full : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async_almost_full use entity WORK.fifo_async_almost_full(fast_read);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
-- component crcrom
-- port(
-- addr : in std_logic_vector(3 downto 0);
-- dout : out std_logic_vector(31 downto 0));
-- end component;
component crc8_blkrom
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
constant INFO_LENGTH : natural := 4;
constant HEAD_LENGTH : natural := 2 ** HEAD_AWIDTH - INFO_LENGTH;
signal rxdv_buf : std_logic;
signal rxd_buf : std_logic_vector(7 downto 0);
-- signal d_ext : std_logic_vector(8 downto 0);
-- signal rxdv_int : std_logic;
-- signal rxd_int : std_logic_vector(7 downto 0);
-- signal d_int : std_logic_vector(8 downto 0);
signal ce : std_logic;
-- signal rd_ena : std_logic;
-- signal empty : std_logic;
signal RxFIFO_clr : std_logic;
signal RxFIFO_wea : std_logic;
signal RxFIFO_dia : std_logic_vector(31 downto 0);
signal RxFIFO_rdb : std_logic;
signal RxFIFO_dob : std_logic_vector(31 downto 0);
signal RxFIFO_empty : std_logic;
signal RxFIFO_not_empty : std_logic;
signal RxFIFO_clr_int : std_logic;
signal rx_state : std_logic_vector(1 downto 0);
signal rx_state_d1 : std_logic_vector(1 downto 0);
signal rx_state_int : std_logic_vector(1 downto 0);
signal rx_state_int_d1 : std_logic_vector(1 downto 0);
signal byte_cnt : std_logic_vector(11 downto 0);
signal byte_cnt_int : std_logic_vector(11 downto 0);
signal byte_cnt_int_d1 : std_logic_vector(11 downto 0);
signal rx_end_ext : std_logic;
signal rx_end_int : std_logic;
signal rxd_buf_d1 : std_logic_vector(7 downto 0);
signal rxd_buf_d2 : std_logic_vector(7 downto 0);
signal rxd_buf_d3 : std_logic_vector(7 downto 0);
signal rxd_buf_d4 : std_logic_vector(7 downto 0);
signal dword_data_ext : std_logic_vector(31 downto 0);
signal dword_data_int : std_logic_vector(31 downto 0);
signal dword_data_buf : std_logic_vector(23 downto 0);
signal byte_data_int : std_logic_vector(7 downto 0);
signal buff_wren_buf : std_logic;
signal buff_waddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(7 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crc_reg_d1 : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(7 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal crc_flag : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_ena : std_logic;
signal start_addr : std_logic_vector(15 downto 0);
signal length : std_logic_vector(15 downto 0);
signal head_wren_buf : std_logic;
signal head_waddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wr_block_buf: std_logic;
signal rxclk_temp : std_logic;
signal localtime_locked_reg: std_logic;
begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if info_ena = '1' then
-- test_crc(0) <= crc_flag;
-- test_crc(1) <= crc_reg(2);
-- test_crc(2) <= crc_reg(4);
-- test_crc(3) <= crc_reg(8);
-- end if;
-- end if;
-- end process;
p_mii_din : process(rxclk, reset) -- MII->ETH-RX ÊäÈëÊý¾Ý»º´æ
begin
if reset = '1' then
rxdv_buf <= '0';
rxd_buf <= (others=>'0');
elsif rising_edge(rxclk) then
-- if falling_edge(rxclk) then
rxdv_buf <= rxdv;
rxd_buf <= rxd;
end if;
end process;
-- rxclk_temp <= not rxclk;
-- u_din_sync : fifo_async
-- generic map(
-- DEPTH => 4,
-- AWIDTH => 2,
-- DWIDTH => 9,
-- RAM_TYPE => "DIS_RAM")
-- port map(
-- reset => reset,
-- clr => '0',
-- clka => rxclk,
---- clka => rxclk_temp,
-- wea => '1',
-- dia => d_ext,
-- clkb => clk,
-- rdb => rd_ena,
-- dob => d_int,
-- empty => empty,
-- full => open,
-- dn => open
-- );
--
-- d_ext <= rxdv_buf & rxd_buf;
-- rxdv_int <= d_int(8);
-- rxd_int <= d_int(7 downto 0);
-- rd_ena <= not empty;
--
-- p_ce : process(clk)
-- begin
-- if rising_edge(clk) then
-- ce <= rd_ena;
-- end if;
-- end process;
------------------------------------------------------------------------------
-- p_state_machine : process(clk, reset)
-- begin
-- if reset = '1' then
-- rx_state <= (others => '0');
-- rx_state_d1 <= (others => '0');
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- case rx_state is
-- when "00" =>
-- if rxdv_int = '1' and rxd_int = "01010101" then
-- rx_state <= "01";
-- else
-- rx_state <= "00";
-- end if;
-- when "01" =>
-- if rxdv_int = '1' then
-- if rxd_int = "11010101" then
-- rx_state <= "10";
-- elsif rxd_int = "01010101" then
-- rx_state <= "01";
-- else
-- rx_state <= "00";
-- end if;
-- else
-- rx_state <= "00";
-- end if;
-- when "10" =>
-- if rxdv_int = '1' then
-- rx_state <= "11";
-- end if;
-- when "11" =>
-- if rxdv_int = '0' then
-- rx_state <= "00";
-- end if;
-- when others =>
-- NULL;
-- end case;
-- end if;
-- rx_state_d1 <= rx_state;
-- end if;
-- end process;
p_state_machine : process(rxclk, reset)
begin
if reset = '1' then
rx_state <= (others => '0');
rx_state_d1 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
case rx_state is
when "00" =>
if rxdv_buf = '1' and rxd_buf = "01010101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
when "01" =>
if rxdv_buf = '1' then
if rxd_buf = "11010101" then
rx_state <= "10";
elsif rxd_buf = "01010101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
else
rx_state <= "00";
end if;
when "10" =>
if rxdv_buf = '1' then
rx_state <= "11";
end if;
when "11" =>
if rxdv_buf = '0' then
rx_state <= "00";
end if;
when others =>
NULL;
end case;
-- end if;
rx_state_d1 <= rx_state;
end if;
end process;
p_byte_cnt : process(rxclk, reset) -- byte count
begin
if reset = '1' then
byte_cnt <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "00" then
byte_cnt <= (others => '0');
elsif rx_state = "11" then
byte_cnt <= byte_cnt + 1;
end if;
-- end if;
end if;
end process;
p_length : process(rxclk, reset)
begin
if reset = '1' then
length <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "11" and rxdv_buf = '0' then
length <= "0000" & byte_cnt - 3; -- Êý¾Ý³¤¶È£¬³ýµô4Bytes CRCУÑé
end if;
-- end if;
end if;
end process;
------------------------------------------------------------------------------
-- u_crc_rom : CRCRom
-- port map(
-- addr => crcrom_addr,
-- dout => crcrom_dout
-- );
--
-- crcrom_addr <= crc_reg(31 downto 28);
--
-- p_calc_crc : process(clk, reset)
-- begin
-- if reset = '1' then
-- crc_din <= (others => '0');
-- crc_reg <= (others => '0');
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- if nibble_cnt < 7 then
-- crc_din <= not (rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3));
-- else
-- crc_din <= rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3);
-- end if;
--
-- if rx_state = "10" then
-- crc_reg <= (others => '0');
-- elsif rx_state = "11" then
-- crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
-- end if;
-- end if;
-- end if;
-- end process;
u_crc_rom : CRC8_BlkRom
port map(
clk => rxclk,
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 24);
crc_reg <= (others=>'0') when rx_state_d1 = "10" else
crc_reg_d1 xor crcrom_dout when rx_state_d1 = "11" else
crc_reg_d1;
p_calc_crc : process(rxclk, reset)
begin
if reset = '1' then
crc_din <= (others => '0');
crc_reg_d1 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if byte_cnt < 3 then
crc_din <= not (rxd_buf(0) & rxd_buf(1) & rxd_buf(2) & rxd_buf(3) & rxd_buf(4) & rxd_buf(5) & rxd_buf(6) & rxd_buf(7));
else
crc_din <= rxd_buf(0) & rxd_buf(1) & rxd_buf(2) & rxd_buf(3) & rxd_buf(4) & rxd_buf(5) & rxd_buf(6) & rxd_buf(7);
end if;
if rx_state = "10" then
crc_reg_d1 <= (others => '0');
elsif rx_state = "11" then
crc_reg_d1 <= (crc_reg(23 downto 0) & crc_din);
end if;
-- else
-- crc_reg_d1 <= crc_reg;
-- end if;
end if;
end process;
p_crc_flag : process(rxclk, reset)
begin
if reset = '1' then
crc_flag <= '0';
g_Test_EthRec_CRCFlag <= '0';
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "00" and crc_reg = X"FFFFFFFF" then
crc_flag <= '1';
elsif rx_state = "10" then
crc_flag <= '0';
end if;
-- end if;
g_Test_EthRec_CRCFlag <= crc_flag;
end if;
end process;
--------------------------------------------------------------------------------
p_s2p : process(rxclk, reset)
begin
if reset = '1' then
rxd_buf_d1 <= (others => '0');
rxd_buf_d2 <= (others => '0');
rxd_buf_d3 <= (others => '0');
rxd_buf_d4 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
rxd_buf_d1 <= rxd_buf;
rxd_buf_d2 <= rxd_buf_d1;
rxd_buf_d3 <= rxd_buf_d2;
rxd_buf_d4 <= rxd_buf_d3;
-- end if;
end if;
end process;
-- dword_data_ext <= rxd_buf_d4 & rxd_buf_d3 & rxd_buf_d2 & rxd_buf_d1;
dword_data_ext <= rxd_buf_d1 & rxd_buf_d2 & rxd_buf_d3 & rxd_buf_d4;
-----------------------------------------------------------------------------
RxFIFO_clr <= '1' when rx_state = "10" else '0';
RxFIFO_wea <= '1' when rx_state = "11" and byte_cnt(1 downto 0) = "11" else '0';
RxFIFO_dia <= dword_data_ext;
u_din_sync : fifo_async_almost_full
generic map(
DEPTH => 2**(HEAD_AWIDTH-1),
AWIDTH => HEAD_AWIDTH-1,
DWIDTH => 32,
RAM_TYPE => "DIS_RAM")
port map(
reset => reset,
clr => RxFIFO_clr,
clka => rxclk,
-- clka => rxclk_temp,
wea => RxFIFO_wea,
dia => RxFIFO_dia,
clkb => clk,
rdb => RxFIFO_rdb,
dob => RxFIFO_dob,
empty => RxFIFO_empty,
almost_full => open,
full => open,
dn => open
);
RxFIFO_not_empty <= not RxFIFO_empty;
RxFIFO_rdb <= not RxFIFO_empty when (rx_state_int = "01" and byte_cnt_int(1 downto 0) = "00") or rx_state_int = "10" else '0';
dword_data_int <= RxFIFO_dob;
p_ce : process(clk, reset)
begin
if reset = '1' then
ce <= '0';
elsif rising_edge(clk) then
ce <= RxFIFO_rdb;
end if;
end process;
ASYNCWRITE_RxFIFO_clr_int : ASYNCWRITE
port map(
reset => reset,
async_clk => rxclk,
sync_clk => clk,
async_wren => RxFIFO_clr,
trigger => RxFIFO_not_empty,
sync_wren => RxFIFO_clr_int,
over => open,
flag => open
);
p_rx_state_int : process( clk, reset )
begin
if reset = '1' then
rx_state_int <= "00";
rx_state_int_d1 <= "00";
elsif rising_edge( clk ) then
if RxFIFO_clr_int = '1' then
rx_state_int <= "01";
else
case rx_state_int is
when "01" => -- head_ena
if byte_cnt_int = HEAD_LENGTH-1 then
rx_state_int <= "10";
elsif rx_end_int = '1' then
rx_state_int <= "11";
else
rx_state_int <= "01";
end if;
when "10" => -- data_ena
if rx_end_int = '1' then
rx_state_int <= "11";
end if;
when "11" => -- info_ena
if info_cnt = INFO_LENGTH-1 then
rx_state_int <= "00";
end if;
when others =>
NULL;
end case;
end if;
rx_state_int_d1 <= rx_state_int;
end if;
end process;
rx_end_ext <= '1' when rx_state = "11" and rxdv_buf = '0' else '0';
ASYNCWRITE_rx_end_int : ASYNCWRITE
port map(
reset => reset,
async_clk => rxclk,
sync_clk => clk,
async_wren => rx_end_ext,
trigger => RxFIFO_empty,
sync_wren => rx_end_int,
over => open,
flag => open
);
p_dword_cnt : process(clk, reset, RxFIFO_clr) -- byte count
begin
if reset = '1' then
byte_cnt_int <= (others => '0');
byte_cnt_int_d1 <= (others => '0');
elsif rising_edge(clk) then
if rx_state_int = "00" then
byte_cnt_int <= (others=>'0');
elsif rx_state_int = "01" then
byte_cnt_int <= byte_cnt_int + 1;
elsif rx_state_int = "10" then
byte_cnt_int <= byte_cnt_int + 4;
end if;
byte_cnt_int_d1 <= byte_cnt_int;
end if;
end process;
------------------------------------------------------------------------------
-- p_recvtime : process(clk, reset)
-- begin
-- if reset = '1' then
-- recvtime(31 downto 0) <= (others => '0');
-- recvtime_valid <= '0';
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- case dword_cnt is
-- when X"00e" => recvtime(31 downto 24) <= rxd_int;
-- when X"00f" => recvtime(23 downto 16) <= rxd_int;
-- when X"010" => recvtime(15 downto 8) <= rxd_int;
-- when X"011" => recvtime(7 downto 0) <= rxd_int;
-- when X"012" => recvtime_valid <= '1';
-- when others => recvtime_valid <= '0';
-- end case;
-- end if;
-- end if;
-- end process;
p_p2s : process( clk, reset )
begin
if reset = '1' then
dword_data_buf <= (others=>'0');
elsif rising_edge( clk ) then
if byte_cnt_int_d1(1 downto 0) = "00" then
-- dword_data_buf <= dword_data_int(23 downto 0);
dword_data_buf <= dword_data_int(31 downto 8);
else
-- dword_data_buf <= dword_data_buf(15 downto 0) & x"00";
dword_data_buf <= x"00" & dword_data_buf(23 downto 8);
end if;
end if;
end process;
-- byte_data_int <= dword_data_int(31 downto 24) when byte_cnt_int_d1(1 downto 0) = "00" else
-- dword_data_buf(23 downto 16);
byte_data_int <= dword_data_int(7 downto 0) when byte_cnt_int_d1(1 downto 0) = "00" else
dword_data_buf(7 downto 0);
p_recvtime : process(clk, reset)
begin
if reset = '1' then
recvtime(31 downto 0) <= (others => '0');
recvtime_valid <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
case byte_cnt_int_d1 is
when X"00e" => recvtime(31 downto 24) <= byte_data_int;
when X"00f" => recvtime(23 downto 16) <= byte_data_int;
when X"010" => recvtime(15 downto 8) <= byte_data_int;
when X"011" => recvtime(7 downto 0) <= byte_data_int;
when X"012" => recvtime_valid <= '1';
when others => recvtime_valid <= '0';
end case;
-- end if;
end if;
end process;
p_localtime_locked : process(clk, reset)
begin
if reset = '1' then
localtime_locked_reg <= '0';
elsif rising_edge(clk) then
-- if ce = '1' and rx_state = "10" and localtime_locked_reg = '0' then
if RxFIFO_clr_int = '1' and localtime_locked_reg = '0' then
localtime_locked_reg <= '1';
elsif localtime_locked_reg = '1' then
localtime_locked_reg <= '0';
end if;
end if;
end process;
localtime_locked <= localtime_locked_reg;
------------------------------------------------------------------------------
p_buff_wren : process(clk, reset)
begin
if reset = '1' then
buff_wren_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
-- if byte_cnt(1 downto 0) = "11" and rx_state = "11" then -- 4byteдʹÄÜ£¿
-- buff_wren_buf <= '1';
-- else
-- buff_wren_buf <= '0';
-- end if;
-- end if;
-- if ce = '1' and (rx_state_int = "01" or rx_state_int = "10") then
-- buff_wren_buf <= '1';
-- else
-- buff_wren_buf <= '0';
-- end if;
buff_wren_buf <= ce;
end if;
end process;
p_buff_waddr : process(clk, reset)
begin
if reset = '1' then
buff_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
if buff_wren_buf = '1' then
buff_waddr_buf <= buff_waddr_buf + 1; -- buffer address ++
end if;
-- end if;
end if;
end process;
p_buff_wdata : process(clk, reset)
begin
if reset = '1' then
buff_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
buff_wdata <= dword_data_int;
end if;
end if;
end process;
buff_wren <= buff_wren_buf;
buff_waddr <= buff_waddr_buf;
------------------------------------------------------------------------------
p_start_addr : process(clk, reset)
begin
if reset = '1' then
start_addr <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
-- if rx_state = "10" then
if RxFIFO_clr_int = '1' then
start_addr <= EXT(buff_waddr_buf, 16); -- °üÀ¨CRCµØÖ·
-- end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
-- info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
-- if ce = '1' then
-- if rx_state = "11" and rxdv_int = '0' then
-- if rx_end_int = '1' then
-- info_ena <= '1';
-- elsif info_cnt = INFO_LENGTH - 1 then
-- info_ena <= '0';
-- end if;
-- if info_ena = '0' then
-- info_cnt <= 0;
-- else
-- info_cnt <= info_cnt + 1;
-- end if;
-- end if;
if rx_state_int = "11" then
info_cnt <= info_cnt + 1;
else
info_cnt <= 0;
end if;
end if;
end process;
info_ena <= '1' when rx_state_int = "11" else '0';
p_head_wren : process(clk, reset)
begin
if reset = '1' then
head_wren_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
-- if (rx_state = "11" and rxdv_int = '1' and byte_cnt < HEAD_LENGTH) or info_ena = '1' then -- Ç°32¸ö×Ö½Úдʱ£¬ÒÔ¼°×îºóдµØÖ·Ó볤¶È4×Ö½ÚʱΪ1
if rx_state_int_d1 = "01" or rx_state_int = "11" then
head_wren_buf <= '1';
else
head_wren_buf <= '0';
end if;
-- end if;
end if;
end process;
p_head_waddr : process(clk, reset)
begin
if reset = '1' then
head_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
--if rx_state = "10" then
if RxFIFO_clr_int = '1' then
head_waddr_buf <= conv_std_logic_vector(INFO_LENGTH, HEAD_AWIDTH);
--elsif rx_state = "11" and rxdv_int = '0' then
elsif rx_end_int = '1' then
head_waddr_buf <= conv_std_logic_vector(0, HEAD_AWIDTH);
elsif head_wren_buf = '1' then
head_waddr_buf <= head_waddr_buf + 1;
end if;
-- end if;
end if;
end process;
p_head_wdata : process(clk, reset)
begin
if reset = '1' then
head_wdata <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 => head_wdata <= length(7 downto 0);
when 1 => head_wdata <= length(15 downto 8);
when 2 => head_wdata <= start_addr(5 downto 0)&"00";
when 3 => head_wdata <= start_addr(13 downto 6);
when others => null;
end case;
else
head_wdata <= byte_data_int;
end if;
-- end if;
end if;
end process;
head_wren <= head_wren_buf;
head_waddr <= head_waddr_buf;
p_head_wr_block : process(clk, reset)
begin
if reset = '1' then
head_wr_block_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
if info_cnt = INFO_LENGTH and crc_flag = '1' then -- crcУÑéÕýÈ·
head_wr_block_buf <= '1';
else
head_wr_block_buf <= '0';
end if;
-- end if;
end if;
end process;
head_wr_block <= head_wr_block_buf; -- crcУÑéÖ¸Õë
end arch_ethrx_input;
| gpl-2.0 | 8c73aa300824847872d7b6f0c7d98df6 | 0.530263 | 2.563166 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_to_xil_fifo.vhd | 2 | 5,572 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end wishbone_to_xil_fifo;
architecture RTL of wishbone_to_xil_fifo is
constant address_space_nbit : integer := MAX(nbit(WR_FIFO_SIZE), nbit(RD_FIFO_SIZE));
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data, fifo_status : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
signal control_space_data_spacen : std_logic ;
begin
rd_clk <= gls_clk ;
wr_clk <= gls_clk ;
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
control_space_data_spacen <= wbs_address(address_space_nbit) ;
wbs_readdata <= control_latched when control_space_data_spacen = '1' else --data_access = '0' else
fifo_data ;
rd_en <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' else
'0' ;
wr_en <= '1' when control_space_data_spacen = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' and write_ack = '0' else
'0' ;
with conv_integer(wbs_address(address_space_nbit-1 downto 0)) select
control_data <= std_logic_vector(to_unsigned(RD_FIFO_SIZE, 16)) when 0,
std_logic_vector(to_unsigned(WR_FIFO_SIZE, 16)) when 1,
std_logic_vector(resize(unsigned(rd_data_count), 16)) when 2,
std_logic_vector(resize(unsigned(wr_data_count), 16)) when 3,
fifo_status when others;
fifo_status <= X"000" & empty & underflow & full & overflow ;
fifo_rst <= '1' when gls_reset = '1' else
'1' when control_space_data_spacen = '1' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
dout <= wbs_writedata ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
fifo_data <= (others => '0');
elsif rising_edge(gls_clk) then
if control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' then
fifo_data <= din ;
end if ;
end if;
end process;
end RTL;
| lgpl-3.0 | 7c751d2851b23f1a5b7dfceec642f7c3 | 0.61827 | 3.27572 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/addc.vhd | 1 | 697 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity ADDC is
generic (
width : integer
);
port(
opa: in std_logic_vector(width-1 downto 0);
opb: in std_logic_vector(width-1 downto 0);
ci: in std_logic;
sum: out std_logic_vector(width-1 downto 0);
co: out std_logic
);
end ADDC;
architecture behavior of ADDC is
begin
process(opa,opb,ci)
variable res:std_logic_vector( width downto 0 ):=(others=>'0');
begin
res:=('0'&opa)+('0'&opb)+ci;
sum<=res(width-1 downto 0);
co<=res(width);
end process;
end behavior;
| gpl-2.0 | 398bc266c7b0c0693de46aa1febca83e | 0.655667 | 2.754941 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_signal_4.vhd | 2 | 14,980 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_signal_4.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_cond_signal( cond );
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_signal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b001275fc425d5519b8d748ee50d8a0b | 0.536916 | 3.854864 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_thread_manager_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 57,913 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
--
-- Title Thread Manager
--
-- 26 Jul 2004: Mike Finley: Original author
-- 08 Jun 2005: Erik Anderson: Changes for new interface between TM and
-- Scheduler. Also adding function isQueue().
-- 15 Apr 2009: Jim Stevens: Ported to PLB version 4.6.
--
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_RESET_TIMEOUT : natural := 4096
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- Define the memory map for each register, Address[16 to 21]
--
constant C_CLEAR_THREAD : std_logic_vector(0 to 5) := "000000";
constant C_JOIN_THREAD : std_logic_vector(0 to 5) := "000001";
constant C_READ_THREAD : std_logic_vector(0 to 5) := "000011";
constant C_ADD_THREAD : std_logic_vector(0 to 5) := "000100";
constant C_CREATE_THREAD_J : std_logic_vector(0 to 5) := "000101";
constant C_CREATE_THREAD_D : std_logic_vector(0 to 5) := "000110";
constant C_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant C_NEXT_THREAD : std_logic_vector(0 to 5) := "001000";
constant C_YIELD_THREAD : std_logic_vector(0 to 5) := "001001";
constant C_CURRENT_THREAD : std_logic_vector(0 to 5) := "010000";
constant C_IS_DETACHED : std_logic_vector(0 to 5) := "011000";
constant C_IS_QUEUED : std_logic_vector(0 to 5) := "011001";
constant C_EXCEPTION_ADDR : std_logic_vector(0 to 5) := "010011";
constant C_EXCEPTION_REG : std_logic_vector(0 to 5) := "010100";
constant C_SOFT_START : std_logic_vector(0 to 5) := "010101";
constant C_SOFT_STOP : std_logic_vector(0 to 5) := "010110";
constant C_SOFT_RESET : std_logic_vector(0 to 5) := "010111";
constant C_SCHED_LINES : std_logic_vector(0 to 5) := "011010";
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
constant OPCODE_IS_QUEUED : std_logic_vector(0 to 5) := "000001";
constant OPCODE_ENQUEUE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DEQUEUE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_IS_EMPTY : std_logic_vector(0 to 5) := "000110";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant H32 : std_logic_vector(0 to 31) := (others => '1');
constant MAX_QUEUE_SIZE : std_logic_vector(0 to 7) := (others => '1');
constant TOUT_CYCLES : natural := 3; -- assert timeout suppress
signal cycle_count : std_logic_vector(0 to 15);
signal timeout_expired : std_logic;
-- Extended Thread Error Codes returned in lower 4 bits
constant ERROR_IN_STATUS : std_logic_vector(0 to 3) := "0001";
constant THREAD_ALREADY_TERMINATED : std_logic_vector(0 to 3) := "0011";
constant THREAD_ALREADY_QUEUED : std_logic_vector(0 to 3) := "0101";
constant ERROR_FROM_SCHEDULER : std_logic_vector(0 to 3) := "0111";
constant JOIN_ERROR_CHILD_JOINED : std_logic_vector(0 to 3) := "1001";
constant JOIN_ERROR_NOT_CHILD : std_logic_vector(0 to 3) := "1011";
constant JOIN_ERROR_CHILD_DETACHED : std_logic_vector(0 to 3) := "1101";
constant JOIN_ERROR_CHILD_NOT_USED : std_logic_vector(0 to 3) := "1111";
constant JOIN_ERROR_UNKNOWN : std_logic_vector(0 to 3) := "0001";
constant CLEAR_ERROR_NOT_USED : std_logic_vector(0 to 3) := "1001";
-- Exception "cause" returned in Exception register
constant EXCEPTION_WRITE_TO_READ_ONLY : std_logic_vector(0 to 3) := "0001";
constant EXCEPTION_UNDEFINED_ADDRESS : std_logic_vector(0 to 3) := "0010";
constant EXCEPTION_TO_SOFT_RESET : std_logic_vector(0 to 3) := "0011";
constant EXCEPTION_TO_SCHD_ISQUEUED : std_logic_vector(0 to 3) := "0100";
constant EXCEPTION_TO_SCHD_ENQUEUE : std_logic_vector(0 to 3) := "0101";
constant EXCEPTION_TO_SCHD_DEQUEUE : std_logic_vector(0 to 3) := "0110";
constant EXCEPTION_TO_SCHD_ISEMPTY : std_logic_vector(0 to 3) := "0111";
constant EXCEPTION_TO_SCHD_NEXT_THREAD : std_logic_vector(0 to 3) := "1000";
constant EXCEPTION_SCHD_INVALID_THREAD : std_logic_vector(0 to 3) := "1001";
constant EXCEPTION_ILLEGAL_STATE : std_logic_vector(0 to 3) := "1111";
-- BRAM constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- Address,Cause for access exceptions
--
signal Exception_Address : std_logic_vector(0 to 31);
signal Exception_Address_next : std_logic_vector(0 to 31);
signal Exception_Cause : std_logic_vector(0 to 3);
signal Exception_Cause_next : std_logic_vector(0 to 3);
signal access_error : std_logic;
-- Debug control signals
--
-- Soft reset signals, LSB = SWTM reset; reset IP(s) if '1'
-- Resets done, handshake from IPs if done resetting(1)
-- core_stop , halt state machines at next appropriate point if '1'
--
signal soft_resets : std_logic_vector(0 to 4);
signal soft_resets_next : std_logic_vector(0 to 4);
signal resets_done : std_logic_vector(0 to 4);
signal reset_status : std_logic_vector(0 to 4);
signal reset_status_next : std_logic_vector(0 to 4);
signal core_stop : std_logic;
signal core_stop_next : std_logic;
-- Declarations for each register
-- Current thread,Idle thread : bits 0..7 = ID, bit 8 = '1' = invalid
signal current_cpu_thread : std_logic_vector(0 to 8);
signal current_cpu_thread_next : std_logic_vector(0 to 8);
-- internal signals
signal next_ID : std_logic_vector(0 to 8);
signal next_ID_next : std_logic_vector(0 to 8);
signal temp_thread_id : std_logic_vector(0 to 7);
signal temp_thread_id_next : std_logic_vector(0 to 7);
signal temp_thread_id2 : std_logic_vector(0 to 7);
signal temp_thread_id2_next : std_logic_vector(0 to 7);
signal reset_ID : std_logic_vector(0 to 8);
type swtm_state_type is
(IDLE_STATE,
SOFT_RESET_WRITE_INIT,
SOFT_RESET_INIT_TABLE,
SOFT_RESET_WAIT,
READ_THREAD_INIT,
READ_THREAD_RD_WAIT,
READ_THREAD_DONE,
CREATE_THREAD_INIT,
CT_NEW_ID_RD_WAIT,
CT_NEW_ID_AVAILABLE,
CT_ENTRY_RD_WAIT,
CT_ENTRY_AVAILABLE,
CT_DONE,
CLEAR_THREAD_INIT,
CLEAR_ENTRY_RD_WAIT,
CLEAR_ENTRY_AVAIABLE,
DEALLOCATE_ID,
DEALLOCATE_NEXT_ENTRY_RD_WAIT,
DEALLOCATE_NEXT_ENTRY_AVAIL,
JOIN_THREAD_INIT,
JOIN_RD_ENTRY_RD_WAIT,
JOIN_RD_ENTRY_AVAILABLE,
IS_QUEUED_INIT,
IS_QUEUED_DONE,
IS_DETACHED_THREAD_INIT,
IS_DETACHED_ENTRY_RD_WAIT,
IS_DETACHED_ENTRY_AVAILABLE,
NEXT_THREAD_INIT,
NEXT_THREAD_WAIT4_SCHEDULER,
NEXT_THREAD_RD_WAIT,
NEXT_THREAD_AVAILABLE,
NEXT_THREAD_CHECK_DEQUEUE,
ADD_THREAD_INIT,
AT_ENTRY_RD_WAIT,
AT_ENTRY_AVAILABLE,
AT_ISQUEUED_WAIT,
AT_CHECK_ISQUEUE,
AT_ENQUEUE_WAIT,
AT_CHECK_ENQUEUE,
ISQUEUED_WAIT_ACK,
ISQUEUED_WAIT_COMPLETE,
ENQUEUE_WAIT_ACK,
ENQUEUE_WAIT_COMPLETE,
DEQUEUE_WAIT_ACK,
DEQUEUE_WAIT_COMPLETE,
IS_QUEUE_EMPTY_WAIT_ACK,
IS_QUEUE_EMPTY_WAIT_COMPLETE,
YIELD_THREAD_INIT,
YIELD_CURRENT_THREAD_RD_WAIT,
YIELD_CURRENT_THREAD_AVAILABLE,
YIELD_CHECK_QUEUE_EMPTY,
YIELD_ENQUEUE,
YIELD_CHECK_ENQUEUE,
-- YIELD_dummy_is_queued,
YIELD_DEQUEUE,
YIELD_CHECK_DEQUEUE,
EXIT_THREAD_INIT,
EXIT_THREAD_RD_WAIT,
EXIT_THREAD_AVAIABLE,
EXIT_DEALLOCATE,
EXIT_NEXT_THREAD_RD_WAIT,
EXIT_NEXT_THREAD_AVAILABLE,
EXIT_READ_PARENT,
EXIT_READ_PARENT_WAIT,
EXIT_READ_PARENT_AVAILABLE,
EXIT_CHECK_ENQUEUE,
RAISE_EXCEPTION,
END_TRANSACTION,
END_TRANSACTION_WAIT);
signal current_state, next_state : swtm_state_type := IDLE_STATE;
signal return_state, return_state_next : swtm_state_type := IDLE_STATE;
signal bus_data_out : std_logic_vector(0 to 31);
signal bus_data_out_next : std_logic_vector(0 to 31);
signal current_status : std_logic_vector(0 to 31);
signal current_status_next : std_logic_vector(0 to 31);
signal Swtm_Reset_Done : std_logic;
signal Swtm_Reset_Done_next : std_logic;
signal new_ID : std_logic_vector(0 to 7);
signal new_ID_next : std_logic_vector(0 to 7);
signal tm2sch_request_next : std_logic;
signal tm2sch_request_reg : std_logic;
signal tm2sch_data_next : std_logic_vector(0 to 7);
signal tm2sch_data_reg : std_logic_vector(0 to 7);
signal tm2sch_opcode_next : std_logic_vector(0 to 5);
signal tm2sch_opcode_reg : std_logic_vector(0 to 5);
-- Signals for thread table BRAM
signal ENA : std_logic;
signal WEA : std_logic;
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1);
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
alias addr :std_logic_vector(0 to 5) is Bus2IP_Addr(16 to 21);
---------------------------------------------------------------------------
-- Component Instantiation of inferred dual ported block RAM
---------------------------------------------------------------------------
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-------------------------------------------------------------------
-- ICON core signal declarations
-------------------------------------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal my_ack, my_tout_sup, my_error, my_sched_req : std_logic; -- TODO: This line might be gone.
signal my_counter : std_logic_vector(0 to 31);
-------------------------------------------------------------------
-- ICON core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_icon_v1_03_a
-- port
-- (
-- control0 : out std_logic_vector(35 downto 0)
-- );
--end component;
-- simulation translate_on
-------------------------------------------------------------------
-- ILA core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_ila_v1_02_a
-- port
-- (
--- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- trig0 : in std_logic_vector(63 downto 0);
-- trig1 : in std_logic_vector(63 downto 0);
-- trig2 : in std_logic_vector(31 downto 0);
-- trig3 : in std_logic_vector(31 downto 0);
-- trig4 : in std_logic_vector(15 downto 0)
-- );
--end component;
-- simulation translate_on
begin
-----------------------------------------------------------------------
-- thread_data_bram_tmp : infer_bram
-- generic map
-- (
-- ADDRESS_BITS => BRAM_ADDRESS_BITS,
-- DATA_BITS => BRAM_DATA_BITS
-- )
-- port map
-- (
-- CLKA => Bus2IP_Clk,
-- ENA => ENA,
-- WEA => WEA,
-- ADDRA => ADDRA,
-- DIA => DIA,
-- DOA => DOA
-- );
-----------------------------------------------------------------------
thread_table_bram : infer_bram_dual_port
generic map (
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map (
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
CLKB => Bus2IP_Clk,
ENB => sch2tm_ENB,
WEB => sch2tm_WEB,
ADDRB => sch2tm_ADDRB,
DIB => sch2tm_DIB,
DOB => tm2sch_DOB
);
tm2sch_opcode <= tm2sch_opcode_reg;
tm2sch_data <= tm2sch_data_reg;
tm2sch_request <= tm2sch_request_reg;
Soft_Stop <= core_stop;
Scheduler_Reset <= soft_resets(3);
Semaphore_Reset <= soft_resets(2);
SpinLock_Reset <= soft_resets(1);
User_IP_Reset <= soft_resets(0);
Access_Intr <= access_error;
CYCLE_PROC : process (Bus2IP_Clk, Bus2IP_CS) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if( Bus2IP_CS(0) = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
--
-- create a counter for the number of elapsed cycles
-- in each bus transaction.
-- assert TimeOut suppress when count = TOUT_CYCLES
--
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_Error <= '0'; -- no error
--
-- count the number of elapsed clock cycles in transaction
--
if cycle_count < C_RESET_TIMEOUT then
timeout_expired <= '0';
else
--timeout_expired <= '1';
timeout_expired <= '0'; -- Disable timeouts.
end if;
--
-- activate time out suppress if count exceeds TOUT_CYCLES
-- edk. Why isn't this done inside the clk_event ???
--
-- if cycle_count > TOUT_CYCLES then
-- --IP2Bus_ToutSup <= '1'; -- halt time out counter
-- my_tout_sup <= '1'; -- halt time out counter
-- else
-- --IP2Bus_ToutSup <= '0'; -- release
-- my_tout_sup <= '0'; -- release
-- end if;
end process CYCLE_CONTROL;
-- IP2Bus_ToutSup <= my_tout_sup;
RESET_PROC : process (Bus2IP_Clk, addr, current_state)
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( addr = C_SOFT_RESET and current_state = SOFT_RESET_WRITE_INIT ) then
reset_ID <= (others => '0');
else
reset_ID <= reset_ID + 1;
end if;
end if;
end process;
ACK_PROC : process(my_ack, Bus2IP_RdCE, Bus2IP_WrCE)
begin
if (Bus2IP_RdCE(0) = '1') then
IP2Bus_RdAck <= my_ack;
else
IP2Bus_RdAck <= '0';
end if;
if (Bus2IP_WrCE(0) = '1') then
IP2Bus_WrAck <= my_ack;
else
IP2Bus_WrAck <= '0';
end if;
end process;
SWTM_STATE_PROC : process (Bus2IP_Clk, core_stop_next, new_ID_next, next_ID_next, temp_thread_id_next, temp_thread_id2_next, current_cpu_thread_next, Current_status_next, soft_resets_next, reset_status_next, Swtm_Reset_Done_next, Scheduler_Reset_Done, Semaphore_Reset_Done, SpinLock_Reset_Done, User_IP_Reset_Done, next_state, return_state_next, Bus2IP_Reset,Exception_Cause_next) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
core_stop <= core_stop_next;
new_ID <= new_ID_next;
next_ID <= next_ID_next;
temp_thread_id <= temp_thread_id_next;
temp_thread_id2 <= temp_thread_id2_next;
current_cpu_thread <= current_cpu_thread_next;
tm2sch_cpu_thread_id <= current_cpu_thread_next(0 to 7);
tm2sch_data_reg <= tm2sch_data_next;
tm2sch_opcode_reg <= tm2sch_opcode_next;
tm2sch_request_reg <= tm2sch_request_next;
current_status <= current_status_next;
Exception_Address <= Exception_Address_next;
Exception_Cause <= Exception_Cause_next;
soft_resets <= soft_resets_next;
reset_status <= reset_status_next;
bus_data_out <= bus_data_out_next;
Swtm_Reset_Done <= Swtm_Reset_Done_next;
resets_done(4) <= Swtm_Reset_Done_next;
resets_done(3) <= Scheduler_Reset_Done;
resets_done(2) <= Semaphore_Reset_Done;
resets_done(1) <= SpinLock_Reset_Done;
resets_done(0) <= User_IP_Reset_Done;
return_state <= return_state_next;
if( Bus2IP_Reset = '1' ) then
current_state <= IDLE_STATE;
else
current_state <= next_state;
end if;
end if;
end process SWTM_STATE_PROC;
-- IP2Bus_Ack <= my_ack; -- pulse(010) to end bus transaction
SWTM_LOGIC_PROC : process (current_state, core_stop, new_ID, next_ID, current_cpu_thread, current_status, reset_status, Swtm_Reset_Done, soft_resets, Bus2IP_Addr, Bus2IP_Data, Exception_Address, Bus2IP_WrCE, addr, Bus2IP_RdCE, reset_ID, resets_done, timeout_expired, DOA, sch2tm_next_id_valid, sch2tm_next_id, sch2tm_busy, bus_data_out, Exception_Cause, tm2sch_request_reg, tm2sch_data_reg, tm2sch_opcode_reg, temp_thread_id, temp_thread_id2) is
begin
-- -------------------------------------------------
-- default output signal assignments
-- -------------------------------------------------
my_ack <= '0'; -- pulse(010) to end bus transaction
access_error <= '0'; -- pulse(010) for access error interrupt
IP2Bus_Data <= (others => '0');
ADDRA <= (others => '0');
ENA <= '0';
WEA <= '0';
DIA <= (others => '0');
-- -------------------------------------------------
-- default register assignments
-- -------------------------------------------------
next_state <= current_state;
return_state_next <= return_state;
core_stop_next <= core_stop;
new_ID_next <= new_ID;
next_ID_next <= next_ID;
temp_thread_id_next <= temp_thread_id;
temp_thread_id2_next <= temp_thread_id2;
current_cpu_thread_next <= current_cpu_thread;
current_status_next <= current_status;
Exception_Address_next <= Exception_Address;
reset_status_next <= reset_status;
Swtm_Reset_Done_next <= Swtm_Reset_Done;
Exception_Cause_next <= Exception_Cause;
tm2sch_request_next <= tm2sch_request_reg;
tm2sch_data_next <= tm2sch_data_reg;
tm2sch_opcode_next <= tm2sch_opcode_reg;
bus_data_out_next <= bus_data_out;
soft_resets_next <= soft_resets;
case current_state is
-- Command (addr) decode whenever we are waiting for something new to do.
when IDLE_STATE =>
bus_data_out_next <= (others => '0');
if (Bus2IP_WrCE(0) = '1') then
case addr is
when C_SOFT_START =>
-- Any write to soft_start address clears
-- all soft reset signals and the Soft_Stop signal
soft_resets_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset done
core_stop_next <= '0'; -- clear core_stop
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- write any data to Soft_Stop to assert the Soft_Stop signal
core_stop_next <= '1';
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
next_state <= SOFT_RESET_WRITE_INIT;
when C_READ_THREAD =>
if (core_stop = '1') then
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '1';
ENA <= '1';
DIA <= Bus2IP_Data(0 to 31);
next_state <= END_TRANSACTION;
else
Exception_Cause_next <= EXCEPTION_WRITE_TO_READ_ONLY;
next_state <= RAISE_EXCEPTION;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
elsif (Bus2IP_RdCE(0) = '1') then
case addr is
when C_SOFT_START =>
bus_data_out_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- returns signal level in LSB on read
bus_data_out_next <= Z32(0 to 30) & core_stop;
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
-- returns 1's in bit positions that failed
bus_data_out_next <= Z32(0 to 26) & reset_status;
next_state <= END_TRANSACTION;
when C_CURRENT_THREAD =>
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
when C_EXCEPTION_ADDR =>
bus_data_out_next <= Exception_Address;
Exception_Address_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_EXCEPTION_REG =>
bus_data_out_next <= Z32(0 to 27) & Exception_Cause;
Exception_Cause_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SCHED_LINES =>
bus_data_out_next <= Z32(0 to 6) & sch2tm_busy & sch2tm_data &
Z32(16 to 22) & sch2tm_next_id_valid &
sch2tm_next_id;
next_state <= END_TRANSACTION;
when C_READ_THREAD => next_state <= READ_THREAD_INIT;
when C_CREATE_THREAD_D => next_state <= CREATE_THREAD_INIT;
when C_CREATE_THREAD_J => next_state <= CREATE_THREAD_INIT;
when C_CLEAR_THREAD => next_state <= CLEAR_THREAD_INIT;
when C_JOIN_THREAD => next_state <= JOIN_THREAD_INIT;
when C_IS_DETACHED => next_state <= IS_DETACHED_THREAD_INIT;
when C_IS_QUEUED => next_state <= IS_QUEUED_INIT;
when C_NEXT_THREAD => next_state <= NEXT_THREAD_INIT;
when C_ADD_THREAD => next_state <= ADD_THREAD_INIT;
when C_YIELD_THREAD => next_state <= YIELD_THREAD_INIT;
when C_EXIT_THREAD => next_state <= EXIT_THREAD_INIT;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
end if;
--
-- read/write to the soft resets register (1 bit per IP)
-- write '1' to reset, reads '1' if timeout error occured
-- before IP reports finished
--
-- SW Thread Manager = bit#4 (LSB)
-- Scheduler = bit#3
-- Semaphore = bit#2
-- SpinLock = bit#1
-- User_IP = bit#0
--
when SOFT_RESET_WRITE_INIT =>
soft_resets_next <= Bus2IP_Data(27 to 31);
reset_status_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset_done
if (Bus2IP_Data(31) = '1') then -- soft_resets(4)
--
-- perform a soft reset on SWTM
--
bus_data_out_next <= (others => '0');
new_ID_next <= (others => '0');
next_ID_next <= (others => '0');
temp_thread_id_next <= (others => '0');
current_cpu_thread_next <= Z32(0 to 7) & '1';
core_stop_next <= '0';
tm2sch_opcode_next <= OPCODE_NOOP;
tm2sch_data_next <= (others => '0');
tm2sch_request_next <= '0';
next_state <= SOFT_RESET_INIT_TABLE;
else
next_state <= SOFT_RESET_WAIT;
end if;
-- initialize the thread ID table to all zeros
-- and the next available stack to 0..255
when SOFT_RESET_INIT_TABLE =>
ADDRA <= reset_ID;
ENA <= '1';
WEA <= '1';
if( reset_ID(0) = '0' ) then
-- init available ID stack & thread ID table
DIA <= reset_ID(1 to 8) & Z32(0 to 23);
else
-- clear 2nd half of table (unused)
DIA <= Z32(0 to 31);
end if;
if( reset_ID = H32(0 to 8) ) then
swtm_reset_done_next<= '1'; -- done
next_state <= soft_reset_wait;
end if;
-- wait for all IPs to finish initialization or
-- the maximum time to be exceeded then
-- ack to finish transaction
when SOFT_RESET_WAIT =>
if (resets_done = soft_resets) then -- done
next_state <= END_TRANSACTION;
elsif (timeout_expired = '1') then
reset_status_next <= (resets_done xor soft_resets);
Exception_Cause_next <= EXCEPTION_TO_SOFT_RESET;
next_state <= RAISE_EXCEPTION; -- timeout
else
next_state <= current_state;
end if;
when READ_THREAD_INIT =>
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '0';
ENA <= '1';
next_state <= READ_THREAD_RD_WAIT;
when READ_THREAD_RD_WAIT =>
next_state <= READ_THREAD_DONE;
when READ_THREAD_DONE =>
bus_data_out_next <= DOA;
next_state <= END_TRANSACTION;
when CREATE_THREAD_INIT =>
if next_ID(0) = '1' then
-- no IDs available, return with error bit set
--
bus_data_out_next <= Z32(0 to 30) & '1';
next_state <= END_TRANSACTION;
else
-- read next ID from stack
--
ADDRA <= next_ID;
ENA <= '1';
next_state <= CT_NEW_ID_RD_WAIT;
end if;
when CT_NEW_ID_RD_WAIT =>
next_state <= CT_NEW_ID_AVAILABLE;
when CT_NEW_ID_AVAILABLE =>
new_ID_next <= DOA(0 to 7); -- save new ID#
ADDRA <= '0' & DOA(0 to 7); -- point to new thread
ENA <= '1';
next_state <= CT_ENTRY_RD_WAIT;
when CT_ENTRY_RD_WAIT =>
next_state <= CT_ENTRY_AVAILABLE;
when CT_ENTRY_AVAILABLE =>
ADDRA <= '0' & new_ID;
ENA <= '1';
WEA <= '1'; -- enable write to bram
-- Determine if the thread to create is DETACHED / JOINABLE
if addr = C_CREATE_THREAD_D then -- set new thread status
-- create detached
DIA <= DOA(0 to 7) & Z32(0 to 7) &
Z32(0 to 7) & "1011" & Z32(0 to 3);
else
-- create joinable
DIA <= DOA(0 to 7) & Z32(0 to 7) &
current_cpu_thread(0 to 7) & "0011" & Z32(0 to 3);
end if;
next_state <= CT_DONE;
when CT_DONE =>
-- return new ID with no error,
bus_data_out_next <= Z32(0 to 22) & new_ID & '0';
-- point to next available ID
next_ID_next <= next_ID + 1;
next_state <= END_TRANSACTION;
when CLEAR_THREAD_INIT =>
-- clear the encoded thread ID if it is used and exited
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= CLEAR_ENTRY_RD_WAIT;
when CLEAR_ENTRY_RD_WAIT =>
next_state <= CLEAR_ENTRY_AVAIABLE ;
when CLEAR_ENTRY_AVAIABLE =>
if (DOA(26 to 27) = "10") then -- used and exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1'; -- clear old status but
DIA <= DOA(0 to 7) & Z32(0 to 23); -- preserve ID stack
next_state <= DEALLOCATE_ID;
else
-- error occurred, return thread status w/ LSB=1
bus_data_out_next <= DOA(0 to 27) & CLEAR_ERROR_NOT_USED;
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_ID =>
if (next_ID /= Z32(0 to 8)) then
ADDRA <= next_ID - 1;
ENA <= '1';
next_ID_next <= next_ID - 1;
next_state <= DEALLOCATE_NEXT_ENTRY_RD_WAIT;
else
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_NEXT_ENTRY_RD_WAIT =>
next_state <= DEALLOCATE_NEXT_ENTRY_AVAIL;
when DEALLOCATE_NEXT_ENTRY_AVAIL =>
-- put ID back on stack, preserve other bits
ADDRA <= next_ID;
ENA <= '1';
WEA <= '1';
DIA <= Bus2IP_Addr(22 to 29) & DOA(8 to 31);
next_state <= END_TRANSACTION;
when JOIN_THREAD_INIT =>
-- join on the encoded thread ID if its PID = current_thread
-- and its status = used,~joined,~detached
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= JOIN_RD_ENTRY_RD_WAIT;
when JOIN_RD_ENTRY_RD_WAIT =>
next_state <= JOIN_RD_ENTRY_AVAILABLE;
when JOIN_RD_ENTRY_AVAILABLE =>
if ((DOA(16 to 23) & '0' = current_cpu_thread) and -- PID = current thread
(DOA(24 to 25) = "00") and -- ~detached,~joined
(DOA(26 to 27) /= "00")) then -- not unused
if DOA(27) = '0' then
-- thread has already exited, return a WARNING code
bus_data_out_next <= Z32(0 to 27) & THREAD_ALREADY_TERMINATED;
next_state <= END_TRANSACTION;
else
-- thread has not exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1';
-- clear old status but
-- set joined bit; and preserve all other bits
DIA <= DOA(0 to 24) & '1' & DOA(26 to 31);
next_state <= END_TRANSACTION;
end if;
else
-- An error occured. Determine the error and return correct error code.
if( DOA(24) = '1' ) then
-- trying to join on a detached thread
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_DETACHED;
elsif ( DOA(24 to 25) = "01" ) then
-- tyring to join on a thread that is already joined
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_JOINED;
elsif( DOA(26) = '0' ) then
-- trying to join on a thread that is not used
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_NOT_USED;
elsif( DOA(16 to 23) & '0' /= current_cpu_thread ) then
-- trying to join to a thread that is not the current thread's child
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_NOT_CHILD;
else
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_UNKNOWN;
end if;
next_state <= END_TRANSACTION;
end if;
when IS_DETACHED_THREAD_INIT =>
-- Returns a 1 if the encoded thread ID is detached, else returns 0
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= IS_DETACHED_ENTRY_RD_WAIT;
when IS_DETACHED_ENTRY_RD_WAIT =>
next_state <= IS_DETACHED_ENTRY_AVAILABLE;
when IS_DETACHED_ENTRY_AVAILABLE =>
if (DOA(24) = '1' and DOA(26) = '1') then
-- Thread is detached, return 1
bus_data_out_next <= Z32(0 to 29) & "10"; -- The 0 in the last bit indicates no error
else
-- Thread is not detached, or not used, return 0
bus_data_out_next <= Z32;
end if;
next_state <= END_TRANSACTION;
when IS_QUEUED_INIT =>
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29); -- thread ID
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= IS_QUEUED_DONE;
when IS_QUEUED_DONE =>
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
when NEXT_THREAD_INIT =>
-- Return to the caller the value of the next thread to run
if sch2tm_next_id_valid = '1' then
-- the next thread has been identified,
-- read from Scheduler and check thread status
-- as stored by SWTM for consistency
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
else
next_state <= NEXT_THREAD_WAIT4_SCHEDULER;
end if;
when NEXT_THREAD_WAIT4_SCHEDULER =>
if (sch2tm_next_id_valid = '1') then
-- Scheduler has made a scheduling decision
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
elsif (timeout_expired = '1') then
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_NEXT_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
else
-- Continue waiting for scheduler
next_state <= current_state;
end if;
when NEXT_THREAD_RD_WAIT =>
next_state <= NEXT_THREAD_AVAILABLE;
when NEXT_THREAD_AVAILABLE =>
if DOA(26 to 27) = "11" then
-- thread status is used and not exited
-- dequeue the next_thread_id from the scheduler's queue
current_cpu_thread_next <= sch2tm_next_id & '0';
-- Send dequeue opperation to scheduler
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_DEQUEUE;
else
-- TM and SCHEDULER disagree if thread was used and not exited
-- return thread ID, set error bit and raise exception
bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '1';
Exception_Cause_next <= EXCEPTION_SCHD_INVALID_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
end if;
when NEXT_THREAD_CHECK_DEQUEUE =>
-- Perform a check to make sure scheduler completed successfully
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
-- return the value of the next thread id (which by now is in the current_cpu_thread register)
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0';
next_state <= END_TRANSACTION;
end if;
when ADD_THREAD_INIT =>
-- if the thread is !used or exited return error
-- call scheduler to check queued status
-- if queued return error
-- call scheduler to enqueue thread ID
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- encoded thread ID
ENA <= '1';
next_state <= AT_ENTRY_RD_WAIT;
when AT_ENTRY_RD_WAIT =>
next_state <= AT_ENTRY_AVAILABLE;
when AT_ENTRY_AVAILABLE =>
-- check to see if the thread is used and !exited
if (DOA(26 to 27) = "11") then
-- thread is used and not exited
-- call scheduler isQueued
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= AT_CHECK_ISQUEUE;
else
-- thread is unused or exited (or both)
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ISQUEUE =>
-- Check to see if the thread is queued
if sch2tm_data(7) = '0' then
-- Thread is not queued, call scheduler's enqueue
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= AT_CHECK_ENQUEUE;
else
-- Thread is queued, return error
bus_data_out_next <= DOA(0 to 7) & sch2tm_data & DOA(16 to 27) & THREAD_ALREADY_QUEUED;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 31);
next_state <= END_TRANSACTION;
end if;
when ISQUEUED_WAIT_ACK =>
-- wait for the scheduler to acknowledge the isqueued request
if sch2tm_busy = '0' then
-- scheduler has not yet responded to request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler acknowledged request, lower request line
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ISQUEUED_WAIT_COMPLETE;
end if;
when ISQUEUED_WAIT_COMPLETE =>
-- wait for the scheduler to complete the isqueued request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler finished request, and (should) have data on data_return line
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when ENQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the enqueue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ENQUEUE_WAIT_COMPLETE;
end if;
when ENQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the enqueue request
if sch2tm_busy = '1' then
-- scheduler has notyet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when DEQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the dequeue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= DEQUEUE_WAIT_COMPLETE;
end if;
when DEQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the dequeue request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when IS_QUEUE_EMPTY_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= IS_QUEUE_EMPTY_WAIT_COMPLETE;
end if;
when IS_QUEUE_EMPTY_WAIT_COMPLETE =>
-- wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when YIELD_THREAD_INIT =>
-- Retrieve the status of the current cpu thread
ADDRA <= '0' & current_cpu_thread(0 to 7);
ENA <= '1';
next_state <= YIELD_CURRENT_THREAD_RD_WAIT;
when YIELD_CURRENT_THREAD_RD_WAIT =>
next_state <= YIELD_CURRENT_THREAD_AVAILABLE;
when YIELD_CURRENT_THREAD_AVAILABLE =>
-- check to see if thread's status is used,~exited,~queued
if (DOA(26 to 27) = "11") then
-- check to see if the scheduler's queue is empty
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= YIELD_CHECK_QUEUE_EMPTY;
else
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when YIELD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
-- Queue is empty, return the current thread id
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
else
-- Queue is not empty, add currently running thread to Q and then follow with a DEQ
next_state <= YIELD_ENQUEUE;
end if;
when YIELD_ENQUEUE =>
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_data_next <= current_cpu_thread(0 to 7);
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_ENQUEUE;
when YIELD_CHECK_ENQUEUE =>
if (sch2tm_data(7) = '0') then
-- ENQ was successful, now DEQ to get next scheduling decision
current_cpu_thread_next <= sch2tm_next_id & '0'; -- update the currently running thread to the one that is scheduled to run next (AKA to be DEQ'd)
-- next_state <= YIELD_dummy_is_queued;
next_state <= YIELD_DEQUEUE;
else
-- ENQ failed, return error to caller
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
end if;
-- when YIELD_dummy_is_queued =>
-- tm2sch_request_next <= '1'; -- request the dummy is_queued operation
-- tm2sch_opcode_next <= OPCODE_IS_QUEUED;
-- tm2sch_data_next <= "11111111";
-- next_state <= ISQUEUED_WAIT_ACK;
-- return_state_next <= YIELD_DEQUEUE;
when YIELD_DEQUEUE =>
tm2sch_request_next <= '1'; -- request the DEQ operation to remove the thread to run from Q
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_DEQUEUE;
when YIELD_CHECK_DEQUEUE =>
if (sch2tm_data(7) = '1') then
-- error during DEQ...
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- DEQ completed successfully, end operation
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0'; -- setup the return value of the next thread to run (now in the currently running thread)
next_state <= END_TRANSACTION;
end if;
when EXIT_THREAD_INIT =>
bus_data_out_next <= Z32; -- change if failure occurs
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
next_state <= EXIT_THREAD_RD_WAIT;
when EXIT_THREAD_RD_WAIT =>
next_state <= EXIT_THREAD_AVAIABLE;
when EXIT_THREAD_AVAIABLE =>
-- full entry for the current_thread is required in later states
current_status_next <= DOA(0 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
WEA <= '1';
if (DOA(24) = '1') then
-- Thread is detached
-- Make the thread status used and exited.
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
elsif (DOA(25) = '1') then
-- Thread is joined
-- Make the thread status used and exited, and wake the parent
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= EXIT_READ_PARENT;
else
-- Thread is not detached and still joinable
-- Set the thread status to used and exited
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
end if;
when EXIT_READ_PARENT =>
-- The thread that is exiting was joined, wake the parent up
ADDRA <= '0' & current_status(16 to 23);
ENA <= '1';
next_state <= EXIT_READ_PARENT_WAIT;
when EXIT_READ_PARENT_WAIT =>
next_state <= EXIT_READ_PARENT_AVAILABLE;
when EXIT_READ_PARENT_AVAILABLE =>
-- Make sure the parent thread is used and not exited
if (DOA(26 to 27) = "11") then
-- Parent thread is used and not exited.
-- Add the parent thread tothe scheduler's queue
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= current_status(16 to 23);
return_state_next <= EXIT_CHECK_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
else
-- Parent thread is either unused or exited, neither of which it should be
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when EXIT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 31);
next_state <= END_TRANSACTION;
end if;
when RAISE_EXCEPTION =>
-- NOTE !!! You must assign Exception_Cause
-- where-ever you assign next_state <= RAISE_EXCEPTION;
Exception_Address_next <= Bus2IP_Addr(0 to 31); -- save address
access_error <= '1'; -- assert interrupt
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION =>
IP2Bus_Data <= bus_data_out;
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION_WAIT =>
if( Bus2IP_RdCE(0)='0' and Bus2IP_WrCE(0)='0' ) then
next_state <= IDLE_STATE;
else
next_state <= current_state;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_ILLEGAL_STATE;
next_state <= RAISE_EXCEPTION;
end case; -- case current_state
end process SWTM_LOGIC_PROC;
-------------------------------------------------------------------
-- ICON core instance
-------------------------------------------------------------------
-- -- simulation translate_off
-- i_icon : chipscope_icon_v1_03_a
-- port map
-- (
-- control0 => control0
-- );
-- -- simulation translate_on
--
-- COUNTER_PROC : process (Bus2IP_Clk) is
-- begin
-- if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
-- if (Bus2IP_Reset = '1') then
-- my_counter <= (others => '0');
-- else
-- my_counter <= my_counter + 1;
-- end if;
-- end if;
-- end process COUNTER_PROC;
--
-- --
--
-- -------------------------------------------------------------------
-- -- ILA core instance
-- -------------------------------------------------------------------
--
-- -- simulation translate_off
-- i_ila : chipscope_ila_v1_02_a
-- port map
-- (
-- control => control0,
-- clk => Bus2IP_Clk,
-- trig0(63 downto 32) => Bus2IP_Data,
-- trig0(31 downto 0) => my_counter, -- 64 bits -- Add in chipscope signals and run on board!!!!
-- trig1(63 downto 32) => Bus2IP_Addr,
-- trig1(31 downto 0) => bus_data_out, -- 64 bits
-- trig2 => current_status, -- 32 bits
-- trig3 => Bus2IP_Addr, -- 32 bits
-- trig4(0) => Bus2IP_RdCE, -- 16 bits
-- trig4(1) => Bus2IP_WrCE,
-- trig4(2) => my_ack,
-- trig4(3) => my_tout_sup,
-- trig4(4) => Bus2IP_Reset,
-- trig4(5) => '0',
-- trig4(6) => tm2sch_request_reg,
-- trig4(7) => next_ID(0),
-- trig4(8) => next_ID(1),
-- trig4(9) => next_ID(2),
-- trig4(10) => next_ID(3),
-- trig4(11) => next_ID(4),
-- trig4(12) => next_ID(5),
-- trig4(13) => next_ID(6),
-- trig4(14) => next_ID(7),
-- trig4(15) => next_ID(8)
-- );
-- -- simulation translate_on
--
end IMP;
| bsd-3-clause | c5984ec38b94d25ee0350cabd859f216 | 0.534198 | 3.694138 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/steer_module_write.vhd | 3 | 26,663 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_write.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Write - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: steer_module_write.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- steer_module_write.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 4-26-2002 -- First version
-- ^^^^^^
-- First version of steering logic module.
-- ~~~~~~
--
-- DET 8/26/2002 Initial
-- ^^^^^^
-- - Corrected a problem with the BE outputs when Decode_size = "100" and
-- the decode_size is supposed to be used.
-- ~~~~~~
--
-- BLT 11-18-2002 -- Update to version v1.00b
-- ^^^^^^
-- Updated to use ipif_common_v1_00_b, which fixed a simulation problem
-- in the ipif_steer logic
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.STEER_TYPES.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_LARGEST : integer := width of largest device (not access size)
-- attached to the IPIF
-- C_MIRROR_SIZE : integer := smallest unit of data that is mirrored
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-- Note: I have no way of knowing what the master size is for master writes
-- so smaller masters on the
-------------------------------------------------------------------------------
entity Steer_Module_Write is
generic (
C_DWIDTH_IN : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer := 32
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end entity Steer_Module_Write;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of Steer_Module_Write is
-------------------------------------------------------------------------------
-- Function max -- returns maximum of x and y
-------------------------------------------------------------------------------
function max(x : integer; y : integer) return integer is
begin
if x > y then return x;
else return y;
end if;
end function max;
-------------------------------------------------------------------------------
-- Function min -- returns minimum of x and y
-------------------------------------------------------------------------------
function min(x : integer; y : integer) return integer is
begin
if x < y then return x;
else return y;
end if;
end function min;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- returns x**y for integers x and y, y>=0
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
function Addr_Start_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Start;
end function Addr_Start_Func;
function Addr_Stop_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Stop;
end function Addr_Stop_Func;
constant Addr_Size : integer_array_type(0 to 63) :=
(1=>1,3=>1,5=>1,7=>1,9=>1,11=>1,13=>1,15=>1,
17=>1,19=>1,21=>1,23=>1,25=>1,27=>1,29=>1,31=>1,
33=>1,35=>1,37=>1,39=>1,41=>1,43=>1,45=>1,47=>1,
49=>1,51=>1,53=>1,55=>1,57=>1,59=>1,61=>1,63=>1,
2=>2,6=>2,10=>2,14=>2,18=>2,22=>2,26=>2,30=>2,
34=>2,38=>2,42=>2,46=>2,50=>2,54=>2,58=>2,62=>2,
4=>4,12=>4,20=>4,28=>4,36=>4,44=>4,52=>4,60=>4,
8=>8,24=>8,40=>8,56=>8,16=>16,48=>16,32=>32,0=>64);
constant IP_Addr_Start : integer := Addr_Start_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
constant IP_Addr_Stop : integer := Addr_Stop_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- BE_STEER_PROC: process( Decode_size ) is
-- begin
-- BE_Steer <= '0';
-- case Decode_size is
-- when "000" => BE_Steer <= '0';
-- when "001" => if C_DWIDTH_IN > 8 then BE_Steer <= '1'; end if;
-- when "010" => if C_DWIDTH_IN > 16 then BE_Steer <= '1'; end if;
-- when "011" => if C_DWIDTH_IN > 32 then BE_Steer <= '1'; end if;
-- when "100" => if C_DWIDTH_IN > 64 then BE_Steer <= '1'; end if;
-- when "101" => if C_DWIDTH_IN > 128 then BE_Steer <= '1'; end if;
-- when "110" => if C_DWIDTH_IN > 256 then BE_Steer <= '1'; end if;
-- when "111" => if C_DWIDTH_IN > 512 then BE_Steer <= '1'; end if;
-- when others => BE_Steer <= '0';
-- end case;
-- end process BE_STEER_PROC;
MUX_PROCESS: process( Data_In,Decode_size,Addr,BE_In ) is
variable factor : integer;
variable addr_loop : integer;
variable addr_integer : integer;
variable num_addr_bits : integer;
variable size : integer;
variable address : integer;
variable data_address : integer;
variable replicate_factor : integer;
variable be_addr_base : integer;
variable be_addr_right : integer;
variable be_addr_left : integer;
variable be_num_addr_bits : integer;
variable be_uses_addr : boolean;
variable be_uses_decode_size : boolean;
variable be_start_addr : integer;
variable be_stop_addr : integer;
begin
num_addr_bits := IP_Addr_Stop-IP_Addr_Start+1;
-- Set up default condition
if C_DWIDTH_IN <= C_DWIDTH_OUT then
BE_Out(0 to C_DWIDTH_OUT/8-1) <= (others => '0');
for i in 0 to C_DWIDTH_OUT/C_DWIDTH_IN-1 loop
Data_Out(i*C_DWIDTH_IN to (i+1)*C_DWIDTH_IN-1) <= Data_In;
end loop;
else
Data_Out <= Data_In(0 to C_DWIDTH_OUT-1);
BE_Out <= BE_In(0 to C_DWIDTH_OUT/8-1);
end if;
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/C_SMALLEST_OUT);
be_addr_left := log2(C_DWIDTH_OUT/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if C_DWIDTH_OUT > C_SMALLEST_OUT then
be_uses_decode_size := TRUE;
else
be_uses_decode_size := FALSE;
end if;
if be_uses_decode_size then
for k in log2(C_SMALLEST_OUT/8)+1 to log2(C_DWIDTH_OUT/8)+1 loop -- 1,2,3,4,5,6,7 6 for now
factor := pwr(2,k)/2; -- 1,2,4,8,16,32,64 number of byte lanes
if Decode_size = Conv_std_logic_vector(k,3) then
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/factor/8);
be_addr_left := log2((factor*8)/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if be_uses_addr then -- BE IS a function of address -- TESTED
for j in 0 to pwr(2,be_num_addr_bits)-1 loop
if Addr(be_start_addr to be_stop_addr) = Conv_std_logic_vector(j,be_num_addr_bits) then
address := j*pwr(2,C_AWIDTH-be_stop_addr-1); -- generate real address from j loop variable
data_address := address;
if C_DWIDTH_IN < factor*8 then
for chunk in 0 to C_DWIDTH_IN/8-1 loop
BE_Out(address+chunk) <= BE_In(chunk);
end loop;
else
for chunk in 0 to factor-1 loop
BE_Out(chunk) <= BE_In(address+chunk);
end loop;
end if;
end if;
end loop;
else -- ADDED DET 8-26-02
BE_Out <= BE_In; -- ADDED DET 8-26-02
end if;
end if;
end loop;
else -- BE_Out is not a function of Decode_Size
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/C_DWIDTH_OUT);
be_addr_left := log2(C_DWIDTH_OUT/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if be_uses_addr then -- BE IS a function of address -- TESTED
for j in 0 to pwr(2,be_num_addr_bits)-1 loop
if Addr(be_start_addr to be_stop_addr) = Conv_std_logic_vector(j,be_num_addr_bits) then
address := j*pwr(2,C_AWIDTH-be_stop_addr-1); -- generate real address from j loop variable
data_address := address;
if C_DWIDTH_IN < C_DWIDTH_OUT then
for chunk in 0 to C_DWIDTH_IN/8-1 loop
BE_Out(address+chunk) <= BE_In(chunk);
end loop;
else
for chunk in 0 to C_DWIDTH_OUT/8-1 loop
BE_Out(chunk) <= BE_In(address+chunk);
end loop;
end if;
end if;
end loop;
else
BE_Out <= BE_In;
end if;
end if;
-- end of be logic
-- Data_Out is not a function of Decode_Size
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
if address = 0 then -- special case for address zero
size := C_DWIDTH_IN; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if C_DWIDTH_OUT >= C_DWIDTH_IN then -- peripheral is bigger than host bus
replicate_factor := C_DWIDTH_OUT/C_DWIDTH_IN;
else replicate_factor := 1;
end if;
for r in 0 to replicate_factor-1 loop
for p in 0 to (address*8)/size+1 loop -- loop only until address is covered
for m in 0 to size-1 loop -- set data to data on Data_In at "address"
if p*size+m+r*C_DWIDTH_IN < C_DWIDTH_OUT then -- stop at width of C_DWIDTH_OUT
Data_Out(p*size+m+r*C_DWIDTH_IN) <= Data_In(address*8+m);
end if;
end loop;
end loop;
end loop;
end if;
end loop;
else -- Data_Out is not a function of address
for m in 0 to C_DWIDTH_OUT-1 loop -- 0 to 3
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end process MUX_PROCESS;
end architecture IMP;
| bsd-3-clause | 44df21a55f212593eb59f15a2b9448dc | 0.449724 | 3.615812 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_arrayloops.vhd | 2 | 16,710 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
FOR_LOOP_1,
FOR_LOOP_2,
FOR_LOOP_3,
FOR_LOOP_4,
FOR_LOOP_5,
FOR_LOOP_6,
END_1,
END_2,
END_3,
END_4,
END_5,
END_6,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_END_3 : std_logic_vector(0 to 15) := x"0103";
constant U_EXIT_1 : std_logic_vector(0 to 15) := x"0201";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- Program constants
constant NTHREADS : std_logic_vector(0 to 31) := x"00000004";
constant ARRAYSIZE : std_logic_vector(0 to 31) := x"00002710";
constant ITERATIONS : std_logic_vector(0 to 31) := x"000009C4";
--constant ITERATIONS : std_logic_vector(0 to 31) := x"00000010";
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal sumAddr, sumAddr_next : std_logic_vector(0 to 31);
signal arrayAddr, arrayAddr_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal tid, tid_next : std_logic_vector(0 to 1);
signal mySum, mySum_next: std_logic_vector(0 to 31);
signal i, i_next : std_logic_vector(0 to 31);
signal start, start_next : std_logic_vector(0 to 31);
signal endd, endd_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
structAddr <= structAddr_next;
sumAddr <= sumAddr_next;
arrayAddr <= arrayAddr_next;
mutexAddr <= mutexAddr_next;
tid <= tid_next;
mySum <= mySum_next;
i <= i_next;
start <= start_next;
endd <= endd_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_END_3 =>
current_state <= END_3;
when U_EXIT_1=>
current_state <= FUNCTION_EXIT_1;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
sumAddr_next <= sumAddr;
arrayAddr_next <= arrayAddr;
mutexAddr_next <= mutexAddr;
tid_next <= tid;
mySum_next <= mySum;
i_next <= i;
start_next <= start;
endd_next <= endd;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, sumAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of sumAddr
sumAddr_next <= toUser_value;
-- Initiate the reading of the second variable in the struct, arrayAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of arrayAddr
arrayAddr_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, mutexAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of mutexAddr
mutexAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, tid
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= SETUP_5;
when SETUP_5 =>
-- Read the value of tid
tid_next <= toUser_value(30 to 31);
-- Calculate the start value
-- Note: that I'm avoiding the multiplication
case toUser_value(30 to 31) is
when "00" =>
start_next <= Z32;
when "01" =>
start_next <= ITERATIONS;
when "10" =>
start_next <= ITERATIONS(1 to 31) & '0';
when others => -- "11"
start_next <= (ITERATIONS(1 to 31) & '0') + ITERATIONS;
end case;
next_state <= SETUP_6;
when SETUP_6 =>
-- initialize mySum
mySum_next <= Z32;
-- Calculate end value
endd_next <= start + ITERATIONS;
next_state <= FOR_LOOP_1;
-- Skipping the printf statement
when FOR_LOOP_1 =>
-- Initialize i value
i_next <= start;
next_state <= FOR_LOOP_2;
when FOR_LOOP_2 =>
-- store the value of the a[i] as i
-- note storing as an int instead of a double
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= arrayAddr + (i(2 to 31) & "00");
thrd2intrfc_value <= i;
next_state <= WAIT_STATE;
return_state_next <= FOR_LOOP_3;
when FOR_LOOP_3 =>
-- Load the value of a[i] (which we just set)
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arrayAddr + (i(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= FOR_LOOP_4;
when FOR_LOOP_4 =>
-- increment mySum
mySum_next <= mySum + toUser_value;
next_state <= FOR_LOOP_5;
when FOR_LOOP_5 =>
-- Increment i
i_next <= i + 1;
next_state <= FOR_LOOP_6;
when FOR_LOOP_6 =>
-- Check for end of loop condition
if ( i < endd ) then
next_state <= FOR_LOOP_2;
else
next_state <= END_1;
end if;
when END_1 =>
--push arugment for pthread_mutex_lock
thrd2intrfc_value <= mutexAddr;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= END_2;
when END_2 =>
--call mutex lock
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_END_3;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when END_3 =>
--Initiate the reading of the value of sum
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= sumAddr;
next_state <= WAIT_STATE;
return_state_next <= END_4;
when END_4 =>
--Add value of sum to mySum and store
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= sumAddr;
thrd2intrfc_value <= toUser_value + mySum;
next_state <= WAIT_STATE;
return_state_next <= END_5;
when END_5 =>
--push arugment for pthread_mutex_unlock
thrd2intrfc_value <= mutexAddr;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= END_6;
when END_6 =>
--call mutex unlock
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_EXIT_1;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when FUNCTION_EXIT_1 =>
--push the argument for pthread_exit
--For debug reasons, pushing start instead of NULL
thrd2intrfc_value <= start;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 53549e588b42ded90bdaebe0e292d3c5 | 0.567804 | 3.895105 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/steer_module_read.vhd | 3 | 23,737 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_read.vhd,v 1.2 2003/05/19 17:34:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Read - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: steer_module_read.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- steer_module_read.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 4-26-2002 -- First version
-- ^^^^^^
-- First version of steering logic module.
-- ~~~~~~
-- BLT 11-18-2002 -- Update to version v1.00b
-- ^^^^^^
-- Updated to use ipif_common_v1_00_b, which fixed a simulation problem
-- in the ipif_steer logic
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.STEER_TYPES.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_LARGEST : integer := width of largest device (not access size)
-- attached to the IPIF
-- C_MIRROR_SIZE : integer := smallest unit of data that is mirrored
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity Steer_Module_Read is
generic (
C_DWIDTH_IN : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_OUT : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_OUT : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IN : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end entity Steer_Module_Read;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of Steer_Module_Read is
-------------------------------------------------------------------------------
-- Function max -- returns maximum of x and y
-------------------------------------------------------------------------------
function max(x : integer; y : integer) return integer is
begin
if x > y then return x;
else return y;
end if;
end function max;
-------------------------------------------------------------------------------
-- Function min -- returns minimum of x and y
-------------------------------------------------------------------------------
function min(x : integer; y : integer) return integer is
begin
if x < y then return x;
else return y;
end if;
end function min;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- returns x**y for integers x and y, y>=0
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
function Addr_Start_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Start;
end function Addr_Start_Func;
function Addr_Stop_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Stop;
end function Addr_Stop_Func;
constant Addr_Size : integer_array_type(0 to 63) :=
(1=>1,3=>1,5=>1,7=>1,9=>1,11=>1,13=>1,15=>1,
17=>1,19=>1,21=>1,23=>1,25=>1,27=>1,29=>1,31=>1,
33=>1,35=>1,37=>1,39=>1,41=>1,43=>1,45=>1,47=>1,
49=>1,51=>1,53=>1,55=>1,57=>1,59=>1,61=>1,63=>1,
2=>2,6=>2,10=>2,14=>2,18=>2,22=>2,26=>2,30=>2,
34=>2,38=>2,42=>2,46=>2,50=>2,54=>2,58=>2,62=>2,
4=>4,12=>4,20=>4,28=>4,36=>4,44=>4,52=>4,60=>4,
8=>8,24=>8,40=>8,56=>8,16=>16,48=>16,32=>32,0=>64);
constant IP_Addr_Start : integer := Addr_Start_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
constant IP_Addr_Stop : integer := Addr_Stop_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
MUX_PROCESS: process( Data_In,Decode_size,Addr ) is
variable factor : integer;
variable addr_loop : integer;
variable addr_integer : integer;
variable num_addr_bits : integer;
variable size : integer;
variable address : integer;
variable data_address : integer;
variable replicate_factor : integer;
begin
num_addr_bits := IP_Addr_Stop-IP_Addr_Start+1;
-- Set up default condition
if C_DWIDTH_IN <= C_DWIDTH_OUT then
for i in 0 to C_DWIDTH_OUT/C_DWIDTH_IN-1 loop
Data_Out(i*C_DWIDTH_IN to (i+1)*C_DWIDTH_IN-1) <= Data_In;
end loop;
else
Data_Out <= Data_In(0 to C_DWIDTH_OUT-1);
end if;
if C_DWIDTH_IN > C_SMALLEST_IN then -- Data_Out is a function of Decode_size
for k in log2(C_SMALLEST_IN/8)+1 to log2(C_DWIDTH_IN/8)+1 loop -- 1,2,3,4,5,6,7 6 for now
factor := pwr(2,k)/2; -- 1,2,4,8,16,32,64 number of byte lanes
if Decode_size = Conv_std_logic_vector(k,3) then
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
data_address := address;
if address = 0 then -- special case for address zero
size := factor*8; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
while data_address >= factor loop -- modulo operator since mod doesn't work in Synplify if right side isn't constant
data_address := data_address - factor;
end loop;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(data_address*8 + m);
end loop;
end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
if factor*8 <= C_DWIDTH_OUT then
for m in 0 to C_DWIDTH_OUT/(factor*8)-1 loop
Data_Out(factor*8*m to factor*8*(m+1)-1) <= Data_In(0 to factor*8-1);
end loop;
else
for m in 0 to C_DWIDTH_OUT-1 loop
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end if;
end loop;
else -- Data_Out is not a function of Decode_Size
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
if address = 0 then -- special case for address zero
size := C_DWIDTH_IN; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(address*8+m);
end loop;
end loop;
-- for m in size to C_DWIDTH_OUT-1 loop -- set remaining bits to default
-- Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- mod in case host data bus larger than Data_In
-- end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
for m in 0 to C_DWIDTH_OUT-1 loop -- 0 to 3
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end process MUX_PROCESS;
end architecture IMP;
| bsd-3-clause | 053ad6dc19adac6f990759dec5313e18 | 0.448077 | 3.700811 | false | false | false | false |
1995parham/Learning | vhdl/process/process.vhd | 1 | 1,026 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: process.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity process_t is
end entity;
architecture arch_process_t of process_t is
signal a, b : std_logic := '0';
signal y_normal, y_fun : std_logic := '0';
signal w_normal, w_fun, w_var : std_logic := '0';
begin
a <= '0', '1' after 500 ns, '0' after 1000 ns;
b <= '0';
-- checkout when w_normal signal updated.
process (a, b, y_normal)
begin
y_normal <= a xor b;
w_normal <= y_normal;
end process;
-- checkout when w_fun signal updated.
process (a, b)
begin
y_fun <= a xor b;
w_fun <= y_fun;
end process;
-- checkout when w_var signal updated.
process (a, b)
variable y_var : std_logic;
begin
y_var := a xor b;
w_var <= y_var;
end process;
end architecture arch_process_t;
| gpl-2.0 | 8d4e6ac63fd10bfcedef8cf1de5e4461 | 0.537037 | 3.071856 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_flex_addr_cntr.vhd | 3 | 15,871 | -------------------------------------------------------------------------------
-- $Id: opb_flex_addr_cntr.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_flex_addr_cntr.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_flex_addr_cntr.vhd
--
-- Description:
-- This VHDL design file implements a flexible counter that is used to implement
-- the address counting function needed for OPB Slave devices. It provides the
-- ability to increment addresses in the following manner:
-- - linear incrementing x1, x2, x4, x8, x16, x32, x64, x128 (burst support)
--
-- Special notes:
--
-- - Count enables must be held low during load operations
-- - Clock enables must be asserted during load operations
--
--
--
-- This file also implements the BE generator function.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- opb_flex_addr_cntr.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.1 $
-- Date: $3/11/2003$
--
-- History:
-- DET 3/11/2003 Initial Version
--
--
-- DET 7/10/2003 Granite Rls PLB IPIF V1.00.e
-- ^^^^^^
-- - Removed XON generic from LUT4 component declaration and instances.
-- ~~~~~~
--
-- ALS 12/09/2003
-- ^^^^^^
-- Modified for OPB
-- ~~~~~~
-- ALS 12/24/2003
-- ^^^^^^
-- Removed BE generation
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim; -- Required for Xilinx primitives
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity opb_flex_addr_cntr is
Generic (
C_AWIDTH : integer := 32
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- address generation
Load_Enable : in std_logic;
Load_addr : in std_logic_vector(C_AWIDTH-1 downto 0);
Cnt_by_1 : in std_logic;
Cnt_by_2 : in std_logic;
Cnt_by_4 : in std_logic;
Cnt_by_8 : in std_logic;
Cnt_by_16 : in std_logic;
Cnt_by_32 : in std_logic;
Cnt_by_64 : in std_logic;
Cnt_by_128 : in std_logic;
Clk_En_0 : in std_logic;
Clk_En_1 : in std_logic;
Clk_En_2 : in std_logic;
Clk_En_3 : in std_logic;
Clk_En_4 : in std_logic;
Clk_En_5 : in std_logic;
Clk_En_6 : in std_logic;
Clk_En_7 : in std_logic;
Addr_out : out std_logic_vector(C_AWIDTH-1 downto 0);
Next_addr_out : out std_logic_vector(C_AWIDTH-1 downto 0);
Carry_Out : out std_logic
);
end entity opb_flex_addr_cntr;
architecture implementation of opb_flex_addr_cntr is
-- Constants
-- Types
-- Counter Signals
Signal lut_out : std_logic_vector(C_AWIDTH-1 downto 0);
Signal addr_out_i : std_logic_vector(C_AWIDTH-1 downto 0);
Signal next_addr_i : std_logic_vector(C_AWIDTH-1 downto 0);
Signal Cout : std_logic_vector(C_AWIDTH downto 0);
-- Component Declarations
attribute INIT : string;
begin --(architecture implementation)
-- Misc logic assignments
Addr_out <= addr_out_i;
Next_addr_out <= next_addr_i;
Carry_Out <= Cout(C_AWIDTH);
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ADDR_MSB
--
-- For Generate Description:
-- This For-Gen implements bits 7 and beyond for the the
-- address counter. The entire slice shares the same clock
-- enable.
--
--
--
------------------------------------------------------------
-- GEN_ADDR_MSB : for addr_bit_index in 5 to C_AWIDTH-1 generate
GEN_ADDR_MSB : for addr_bit_index in 7 to C_AWIDTH-1 generate
-- local variables
-- local constants
-- local signals
-- local component declarations
begin
-------------------------------------------------------------------------------
---- Address Counter Bits 7 to max address bit
I_LUT_N : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(addr_bit_index),
I0 => addr_out_i(addr_bit_index),
I1 => '0',
I2 => Load_Enable,
I3 => Load_addr(addr_bit_index)
);
I_MUXCY_N : MUXCY
port map (
DI => '0',
CI => Cout(addr_bit_index),
S => lut_out(addr_bit_index),
O => Cout(addr_bit_index+1)
);
I_XOR_N : XORCY
port map (
LI => lut_out(addr_bit_index),
CI => Cout(addr_bit_index),
O => next_addr_i(addr_bit_index)
);
I_FDRE_N: FDRE
port map (
Q => addr_out_i(addr_bit_index),
C => Clk,
CE => Clk_En_7,
D => next_addr_i(addr_bit_index),
R => Rst
);
end generate GEN_ADDR_MSB;
-------------------------------------------------------------------------------
---- Address Counter Bit 6
I_LUT6 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(6),
I0 => addr_out_i(6),
I1 => Cnt_by_128,
I2 => Load_Enable,
I3 => Load_addr(6)
);
I_MUXCY6 : MUXCY
port map (
DI => Cnt_by_128,
CI => Cout(6),
S => lut_out(6),
O => Cout(7)
);
I_XOR6 : XORCY
port map (
LI => lut_out(6),
CI => Cout(6),
O => next_addr_i(6)
);
I_FDRE6 : FDRE
port map (
Q => addr_out_i(6),
C => Clk,
CE => Clk_En_6,
D => next_addr_i(6),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 5
I_LUT5 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(5),
I0 => addr_out_i(5),
I1 => Cnt_by_64,
I2 => Load_Enable,
I3 => Load_addr(5)
);
I_MUXCY5 : MUXCY
port map (
DI => Cnt_by_64,
CI => Cout(5),
S => lut_out(5),
O => Cout(6)
);
I_XOR5 : XORCY
port map (
LI => lut_out(5),
CI => Cout(5),
O => next_addr_i(5)
);
I_FDRE5: FDRE
port map (
Q => addr_out_i(5),
C => Clk,
CE => Clk_En_5,
D => next_addr_i(5),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 4
I_LUT4 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(4),
I0 => addr_out_i(4),
I1 => Cnt_by_32,
I2 => Load_Enable,
I3 => Load_addr(4)
);
I_MUXCY4 : MUXCY
port map (
DI => Cnt_by_32,
CI => Cout(4),
S => lut_out(4),
O => Cout(5)
);
I_XOR4 : XORCY
port map (
LI => lut_out(4),
CI => Cout(4),
O => next_addr_i(4)
);
I_FDRE4: FDRE
port map (
Q => addr_out_i(4),
C => Clk,
CE => Clk_En_4,
D => next_addr_i(4),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 3
I_LUT3 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(3),
I0 => addr_out_i(3),
I1 => Cnt_by_16,
I2 => Load_Enable,
I3 => Load_addr(3)
);
I_MUXCY3 : MUXCY
port map (
DI => Cnt_by_16,
CI => Cout(3),
S => lut_out(3),
O => Cout(4)
);
I_XOR3 : XORCY
port map (
LI => lut_out(3),
CI => Cout(3),
O => next_addr_i(3)
);
I_FDRE3: FDRE
port map (
Q => addr_out_i(3),
C => Clk,
CE => Clk_En_3,
D => next_addr_i(3),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 2
I_LUT2 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(2),
I0 => addr_out_i(2),
I1 => Cnt_by_8,
I2 => Load_Enable,
I3 => Load_addr(2)
);
I_MUXCY2 : MUXCY
port map (
DI => Cnt_by_8,
CI => Cout(2),
S => lut_out(2),
O => Cout(3)
);
I_XOR2 : XORCY
port map (
LI => lut_out(2),
CI => Cout(2),
O => next_addr_i(2)
);
I_FDRE2: FDRE
port map (
Q => addr_out_i(2),
C => Clk,
CE => Clk_En_2,
D => next_addr_i(2),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 1
I_LUT1 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(1),
I0 => addr_out_i(1),
I1 => Cnt_by_4,
I2 => Load_Enable,
I3 => Load_addr(1)
);
I_MUXCY1 : MUXCY
port map (
DI => Cnt_by_4,
CI => Cout(1),
S => lut_out(1),
O => Cout(2)
);
I_XOR1 : XORCY
port map (
LI => lut_out(1),
CI => Cout(1),
O => next_addr_i(1)
);
I_FDRE1: FDRE
port map (
Q => addr_out_i(1),
C => Clk,
CE => Clk_En_1,
D => next_addr_i(1),
R => Rst
);
-------------------------------------------------------------------------------
---- Address Counter Bit 0
I_LUT0 : LUT4
generic map(
INIT => X"F202"
)
port map (
O => lut_out(0),
I0 => addr_out_i(0),
I1 => Cnt_by_2,
I2 => Load_Enable,
I3 => Load_addr(0)
);
I_MUXCY0 : MUXCY
port map (
DI => Cnt_by_2,
CI => Cout(0),
S => lut_out(0),
O => Cout(1)
);
I_XOR0 : XORCY
port map (
LI => lut_out(0),
CI => Cout(0),
O => next_addr_i(0)
);
I_FDRE0: FDRE
port map (
Q => addr_out_i(0),
C => Clk,
CE => Clk_En_0,
D => next_addr_i(0),
R => Rst
);
-------------------------------------------------------------------------------
---- Carry in selection for LS Bit
I_MUXCY : MUXCY
port map (
DI => Cnt_by_1,
CI => '0',
S => Load_Enable,
O => Cout(0)
);
end implementation;
| bsd-3-clause | 19bd79b17ca2447b75f708e38e10907f | 0.412387 | 3.980687 | false | false | false | false |
iocoder/graduation | hardware/cpu/cache.vhd | 1 | 17,027 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.cpu_pkg.all;
entity cache is
Port (
CLK : in STD_LOGIC;
CACHE_EN : in STD_LOGIC;
STALL : out STD_LOGIC;
-- CPU interface
iMEME : in STD_LOGIC;
iRW : in STD_LOGIC;
iADDR : in STD_LOGIC_VECTOR (31 downto 0);
iDin : in STD_LOGIC_VECTOR (31 downto 0);
iDout : out STD_LOGIC_VECTOR (31 downto 0);
iDTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
dMEME : in STD_LOGIC;
dRW : in STD_LOGIC;
dADDR : in STD_LOGIC_VECTOR (31 downto 0);
dDin : in STD_LOGIC_VECTOR (31 downto 0);
dDout : out STD_LOGIC_VECTOR (31 downto 0);
dDTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
-- system bus interface
MEME : out STD_LOGIC := '0';
RW : out STD_LOGIC := '0';
ADDR : out STD_LOGIC_VECTOR (31 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : out STD_LOGIC_VECTOR ( 2 downto 0);
RDY : in STD_LOGIC
);
end entity;
architecture Behavioral of cache is
component cachearray is
Port (
CLK : in STD_LOGIC;
-- bus interface
RW : in STD_LOGIC;
RD_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
WR_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
-- inputs
Vin : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
TAGin : in STD_LOGIC_VECTOR (19 downto 0);
-- outputs
Vout : out STD_LOGIC;
Dout : out STD_LOGIC_VECTOR (31 downto 0);
TAGout : out STD_LOGIC_VECTOR (19 downto 0)
);
end component;
-- stall signal
signal STALLout : STD_LOGIC := '0';
-- phase
signal phase : integer range 0 to 15 := 0;
--------------------------------------------------------------------------------
-- R/W BUFFER --
--------------------------------------------------------------------------------
constant BUFFER_SIZE : integer := 10;
signal buf_head : integer range 0 to 100 := 0;
signal buf_tail : integer range 0 to 100 := 0;
signal buf_cycle : integer range 0 to 100 := 0;
type buf_entry_t is record
USED : BOOLEAN;
RW : STD_LOGIC;
ADDR : STD_LOGIC_VECTOR (31 downto 0);
DATA : STD_LOGIC_VECTOR (31 downto 0);
DTYPE : STD_LOGIC_VECTOR ( 2 downto 0);
DSRC : STD_LOGIC; -- instruction cache or data cache
end record buf_entry_t;
type buf_t is array (0 to BUFFER_SIZE-1) of buf_entry_t;
signal buf0 : buf_entry_t := (USED => false, RW => '0',
ADDR => x"00000000", DATA => x"00000000",
DTYPE => "000", DSRC => '0');
signal buf1 : buf_entry_t := (USED => false, RW => '0',
ADDR => x"00000000", DATA => x"00000000",
DTYPE => "000", DSRC => '0');
signal cur_buf : buf_entry_t;
--------------------------------------------------------------------------------
-- CACHE PARAMETERS --
--------------------------------------------------------------------------------
-- +-------+-------+--------+
-- | TAG | INDEX | OFFSET |
-- +-------+-------+--------+
-- 20 10 2
constant CACHE_LINES : integer range 0 to 100000 := 1024;
constant OFFSET_BITS : integer range 0 to 100000 := 2;
constant INDEX_BITS : integer range 0 to 100000 := 10;
constant INDEX_LOW : integer range 0 to 100000 := 2;
constant INDEX_HIGH : integer range 0 to 100000 := 11;
constant TAG_BITS : integer range 0 to 100000 := 20;
constant TAG_LOW : integer range 0 to 100000 := 12;
constant TAG_HIGH : integer range 0 to 100000 := 31;
-- icache interface
signal icache_rw : std_logic := '0';
signal icache_rd_v : std_logic;
signal icache_rd_data : std_logic_vector(31 downto 0);
signal icache_rd_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal icache_wr_index : std_logic_vector(INDEX_BITS-1 downto 0);
signal icache_wr_v : std_logic;
signal icache_wr_data : std_logic_vector(31 downto 0);
signal icache_wr_tag : std_logic_vector(TAG_BITS-1 downto 0);
-- dcache interface
signal dcache_rw : std_logic := '0';
signal dcache_rd_v : std_logic;
signal dcache_rd_data : std_logic_vector(31 downto 0);
signal dcache_rd_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal dcache_wr_index : std_logic_vector(INDEX_BITS-1 downto 0);
signal dcache_wr_v : std_logic;
signal dcache_wr_data : std_logic_vector(31 downto 0);
signal dcache_wr_tag : std_logic_vector(TAG_BITS-1 downto 0);
-- detect cache hits
signal icache_hit : boolean;
signal dcache_hit : boolean;
begin
--------------------------------------------------------------------------------
-- CACHE ARRAYS --
--------------------------------------------------------------------------------
C1: cachearray port map (
CLK, icache_rw, iADDR(INDEX_HIGH downto INDEX_LOW), icache_wr_index,
icache_wr_v, icache_wr_data, icache_wr_tag,
icache_rd_v, icache_rd_data, icache_rd_tag
);
C2: cachearray port map (
CLK, dcache_rw, dADDR(INDEX_HIGH downto INDEX_LOW), dcache_wr_index,
dcache_wr_v, dcache_wr_data, dcache_wr_tag,
dcache_rd_v, dcache_rd_data, dcache_rd_tag
);
-- detect cache hits
icache_hit <= icache_rd_v = '1' and
icache_rd_tag = iADDR(TAG_HIGH downto TAG_LOW);
dcache_hit <= dcache_rd_v = '1' and
dcache_rd_tag = dADDR(TAG_HIGH downto TAG_LOW);
--------------------------------------------------------------------------------
-- FINITE STATE MACHINE --
--------------------------------------------------------------------------------
-- Synchronization note:
--
-- pipeline cycle begins with rising edge of even cache cycles:
-- _ _ _ _ _ _
-- | |_| |_| |_| |_| |_| |_
-- + + + + pipeline cycles
-- ^ ^ ^ ^ ^ ^ ^ cache array cycles
-- 001111000011110000111100 phase variable
--
-- if a cache miss occurs, phase will be updated from 1 to 2
-- instead of going back to 0, and STALLout will be set to 1.
--
process(CLK)
variable buf_empty : boolean := true;
function extract(dtype : in STD_LOGIC_VECTOR (2 downto 0);
addr : in STD_LOGIC_VECTOR (31 downto 0);
word : in STD_LOGIC_VECTOR (31 downto 0))
return STD_LOGIC_VECTOR is
variable retval : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
begin
if (dtype = "001") then
if (addr(1 downto 0) = "00") then
retval := x"000000" & word(7 downto 0);
elsif (addr(1 downto 0) = "01") then
retval := x"000000" & word(15 downto 8);
elsif (addr(1 downto 0) = "10") then
retval := x"000000" & word(23 downto 16);
else
retval := x"000000" & word(31 downto 24);
end if;
elsif (dtype = "010") then
if (addr(1) = '0') then
retval := x"0000" & word(15 downto 0);
elsif (addr(1) = '1') then
retval := x"0000" & word(31 downto 16);
end if;
else
retval := word;
end if;
return retval;
end extract;
function merge(dtype : in STD_LOGIC_VECTOR (2 downto 0);
addr : in STD_LOGIC_VECTOR (31 downto 0);
orig : in STD_LOGIC_VECTOR (31 downto 0);
word : in STD_LOGIC_VECTOR (31 downto 0))
return STD_LOGIC_VECTOR is
variable retval : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
begin
if (dtype = "001") then
if (addr(1 downto 0) = "00") then
retval:=orig(31 downto 8)&word(7 downto 0);
elsif (addr(1 downto 0) = "01") then
retval:=orig(31 downto 16)&word(7 downto 0)&orig(7 downto 0);
elsif (addr(1 downto 0) = "10") then
retval:=orig(31 downto 24)&word(7 downto 0)&orig(15 downto 0);
else
retval:=word(7 downto 0)&orig(23 downto 0);
end if;
elsif (dtype = "010") then
if (addr(1) = '0') then
retval := orig(31 downto 16) & word(15 downto 0);
elsif (addr(1) = '1') then
retval := word(15 downto 0) & orig(15 downto 0);
end if;
else
retval := word;
end if;
return retval;
end merge;
function cacheable(addr : in STD_LOGIC_VECTOR (31 downto 0))
return STD_LOGIC is
begin
if (addr(31 downto 24) = x"1E") then
return '0';
else
return '1';
end if;
end cacheable;
begin
-- TODO: set cachearray clock to rising edge.
if ( CLK='0' and CLK'event and CACHE_EN = '1' ) then
-- execute fsm
if (phase = 0) then
-------------------
-- initial delay --
-------------------
-- wait until address is resolved and cache array is queried
phase <= 1;
elsif (phase = 1) then
-------------------------------
-- cache hit/miss processing --
-------------------------------
-- detect cache misses:
buf_empty := true;
if (iMEME = '1') then
if (iRW = '1' or not icache_hit) then
-- icache miss
buf0.USED <= true;
buf_empty := false;
else
iDout <= icache_rd_data;
end if;
end if;
if (dMEME = '1') then
if (dRW = '1' or not dcache_hit) then
-- dcache miss
buf1.USED <= true;
buf_empty := false;
else
dDout <= extract(dDTYPE, dADDR, dcache_rd_data);
end if;
end if;
-- determine next phase
if (buf_empty) then
-- no cache misses.
phase <= 0;
else
-- there is at least one cache miss
phase <= 2;
STALLout <= '1';
end if;
elsif (phase = 2) then
-- icache miss or write through
buf0.RW <= iRW;
buf0.ADDR <= iADDR;
buf0.DATA <= iDin;
buf0.DTYPE <= iDTYPE;
buf0.DSRC <= '0';
-- dcache miss or write through
buf1.RW <= dRW;
buf1.ADDR <= dADDR;
buf1.DATA <= dDin;
buf1.DTYPE <= dDTYPE;
buf1.DSRC <= '1';
-- reset buffer head
buf_head <= 0;
buf_cycle <= 0;
-- jump to next phase
phase <= 3;
elsif (phase = 3) then
-- note: removing this state corrupts the design cuz
-- CLK25 and CLK50 of pipeline become no longer synced.
phase <= 4;
elsif (phase = 4) then
-----------------------
-- buffer processing --
-----------------------
if (buf_cycle = 0) then
-- setup memory interface
if (buf_head = 0) then
if (buf0.used) then
MEME <= '1';
RW <= buf0.RW;
Dout <= buf0.DATA;
if (buf0.RW = '0') then
DTYPE <= "100";
ADDR <= buf0.ADDR(31 downto 2) & "00";
else
ADDR <= buf0.ADDR;
DTYPE <= buf0.DTYPE;
end if;
buf0.used <= FALSE;
cur_buf <= buf0;
buf_cycle <= buf_cycle + 1;
else
buf_cycle <= 27;
end if;
else
if (buf1.used) then
MEME <= '1';
RW <= buf1.RW;
Dout <= buf1.DATA;
if (buf1.RW='0' and cacheable(buf1.ADDR)='1') then
DTYPE <= "100";
ADDR <= buf1.ADDR(31 downto 2) & "00";
else
ADDR <= buf1.ADDR;
DTYPE <= buf1.DTYPE;
end if;
buf1.used <= FALSE;
cur_buf <= buf1;
buf_cycle <= buf_cycle + 1;
else
buf_cycle <= 27;
end if;
end if;
elsif (buf_cycle < 25) then
if (buf_cycle > 3 and RDY = '1') then
buf_cycle <= 25;
else
buf_cycle <= buf_cycle + 1;
end if;
elsif (buf_cycle = 25) then
-- read in data if read operation
if (cur_buf.RW = '0') then
-- read operation
if (cur_buf.DSRC = '0') then
-- IMEM read
iDout <= Din;
icache_rw <= cacheable(cur_buf.ADDR);
icache_wr_index <=
cur_buf.ADDR(INDEX_HIGH downto INDEX_LOW);
icache_wr_v <= '1';
icache_wr_data <= Din;
icache_wr_tag <=
cur_buf.ADDR(TAG_HIGH downto TAG_LOW);
else
-- DMEM read
if (cacheable(cur_buf.ADDR) = '1') then
dDout <= extract(dDTYPE, dADDR, Din);
else
dDout <= Din;
end if;
dcache_rw <= cacheable(cur_buf.ADDR);
dcache_wr_index <=
cur_buf.ADDR(INDEX_HIGH downto INDEX_LOW);
dcache_wr_v <= '1';
dcache_wr_data <= Din;
dcache_wr_tag <=
cur_buf.ADDR(TAG_HIGH downto TAG_LOW);
end if;
elsif (cur_buf.DTYPE = "100") then
-- write word operation
if (cur_buf.DSRC = '0') then
-- IMEM write word
else
-- DMEM write word
dcache_rw <= cacheable(cur_buf.ADDR);
dcache_wr_index <=
cur_buf.ADDR(INDEX_HIGH downto INDEX_LOW);
dcache_wr_v <= '1';
dcache_wr_data <= cur_buf.DATA;
dcache_wr_tag <=
cur_buf.ADDR(TAG_HIGH downto TAG_LOW);
end if;
else
-- write byte/half operation
if (cur_buf.DSRC = '0') then
else
-- DMEM write byte/half
if (dcache_hit) then
-- found in cache, do merge
dcache_rw <= cacheable(cur_buf.ADDR);
dcache_wr_index <=
cur_buf.ADDR(INDEX_HIGH downto INDEX_LOW);
dcache_wr_v <= '1';
dcache_wr_data <= merge(cur_buf.DTYPE,
cur_buf.ADDR,
dcache_rd_data,
cur_buf.DATA);
dcache_wr_tag <=
cur_buf.ADDR(TAG_HIGH downto TAG_LOW);
end if;
end if;
end if;
buf_cycle <= buf_cycle + 1;
elsif (buf_cycle = 26) then
buf_cycle <= buf_cycle + 1;
elsif (buf_cycle = 27) then
icache_rw <= '0';
dcache_rw <= '0';
MEME <= '0';
RW <= '0';
ADDR <= x"00000000";
Dout <= x"00000000";
DTYPE <= "000";
if (buf_head = 1) then
phase <= 0;
STALLout <= '0';
else
buf_head <= buf_head + 1;
end if;
buf_cycle <= 0;
end if;
elsif (phase = 5) then
phase <= 0;
end if;
end if;
end process;
-- stall
STALL <= STALLout;
end Behavioral;
| gpl-3.0 | 909ff548363c95e103f11293d13f7c86 | 0.424444 | 4.285678 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_fifo.vhd | 1 | 5,964 | --------------------------------------------------------------------------------
-- Title : FIFO for DMA
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_fifo.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 18/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of a fifo 256 x 32bit with logic.
-- A almost full and almost empty bit are generated.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_dma_fifo.vhd,v $
-- Revision 1.1 2012/03/29 10:14:43 MMiehling
-- Initial Revision
--
-- Revision 1.5 2006/05/18 14:02:24 MMiehling
-- changed fifo depth from 16 to 64
--
-- Revision 1.1 2005/10/28 17:52:25 mmiehling
-- Initial Revision
--
-- Revision 1.4 2004/11/02 11:19:41 mmiehling
-- changed sclr to aclr
--
-- Revision 1.3 2004/08/13 15:41:14 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:24 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:51 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY vme_dma_fifo IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
fifo_clr : IN std_logic;
fifo_wr : IN std_logic;
fifo_rd : IN std_logic;
fifo_dat_i : IN std_logic_vector(31 DOWNTO 0);
fifo_dat_o : OUT std_logic_vector(31 DOWNTO 0);
fifo_almost_full : OUT std_logic; -- two words can be written before fifo is full
fifo_almost_empty : OUT std_logic; -- one word is in fifo before empty
fifo_full : OUT std_logic; -- fifo is full
fifo_empty : OUT std_logic -- fifo is empty
);
END vme_dma_fifo;
ARCHITECTURE vme_dma_fifo_arch OF vme_dma_fifo IS
constant CONST_FIFO_SIZE : integer := 512;
SIGNAL fifo_usedw : std_logic_vector(8 DOWNTO 0);
SIGNAL low_level : std_logic:='0';
SIGNAL dat_o : std_logic_vector(31 DOWNTO 0);
BEGIN
PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
fifo_almost_full <= '0';
fifo_full <= '0';
fifo_empty <= '1';
fifo_almost_empty <= '0';
fifo_dat_o <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
-- indicate whether two words can be written to fifo before full
IF fifo_usedw = conv_std_logic_vector(CONST_FIFO_SIZE-3, 9) AND fifo_wr = '1' THEN
fifo_almost_full <= '1';
ELSIF fifo_rd = '1' THEN
fifo_almost_full <= '0';
END IF;
-- indicate whether fifo is full
IF fifo_usedw = conv_std_logic_vector(CONST_FIFO_SIZE-2, 9) AND fifo_wr = '1' THEN
fifo_full <= '1';
ELSIF fifo_rd = '1' THEN
fifo_full <= '0';
END IF;
-- indicate whether fifo is empty
IF fifo_usedw = conv_std_logic_vector(1, 9) AND fifo_rd = '1' THEN
fifo_empty <= '1';
ELSIF fifo_wr = '1' THEN
fifo_empty <= '0';
END IF;
-- indicate whether one word can be read before empty
IF fifo_usedw = conv_std_logic_vector(2, 9) AND fifo_rd = '1' THEN
fifo_almost_empty <= '1';
ELSIF fifo_usedw = conv_std_logic_vector(0, 9) AND fifo_wr = '1' THEN -- if fifo is empty an one word gets written
fifo_almost_empty <= '1';
ELSIF fifo_wr = '1' OR fifo_rd = '1' THEN
fifo_almost_empty <= '0';
END IF;
-- register for convertion of look-ahead fifo to normal fifo behaviour
IF fifo_clr = '1' THEN
fifo_dat_o <= (OTHERS => '0');
ELSIF fifo_rd = '1' THEN
fifo_dat_o <= dat_o;
END IF;
END IF;
END PROCESS;
fifo: scfifo --256x32bit
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Cyclone IV GX",
lpm_numwords => 512,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 32,
lpm_widthu => 9,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON")
PORT MAP (
aclr => fifo_clr,
clock => clk,
data => fifo_dat_i,
rdreq => fifo_rd,
wrreq => fifo_wr,
usedw => fifo_usedw,
q => dat_o);
END vme_dma_fifo_arch;
| gpl-3.0 | 2d10d7e0a11c1c3bf5fba5312d300a5f | 0.508719 | 3.852713 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/acc_vadd/solution1/syn/vhdl/acc_vadd.vhd | 4 | 5,291 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acc_vadd is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
sI1_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
sI1_TVALID : IN STD_LOGIC;
sI1_TREADY : OUT STD_LOGIC;
sI2_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
sI2_TVALID : IN STD_LOGIC;
sI2_TREADY : OUT STD_LOGIC;
mO1_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
mO1_TVALID : OUT STD_LOGIC;
mO1_TREADY : IN STD_LOGIC );
end;
architecture behav of acc_vadd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"acc_vadd,hls_ip_2014_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg900-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.600000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_sig_bdd_23 : BOOLEAN;
signal ap_sig_ioackin_mO1_TREADY : STD_LOGIC;
signal ap_reg_ioackin_mO1_TREADY : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_48 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_mO1_TREADY assign process. --
ap_reg_ioackin_mO1_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_0;
else
if ((ap_ST_st1_fsm_0 = ap_CS_fsm)) then
if (not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY)))) then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_0;
elsif (ap_sig_bdd_48) then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(sI1_TVALID, sI2_TVALID)
begin
ap_sig_bdd_23 <= ((sI1_TVALID = ap_const_logic_0) or (sI2_TVALID = ap_const_logic_0));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(mO1_TREADY, ap_sig_bdd_23)
begin
ap_sig_bdd_48 <= (not(ap_sig_bdd_23) and (ap_const_logic_1 = mO1_TREADY));
end process;
-- ap_sig_ioackin_mO1_TREADY assign process. --
ap_sig_ioackin_mO1_TREADY_assign_proc : process(mO1_TREADY, ap_reg_ioackin_mO1_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_mO1_TREADY)) then
ap_sig_ioackin_mO1_TREADY <= mO1_TREADY;
else
ap_sig_ioackin_mO1_TREADY <= ap_const_logic_1;
end if;
end process;
mO1_TDATA <= std_logic_vector(unsigned(sI2_TDATA) + unsigned(sI1_TDATA));
-- mO1_TVALID assign process. --
mO1_TVALID_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_reg_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_23) and (ap_const_logic_0 = ap_reg_ioackin_mO1_TREADY))) then
mO1_TVALID <= ap_const_logic_1;
else
mO1_TVALID <= ap_const_logic_0;
end if;
end process;
-- sI1_TREADY assign process. --
sI1_TREADY_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY))))) then
sI1_TREADY <= ap_const_logic_1;
else
sI1_TREADY <= ap_const_logic_0;
end if;
end process;
-- sI2_TREADY assign process. --
sI2_TREADY_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY))))) then
sI2_TREADY <= ap_const_logic_1;
else
sI2_TREADY <= ap_const_logic_0;
end if;
end process;
end behav;
| bsd-3-clause | bf5d2fb9ae8dbf2566279386dd569a43 | 0.56719 | 3.026888 | false | false | false | false |
michaelmiehling/A25_VME | Source/wb_adr_dec.vhd | 1 | 5,389 |
---------------------------------------------------------------
-- Title : Adress decoder for whisbone bus
-- Project : <A025-00>
---------------------------------------------------------------
-- File : wb_adr_dec.vhd
-- Author : Chameleon_V2.exe
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2017/6/1 - 12:2:21
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description : Created with Chameleon_V2.exe
-- v1.18
-- 2016-06-14
--
--
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 10 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 200 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- | 16z002-01 VME CR/CSR | 9 | 0 | 1000000 | 4 |
-- +-------------------------------+-----+----------+----------+-----+
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2017, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
ENTITY wb_adr_dec IS
PORT (
pci_cyc_i : IN std_logic_vector(4 DOWNTO 0);
wbm_adr_o_q : IN std_logic_vector(31 DOWNTO 2);
wbm_cyc_o : OUT std_logic_vector(9 DOWNTO 0)
);
END wb_adr_dec;
ARCHITECTURE wb_adr_dec_arch OF wb_adr_dec IS
SIGNAL zero : std_logic_vector(4 DOWNTO 0);
BEGIN
zero <= (OTHERS => '0');
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(9 DOWNTO 0);
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 10 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 4) = "00000000100000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "010000000" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CR/CSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF pci_cyc_i /= zero AND wbm_cyc_o_int = "0000000000" THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
END wb_adr_dec_arch;
| gpl-3.0 | b84fdb7a33b177b5d413f7ad430ad4bc | 0.403229 | 3.353454 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux.vhd | 3 | 7,007 | -------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET Apr-25-01 -- First version
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ip2bus_srmux is
port (
-- Status Reply inputs from the IP
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Write FIFO
WFIFO_WrAck : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the Read FIFO
RFIFO_WrAck : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_Error : in std_logic;
RFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the DMA/SG engine
DMA2Bus_WrAck : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_Error : in std_logic;
DMA2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Interrupt Collector
IRPT_WrAck : in std_logic;
IRPT_RdAck : in std_logic;
IRPT_Retry : in std_logic;
IRPT_Error : in std_logic;
IRPT_ToutSup : in std_logic;
-- Status reply from the Reset block
RESET_WrAck : In std_logic;
RESET_RdAck : in std_logic;
RESET_Retry : in std_logic;
RESET_Error : in std_logic;
RESET_ToutSup : in std_logic;
-- Status Reply outputs to the Slave Attachment
IP2Bus_WrAck_mx : out std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_ToutSup_mx : out std_logic
);
end ip2bus_srmux;
architecture implementation of ip2bus_srmux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
-- The following code is for a simple 'OR' function of the input signals
-- to generate a single output. This method works in place of a multiplexer
-- since by definition inactive signals are driven to a logic '0'.
-- Combinational logic
IP2Bus_WrAck_mx <= IP2Bus_WrAck or
WFIFO_WrAck or
RFIFO_WrAck or
DMA2Bus_WrAck or
IRPT_WrAck or
RESET_WrAck;
IP2Bus_RdAck_mx <= IP2Bus_RdAck or
WFIFO_RdAck or
RFIFO_RdAck or
DMA2Bus_RdAck or
IRPT_RdAck or
RESET_RdAck;
IP2Bus_Retry_mx <= IP2Bus_Retry or
WFIFO_Retry or
RFIFO_Retry or
DMA2Bus_Retry or
IRPT_Retry or
RESET_Retry;
IP2Bus_Error_mx <= IP2Bus_Error or
WFIFO_Error or
RFIFO_Error or
DMA2Bus_Error or
IRPT_Error or
RESET_Error;
IP2Bus_ToutSup_mx <= IP2Bus_ToutSup or
WFIFO_ToutSup or
RFIFO_ToutSup or
DMA2Bus_ToutSup or
IRPT_ToutSup or
RESET_ToutSup;
end implementation;
| bsd-3-clause | a821530dc2e15217c89f7a4058c7ad5e | 0.37434 | 5.171218 | false | false | false | false |
iocoder/graduation | hardware/vga/vgaram.vhd | 1 | 1,444 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaram is
Port (CLK : in STD_LOGIC;
-- sequencer port:
SeqReadEnable : in STD_LOGIC;
SeqAddr : in STD_LOGIC_VECTOR (10 downto 0);
SeqDataOut : out STD_LOGIC_VECTOR ( 8 downto 0) := "000000000";
-- GU port:
GUReadEnable : in STD_LOGIC;
GUWriteEnable : in STD_LOGIC;
GUAddr : in STD_LOGIC_VECTOR (10 downto 0);
GUDataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
GUDataOut : out STD_LOGIC_VECTOR ( 8 downto 0));
end vgaram;
architecture Behavioral of vgaram is
type ram_t is array (0 to 2047) of STD_LOGIC_VECTOR (8 downto 0);
signal ram : ram_t := (others => "0" & x"1F");
begin
process (clk)
begin
if (clk = '0' and clk'event) then
if (GUWriteEnable = '1') then
ram(conv_integer(unsigned(GUAddr))) <= GUDataIn;
end if;
if (GUReadEnable = '1') then
SeqDataOut <= "000000000";
GUDataOut <= ram(conv_integer(unsigned(GUAddr)));
elsif (SeqReadEnable = '1') then
SeqDataOut <= ram(conv_integer(unsigned(SeqAddr)));
GUDataOut <= "000000000";
else
SeqDataOut <= "000000000";
GUDataOut <= "000000000";
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | d5869a6ac46f0301ef2f82e3876793bd | 0.563712 | 3.655696 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma.vhd | 1 | 24,988 | --------------------------------------------------------------------------------
-- Title : DMA for VME Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : dma.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 24/06/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The vme core has a DMA controller for high performance data transfers between
-- the SRAM, PCI space and VMEbus. It is operated through a series of registers
-- that control the source/destination for the data, length of the transfer and
-- the transfer protocol (A24 or A32) to be used. These registers are not
-- directly accessible, but they will be loaded with the content of the Buffer
-- Descriptor(s) located in the local SRAM.
-- One buffer descriptor may be linked to the next buffer descriptor, such that
-- when the DMA has completed the operations described by one buffer descriptor,
-- it automatically moves on to the next buffer descriptor in the local SRAM
-- list. The last buffer descriptor is reached, when the DMA_NULL bit is set in
-- the corresponding buffer descriptor. The maximum number of linked buffer
-- descriptors is 112.
-- The DMA supports interrupt assertion when all specified buffer descriptors
-- are processed (signaled via dma_irq to PCIe, see DMA_IEN).
-- The DMA controller is able to transfer data from the SRAM, PCI space and
-- VMEbus to each other. For this reason source and/or destination address can
-- be incremented or not depending on the settings. The source and destination
-- address must be 8-byte aligned to each other.
-- The scatter-gather list is located in the local SRAM area, so a DMA can also
-- be initiated by an external VME master by accessing the SRAM via A24/A32
-- slave and the DMA Status Register via A16 slave.
-- If transfers to PCI space has to be done, the used memory space must be
-- allocated for this function in order to prevent data mismatch!
-- If DMA functionality is used, the entire local SRAM cannot be used by other
-- functions, because the buffer descriptors are located at the end of this!
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_mstr
-- vme_dma_slv
-- vme_dma_arbiter
-- vme_dma_du
-- vme_dma_au
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_dma.vhd,v $
-- Revision 1.2 2013/09/12 08:45:30 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.1 2012/03/29 10:14:48 MMiehling
-- Initial Revision
--
-- Revision 1.4 2006/05/18 14:02:16 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:20 mmiehling
-- Initial Revision
--
-- Revision 1.3 2004/08/13 15:41:08 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:15 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:46 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
irq_o : OUT std_logic;
-- vme_du
dma_sta : IN std_logic_vector(9 DOWNTO 0);
clr_dma_en : OUT std_logic;
set_dma_err : OUT std_logic;
dma_act_bd : OUT std_logic_vector(7 DOWNTO 4);
-- wb-slave
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
sel_i : IN std_logic_vector(3 DOWNTO 0);
adr_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
-- wb-master
stb_o : OUT std_logic;
ack_i : IN std_logic;
we_o : OUT std_logic;
cti : OUT std_logic_vector(2 DOWNTO 0);
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
err_i : IN std_logic;
cyc_o_sram : OUT std_logic;
cyc_o_vme : OUT std_logic;
cyc_o_pci : OUT std_logic;
sel_o : OUT std_logic_vector(3 DOWNTO 0);
adr_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0)
);
END vme_dma;
ARCHITECTURE vme_dma_arch OF vme_dma IS
COMPONENT vme_dma_arbiter
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- vme_dma_slv
slv_req : IN std_logic;
slv_ack : OUT std_logic;
-- vme_dma_mstr
mstr_req : IN std_logic;
mstr_ack : OUT std_logic;
-- result
arbit_slv : OUT std_logic -- if set, vme_dma_slv has access and vica verse
);
END COMPONENT;
COMPONENT vme_dma_slv
PORT (
rst : IN std_logic;
clk : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
slv_req : OUT std_logic;
slv_ack : IN std_logic
);
END COMPONENT;
COMPONENT vme_dma_au
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_signals
adr_o : OUT std_logic_vector(31 DOWNTO 0); -- adress for wb-bus
sel_o : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for wb_bus
we_o : OUT std_logic; -- write/read
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
cyc_o_sram : OUT std_logic; -- chip select for sram
cyc_o_pci : OUT std_logic; -- chip select for pci
cyc_o_vme : OUT std_logic; -- chip select for vme
stb_o : IN std_logic; -- request signal for cyc switching
-- fifo
fifo_empty : in std_logic;
fifo_full : in std_logic;
-- vme_dma_mstr
sour_dest : IN std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : IN std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : IN std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : OUT std_logic; -- if all data from one bd was read and stored in the fifo
load_cnt : IN std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : OUT std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : out std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : out std_logic; -- if all data from one bd was read and stored in the fifo
clr_dma_act_bd : IN std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
dma_act_bd : OUT std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
dma_dest_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : IN std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : IN std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : IN std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : IN std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0) -- size of data package
);
END COMPONENT;
COMPONENT vme_dma_du
PORT (
rst : IN std_logic;
clk : IN std_logic;
dma_sta : IN std_logic_vector(9 DOWNTO 0);
irq_o : OUT std_logic; -- irq for cpu; asserted when done or error (if enabled)
arbit_slv : IN std_logic; -- if set, dma_slv has access and vica verse
slv_ack : IN std_logic; -- if set, write from slave side will be done
mstr_ack : IN std_logic; -- if set, write from master side will be done
-- slave signals
adr_i : IN std_logic_vector(6 DOWNTO 2);
sel_i : IN std_logic_vector(3 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
we_i : IN std_logic;
ack_o : IN std_logic;
-- wb_master singals
adr_o : IN std_logic_vector(6 DOWNTO 2);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vme_dma_au
dma_act_bd : IN std_logic_vector(7 DOWNTO 4); -- active bd number
dma_dest_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : OUT std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : OUT std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : OUT std_logic; -- indicates if source adress should be incremented
inc_dest : OUT std_logic; -- indicates if destination adress should be incremented
dma_size : OUT std_logic_vector(15 DOWNTO 0); -- size of data package
clr_dma_act_bd : OUT std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- dma_mstr
set_dma_err : IN std_logic; -- sets dma error bit if vme error
clr_dma_en : IN std_logic; -- clears dma en bit if dma_mstr has done
dma_en : OUT std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : OUT std_logic; -- indicates the last bd
en_mstr_dat_i_reg : IN std_logic -- enable for data in
);
END COMPONENT;
COMPONENT vme_dma_mstr
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_master_bus
stb_o : OUT std_logic; -- request for wb_mstr_bus
ack_i : IN std_logic; -- acknoledge from wb_mstr_bus
err_i : IN std_logic; -- error answer from slave
cti : OUT std_logic_vector(2 DOWNTO 0);
-- fifo
fifo_empty : IN std_logic; -- indicates that no more data is available
fifo_full : in std_logic; -- indicates that no more data can be stored in fifo
fifo_almost_full : IN std_logic; -- indicates that only one data can be stored in the fifo
fifo_almost_empty : IN std_logic; -- indicates that only one data is stored in the fifo
fifo_wr : OUT std_logic; -- if asserted, fifo will be filled with another data
fifo_rd : OUT std_logic; -- if asserted, data will be read out from fifo
-- vme_dma_au
sour_dest : OUT std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : OUT std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : OUT std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
dma_act_bd : IN std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
load_cnt : OUT std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
we_o_int : IN std_logic;
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
set_dma_err : OUT std_logic; -- sets dma error bit if vme error
clr_dma_en : OUT std_logic; -- clears dma en bit if dma_mstr has done
dma_en : IN std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : IN std_logic; -- indicates the last bd
en_mstr_dat_i_reg : OUT std_logic; -- enable for data in
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0); -- size of data package
-- arbiter
mstr_req : OUT std_logic -- request for internal register access
);
END COMPONENT;
COMPONENT vme_dma_fifo
PORT (
rst : IN std_logic;
clk : IN std_logic;
fifo_clr : IN std_logic;
fifo_wr : IN std_logic;
fifo_rd : IN std_logic;
fifo_dat_i : IN std_logic_vector(31 DOWNTO 0);
fifo_dat_o : OUT std_logic_vector(31 DOWNTO 0);
fifo_almost_full : OUT std_logic;
fifo_almost_empty : OUT std_logic;
fifo_full : OUT std_logic;
fifo_empty : OUT std_logic
);
END COMPONENT;
-- fifo
SIGNAL fifo_almost_full : std_logic;
SIGNAL fifo_almost_empty : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
-- slv
SIGNAL slv_req : std_logic;
SIGNAL ack_o_int : std_logic;
-- arbiter
SIGNAL slv_ack : std_logic;
SIGNAL mstr_ack : std_logic;
SIGNAL arbit_slv : std_logic;
-- mstr
SIGNAL fifo_wr : std_logic;
SIGNAL fifo_rd : std_logic;
SIGNAL sour_dest : std_logic;
SIGNAL inc_adr : std_logic;
SIGNAL get_bd : std_logic;
SIGNAL load_cnt : std_logic;
SIGNAL set_dma_err_int : std_logic;
SIGNAL clr_dma_en_int : std_logic;
SIGNAL en_mstr_dat_i_reg : std_logic;
SIGNAL mstr_req : std_logic;
SIGNAL stb_o_int : std_logic;
-- du
SIGNAL dma_dest_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_dest_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_vme_am : std_logic_vector(4 DOWNTO 0);
SIGNAL blk_sgl : std_logic;
SIGNAL inc_sour : std_logic;
SIGNAL inc_dest : std_logic;
SIGNAL dma_size : std_logic_vector(15 DOWNTO 0);
SIGNAL start_dma : std_logic;
SIGNAL clr_fifo : std_logic;
SIGNAL dma_en : std_logic;
SIGNAL dma_null : std_logic;
SIGNAL clr_dma_act_bd : std_logic;
-- au
SIGNAL adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL reached_size : std_logic;
SIGNAL almost_reached_size : std_logic;
SIGNAL dma_act_bd_int : std_logic_vector(7 DOWNTO 2);
SIGNAL boundary : std_logic;
SIGNAL almost_boundary : std_logic;
SIGNAL we_o_int : std_logic;
BEGIN
adr_o <= adr_o_int;
ack_o <= ack_o_int;
stb_o <= stb_o_int;
we_o <= we_o_int;
clr_dma_en <= clr_dma_en_int;
set_dma_err <= set_dma_err_int;
dma_act_bd <= dma_act_bd_int(7 DOWNTO 4);
clr_fifo <= start_dma;
start_dma <= dma_sta(8);
dma_arb: vme_dma_arbiter
PORT MAP (
rst => rst ,
clk => clk ,
slv_req => slv_req ,
slv_ack => slv_ack ,
mstr_req => mstr_req ,
mstr_ack => mstr_ack ,
arbit_slv => arbit_slv
);
dma_slv: vme_dma_slv
PORT MAP (
rst => rst ,
clk => clk ,
stb_i => stb_i ,
ack_o => ack_o_int ,
we_i => we_i ,
cyc_i => cyc_i ,
slv_req => slv_req ,
slv_ack => slv_ack
);
dma_au: vme_dma_au
PORT MAP (
rst => rst ,
clk => clk ,
adr_o => adr_o_int ,
sel_o => sel_o ,
tga_o => tga_o,
we_o => we_o_int ,
boundary => boundary,
almost_boundary => almost_boundary,
cyc_o_sram => cyc_o_sram ,
cyc_o_pci => cyc_o_pci ,
cyc_o_vme => cyc_o_vme ,
stb_o => stb_o_int,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
clr_dma_act_bd => clr_dma_act_bd,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
load_cnt => load_cnt ,
start_dma => start_dma ,
dma_act_bd => dma_act_bd_int ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device,
dma_dest_device => dma_dest_device,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size
);
dma_du: vme_dma_du
PORT MAP (
rst => rst ,
clk => clk ,
dma_sta => dma_sta,
irq_o => irq_o ,
arbit_slv => arbit_slv ,
slv_ack => slv_ack ,
mstr_ack => mstr_ack ,
ack_o => ack_o_int ,
we_i => we_i,
adr_i => adr_i(6 DOWNTO 2) ,
sel_i => sel_i ,
slv_dat_i => slv_dat_i ,
slv_dat_o => slv_dat_o ,
clr_dma_act_bd => clr_dma_act_bd,
adr_o => adr_o_int(6 DOWNTO 2) ,
mstr_dat_i => mstr_dat_i ,
dma_act_bd => dma_act_bd_int(7 DOWNTO 4) ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device ,
dma_dest_device => dma_dest_device ,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size ,
-- start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg
);
dma_mstr: vme_dma_mstr
PORT MAP (
rst => rst ,
clk => clk ,
stb_o => stb_o_int ,
ack_i => ack_i ,
err_i => err_i ,
cti => cti,
fifo_empty => fifo_empty ,
fifo_full => fifo_full,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty ,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
boundary => boundary,
almost_boundary => almost_boundary,
we_o_int => we_o_int,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
dma_act_bd => dma_act_bd_int ,
load_cnt => load_cnt ,
start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
inc_sour => inc_sour,
inc_dest => inc_dest,
dma_size => dma_size,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg ,
mstr_req => mstr_req
);
dma_fifo: vme_dma_fifo
PORT MAP (
rst => rst ,
clk => clk ,
fifo_clr => clr_fifo,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
fifo_dat_i => mstr_dat_i ,
fifo_dat_o => mstr_dat_o ,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty,
fifo_full => fifo_full ,
fifo_empty => fifo_empty
);
END vme_dma_arch;
| gpl-3.0 | 08d7860eded95207ca0b79bb5c2d0283 | 0.480551 | 3.978981 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd | 2 | 310,602 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and FIFO Generator when XST elaborated the client core
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-- |
-- |--- XilinxCoreLib.fifo_generator_v4_2
-- |
-- |--- XilinxCoreLib.fifo_generator_v4_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v2_7
-- |
-- |--- XilinxCoreLib.fifo_generator_v5_1
-- |--- XilinxCoreLib.fifo_generator_v5_2
-- |--- XilinxCoreLib.fifo_generator_v5_3
-- |--- XilinxCoreLib.fifo_generator_v6_1
-- |--- XilinxCoreLib.fifo_generator_v8_1
-- |--- XilinxCoreLib.fifo_generator_v8_2
-- |--- XilinxCoreLib.fifo_generator_v8_3
-- |--- XilinxCoreLib.fifo_generator_v9_1
-- |--- XilinxCoreLib.fifo_generator_v9_2
-- |--- XilinxCoreLib.fifo_generator_v9_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v3_1
-- |--- XilinxCoreLib.blk_mem_gen_v3_2
-- |--- XilinxCoreLib.blk_mem_gen_v3_3
-- |--- XilinxCoreLib.blk_mem_gen_v4_1
-- |--- XilinxCoreLib.blk_mem_gen_v5_2
-- |--- XilinxCoreLib.blk_mem_gen_v6_2
-- |--- XilinxCoreLib.blk_mem_gen_v7_1
-- |--- XilinxCoreLib.blk_mem_gen_v7_3
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/01/2008 Initial Version
--
-- DET 2/01/2008 for proc_common_v3_00_a
-- ~~~~~~
-- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create
-- this file.
-- - Changed instance of sync fifo to use new wrapper file that will adapt
-- to FIFO Generator primitive.
-- - Replaced "edk_generatecore" with "generatecore" utility call
-- - Removed the CAM component
-- ^^^^^^
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 4.3
-- - Added Block Memory Generator Component Version 2.7
-- ^^^^^^
--
-- MSH 2/26/2009 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 5.1
-- - Added Block Memory Generator Component Version 3.1
-- ^^^^^^
--
-- DET 3/2/2009 for EDK 11.1
-- ~~~~~~
-- - Added new Parameters and ports for Fifo Generatore 5.1.
-- ^^^^^^
--
-- DET 3/30/2009 EDK 11.2
-- ~~~~~~
-- - Had to reorder parameter list of FIFO Generator 4.3 component to match
-- the corresponding Verilog model due to NCSIM positional order
-- dependancy of parameters in vhdl/verilog use case.
-- ^^^^^^
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Added fifo_generator_v5_2
-- ^^^^^^
--
-- DET 2/9/2010 For EDK 12.1
-- ~~~~~~
-- - Added fifo_generator_v5_3
-- - Added blk_mem_gen_v3_3
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Added fifo_generator_v6_1
-- - Added blk_mem_gen_v4_1
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 10/04/2010 EDK 13.1
-- ~~~~~~
-- - Added fifo_generator_v7_3
-- - Added blk_mem_gen_v5_2
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Replaced fifo_generator v7.3 with v8.1
-- - Added blk_mem_gen_v6_1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Removed blk_mem_gen v6_1
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- - Update to use blk_mem_gen_v6_2
-- - Remove out of date components.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the component decalarion
-- ^^^^^^
--
-- DET 3/7/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR596052
-- - Added removed fifo generator and Blk Mem Gen components back into
-- coregen_comp_defs.
-- ^^^^^^
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
--------------------------------------------------------
-- Declare general attributes used in this file
-- for defining each component being used with
-- the generatecore utility
attribute box_type: string;
attribute GENERATOR_DEFAULT: string;
-------------------------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V4_2
-- Component declaration for V4_2 pulled from the K.30\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v4_2_comp.vhd
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support is not
-- provided in FIFO Generator V4.2 so don't use this for Hard Block FIFOs.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v4_2
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_REGS : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_USE_ECC : integer := 0;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_INT_CLK : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK : IN std_logic := '0';
RD_EN : IN std_logic := '0';
RD_RST : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v4_2 is a black box
-- which should be generated using the command given by the value of this attribute
attribute box_type of fifo_generator_v4_2: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v4_2: component is
"generatecore com.xilinx.ip.fifo_generator_v4_2.fifo_generator_v4_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator 4.2 Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V4_3
-- Component declaration for V4_3 pulled from the L.16\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v4_3_comp.vhd
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support is not
-- provided in FIFO Generator V4.3 so don't use this for Hard Block FIFOs.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v4_3
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK : IN std_logic := '0';
RD_EN : IN std_logic := '0';
RD_RST : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v4_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v4_3: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v4_3: component is
"generatecore com.xilinx.ip.fifo_generator_v4_3.fifo_generator_v4_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator 4.3 Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V5_1
-- Component declaration for V5_1 pulled from the L.16\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v5_1_comp.vhd
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support is not
-- provided in FIFO Generator V4.3 so don't use this for Hard Block FIFOs.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v5_1
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_REGS : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_USE_ECC : integer := 0;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_INT_CLK : integer := 0;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1; -- New FG 5.1
C_ERROR_INJECTION_TYPE : integer := 0 -- New FG 5.1
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK : IN std_logic := '0';
RD_EN : IN std_logic := '0';
RD_RST : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0'; -- New FG 5.1
INJECTSBITERR : IN std_logic := '0'; -- New FG 5.1
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v5_1 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v5_1: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v5_1: component is
"generatecore com.xilinx.ip.fifo_generator_v5_1.fifo_generator_v5_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V5_2
-- The Component declaration for V5_2 pulled from the L.38\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v5_1_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in L.38\rtf\verilog\src\XilinxCoreLib\fifo_generator_v5_2.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V5.2 so not supported here.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v5_2
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_REGS : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_USE_ECC : integer := 0;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_INT_CLK : integer := 0;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1; -- New FG 5.1/5.2
C_ERROR_INJECTION_TYPE : integer := 0 -- New FG 5.1/5.2
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK : IN std_logic := '0';
RD_EN : IN std_logic := '0';
RD_RST : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
INJECTSBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v5_2 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v5_2: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v5_2: component is
"generatecore com.xilinx.ip.fifo_generator_v5_2.fifo_generator_v5_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V5_3
-- The Component declaration for V5_2 pulled from the L.69\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v5_3_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in L.38\rtf\verilog\src\XilinxCoreLib\fifo_generator_v5_3.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V5.3 so not supported here.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v5_3
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_REGS : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_USE_ECC : integer := 0;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_INT_CLK : integer := 0;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1; -- New FG 5.1/5.2
C_ERROR_INJECTION_TYPE : integer := 0 -- New FG 5.1/5.2
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK : IN std_logic := '0';
RD_EN : IN std_logic := '0';
RD_RST : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST : IN std_logic := '0';
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
INJECTSBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v5_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v5_3: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v5_3: component is
"generatecore com.xilinx.ip.fifo_generator_v5_3.fifo_generator_v5_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V6_1
-- The Component declaration for V5_2 pulled from the M.50\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v6_1_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in M.50\rtf\verilog\src\XilinxCoreLib\fifo_generator_v6_1.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V6.1 so not supported here.
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v6_1
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0'; --Mandatory input
RD_EN : IN std_logic := '0'; --Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
INJECTSBITERR : IN std_logic := '0'; -- New FG 5.1/5.2
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v6_1 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v6_1: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v6_1: component is
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for V8.1
-- The Component declaration for V8.1 pulled from the O.36\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v8_1_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in O.36\rtf\verilog\src\XilinxCoreLib\fifo_generator_v8_1.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.1 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v8_1
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4 ;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_HAS_AXI_AWUSER : integer := 0 ;
C_HAS_AXI_WUSER : integer := 0 ;
C_HAS_AXI_BUSER : integer := 0 ;
C_HAS_AXI_ARUSER : integer := 0 ;
C_HAS_AXI_RUSER : integer := 0 ;
C_AXI_ARUSER_WIDTH : integer := 1 ;
C_AXI_AWUSER_WIDTH : integer := 1 ;
C_AXI_WUSER_WIDTH : integer := 1 ;
C_AXI_BUSER_WIDTH : integer := 1 ;
C_AXI_RUSER_WIDTH : integer := 1 ;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0 ;
C_HAS_AXIS_TID : integer := 0 ;
C_HAS_AXIS_TDEST : integer := 0 ;
C_HAS_AXIS_TUSER : integer := 0 ;
C_HAS_AXIS_TREADY : integer := 1 ;
C_HAS_AXIS_TLAST : integer := 0 ;
C_HAS_AXIS_TSTRB : integer := 0 ;
C_HAS_AXIS_TKEEP : integer := 0 ;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8 ;
C_AXIS_TDEST_WIDTH : integer := 4 ;
C_AXIS_TUSER_WIDTH : integer := 4 ;
C_AXIS_TSTRB_WIDTH : integer := 4 ;
C_AXIS_TKEEP_WIDTH : integer := 4 ;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2 ;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1 ;
C_WR_DEPTH_WACH : integer := 16 ;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16 ;
C_WR_DEPTH_RACH : integer := 16 ;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4 ;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4 ;
C_WR_PNTR_WIDTH_RACH : integer := 4 ;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 5 ;
C_PROG_FULL_TYPE_WDCH : integer := 5 ;
C_PROG_FULL_TYPE_WRCH : integer := 5 ;
C_PROG_FULL_TYPE_RACH : integer := 5 ;
C_PROG_FULL_TYPE_RDCH : integer := 5 ;
C_PROG_FULL_TYPE_AXIS : integer := 5 ;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
C_PROG_EMPTY_TYPE_WACH : integer := 5 ;
C_PROG_EMPTY_TYPE_WDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_WRCH : integer := 5 ;
C_PROG_EMPTY_TYPE_RACH : integer := 5 ;
C_PROG_EMPTY_TYPE_RDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_AXIS : integer := 5 ;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0'; --Mandatory input
RD_EN : IN std_logic := '0'; --Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic;
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '0';
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_1 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v8_1: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v8_1: component is
"generatecore com.xilinx.ip.fifo_generator_v8_1.fifo_generator_v8_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v8_2
-- The Component declaration for fifo_generator_v8_2 pulled from the
-- O.48\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v8_2_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in O.48\rtf\verilog\src\XilinxCoreLib\fifo_generator_v8_2.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.2 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v8_2
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4 ;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_HAS_AXI_AWUSER : integer := 0 ;
C_HAS_AXI_WUSER : integer := 0 ;
C_HAS_AXI_BUSER : integer := 0 ;
C_HAS_AXI_ARUSER : integer := 0 ;
C_HAS_AXI_RUSER : integer := 0 ;
C_AXI_ARUSER_WIDTH : integer := 1 ;
C_AXI_AWUSER_WIDTH : integer := 1 ;
C_AXI_WUSER_WIDTH : integer := 1 ;
C_AXI_BUSER_WIDTH : integer := 1 ;
C_AXI_RUSER_WIDTH : integer := 1 ;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0 ;
C_HAS_AXIS_TID : integer := 0 ;
C_HAS_AXIS_TDEST : integer := 0 ;
C_HAS_AXIS_TUSER : integer := 0 ;
C_HAS_AXIS_TREADY : integer := 1 ;
C_HAS_AXIS_TLAST : integer := 0 ;
C_HAS_AXIS_TSTRB : integer := 0 ;
C_HAS_AXIS_TKEEP : integer := 0 ;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8 ;
C_AXIS_TDEST_WIDTH : integer := 4 ;
C_AXIS_TUSER_WIDTH : integer := 4 ;
C_AXIS_TSTRB_WIDTH : integer := 4 ;
C_AXIS_TKEEP_WIDTH : integer := 4 ;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2 ;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1 ;
C_WR_DEPTH_WACH : integer := 16 ;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16 ;
C_WR_DEPTH_RACH : integer := 16 ;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4 ;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4 ;
C_WR_PNTR_WIDTH_RACH : integer := 4 ;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 5 ;
C_PROG_FULL_TYPE_WDCH : integer := 5 ;
C_PROG_FULL_TYPE_WRCH : integer := 5 ;
C_PROG_FULL_TYPE_RACH : integer := 5 ;
C_PROG_FULL_TYPE_RDCH : integer := 5 ;
C_PROG_FULL_TYPE_AXIS : integer := 5 ;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
C_PROG_EMPTY_TYPE_WACH : integer := 5 ;
C_PROG_EMPTY_TYPE_WDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_WRCH : integer := 5 ;
C_PROG_EMPTY_TYPE_RACH : integer := 5 ;
C_PROG_EMPTY_TYPE_RDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_AXIS : integer := 5 ;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0'; --Mandatory input
RD_EN : IN std_logic := '0'; --Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic;
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '0';
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_2 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v8_2: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v8_2: component is
"generatecore com.xilinx.ip.fifo_generator_v8_2.fifo_generator_v8_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v8_3
-- The Component declaration for fifo_generator_v8_3 pulled from the
-- O.48\rtf\vhdl\src\XilinxCoreLib
-- file: fifo_generator_v8_3_comp.vhd.
-- However, to support NCSIM, Params and Ports are ordered to match the verilog
-- definition in O.48\rtf\verilog\src\XilinxCoreLib\fifo_generator_v8_3.v .
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.2 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v8_3
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4 ;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_HAS_AXI_AWUSER : integer := 0 ;
C_HAS_AXI_WUSER : integer := 0 ;
C_HAS_AXI_BUSER : integer := 0 ;
C_HAS_AXI_ARUSER : integer := 0 ;
C_HAS_AXI_RUSER : integer := 0 ;
C_AXI_ARUSER_WIDTH : integer := 1 ;
C_AXI_AWUSER_WIDTH : integer := 1 ;
C_AXI_WUSER_WIDTH : integer := 1 ;
C_AXI_BUSER_WIDTH : integer := 1 ;
C_AXI_RUSER_WIDTH : integer := 1 ;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0 ;
C_HAS_AXIS_TID : integer := 0 ;
C_HAS_AXIS_TDEST : integer := 0 ;
C_HAS_AXIS_TUSER : integer := 0 ;
C_HAS_AXIS_TREADY : integer := 1 ;
C_HAS_AXIS_TLAST : integer := 0 ;
C_HAS_AXIS_TSTRB : integer := 0 ;
C_HAS_AXIS_TKEEP : integer := 0 ;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8 ;
C_AXIS_TDEST_WIDTH : integer := 4 ;
C_AXIS_TUSER_WIDTH : integer := 4 ;
C_AXIS_TSTRB_WIDTH : integer := 4 ;
C_AXIS_TKEEP_WIDTH : integer := 4 ;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2 ;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1 ;
C_WR_DEPTH_WACH : integer := 16 ;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16 ;
C_WR_DEPTH_RACH : integer := 16 ;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4 ;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4 ;
C_WR_PNTR_WIDTH_RACH : integer := 4 ;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 5 ;
C_PROG_FULL_TYPE_WDCH : integer := 5 ;
C_PROG_FULL_TYPE_WRCH : integer := 5 ;
C_PROG_FULL_TYPE_RACH : integer := 5 ;
C_PROG_FULL_TYPE_RDCH : integer := 5 ;
C_PROG_FULL_TYPE_AXIS : integer := 5 ;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
C_PROG_EMPTY_TYPE_WACH : integer := 5 ;
C_PROG_EMPTY_TYPE_WDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_WRCH : integer := 5 ;
C_PROG_EMPTY_TYPE_RACH : integer := 5 ;
C_PROG_EMPTY_TYPE_RDCH : integer := 5 ;
C_PROG_EMPTY_TYPE_AXIS : integer := 5 ;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0'; --Mandatory input
RD_EN : IN std_logic := '0'; --Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic;
DBITERR : OUT std_logic;
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '0';
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v8_3: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v8_3: component is
"generatecore com.xilinx.ip.fifo_generator_v8_3.fifo_generator_v8_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v9_1
-- The Component declaration for fifo_generator_v9_1 pulled from the
-- Coregen version of
-- file: fifo_generator_v9_1_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.2 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v9_1
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 0;
C_AXI_ADDR_WIDTH : integer := 0;
C_AXI_DATA_WIDTH : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 0;
C_AXI_AWUSER_WIDTH : integer := 0;
C_AXI_WUSER_WIDTH : integer := 0;
C_AXI_BUSER_WIDTH : integer := 0;
C_AXI_RUSER_WIDTH : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 0;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 1;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_AXIS_TUSER_WIDTH : integer := 1;
C_AXIS_TSTRB_WIDTH : integer := 1;
C_AXIS_TKEEP_WIDTH : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH : integer := 0;
C_IMPLEMENTATION_TYPE_RACH : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 1;
C_DIN_WIDTH_WDCH : integer := 1;
C_DIN_WIDTH_WRCH : integer := 1;
C_DIN_WIDTH_RACH : integer := 1;
C_DIN_WIDTH_RDCH : integer := 1;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 16;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 16;
C_WR_DEPTH_AXIS : integer := 16;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 4;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 4;
C_WR_PNTR_WIDTH_AXIS : integer := 4;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 0;
C_PROG_FULL_TYPE_WDCH : integer := 0;
C_PROG_FULL_TYPE_WRCH : integer := 0;
C_PROG_FULL_TYPE_RACH : integer := 0;
C_PROG_FULL_TYPE_RDCH : integer := 0;
C_PROG_FULL_TYPE_AXIS : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_PROG_EMPTY_TYPE_WACH : integer := 0;
C_PROG_EMPTY_TYPE_WDCH : integer := 0;
C_PROG_EMPTY_TYPE_WRCH : integer := 0;
C_PROG_EMPTY_TYPE_RACH : integer := 0;
C_PROG_EMPTY_TYPE_RDCH : integer := 0;
C_PROG_EMPTY_TYPE_AXIS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v9_1: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v9_1: component is
"generatecore com.xilinx.ip.fifo_generator_v9_1.fifo_generator_v9_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v9_2
-- The Component declaration for fifo_generator_v9_2 pulled from the
-- Coregen version of
-- file: fifo_generator_v9_2_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.2 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v9_2
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 0;
C_AXI_ADDR_WIDTH : integer := 0;
C_AXI_DATA_WIDTH : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 0;
C_AXI_AWUSER_WIDTH : integer := 0;
C_AXI_WUSER_WIDTH : integer := 0;
C_AXI_BUSER_WIDTH : integer := 0;
C_AXI_RUSER_WIDTH : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 0;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 1;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_AXIS_TUSER_WIDTH : integer := 1;
C_AXIS_TSTRB_WIDTH : integer := 1;
C_AXIS_TKEEP_WIDTH : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH : integer := 0;
C_IMPLEMENTATION_TYPE_RACH : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 1;
C_DIN_WIDTH_WDCH : integer := 1;
C_DIN_WIDTH_WRCH : integer := 1;
C_DIN_WIDTH_RACH : integer := 1;
C_DIN_WIDTH_RDCH : integer := 1;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 16;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 16;
C_WR_DEPTH_AXIS : integer := 16;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 4;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 4;
C_WR_PNTR_WIDTH_AXIS : integer := 4;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 0;
C_PROG_FULL_TYPE_WDCH : integer := 0;
C_PROG_FULL_TYPE_WRCH : integer := 0;
C_PROG_FULL_TYPE_RACH : integer := 0;
C_PROG_FULL_TYPE_RDCH : integer := 0;
C_PROG_FULL_TYPE_AXIS : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_PROG_EMPTY_TYPE_WACH : integer := 0;
C_PROG_EMPTY_TYPE_WDCH : integer := 0;
C_PROG_EMPTY_TYPE_WRCH : integer := 0;
C_PROG_EMPTY_TYPE_RACH : integer := 0;
C_PROG_EMPTY_TYPE_RDCH : integer := 0;
C_PROG_EMPTY_TYPE_AXIS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v9_2: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v9_2: component is
"generatecore com.xilinx.ip.fifo_generator_v9_2.fifo_generator_v9_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v9_3
-- The Component declaration for fifo_generator_v9_3 pulled from the
-- Coregen version of
-- file: fifo_generator_v9_3_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V8.2 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v9_3
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (verilog model ordering)
--------------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 0;
C_AXI_ADDR_WIDTH : integer := 0;
C_AXI_DATA_WIDTH : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 0;
C_AXI_AWUSER_WIDTH : integer := 0;
C_AXI_WUSER_WIDTH : integer := 0;
C_AXI_BUSER_WIDTH : integer := 0;
C_AXI_RUSER_WIDTH : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 0;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 1;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_AXIS_TUSER_WIDTH : integer := 1;
C_AXIS_TSTRB_WIDTH : integer := 1;
C_AXIS_TKEEP_WIDTH : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH : integer := 0;
C_IMPLEMENTATION_TYPE_RACH : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 1;
C_DIN_WIDTH_WDCH : integer := 1;
C_DIN_WIDTH_WRCH : integer := 1;
C_DIN_WIDTH_RACH : integer := 1;
C_DIN_WIDTH_RDCH : integer := 1;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 16;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 16;
C_WR_DEPTH_AXIS : integer := 16;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 4;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 4;
C_WR_PNTR_WIDTH_AXIS : integer := 4;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
C_PROG_FULL_TYPE_WACH : integer := 0;
C_PROG_FULL_TYPE_WDCH : integer := 0;
C_PROG_FULL_TYPE_WRCH : integer := 0;
C_PROG_FULL_TYPE_RACH : integer := 0;
C_PROG_FULL_TYPE_RDCH : integer := 0;
C_PROG_FULL_TYPE_AXIS : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_PROG_EMPTY_TYPE_WACH : integer := 0;
C_PROG_EMPTY_TYPE_WDCH : integer := 0;
C_PROG_EMPTY_TYPE_WRCH : integer := 0;
C_PROG_EMPTY_TYPE_RACH : integer := 0;
C_PROG_EMPTY_TYPE_RDCH : integer := 0;
C_PROG_EMPTY_TYPE_AXIS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END COMPONENT;
-- The following attributes tells XST that the fifo_generator_v8_3 is a black box
-- which should be generated using the command given by the value
-- of this attribute
attribute box_type of fifo_generator_v9_3: component is "black_box";
attribute GENERATOR_DEFAULT of fifo_generator_v9_3: component is
"generatecore com.xilinx.ip.fifo_generator_v9_3.fifo_generator_v9_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V2_7
-- Component declaration for V2_7 pulled from the L.16\rtf\vhdl\src\XilinxCoreLib
-- file: blk_mem_gen_v2_7_comp.vhd
-------------------------------------------------------------------------------------
component blk_mem_gen_v2_7
generic (
C_ADDRA_WIDTH : integer := 6;
C_ADDRB_WIDTH : integer := 6;
C_ALGORITHM : integer := 2;
C_BYTE_SIZE : integer := 8;
C_COMMON_CLK : integer := 1;
C_DEFAULT_DATA : string := "";
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_FAMILY : string := "virtex4";
C_XDEVICEFAMILY : string := "virtex4";
C_HAS_ENA : integer := 1;
C_HAS_ENB : integer := 1;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_REGCEA : integer := 0;
C_HAS_REGCEB : integer := 0;
C_HAS_SSRA : integer := 0;
C_HAS_SSRB : integer := 0;
C_INIT_FILE_NAME : string := "";
C_LOAD_INIT_FILE : integer := 0;
C_MEM_TYPE : integer := 2;
C_PRIM_TYPE : integer := 3;
C_READ_DEPTH_A : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_READ_WIDTH_A : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_SIM_COLLISION_CHECK : string := "NONE";
C_SINITA_VAL : string := "";
C_SINITB_VAL : string := "";
C_USE_BYTE_WEA : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_USE_DEFAULT_DATA : integer := 0;
C_USE_ECC : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WEB_WIDTH : integer := 1;
C_WRITE_DEPTH_A : integer := 64;
C_WRITE_DEPTH_B : integer := 64;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_WRITE_WIDTH_B : integer := 32;
-- C_CORENAME : string := "blk_mem_gen_v2_7";
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
C_USE_RAMB16BWER_RST_BHV : INTEGER := 0);
port (
CLKA : in std_logic;
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
SSRA : in std_logic := '0';
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
SSRB : in std_logic := '0';
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
DBITERR : out std_logic;
SBITERR : out std_logic
);
end component; --blk_mem_gen_v2_7
-- The following tells XST that blk_mem_gen_v2_7 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v2_7 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v2_7 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v2_7.blk_mem_gen_v2_7 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for V2_7-------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V3_1
-- Component declaration for V3_1 pulled from the L.16\rtf\vhdl\src\XilinxCoreLib
-- file: blk_mem_gen_v3_1_comp.vhd
-------------------------------------------------------------------------------------
component blk_mem_gen_v3_1
generic (
C_RSTRAM_B : integer := 0;
C_RSTRAM_A : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_RST_TYPE : string := "SYNC";
C_ADDRA_WIDTH : integer := 6;
C_ADDRB_WIDTH : integer := 6;
C_ALGORITHM : integer := 2;
C_BYTE_SIZE : integer := 8;
C_COMMON_CLK : integer := 1;
C_DEFAULT_DATA : string := "";
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_FAMILY : string := "virtex4";
C_XDEVICEFAMILY : string := "virtex4";
C_HAS_ENA : integer := 1;
C_HAS_ENB : integer := 1;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_REGCEA : integer := 0;
C_HAS_REGCEB : integer := 0;
C_HAS_RSTA : integer := 0;
C_HAS_RSTB : integer := 0;
C_INIT_FILE_NAME : string := "";
C_LOAD_INIT_FILE : integer := 0;
C_MEM_TYPE : integer := 2;
C_PRIM_TYPE : integer := 3;
C_READ_DEPTH_A : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_READ_WIDTH_A : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_SIM_COLLISION_CHECK : string := "NONE";
C_INITA_VAL : string := "";
C_INITB_VAL : string := "";
C_USE_BYTE_WEA : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_USE_DEFAULT_DATA : integer := 0;
C_USE_ECC : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WEB_WIDTH : integer := 1;
C_WRITE_DEPTH_A : integer := 64;
C_WRITE_DEPTH_B : integer := 64;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_WRITE_WIDTH_B : integer := 32;
-- C_CORENAME : string := "blk_mem_gen_v3_1";
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
C_RST_PRIORITY_B : string := "CE";
C_RST_PRIORITY_A : string := "CE"
);
port (
CLKA : in std_logic;
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
RSTA : in std_logic := '0';
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
RSTB : in std_logic := '0';
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
DBITERR : out std_logic;
SBITERR : out std_logic
);
end component; --blk_mem_gen_v3_1
-- The following tells XST that blk_mem_gen_v3_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v3_1 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v3_1 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v3_1.blk_mem_gen_v3_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for V3_1-------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V3_2
-- Component declaration for V3_2 pulled from the L.38\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v3_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v3_2
generic (
-- synthesis translate_off
C_CORENAME : string := "blk_mem_gen_v3_2";
-- synthesis translate_on
C_FAMILY : string := "virtex6";
C_XDEVICEFAMILY : string := "virtex6";
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 8;
C_ALGORITHM : integer := 2;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "";
C_RST_TYPE : string := "SYNC";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "CE";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_READ_WIDTH_A : integer := 32;
C_WRITE_DEPTH_A : integer := 64;
C_READ_DEPTH_A : integer := 64;
C_ADDRA_WIDTH : integer := 6;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "CE";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_WRITE_DEPTH_B : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_ADDRB_WIDTH : integer := 6;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_USE_ECC : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "NONE";
C_COMMON_CLK : integer := 1;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0
);
port (
CLKA : in std_logic;
RSTA : in std_logic := '0';
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
RSTB : in std_logic := '0';
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
INJECTSBITERR : in std_logic;
INJECTDBITERR : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
RDADDRECC : out std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0')
);
end component; --blk_mem_gen_v3_2
-- The following tells XST that blk_mem_gen_v3_2 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v3_2 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v3_2 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v3_2.blk_mem_gen_v3_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for V3_2 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V3_3
-- Component declaration for V3_3 pulled from the L.69\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v3_3.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v3_3
generic (
-- synthesis translate_off
C_CORENAME : string := "blk_mem_gen_v3_3";
-- synthesis translate_on
C_FAMILY : string := "virtex6";
C_XDEVICEFAMILY : string := "virtex6";
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 8;
C_ALGORITHM : integer := 2;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "";
C_RST_TYPE : string := "SYNC";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "CE";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_READ_WIDTH_A : integer := 32;
C_WRITE_DEPTH_A : integer := 64;
C_READ_DEPTH_A : integer := 64;
C_ADDRA_WIDTH : integer := 6;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "CE";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_WRITE_DEPTH_B : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_ADDRB_WIDTH : integer := 6;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_USE_ECC : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "NONE";
C_COMMON_CLK : integer := 1;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0
);
port (
CLKA : in std_logic;
RSTA : in std_logic := '0';
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
RSTB : in std_logic := '0';
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
INJECTSBITERR : in std_logic;
INJECTDBITERR : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
RDADDRECC : out std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0')
);
end component; --blk_mem_gen_v3_3
-- The following tells XST that blk_mem_gen_v3_3 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v3_3 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v3_3 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v3_3.blk_mem_gen_v3_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for V3_3 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V4_1
-- Component declaration for V3_3 pulled from the M.50\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v4_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v4_1
generic (
-- synthesis translate_off
C_CORENAME : string := "blk_mem_gen_v4_1";
-- synthesis translate_on
C_FAMILY : string := "virtex6";
C_XDEVICEFAMILY : string := "virtex6";
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 8;
C_ALGORITHM : integer := 2;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "";
C_RST_TYPE : string := "SYNC";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "CE";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_READ_WIDTH_A : integer := 32;
C_WRITE_DEPTH_A : integer := 64;
C_READ_DEPTH_A : integer := 64;
C_ADDRA_WIDTH : integer := 6;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "CE";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_WRITE_DEPTH_B : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_ADDRB_WIDTH : integer := 6;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; -- new BMG_v4_1
C_HAS_SOFTECC_INPUT_REGS_B : INTEGER := 0; -- new BMG_v4_1
C_HAS_SOFTECC_OUTPUT_REGS_A : INTEGER := 0; -- new BMG_v4_1
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; -- new BMG_v4_1
C_MUX_PIPELINE_STAGES : integer := 0;
C_USE_SOFTECC : INTEGER := 0; -- new BMG_v4_1
C_USE_ECC : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "NONE";
C_COMMON_CLK : integer := 1;
--FLOP_DELAY : integer := 100; -- new BMG_v4_1
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0
);
port (
CLKA : in std_logic;
RSTA : in std_logic := '0';
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
RSTB : in std_logic := '0';
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
INJECTSBITERR : in std_logic;
INJECTDBITERR : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
RDADDRECC : out std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0')
);
end component; --blk_mem_gen_v4_1
-- The following tells XST that blk_mem_gen_v4_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v4_1 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v4_1 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v4_1.blk_mem_gen_v4_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for V4_1 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for V5_2
-- Component declaration for V3_3 pulled from the O.26\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v5_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v5_2
generic (
-- synthesis translate_off
C_CORENAME : string := "blk_mem_gen_v5_2";
-- synthesis translate_on
C_FAMILY : string := "virtex6";
C_XDEVICEFAMILY : string := "virtex6";
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 8;
C_ALGORITHM : integer := 2;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "";
C_RST_TYPE : string := "SYNC";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "CE";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_READ_WIDTH_A : integer := 32;
C_WRITE_DEPTH_A : integer := 64;
C_READ_DEPTH_A : integer := 64;
C_ADDRA_WIDTH : integer := 6;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "CE";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_WRITE_DEPTH_B : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_ADDRB_WIDTH : integer := 6;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
--C_HAS_SOFTECC_INPUT_REGS_B : INTEGER := 0; -- Rmoved BMG_v4_3
--C_HAS_SOFTECC_OUTPUT_REGS_A : INTEGER := 0; -- Rmoved BMG_v4_3
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "NONE";
C_COMMON_CLK : integer := 1;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0
);
port (
CLKA : in std_logic;
RSTA : in std_logic := '0';
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
RSTB : in std_logic := '0';
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
INJECTSBITERR : in std_logic;
INJECTDBITERR : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
RDADDRECC : out std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0')
);
end component; --blk_mem_gen_v5_2
-- The following tells XST that blk_mem_gen_v5_2 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v5_2 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v5_2 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v5_2.blk_mem_gen_v5_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v5_2 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v6_2
-- Component declaration for blk_mem_gen_v6_2 pulled from the
-- O.48\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v6_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v6_2
generic (
-- synthesis translate_off
C_CORENAME : string := "blk_mem_gen_v6_2";
-- synthesis translate_on
C_FAMILY : string := "virtex6";
C_XDEVICEFAMILY : string := "virtex6";
--
C_INTERFACE_TYPE : INTEGER := 0; -- new for v6.2
C_AXI_TYPE : INTEGER := 0; -- new for v6.2
C_AXI_SLAVE_TYPE : INTEGER := 0; -- new for v6.2
C_HAS_AXI_ID : INTEGER := 0; -- new for v6.2
C_AXI_ID_WIDTH : INTEGER := 4; -- new for v6.2
--
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 8;
C_ALGORITHM : integer := 2;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "";
C_RST_TYPE : string := "SYNC";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "CE";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 32;
C_READ_WIDTH_A : integer := 32;
C_WRITE_DEPTH_A : integer := 64;
C_READ_DEPTH_A : integer := 64;
C_ADDRA_WIDTH : integer := 6;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "CE";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 32;
C_READ_WIDTH_B : integer := 32;
C_WRITE_DEPTH_B : integer := 64;
C_READ_DEPTH_B : integer := 64;
C_ADDRB_WIDTH : integer := 6;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "NONE";
C_COMMON_CLK : integer := 1;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0
);
port (
CLKA : in std_logic;
RSTA : in std_logic := '0';
ENA : in std_logic := '1';
REGCEA : in std_logic := '1';
WEA : in std_logic_vector(C_WEA_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRA : in std_logic_vector(C_ADDRA_WIDTH-1 downto 0);
DINA : in std_logic_vector(C_WRITE_WIDTH_A-1 downto 0):= (OTHERS => '0');
DOUTA : out std_logic_vector(C_READ_WIDTH_A-1 downto 0);
CLKB : in std_logic := '0';
RSTB : in std_logic := '0';
ENB : in std_logic := '1';
REGCEB : in std_logic := '1';
WEB : in std_logic_vector(C_WEB_WIDTH-1 downto 0):= (OTHERS => '0');
ADDRB : in std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0');
DINB : in std_logic_vector(C_WRITE_WIDTH_B-1 downto 0):= (OTHERS => '0');
DOUTB : out std_logic_vector(C_READ_WIDTH_B-1 downto 0);
INJECTSBITERR : in std_logic;
INJECTDBITERR : in std_logic;
SBITERR : out std_logic;
DBITERR : out std_logic;
RDADDRECC : out std_logic_vector(C_ADDRB_WIDTH-1 downto 0):= (OTHERS => '0') ;
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end component; --blk_mem_gen_v6_2
-- The following tells XST that blk_mem_gen_v6_2 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v6_2 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v6_2 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v5_2 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v7_1
-- Component declaration for blk_mem_gen_v6_2 pulled from the
-- P.26\rtf\verilog\src\XilinxCoreLib
-- file: blk_mem_gen_v7_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v7_1
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v7_1
-- The following tells XST that blk_mem_gen_v7_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v7_1 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v7_1 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v7_1.blk_mem_gen_v7_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v7_3
-- Component declaration for blk_mem_gen_v7_3 pulled from the
-- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib
-- file: blk_mem_gen_v7_3.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v7_3 IS
GENERIC (
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC := '0';
DBITERR : OUT STD_LOGIC := '0';
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC := '0';
S_AXI_DBITERR : OUT STD_LOGIC := '0';
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT; --blk_mem_gen_v7_3
-- The following tells XST that blk_mem_gen_v7_3 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
ATTRIBUTE box_type OF blk_mem_gen_v7_3 : COMPONENT IS "black_box";
ATTRIBUTE generator_default OF blk_mem_gen_v7_3 : COMPONENT IS
"generatecore com.xilinx.ip.blk_mem_gen_v7_3.blk_mem_gen_v7_3 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
END coregen_comp_defs;
| bsd-3-clause | e6e91e85f0098fd0b22a9080e344b19c | 0.464405 | 3.70055 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/test/reconos/out.vhd | 2 | 82,715 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use work.common.all;
ENTITY user_logic_hwtul IS
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
END ENTITY user_logic_hwtul;
ARCHITECTURE IMP OF user_logic_hwtul IS
-- HWTI Declarations.
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
-- STATE DECLARATIONS
constant START_STATE : std_logic_vector(0 to 15) := x"0004";
constant WAIT_STATE : std_logic_vector(0 to 15) := x"0005";
constant FUNCTCALL_STATE : std_logic_vector(0 to 15) := x"0006";
constant BOOTSTRAP0 : std_logic_vector(0 to 15) := x"0007";
constant BOOTSTRAP1 : std_logic_vector(0 to 15) := x"0008";
constant mailbox_write_start : std_logic_vector(0 to 15) := x"0009";
constant mailbox_write_save_0 : std_logic_vector(0 to 15) := x"000A";
constant mailbox_write_save_1 : std_logic_vector(0 to 15) := x"000B";
constant mailbox_write_save_2 : std_logic_vector(0 to 15) := x"000C";
constant mailbox_write_save_3 : std_logic_vector(0 to 15) := x"000D";
constant mailbox_write_save_4 : std_logic_vector(0 to 15) := x"000E";
constant mailbox_write_15_0_0 : std_logic_vector(0 to 15) := x"000F";
constant mailbox_write_15_0_1 : std_logic_vector(0 to 15) := x"0010";
constant mailbox_write_15_1_0 : std_logic_vector(0 to 15) := x"0011";
constant mailbox_write_15_1_1 : std_logic_vector(0 to 15) := x"0012";
constant mailbox_write_15_2_0 : std_logic_vector(0 to 15) := x"0013";
constant mailbox_write_15_3_0 : std_logic_vector(0 to 15) := x"0014";
constant mailbox_write_15_4_0 : std_logic_vector(0 to 15) := x"0015";
constant mailbox_write_15_4_1 : std_logic_vector(0 to 15) := x"0016";
constant mailbox_write_15_4_2 : std_logic_vector(0 to 15) := x"0017";
constant mailbox_write_15_5_0 : std_logic_vector(0 to 15) := x"0018";
constant mailbox_write_15_5_1 : std_logic_vector(0 to 15) := x"0019";
constant mailbox_write_15_6_0 : std_logic_vector(0 to 15) := x"001A";
constant mailbox_write_15_6_1 : std_logic_vector(0 to 15) := x"001B";
constant mailbox_write_15_7_0 : std_logic_vector(0 to 15) := x"001C";
constant mailbox_write_16_0_0 : std_logic_vector(0 to 15) := x"001D";
constant mailbox_write_17_0_0 : std_logic_vector(0 to 15) := x"001E";
constant mailbox_write_18_0_0 : std_logic_vector(0 to 15) := x"001F";
constant mailbox_write_18_1_0 : std_logic_vector(0 to 15) := x"0020";
constant mailbox_write_18_1_1 : std_logic_vector(0 to 15) := x"0021";
constant mailbox_write_18_1_2 : std_logic_vector(0 to 15) := x"0022";
constant mailbox_write_18_1_3 : std_logic_vector(0 to 15) := x"0023";
constant mailbox_write_18_2_0 : std_logic_vector(0 to 15) := x"0024";
constant mailbox_write_18_2_1 : std_logic_vector(0 to 15) := x"0025";
constant mailbox_write_18_3_0 : std_logic_vector(0 to 15) := x"0026";
constant mailbox_write_18_4_0 : std_logic_vector(0 to 15) := x"0027";
constant mailbox_write_18_4_1 : std_logic_vector(0 to 15) := x"0028";
constant mailbox_write_18_5_0 : std_logic_vector(0 to 15) := x"0029";
constant mailbox_write_19_0_0 : std_logic_vector(0 to 15) := x"002A";
constant mailbox_write_20_0_0 : std_logic_vector(0 to 15) := x"002B";
constant mailbox_write_21_0_0 : std_logic_vector(0 to 15) := x"002C";
constant mailbox_write_21_0_1 : std_logic_vector(0 to 15) := x"002D";
constant mailbox_write_21_1_0 : std_logic_vector(0 to 15) := x"002E";
constant mailbox_write_21_2_0 : std_logic_vector(0 to 15) := x"002F";
constant mailbox_write_21_2_1 : std_logic_vector(0 to 15) := x"0030";
constant mailbox_write_21_3_0 : std_logic_vector(0 to 15) := x"0031";
constant mailbox_write_21_3_1 : std_logic_vector(0 to 15) := x"0032";
constant mailbox_write_21_4_0 : std_logic_vector(0 to 15) := x"0033";
constant mailbox_write_21_5_0 : std_logic_vector(0 to 15) := x"0034";
constant mailbox_write_21_6_0 : std_logic_vector(0 to 15) := x"0035";
constant mailbox_write_21_7_0 : std_logic_vector(0 to 15) := x"0036";
constant mailbox_write_21_7_1 : std_logic_vector(0 to 15) := x"0037";
constant mailbox_write_21_8_0 : std_logic_vector(0 to 15) := x"0038";
constant mailbox_write_21_9_0 : std_logic_vector(0 to 15) := x"0039";
constant mailbox_write_21_9_1 : std_logic_vector(0 to 15) := x"003A";
constant mailbox_write_21_10_0 : std_logic_vector(0 to 15) := x"003B";
constant mailbox_write_21_10_1 : std_logic_vector(0 to 15) := x"003C";
constant mailbox_write_21_11_0 : std_logic_vector(0 to 15) := x"003D";
constant mailbox_write_21_12_0 : std_logic_vector(0 to 15) := x"003E";
constant mailbox_write_21_12_1 : std_logic_vector(0 to 15) := x"003F";
constant mailbox_write_21_13_0 : std_logic_vector(0 to 15) := x"0040";
constant mailbox_write_21_14_0 : std_logic_vector(0 to 15) := x"0041";
constant mailbox_write_21_15_0 : std_logic_vector(0 to 15) := x"0042";
constant mailbox_write_21_15_1 : std_logic_vector(0 to 15) := x"0043";
constant mailbox_write_21_15_2 : std_logic_vector(0 to 15) := x"0044";
constant mailbox_write_21_16_0 : std_logic_vector(0 to 15) := x"0045";
constant mailbox_write_21_17_0 : std_logic_vector(0 to 15) := x"0046";
constant mailbox_write_21_17_1 : std_logic_vector(0 to 15) := x"0047";
constant mailbox_write_21_17_2 : std_logic_vector(0 to 15) := x"0048";
constant mailbox_write_21_18_0 : std_logic_vector(0 to 15) := x"0049";
constant mailbox_write_restore_0 : std_logic_vector(0 to 15) := x"004A";
constant mailbox_write_restore_1 : std_logic_vector(0 to 15) := x"004B";
constant mailbox_write_restore_2 : std_logic_vector(0 to 15) := x"004C";
constant mailbox_write_restore_3 : std_logic_vector(0 to 15) := x"004D";
constant mailbox_write_restore_4 : std_logic_vector(0 to 15) := x"004E";
constant mailbox_write_end : std_logic_vector(0 to 15) := x"004F";
constant bubblesort_start : std_logic_vector(0 to 15) := x"0050";
constant bubblesort_save_0 : std_logic_vector(0 to 15) := x"0051";
constant bubblesort_save_1 : std_logic_vector(0 to 15) := x"0052";
constant bubblesort_save_2 : std_logic_vector(0 to 15) := x"0053";
constant bubblesort_save_3 : std_logic_vector(0 to 15) := x"0054";
constant bubblesort_save_4 : std_logic_vector(0 to 15) := x"0055";
constant bubblesort_save_5 : std_logic_vector(0 to 15) := x"0056";
constant bubblesort_save_6 : std_logic_vector(0 to 15) := x"0057";
constant bubblesort_save_7 : std_logic_vector(0 to 15) := x"0058";
constant bubblesort_save_8 : std_logic_vector(0 to 15) := x"0059";
constant bubblesort_0_0_0 : std_logic_vector(0 to 15) := x"005A";
constant bubblesort_0_0_1 : std_logic_vector(0 to 15) := x"005B";
constant bubblesort_0_1_0 : std_logic_vector(0 to 15) := x"005C";
constant bubblesort_0_1_1 : std_logic_vector(0 to 15) := x"005D";
constant bubblesort_0_2_0 : std_logic_vector(0 to 15) := x"005E";
constant bubblesort_0_3_0 : std_logic_vector(0 to 15) := x"005F";
constant bubblesort_0_4_0 : std_logic_vector(0 to 15) := x"0060";
constant bubblesort_0_5_0 : std_logic_vector(0 to 15) := x"0061";
constant bubblesort_0_6_0 : std_logic_vector(0 to 15) := x"0062";
constant bubblesort_1_0_0 : std_logic_vector(0 to 15) := x"0063";
constant bubblesort_1_0_1 : std_logic_vector(0 to 15) := x"0064";
constant bubblesort_1_1_0 : std_logic_vector(0 to 15) := x"0065";
constant bubblesort_1_2_0 : std_logic_vector(0 to 15) := x"0066";
constant bubblesort_1_3_0 : std_logic_vector(0 to 15) := x"0067";
constant bubblesort_1_3_1 : std_logic_vector(0 to 15) := x"0068";
constant bubblesort_1_4_0 : std_logic_vector(0 to 15) := x"0069";
constant bubblesort_1_5_0 : std_logic_vector(0 to 15) := x"006A";
constant bubblesort_1_6_0 : std_logic_vector(0 to 15) := x"006B";
constant bubblesort_1_7_0 : std_logic_vector(0 to 15) := x"006C";
constant bubblesort_1_8_0 : std_logic_vector(0 to 15) := x"006D";
constant bubblesort_1_8_1 : std_logic_vector(0 to 15) := x"006E";
constant bubblesort_1_9_0 : std_logic_vector(0 to 15) := x"006F";
constant bubblesort_2_0_0 : std_logic_vector(0 to 15) := x"0070";
constant bubblesort_3_0_0 : std_logic_vector(0 to 15) := x"0071";
constant bubblesort_4_0_0 : std_logic_vector(0 to 15) := x"0072";
constant bubblesort_4_1_0 : std_logic_vector(0 to 15) := x"0073";
constant bubblesort_4_2_0 : std_logic_vector(0 to 15) := x"0074";
constant bubblesort_4_3_0 : std_logic_vector(0 to 15) := x"0075";
constant bubblesort_4_4_0 : std_logic_vector(0 to 15) := x"0076";
constant bubblesort_5_0_0 : std_logic_vector(0 to 15) := x"0077";
constant bubblesort_6_0_0 : std_logic_vector(0 to 15) := x"0078";
constant bubblesort_7_0_0 : std_logic_vector(0 to 15) := x"0079";
constant bubblesort_8_0_0 : std_logic_vector(0 to 15) := x"007A";
constant bubblesort_9_0_0 : std_logic_vector(0 to 15) := x"007B";
constant bubblesort_10_0_0 : std_logic_vector(0 to 15) := x"007C";
constant bubblesort_11_0_0 : std_logic_vector(0 to 15) := x"007D";
constant bubblesort_12_0_0 : std_logic_vector(0 to 15) := x"007E";
constant bubblesort_12_1_0 : std_logic_vector(0 to 15) := x"007F";
constant bubblesort_12_2_0 : std_logic_vector(0 to 15) := x"0080";
constant bubblesort_12_3_0 : std_logic_vector(0 to 15) := x"0081";
constant bubblesort_13_0_0 : std_logic_vector(0 to 15) := x"0082";
constant bubblesort_restore_0 : std_logic_vector(0 to 15) := x"0083";
constant bubblesort_restore_1 : std_logic_vector(0 to 15) := x"0084";
constant bubblesort_restore_2 : std_logic_vector(0 to 15) := x"0085";
constant bubblesort_restore_3 : std_logic_vector(0 to 15) := x"0086";
constant bubblesort_restore_4 : std_logic_vector(0 to 15) := x"0087";
constant bubblesort_restore_5 : std_logic_vector(0 to 15) := x"0088";
constant bubblesort_restore_6 : std_logic_vector(0 to 15) := x"0089";
constant bubblesort_restore_7 : std_logic_vector(0 to 15) := x"008A";
constant bubblesort_restore_8 : std_logic_vector(0 to 15) := x"008B";
constant bubblesort_end : std_logic_vector(0 to 15) := x"008C";
constant mailbox_read_start : std_logic_vector(0 to 15) := x"008D";
constant mailbox_read_save_0 : std_logic_vector(0 to 15) := x"008E";
constant mailbox_read_save_1 : std_logic_vector(0 to 15) := x"008F";
constant mailbox_read_save_2 : std_logic_vector(0 to 15) := x"0090";
constant mailbox_read_save_3 : std_logic_vector(0 to 15) := x"0091";
constant mailbox_read_save_4 : std_logic_vector(0 to 15) := x"0092";
constant mailbox_read_23_0_0 : std_logic_vector(0 to 15) := x"0093";
constant mailbox_read_23_0_1 : std_logic_vector(0 to 15) := x"0094";
constant mailbox_read_23_1_0 : std_logic_vector(0 to 15) := x"0095";
constant mailbox_read_23_2_0 : std_logic_vector(0 to 15) := x"0096";
constant mailbox_read_23_3_0 : std_logic_vector(0 to 15) := x"0097";
constant mailbox_read_23_3_1 : std_logic_vector(0 to 15) := x"0098";
constant mailbox_read_23_3_2 : std_logic_vector(0 to 15) := x"0099";
constant mailbox_read_23_4_0 : std_logic_vector(0 to 15) := x"009A";
constant mailbox_read_23_4_1 : std_logic_vector(0 to 15) := x"009B";
constant mailbox_read_23_5_0 : std_logic_vector(0 to 15) := x"009C";
constant mailbox_read_24_0_0 : std_logic_vector(0 to 15) := x"009D";
constant mailbox_read_25_0_0 : std_logic_vector(0 to 15) := x"009E";
constant mailbox_read_26_0_0 : std_logic_vector(0 to 15) := x"009F";
constant mailbox_read_26_1_0 : std_logic_vector(0 to 15) := x"00A0";
constant mailbox_read_26_1_1 : std_logic_vector(0 to 15) := x"00A1";
constant mailbox_read_26_1_2 : std_logic_vector(0 to 15) := x"00A2";
constant mailbox_read_26_1_3 : std_logic_vector(0 to 15) := x"00A3";
constant mailbox_read_26_2_0 : std_logic_vector(0 to 15) := x"00A4";
constant mailbox_read_26_2_1 : std_logic_vector(0 to 15) := x"00A5";
constant mailbox_read_26_3_0 : std_logic_vector(0 to 15) := x"00A6";
constant mailbox_read_27_0_0 : std_logic_vector(0 to 15) := x"00A7";
constant mailbox_read_28_0_0 : std_logic_vector(0 to 15) := x"00A8";
constant mailbox_read_29_0_0 : std_logic_vector(0 to 15) := x"00A9";
constant mailbox_read_29_0_1 : std_logic_vector(0 to 15) := x"00AA";
constant mailbox_read_29_1_0 : std_logic_vector(0 to 15) := x"00AB";
constant mailbox_read_29_2_0 : std_logic_vector(0 to 15) := x"00AC";
constant mailbox_read_29_2_1 : std_logic_vector(0 to 15) := x"00AD";
constant mailbox_read_29_3_0 : std_logic_vector(0 to 15) := x"00AE";
constant mailbox_read_29_4_0 : std_logic_vector(0 to 15) := x"00AF";
constant mailbox_read_29_5_0 : std_logic_vector(0 to 15) := x"00B0";
constant mailbox_read_29_5_1 : std_logic_vector(0 to 15) := x"00B1";
constant mailbox_read_29_6_0 : std_logic_vector(0 to 15) := x"00B2";
constant mailbox_read_29_7_0 : std_logic_vector(0 to 15) := x"00B3";
constant mailbox_read_29_7_1 : std_logic_vector(0 to 15) := x"00B4";
constant mailbox_read_29_8_0 : std_logic_vector(0 to 15) := x"00B5";
constant mailbox_read_29_9_0 : std_logic_vector(0 to 15) := x"00B6";
constant mailbox_read_29_10_0 : std_logic_vector(0 to 15) := x"00B7";
constant mailbox_read_29_10_1 : std_logic_vector(0 to 15) := x"00B8";
constant mailbox_read_29_11_0 : std_logic_vector(0 to 15) := x"00B9";
constant mailbox_read_29_11_1 : std_logic_vector(0 to 15) := x"00BA";
constant mailbox_read_29_12_0 : std_logic_vector(0 to 15) := x"00BB";
constant mailbox_read_29_13_0 : std_logic_vector(0 to 15) := x"00BC";
constant mailbox_read_29_13_1 : std_logic_vector(0 to 15) := x"00BD";
constant mailbox_read_29_14_0 : std_logic_vector(0 to 15) := x"00BE";
constant mailbox_read_29_15_0 : std_logic_vector(0 to 15) := x"00BF";
constant mailbox_read_29_16_0 : std_logic_vector(0 to 15) := x"00C0";
constant mailbox_read_29_16_1 : std_logic_vector(0 to 15) := x"00C1";
constant mailbox_read_29_16_2 : std_logic_vector(0 to 15) := x"00C2";
constant mailbox_read_29_17_0 : std_logic_vector(0 to 15) := x"00C3";
constant mailbox_read_29_18_0 : std_logic_vector(0 to 15) := x"00C4";
constant mailbox_read_29_18_1 : std_logic_vector(0 to 15) := x"00C5";
constant mailbox_read_29_18_2 : std_logic_vector(0 to 15) := x"00C6";
constant mailbox_read_29_19_0 : std_logic_vector(0 to 15) := x"00C7";
constant mailbox_read_restore_0 : std_logic_vector(0 to 15) := x"00C8";
constant mailbox_read_restore_1 : std_logic_vector(0 to 15) := x"00C9";
constant mailbox_read_restore_2 : std_logic_vector(0 to 15) := x"00CA";
constant mailbox_read_restore_3 : std_logic_vector(0 to 15) := x"00CB";
constant mailbox_read_restore_4 : std_logic_vector(0 to 15) := x"00CC";
constant mailbox_read_end : std_logic_vector(0 to 15) := x"00CD";
constant sort8k_entry_start : std_logic_vector(0 to 15) := x"00CE";
constant sort8k_entry_save_0 : std_logic_vector(0 to 15) := x"00CF";
constant sort8k_entry_save_1 : std_logic_vector(0 to 15) := x"00D0";
constant sort8k_entry_31_0_0 : std_logic_vector(0 to 15) := x"00D1";
constant sort8k_entry_31_0_1 : std_logic_vector(0 to 15) := x"00D2";
constant sort8k_entry_31_1_0 : std_logic_vector(0 to 15) := x"00D3";
constant sort8k_entry_32_0_0 : std_logic_vector(0 to 15) := x"00D4";
constant sort8k_entry_32_1_0 : std_logic_vector(0 to 15) := x"00D5";
constant sort8k_entry_32_1_1 : std_logic_vector(0 to 15) := x"00D6";
constant sort8k_entry_32_1_2 : std_logic_vector(0 to 15) := x"00D7";
constant sort8k_entry_32_2_0 : std_logic_vector(0 to 15) := x"00D8";
constant sort8k_entry_32_2_1 : std_logic_vector(0 to 15) := x"00D9";
constant sort8k_entry_32_2_2 : std_logic_vector(0 to 15) := x"00DA";
constant sort8k_entry_32_2_3 : std_logic_vector(0 to 15) := x"00DB";
constant sort8k_entry_32_3_0 : std_logic_vector(0 to 15) := x"00DC";
constant sort8k_entry_32_4_0 : std_logic_vector(0 to 15) := x"00DD";
constant sort8k_entry_32_4_1 : std_logic_vector(0 to 15) := x"00DE";
constant sort8k_entry_32_4_2 : std_logic_vector(0 to 15) := x"00DF";
constant sort8k_entry_32_4_3 : std_logic_vector(0 to 15) := x"00E0";
constant sort8k_entry_32_5_0 : std_logic_vector(0 to 15) := x"00E1";
constant sort8k_entry_33_0_0 : std_logic_vector(0 to 15) := x"00E2";
constant sort8k_entry_restore_0 : std_logic_vector(0 to 15) := x"00E3";
constant sort8k_entry_restore_1 : std_logic_vector(0 to 15) := x"00E4";
constant sort8k_entry_end : std_logic_vector(0 to 15) := x"00E5";
constant MULT00 : std_logic_vector(0 to 15) := x"00E6";
constant MULT01 : std_logic_vector(0 to 15) := x"00E7";
constant MULT02 : std_logic_vector(0 to 15) := x"00E8";
constant DIVIDE00 : std_logic_vector(0 to 15) := x"00E9";
constant DIVIDE01 : std_logic_vector(0 to 15) := x"00EA";
constant DIVIDE02 : std_logic_vector(0 to 15) := x"00EB";
constant DIVIDE03 : std_logic_vector(0 to 15) := x"00EC";
constant DIVIDE04 : std_logic_vector(0 to 15) := x"00ED";
constant DIVIDE05 : std_logic_vector(0 to 15) := x"00EE";
-- REGISTER DECLARATIONS
-- Special purpose registers
signal curstate : std_logic_vector(0 to 15) := START_STATE;
signal returnstate : std_logic_vector(0 to 15) := WAIT_STATE;
signal returnVal : std_logic_vector(0 to 31) := x"00000000";
signal stack_mem : std_logic_vector(0 to 31) := x"00000000";
signal params_mem : std_logic_vector(0 to 31) := x"00000000";
-- Caller save registers
signal T1 : std_logic_vector(0 to 31) := x"00000000";
signal T2 : std_logic_vector(0 to 31) := x"00000000";
signal T3 : std_logic_vector(0 to 31) := x"00000000";
signal T4 : std_logic_vector(0 to 31) := x"00000000";
signal T5 : std_logic_vector(0 to 31) := x"00000000";
signal T6 : std_logic_vector(0 to 31) := x"00000000";
-- Callee save registers
signal R4 : std_logic_vector(0 to 31) := x"00000000";
signal R5 : std_logic_vector(0 to 31) := x"00000000";
signal R6 : std_logic_vector(0 to 31) := x"00000000";
signal R7 : std_logic_vector(0 to 31) := x"00000000";
signal R0 : std_logic_vector(0 to 31) := x"00000000";
signal R1 : std_logic_vector(0 to 31) := x"00000000";
signal R2 : std_logic_vector(0 to 31) := x"00000000";
signal R3 : std_logic_vector(0 to 31) := x"00000000";
signal R8 : std_logic_vector(0 to 31) := x"00000000";
BEGIN
state_mach : PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF (intrfc2thrd_goWait = '1') and (intrfc2thrd_function = U_FUNCTION_RESET) THEN
-- Reset event
thrd2intrfc_address <= x"00000000";
thrd2intrfc_value <= x"00000000";
thrd2intrfc_function <= x"0000";
thrd2intrfc_opcode <= "000000";
curstate <= START_STATE;
returnstate <= WAIT_STATE;
returnVal <= x"00000000";
stack_mem <= x"00000000";
params_mem <= x"00000000";
T1 <= x"00000000";
T2 <= x"00000000";
T3 <= x"00000000";
T4 <= x"00000000";
T5 <= x"00000000";
T6 <= x"00000000";
R4 <= x"00000000";
R5 <= x"00000000";
R6 <= x"00000000";
R7 <= x"00000000";
R0 <= x"00000000";
R1 <= x"00000000";
R2 <= x"00000000";
R3 <= x"00000000";
R8 <= x"00000000";
ELSE
IF (intrfc2thrd_goWait = '1') THEN
thrd2intrfc_opcode <= OPCODE_NOOP; --OPCODE IS NOOP BY DEFAULT
CASE curstate IS
-- Start loops while function code is "start"
WHEN START_STATE =>
IF intrfc2thrd_function = U_FUNCTION_START THEN
curstate <= START_STATE;
ELSE
curstate <= BOOTSTRAP0;
END IF;
WHEN BOOTSTRAP0 =>
-- Call addressof to get the stack_mem pointer value.
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_ADDRESSOF;
curstate <= WAIT_STATE;
returnstate <= BOOTSTRAP1;
WHEN BOOTSTRAP1 =>
-- Use the result of the addressof to set stack_mem and params_mem.
-- Also call the declare opcode to initialize the stack for the thread main function.
stack_mem <= intrfc2thrd_value;
params_mem <= intrfc2thrd_value - x"00000010";
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
-- Begin of function mailbox_write (from mailbox_no_globals.c.hif)
WHEN mailbox_write_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_0;
WHEN mailbox_write_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_1;
WHEN mailbox_write_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_2;
WHEN mailbox_write_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_3;
WHEN mailbox_write_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_4;
WHEN mailbox_write_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_0;
WHEN mailbox_write_15_0_0 =>
-- arith2: @readarg R2 0 (296)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_1;
WHEN mailbox_write_15_0_1 =>
-- Capture result of readarg.
R2 <= intrfc2thrd_value;
curstate <= mailbox_write_15_1_0;
WHEN mailbox_write_15_1_0 =>
-- arith2: @readarg R4 1 (297)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_1_1;
WHEN mailbox_write_15_1_1 =>
-- Capture result of readarg.
R4 <= intrfc2thrd_value;
curstate <= mailbox_write_15_2_0;
WHEN mailbox_write_15_2_0 =>
-- arith3: @add R0 R2 20 (0)
R0 <= R2 + x"00000014";
curstate <= mailbox_write_15_3_0;
WHEN mailbox_write_15_3_0 =>
-- arith2: @mov R3 R0 (320)
R3 <= R0;
curstate <= mailbox_write_15_4_0;
WHEN mailbox_write_15_4_0 =>
-- call hthread_mutex_lock R3 @returnVal @none (321)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_4_1;
WHEN mailbox_write_15_4_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_15_4_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_15_4_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_5_0;
WHEN mailbox_write_15_5_0 =>
-- read R0 R2 12 (322)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_5_1;
WHEN mailbox_write_15_5_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_15_6_0;
WHEN mailbox_write_15_6_0 =>
-- read R1 R2 0 (323)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_6_1;
WHEN mailbox_write_15_6_1 =>
-- Capture result of read.
R1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_7_0;
WHEN mailbox_write_15_7_0 =>
-- if R1 S> R0 goto hif_label0(17) (324)
if (R1 > R0) then
curstate <= mailbox_write_17_0_0;
else
curstate <= mailbox_write_16_0_0;
end if;
WHEN mailbox_write_16_0_0 =>
-- goto HIFL0(18) (325)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_17_0_0 =>
-- goto HIFL2(21) (328)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_18_0_0 =>
-- arith3: @add R0 R2 32 (0)
R0 <= R2 + x"00000020";
curstate <= mailbox_write_18_1_0;
WHEN mailbox_write_18_1_0 =>
-- call hthread_cond_wait R0 R3 @returnVal @none (333)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_1;
WHEN mailbox_write_18_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_2;
WHEN mailbox_write_18_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_write_18_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_18_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_18_2_0;
WHEN mailbox_write_18_2_0 =>
-- read R0 R2 12 (334)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_2_1;
WHEN mailbox_write_18_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_3_0;
WHEN mailbox_write_18_3_0 =>
-- arith2: @mov R1 R0 (334)
R1 <= R0;
curstate <= mailbox_write_18_4_0;
WHEN mailbox_write_18_4_0 =>
-- read R0 R2 0 (335)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_4_1;
WHEN mailbox_write_18_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_5_0;
WHEN mailbox_write_18_5_0 =>
-- if R1 S< R0 goto hif_label2(20) (336)
if (R1 < R0) then
curstate <= mailbox_write_20_0_0;
else
curstate <= mailbox_write_19_0_0;
end if;
WHEN mailbox_write_19_0_0 =>
-- goto HIFL0(18) (337)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_20_0_0 =>
-- goto HIFL2(21) (340)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_21_0_0 =>
-- read R0 R2 16 (344)
thrd2intrfc_address <= R2 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_0_1;
WHEN mailbox_write_21_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_1_0;
WHEN mailbox_write_21_1_0 =>
-- arith2: @mov R1 R0 (344)
R1 <= R0;
curstate <= mailbox_write_21_2_0;
WHEN mailbox_write_21_2_0 =>
-- read R0 R2 8 (345)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_2_1;
WHEN mailbox_write_21_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_3_0;
WHEN mailbox_write_21_3_0 =>
-- arith3: @mul R0 R0 4 (347)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_3_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_write_21_3_1 =>
R0 <= returnVal;
curstate <= mailbox_write_21_4_0;
WHEN mailbox_write_21_4_0 =>
-- arith3: @add R0 R1 R0 (349)
R0 <= R1 + R0;
curstate <= mailbox_write_21_5_0;
WHEN mailbox_write_21_5_0 =>
-- arith2: @mov R1 R4 (350)
R1 <= R4;
curstate <= mailbox_write_21_6_0;
WHEN mailbox_write_21_6_0 =>
-- write R0 0 R1 (350)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_0;
WHEN mailbox_write_21_7_0 =>
-- read R0 R2 8 (351)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_1;
WHEN mailbox_write_21_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_8_0;
WHEN mailbox_write_21_8_0 =>
-- arith3: @add R1 R0 1 (352)
R1 <= R0 + x"00000001";
curstate <= mailbox_write_21_9_0;
WHEN mailbox_write_21_9_0 =>
-- read R0 R2 0 (353)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_9_1;
WHEN mailbox_write_21_9_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_10_0;
WHEN mailbox_write_21_10_0 =>
-- arith3: @mod R0 R1 R0 (354)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_10_1; --return address
T2 <= R1; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_write_21_10_1 =>
R0 <= T4;
curstate <= mailbox_write_21_11_0;
WHEN mailbox_write_21_11_0 =>
-- write R2 8 R0 (355)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_0;
WHEN mailbox_write_21_12_0 =>
-- read R0 R2 12 (356)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_1;
WHEN mailbox_write_21_12_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_13_0;
WHEN mailbox_write_21_13_0 =>
-- arith3: @add R0 R0 1 (357)
R0 <= R0 + x"00000001";
curstate <= mailbox_write_21_14_0;
WHEN mailbox_write_21_14_0 =>
-- write R2 12 R0 (358)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_0;
WHEN mailbox_write_21_15_0 =>
-- call hthread_mutex_unlock R3 @returnVal @none (359)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_1;
WHEN mailbox_write_21_15_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_21_15_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_15_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_16_0;
WHEN mailbox_write_21_16_0 =>
-- arith3: @add R0 R2 28 (0)
R0 <= R2 + x"0000001C";
curstate <= mailbox_write_21_17_0;
WHEN mailbox_write_21_17_0 =>
-- call hthread_cond_signal R0 @returnVal @none (361)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_17_1;
WHEN mailbox_write_21_17_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_write_21_17_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_17_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_18_0;
WHEN mailbox_write_21_18_0 =>
-- return 0 (362)
T1 <= x"00000000";
curstate <= mailbox_write_restore_0;
WHEN mailbox_write_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_1;
WHEN mailbox_write_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_2;
WHEN mailbox_write_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_3;
WHEN mailbox_write_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_4;
WHEN mailbox_write_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_end;
WHEN mailbox_write_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function bubblesort (from bubblesort.c.hif)
WHEN bubblesort_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000009";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_0;
WHEN bubblesort_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_1;
WHEN bubblesort_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_2;
WHEN bubblesort_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_3;
WHEN bubblesort_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_4;
WHEN bubblesort_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_5;
WHEN bubblesort_save_5 =>
-- Save register R5 on the stack.
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_value <= R5;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_6;
WHEN bubblesort_save_6 =>
-- Save register R6 on the stack.
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_value <= R6;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_7;
WHEN bubblesort_save_7 =>
-- Save register R7 on the stack.
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_value <= R7;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_8;
WHEN bubblesort_save_8 =>
-- Save register R8 on the stack.
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_value <= R8;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_0;
WHEN bubblesort_0_0_0 =>
-- arith2: @readarg R1 0 (7)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_1;
WHEN bubblesort_0_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= bubblesort_0_1_0;
WHEN bubblesort_0_1_0 =>
-- arith2: @readarg R0 1 (8)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_1_1;
WHEN bubblesort_0_1_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_0_2_0;
WHEN bubblesort_0_2_0 =>
-- arith3: @sub R4 R0 1 (24)
R4 <= R0 - x"00000001";
curstate <= bubblesort_0_3_0;
WHEN bubblesort_0_3_0 =>
-- arith2: @mov R2 R4 (25)
R2 <= R4;
curstate <= bubblesort_0_4_0;
WHEN bubblesort_0_4_0 =>
-- arith2: @mov R8 0 (26)
R8 <= x"00000000";
curstate <= bubblesort_0_5_0;
WHEN bubblesort_0_5_0 =>
-- arith2: @mov R3 0 (27)
R3 <= x"00000000";
curstate <= bubblesort_0_6_0;
WHEN bubblesort_0_6_0 =>
-- goto HIFL9(6) (28)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_1_0_0 =>
-- arith3: @mul R7 R3 4 (30)
--call quick function (will set returnVal)
T1 <= x"0000"&bubblesort_1_0_1; --return address
T2 <= R3; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN bubblesort_1_0_1 =>
R7 <= returnVal;
curstate <= bubblesort_1_1_0;
WHEN bubblesort_1_1_0 =>
-- arith2: @mov R0 R7 (31)
R0 <= R7;
curstate <= bubblesort_1_2_0;
WHEN bubblesort_1_2_0 =>
-- arith3: @add R6 R0 R1 (32)
R6 <= R0 + R1;
curstate <= bubblesort_1_3_0;
WHEN bubblesort_1_3_0 =>
-- read R0 R6 0 (33)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_3_1;
WHEN bubblesort_1_3_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_4_0;
WHEN bubblesort_1_4_0 =>
-- arith2: @mov R5 R0 (33)
R5 <= R0;
curstate <= bubblesort_1_5_0;
WHEN bubblesort_1_5_0 =>
-- arith2: @mov R0 R7 (34)
R0 <= R7;
curstate <= bubblesort_1_6_0;
WHEN bubblesort_1_6_0 =>
-- arith3: @add R0 R1 R0 (35)
R0 <= R1 + R0;
curstate <= bubblesort_1_7_0;
WHEN bubblesort_1_7_0 =>
-- arith3: @add R7 R0 4 (36)
R7 <= R0 + x"00000004";
curstate <= bubblesort_1_8_0;
WHEN bubblesort_1_8_0 =>
-- read R0 R7 0 (37)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_8_1;
WHEN bubblesort_1_8_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_9_0;
WHEN bubblesort_1_9_0 =>
-- if R5 U<= R0 goto hif_label0(3) (38)
if (R5 <= R0) then
curstate <= bubblesort_3_0_0;
else
curstate <= bubblesort_2_0_0;
end if;
WHEN bubblesort_2_0_0 =>
-- goto HIFL2(4) (39)
curstate <= bubblesort_4_0_0;
WHEN bubblesort_3_0_0 =>
-- goto HIFL3(5) (42)
curstate <= bubblesort_5_0_0;
WHEN bubblesort_4_0_0 =>
-- write R6 0 R0 (46)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_1_0;
WHEN bubblesort_4_1_0 =>
-- arith2: @mov R0 R5 (47)
R0 <= R5;
curstate <= bubblesort_4_2_0;
WHEN bubblesort_4_2_0 =>
-- write R7 0 R0 (47)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_3_0;
WHEN bubblesort_4_3_0 =>
-- arith2: @mov R2 R3 (48)
R2 <= R3;
curstate <= bubblesort_4_4_0;
WHEN bubblesort_4_4_0 =>
-- arith2: @mov R8 1 (49)
R8 <= x"00000001";
curstate <= bubblesort_5_0_0;
WHEN bubblesort_5_0_0 =>
-- arith3: @add R3 R3 1 (51)
R3 <= R3 + x"00000001";
curstate <= bubblesort_6_0_0;
WHEN bubblesort_6_0_0 =>
-- if R3 U>= R4 goto hif_label2(8) (53)
if (R3 >= R4) then
curstate <= bubblesort_8_0_0;
else
curstate <= bubblesort_7_0_0;
end if;
WHEN bubblesort_7_0_0 =>
-- goto HIFL1(1) (54)
curstate <= bubblesort_1_0_0;
WHEN bubblesort_8_0_0 =>
-- goto HIFL6(9) (57)
curstate <= bubblesort_9_0_0;
WHEN bubblesort_9_0_0 =>
-- if R8 S== 0 goto hif_label4(11) (61)
if (R8 = x"00000000") then
curstate <= bubblesort_11_0_0;
else
curstate <= bubblesort_10_0_0;
end if;
WHEN bubblesort_10_0_0 =>
-- goto HIFL12(12) (62)
curstate <= bubblesort_12_0_0;
WHEN bubblesort_11_0_0 =>
-- goto HIFL7(13) (65)
curstate <= bubblesort_13_0_0;
WHEN bubblesort_12_0_0 =>
-- arith2: @mov R4 R2 (69)
R4 <= R2;
curstate <= bubblesort_12_1_0;
WHEN bubblesort_12_1_0 =>
-- arith2: @mov R8 0 (70)
R8 <= x"00000000";
curstate <= bubblesort_12_2_0;
WHEN bubblesort_12_2_0 =>
-- arith2: @mov R3 0 (71)
R3 <= x"00000000";
curstate <= bubblesort_12_3_0;
WHEN bubblesort_12_3_0 =>
-- goto HIFL9(6) (72)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_13_0_0 =>
-- return @none (74)
T1 <= x"00000000";
curstate <= bubblesort_restore_0;
WHEN bubblesort_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_1;
WHEN bubblesort_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_2;
WHEN bubblesort_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_3;
WHEN bubblesort_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_4;
WHEN bubblesort_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_5;
WHEN bubblesort_restore_5 =>
-- Restore register R5 from the stack.
R4 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_6;
WHEN bubblesort_restore_6 =>
-- Restore register R6 from the stack.
R5 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_7;
WHEN bubblesort_restore_7 =>
-- Restore register R7 from the stack.
R6 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_8;
WHEN bubblesort_restore_8 =>
-- Restore register R8 from the stack.
R7 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_end;
WHEN bubblesort_end =>
-- Use the return opcode to jump back to the caller.
R8 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function mailbox_read (from mailbox_no_globals.c.hif)
WHEN mailbox_read_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_0;
WHEN mailbox_read_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_1;
WHEN mailbox_read_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_2;
WHEN mailbox_read_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_3;
WHEN mailbox_read_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_4;
WHEN mailbox_read_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_0;
WHEN mailbox_read_23_0_0 =>
-- arith2: @readarg R1 0 (57)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_1;
WHEN mailbox_read_23_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_1_0;
WHEN mailbox_read_23_1_0 =>
-- arith3: @add R0 R1 20 (0)
R0 <= R1 + x"00000014";
curstate <= mailbox_read_23_2_0;
WHEN mailbox_read_23_2_0 =>
-- arith2: @mov R2 R0 (78)
R2 <= R0;
curstate <= mailbox_read_23_3_0;
WHEN mailbox_read_23_3_0 =>
-- call hthread_mutex_lock R2 @returnVal @none (79)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_3_1;
WHEN mailbox_read_23_3_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_23_3_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_23_3_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_4_0;
WHEN mailbox_read_23_4_0 =>
-- read R0 R1 12 (80)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_4_1;
WHEN mailbox_read_23_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_23_5_0;
WHEN mailbox_read_23_5_0 =>
-- if R0 S> 0 goto hif_label0(25) (81)
if (R0 > x"00000000") then
curstate <= mailbox_read_25_0_0;
else
curstate <= mailbox_read_24_0_0;
end if;
WHEN mailbox_read_24_0_0 =>
-- goto HIFL0(26) (82)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_25_0_0 =>
-- goto HIFL2(29) (85)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_26_0_0 =>
-- arith3: @add R0 R1 28 (0)
R0 <= R1 + x"0000001C";
curstate <= mailbox_read_26_1_0;
WHEN mailbox_read_26_1_0 =>
-- call hthread_cond_wait R0 R2 @returnVal @none (90)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_1;
WHEN mailbox_read_26_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_2;
WHEN mailbox_read_26_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_read_26_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_26_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_26_2_0;
WHEN mailbox_read_26_2_0 =>
-- read R0 R1 12 (91)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_2_1;
WHEN mailbox_read_26_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_26_3_0;
WHEN mailbox_read_26_3_0 =>
-- if R0 S> 0 goto hif_label2(28) (92)
if (R0 > x"00000000") then
curstate <= mailbox_read_28_0_0;
else
curstate <= mailbox_read_27_0_0;
end if;
WHEN mailbox_read_27_0_0 =>
-- goto HIFL0(26) (93)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_28_0_0 =>
-- goto HIFL2(29) (96)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_29_0_0 =>
-- read R0 R1 16 (100)
thrd2intrfc_address <= R1 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_0_1;
WHEN mailbox_read_29_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_1_0;
WHEN mailbox_read_29_1_0 =>
-- arith2: @mov R4 R0 (100)
R4 <= R0;
curstate <= mailbox_read_29_2_0;
WHEN mailbox_read_29_2_0 =>
-- read R0 R1 4 (101)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_2_1;
WHEN mailbox_read_29_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_3_0;
WHEN mailbox_read_29_3_0 =>
-- arith2: @mov R3 R0 (101)
R3 <= R0;
curstate <= mailbox_read_29_4_0;
WHEN mailbox_read_29_4_0 =>
-- arith2: @mov R0 R3 (102)
R0 <= R3;
curstate <= mailbox_read_29_5_0;
WHEN mailbox_read_29_5_0 =>
-- arith3: @mul R0 R0 4 (103)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_5_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_read_29_5_1 =>
R0 <= returnVal;
curstate <= mailbox_read_29_6_0;
WHEN mailbox_read_29_6_0 =>
-- arith3: @add R0 R4 R0 (105)
R0 <= R4 + R0;
curstate <= mailbox_read_29_7_0;
WHEN mailbox_read_29_7_0 =>
-- read R0 R0 0 (106)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_7_1;
WHEN mailbox_read_29_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_8_0;
WHEN mailbox_read_29_8_0 =>
-- arith2: @mov R4 R0 (106)
R4 <= R0;
curstate <= mailbox_read_29_9_0;
WHEN mailbox_read_29_9_0 =>
-- arith3: @add R3 R3 1 (107)
R3 <= R3 + x"00000001";
curstate <= mailbox_read_29_10_0;
WHEN mailbox_read_29_10_0 =>
-- read R0 R1 0 (108)
thrd2intrfc_address <= R1 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_10_1;
WHEN mailbox_read_29_10_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_11_0;
WHEN mailbox_read_29_11_0 =>
-- arith3: @mod R0 R3 R0 (109)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_11_1; --return address
T2 <= R3; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_read_29_11_1 =>
R0 <= T4;
curstate <= mailbox_read_29_12_0;
WHEN mailbox_read_29_12_0 =>
-- write R1 4 R0 (110)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_0;
WHEN mailbox_read_29_13_0 =>
-- read R0 R1 12 (111)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_1;
WHEN mailbox_read_29_13_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_14_0;
WHEN mailbox_read_29_14_0 =>
-- arith3: @sub R0 R0 1 (112)
R0 <= R0 - x"00000001";
curstate <= mailbox_read_29_15_0;
WHEN mailbox_read_29_15_0 =>
-- write R1 12 R0 (113)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_0;
WHEN mailbox_read_29_16_0 =>
-- call hthread_mutex_unlock R2 @returnVal @none (114)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_1;
WHEN mailbox_read_29_16_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_29_16_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_16_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_17_0;
WHEN mailbox_read_29_17_0 =>
-- arith3: @add R0 R1 32 (0)
R0 <= R1 + x"00000020";
curstate <= mailbox_read_29_18_0;
WHEN mailbox_read_29_18_0 =>
-- call hthread_cond_signal R0 @returnVal @none (116)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_18_1;
WHEN mailbox_read_29_18_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_read_29_18_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_18_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_19_0;
WHEN mailbox_read_29_19_0 =>
-- return R4 (117)
T1 <= R4;
curstate <= mailbox_read_restore_0;
WHEN mailbox_read_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_1;
WHEN mailbox_read_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_2;
WHEN mailbox_read_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_3;
WHEN mailbox_read_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_4;
WHEN mailbox_read_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_end;
WHEN mailbox_read_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function sort8k_entry (from sort8k_no_globals.c.hif)
WHEN sort8k_entry_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_0;
WHEN sort8k_entry_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_1;
WHEN sort8k_entry_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
WHEN sort8k_entry_31_0_0 =>
-- arith2: @readarg R0 0 (7)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_1;
WHEN sort8k_entry_31_0_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_31_1_0;
WHEN sort8k_entry_31_1_0 =>
-- arith2: @mov R1 R0 (37)
R1 <= R0;
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_32_0_0 =>
-- arith2: @mov R0 R1 (0)
R0 <= R1;
curstate <= sort8k_entry_32_1_0;
WHEN sort8k_entry_32_1_0 =>
-- call mailbox_read R0 @returnVal R0 (40)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_1_1;
WHEN sort8k_entry_32_1_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000018";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_read_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_1_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_1_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000018";
params_mem <= stack_mem - x"00000008";
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_2_0;
WHEN sort8k_entry_32_2_0 =>
-- call bubblesort R0 2048 @returnVal @none (43)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_1;
WHEN sort8k_entry_32_2_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000800";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_2;
WHEN sort8k_entry_32_2_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= bubblesort_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_2_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_2_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_3_0;
WHEN sort8k_entry_32_3_0 =>
-- arith3: @add R0 R1 36 (0)
R0 <= R1 + x"00000024";
curstate <= sort8k_entry_32_4_0;
WHEN sort8k_entry_32_4_0 =>
-- call mailbox_write R0 23 @returnVal @none (45)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_1;
WHEN sort8k_entry_32_4_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000017";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_2;
WHEN sort8k_entry_32_4_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_write_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_4_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_4_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_5_0;
WHEN sort8k_entry_32_5_0 =>
-- goto HIFL0(32) (46)
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_33_0_0 =>
-- return @none (0)
T1 <= x"00000000";
curstate <= sort8k_entry_restore_0;
WHEN sort8k_entry_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_restore_1;
WHEN sort8k_entry_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_end;
WHEN sort8k_entry_end =>
-- Use the return opcode to jump back to the caller.
R1 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
--multiply quick function
--implements 32 bit multiply
--assumes return address in T1, operands in T2 and T3
WHEN MULT00 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(16 to 31)), 32));
returnVal <= std_logic_vector(conv_signed(signed(b"00"&T2(0 to 15)) * signed(b"00"&T3(16 to 31)), 32));
curstate <= MULT01;
WHEN MULT01 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(0 to 15)), 32));
returnVal <= T4 + (returnVal(16 to 31)&x"0000");
curstate <= MULT02;
WHEN MULT02 =>
returnVal <= (T4(16 to 31)&x"0000") + returnVal;
curstate <= T1(16 to 31);
-- DIVIDE QUICK FUNCTION
-- inputs
-- T2 - dividend
-- T3 - divisor
-- outputs
-- returnVal - quotient
-- T4 - remainder
-- tmps
-- T5 - tmp_divisor
-- T6 - counter
WHEN DIVIDE00 =>
if (T2 < x"00000000") then -- init quotient
returnVal <= -T2;
else
returnVal <= T2;
end if;
T4 <= x"00000000"; -- init remainder
if (T3 < x"00000000") then -- init tmp_divisor
T5 <= -T3;
else
T5 <= T3;
end if;
T6 <= x"00000000"; -- init counter
curstate <= DIVIDE01;
WHEN DIVIDE01 =>
-- BEGIN LOOP
T6 <= T6 + x"00000001"; -- increment counter
T4 <= T4(1 to 31)&returnVal(0); -- remainder = remainder(1 to 31)"ient(0)
returnVal <= returnVal(1 to 31)&'0'; -- shift quotient left
curstate <= DIVIDE02;
WHEN DIVIDE02 =>
-- if the remainder is greater than tmp_divisor
if (T4 >= T5) then
returnVal(31) <= '1'; -- set lsb of quotient
T4 <= T4 - T5; -- subtract tmp_divisor from remainder
end if;
if (T6 < x"00000020") then -- check loop bound
curstate <= DIVIDE01; -- GO TO NEXT ITERATION
else
curstate <= DIVIDE03; -- LOOP IS DONE
end if;
WHEN DIVIDE03 =>
-- LOOP IS DONE
-- THE FOLLOWING STATES HANDLE THE SIGNED ASPECT
-- if dividend < 0
if (T2 < x"00000000") then
T4 <= -T4; -- remainder = -remainder
curstate <= DIVIDE04;
else
curstate <= DIVIDE05;
end if;
WHEN DIVIDE04 =>
if (T3 > x"00000000") then
returnVal <= -returnVal;
end if;
curstate <= T1(16 to 31); -- return to caller
WHEN DIVIDE05 =>
if (T3 < x"00000000") then
returnVal <= -returnVal; -- negate the quotient
end if;
curstate <= T1(16 to 31); -- return to caller
-- Other states
WHEN WAIT_STATE =>
curstate <= returnstate;
WHEN FUNCTCALL_STATE => -- give the HWTI control over the next state
curstate <= intrfc2thrd_function;
WHEN others => --this case should never be reached
curstate <= START_STATE;
END CASE;
END IF;
END IF;
END PROCESS;
END IMP;
| bsd-3-clause | 4e7630c93668895ce68c9a593937f51f | 0.55262 | 3.533168 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/wrpfifo_top.vhd | 3 | 22,156 | -------------------------------------------------------------------------------
-- $Id: wrpfifo_top.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Write Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
-- wrpfifo_top.vhd
-- |
-- |---> ipif_control_wr.vhd
-- |
-- |---> wrpfifo_dp_cntl.vhd
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | | |
-- | | |-- pf_adder_bit.vhd
-- | |
-- | |
-- | |-- pf_dly1_mux.vhd
-- |
-- |---> pf_dpram.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET Apr-24-01
-- - Change the dual port configuration name to wdport_512x32
-- from dport_512x32.
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- Commented out the rpfifo_lib declarations.
--
-- DET MAY-24-01
-- - v0.00B Incorporated the V0.00c dual port controller module
--
-- DET June-25-01
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
-- - Changed to V1.00b of the IPIF write Control module.
-- - Changed to the V1.00d version of the DP control module.
-- - Added input Generics for MIR enable and Block ID
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
-- - Added additional parameters (generics)
--
-- DET Oct. 02, 2001 (part of v1.02a version)
-- - added the optimization changes
--
--
-- DET Oct. 8, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_dpram_select;
Use opb_v20_v1_10_d.srl16_fifo;
Use opb_v20_v1_10_d.ipif_control_wr;
Use opb_v20_v1_10_d.wrpfifo_dp_cntl;
-------------------------------------------------------------------------------
entity wrpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq : In std_logic;
IP2WFIFO_RdMark : In std_logic;
IP2WFIFO_RdRestore : In std_logic;
IP2WFIFO_RdRelease : In std_logic;
-- Outputs to the IP
WFIFO2IP_Data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck : Out std_logic;
WFIFO2IP_AlmostEmpty : Out std_logic;
WFIFO2IP_Empty : Out std_logic;
WFIFO2IP_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull : Out std_logic;
WFIFO2DMA_Full : Out std_logic;
WFIFO2DMA_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end wrpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_top is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the WrPFIFO design
-- (0 = engineering release,
-- 1 = major release 1, etc.)
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the WrPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter of the WrPFIFO design
-- (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
-- IPIF block protocol Type (Read Packet FIFO = 2, Write PFIFO = 3)
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 3;
----------------------------------------------------------------------------
-- General Use Constants
----------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_fifo_wrack: std_logic;
Signal sig_fifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_wr_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_mem_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
-------------------------------------------------------------------------------
------------------------------- start processes -------------------------------
begin
-- connect I/O signals to internals
WFIFO2IP_RdAck <= sig_fifo_rdack;
WFIFO2IP_Empty <= sig_fifo_empty;
WFIFO2IP_AlmostEmpty <= sig_fifo_almost_empty;
WFIFO2IP_Occupancy <= sig_fifo_occupancy;
WFIFO2DMA_AlmostFull <= sig_fifo_almost_full;
WFIFO2DMA_Full <= sig_fifo_full ;
WFIFO2DMA_Vacancy <= sig_fifo_vacancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_rdreq <= IP2WFIFO_RdReq;
WFIFO2IP_Data <= sig_mem_rd_data;
I_IPIF_INTERFACE_BLOCK : entity opb_v20_v1_10_d.ipif_control_wr
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_clk => Bus_clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => Bus_DBus ,
-- Inputs from the FIFO Interface Logic
Fifo_WrAck => sig_fifo_wrack,
Vacancy => sig_fifo_vacancy,
AlmostFull => sig_fifo_almost_full,
Full => sig_fifo_full,
Deadlock => sig_fifo_deadlock,
-- Outputs to the FIFO
Fifo_wr_data => sig_mem_wr_data,
Fifo_Reset => sig_fifo_logic_reset,
Fifo_WrReq => sig_mem_wrreq,
Fifo_burst_wr_xfer => sig_burst_wr_xfer,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
begin
-- Connect the Dual Port Address Controller the VHDL wrapper
I_DP_CONTROLLER: entity opb_v20_v1_10_d.wrpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_clk,
Rdreq => sig_mem_rdreq,
Wrreq => sig_mem_wrreq,
Burst_wr_xfer => sig_burst_wr_xfer,
Mark => IP2WFIFO_RdMark,
Restore => IP2WFIFO_RdRestore,
Release => IP2WFIFO_RdRelease,
-- Outputs
WrAck => sig_fifo_wrack,
RdAck => sig_fifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_v20_v1_10_d.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_fifo_rdack <= sig_mem_rdreq and not(sig_fifo_empty);
sig_fifo_wrack <= sig_mem_wrreq and not(sig_fifo_full);
I_SRL_MEM : entity opb_v20_v1_10_d.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_mem_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
| bsd-3-clause | b5f9b8308130edf2a418475944fa9026 | 0.451661 | 4.166228 | false | false | false | false |
xdsopl/vhdl | ring_counter.vhd | 1 | 1,252 | -- ring_counter - ring counter logic written in vhdl
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity ring_counter is
generic (
SIZE : positive := 5;
START : natural := 2
);
port (
reset : in std_logic := '0';
direction : in std_logic;
clock : in std_logic;
output : out std_logic_vector (SIZE-1 downto 0) := (START => '1', others => '0')
);
end ring_counter;
architecture rtl of ring_counter is
signal cnt : std_logic_vector (SIZE-1 downto 0) := (START => '1', others => '0');
begin
output <= cnt;
process (reset, clock)
begin
if reset = '1' then
cnt <= (START => '1', others => '0');
elsif rising_edge(clock) then
if direction = '0' then
cnt <= cnt(0) & cnt(SIZE-1 downto 1);
else
cnt <= cnt(SIZE-2 downto 0) & cnt(SIZE-1);
end if;
end if;
end process;
end rtl;
| cc0-1.0 | c5e259aee939efa8d0f4b0b4a18737a7 | 0.674121 | 3.260417 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_eth.vhd | 1 | 21,823 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity g_eth is
generic(
RAM_RD_CYCLE : natural := 1;
RAM_WR_CYCLE : natural := 1;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(31 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of g_eth is
component g_ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component g_ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal debug_prog_ce : std_logic;
-- signal test_0 : std_logic_vector(3 downto 0);
signal txen_buf : std_logic;
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
-- test(2) <= test_0(2);
-- test(3) <= test_0(3);
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
u_rx : g_ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
-- test => test_0,
ram_wdata => ram_wdata
);
db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
(others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
u_tx : g_ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
txen <= txen_buf;
db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
(others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
(others => 'Z');
end arch_eth;
| gpl-2.0 | 9f0e6ebb1d3e0554cbe72dfa500763a8 | 0.57696 | 2.729922 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter.vhd | 3 | 6,847 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY_L
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
LO => carry_in_lsb);
I_COUNTER_BIT_LSB : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY_L
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
LO => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| bsd-3-clause | 5c2d1685c4d05d24768c3394f19cbe92 | 0.424419 | 4.102457 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/arb2bus_data_mux.vhd | 3 | 13,208 | -------------------------------------------------------------------------------
-- $Id: arb2bus_data_mux.vhd,v 1.1.2.1 2009/10/06 21:14:59 gburch Exp $
-------------------------------------------------------------------------------
-- arb2bus_data_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Filename: arb2bus_data_mux.vhd
-- Version: v1.02e
-- Description:
-- This file muxes the priority register and control register
-- data to the IP2BUS data bus during a read cycle.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
--
-- Definition of Ports:
--
-- -- IPIF interface signals
-- input Bus2IP_Reg_RdCE -- Read clock enables for registers
-- input Bus2IP_Reg_WrCE -- Write clock enables for registers
--
-- -- Data from control register
-- input Ctrl_reg
--
-- -- Data from priority registers
-- input Priority_regs
--
-- -- Multiplexed outputs based on register clock enables and
-- -- read/write requests
-- output Arb2bus_wrack -- mux'd output from register wracks
-- output Arb2bus_rdack -- register read acknowledge
-- output Arb2bus_data -- mux'd output data
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity arb2bus_data_mux is
generic ( C_NUM_MASTERS : integer := 4;
C_OPBDATA_WIDTH : integer := 32
);
port ( Bus2IP_Reg_RdCE : in std_logic_vector(0 to C_NUM_MASTERS);
Bus2IP_Reg_WrCE : in std_logic_vector(0 to C_NUM_MASTERS);
Ctrl_reg : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Priority_regs : in std_logic_vector (0 to C_NUM_MASTERS*C_OPBDATA_WIDTH-1);
Arb2bus_wrack : out std_logic ;
Arb2bus_rdack : out std_logic ;
Arb2bus_data : out std_logic_vector (0 to C_OPBDATA_WIDTH-1)
);
end arb2bus_data_mux;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of arb2bus_data_mux is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal all_registers : std_logic_vector(0 to (C_NUM_MASTERS+1)*C_OPBDATA_WIDTH -1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- ARB2BUS_DATA_PROCESS
-------------------------------------------------------------------------------
-- This process multiplexes the data from the priority registers and the
-- control register based on the register chip enables to generate
-- ARB2BUS_DATA
-------------------------------------------------------------------------------
all_registers <= Ctrl_reg & Priority_regs;
ARB2BUS_DATAMUX_I: entity opb_v20_v1_10_d.mux_onehot
generic map ( C_DW => C_OPBDATA_WIDTH,
C_NB => C_NUM_MASTERS+1)
port map (
D => all_registers,
S => Bus2IP_Reg_RdCE,
Y => Arb2bus_data
);
-------------------------------------------------------------------------------
-- ARB2BUS_RDACK
-------------------------------------------------------------------------------
-- ARB2BUS_RDACK is simply the OR of all Bus2IP read register chip enables
-- Use the OR_BITS component to perform the OR of these bits most efficiently
-------------------------------------------------------------------------------
ARB2BUS_RDACK_I: entity opb_v20_v1_10_d.or_bits
generic map ( C_NUM_BITS => C_NUM_MASTERS+1,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS+1)
port map (
In_bus => Bus2Ip_Reg_RdCE,
Sig => '0',
Or_out => Arb2bus_rdack
);
-------------------------------------------------------------------------------
-- ARB2BUS_WRACK generation
-------------------------------------------------------------------------------
-- This process ORs the wrack from the priority register logic and the
-- control register logic to generate ARB2BUS_WRACK
-------------------------------------------------------------------------------
ARB2BUS_WRACK_I: entity opb_v20_v1_10_d.or_bits
generic map ( C_NUM_BITS => C_NUM_MASTERS+1,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS+1)
port map (
In_bus => Bus2Ip_Reg_WrCE,
Sig => '0',
Or_out => Arb2bus_wrack
);
end implementation;
| bsd-3-clause | a4c447b8a2af454e2dfcacc412606950 | 0.394306 | 5.281088 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_3.vhd | 2 | 17,254 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_3.c
-- reg6 = * function
-- reg7 = thread
-- reg8 = * attr
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread, data->attr, data->function, (void *) data );
when STATE_3 =>
reg8_next <= intrfc2thrd_value;
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg8;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- data->attr->detached = Htrue;
when STATE_8 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg8;
thrd2intrfc_value <= x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
-- hthread_join( data->thread, NULL );
when STATE_9 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
when STATE_13 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 279487bdb4388c96a8dfeff021edfbc6 | 0.544685 | 3.800441 | false | false | false | false |
iocoder/graduation | hardware/kbd/ps2.vhd | 1 | 2,098 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ps2 is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Outputs
SENSE : out STD_LOGIC;
PACKET : out STD_LOGIC_VECTOR (7 downto 0) := x"00"
);
end entity;
architecture Behavioral of ps2 is
signal LAST_CLK : STD_LOGIC := '0';
signal SENSE_VAL : STD_LOGIC := '0';
signal PACKET_VAL : STD_LOGIC_VECTOR (7 downto 0) := x"00";
signal counter : integer range 0 to 15 := 0;
signal waiting : integer range 0 to 1000000 := 0;
begin
process (CLK)
begin
if (CLK = '1' and CLK'event) then
if (PS2CLK = '0' and LAST_CLK = '1') then
if (counter = 0) then
-- zero starting bit
counter <= counter + 1;
elsif (counter < 9) then
-- packer data
PACKET_VAL(counter-1) <= PS2DATA;
counter <= counter + 1;
elsif (counter = 9) then
-- parity
SENSE <= '1';
PACKET <= PACKET_VAL;
counter <= 10;
elsif (counter = 10) then
-- stopping bit.
SENSE <= '0';
counter <= 0;
elsif (counter = 11) then
-- wait for both CLK and DATA to be high.
if (PS2CLK = '1' and PS2DATA = '1') then
if (waiting = 10000) then
waiting <= 0;
counter <= 0;
else
waiting <= waiting+1;
end if;
else
waiting <= 0;
end if;
end if;
end if;
LAST_CLK <= PS2CLK;
end if;
end process;
end architecture;
| gpl-3.0 | 226c7e48db4a923b0ca26fcd969e8fbe | 0.42326 | 4.29918 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/queue/fifo2zcpsm.vhd | 1 | 3,928 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------------------
-- zcpsm fifo2zcpsm fifo_block
-- km_clk -- -- reset
-- ------------------- \ \
-- \ \ ------------------------------------
-- reset--\ in_port\--<--\zcpsm_in_port clk \--<--\ clk
--km_clk --\ out_port\-->--\zcpsm_out_port fifo_rdata\--<--\ fifo_rdata
-- \ port_id\-->--\zcpsm_port_id fifo_raddr\-->--\ fifo_raddr
-- \ read_strobe\-->--\zcpsm_read_strobe fifo_full \--<--\ fifo_full
-- \ write_strobe\-->--\zcpsm_write_strobe fifo_empty\--<--\ fifo_empty
-- \ \ \ fifo_rd_block\-->--\ fifo_rd_block
-- \
-- \
-- zcpsm_ce \--<-- eth_dma_ce
entity fifo2zcpsm is
generic(
BLOCK_AWIDTH : integer; --5
DWIDTH : integer -- 8
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_rd_block : out std_logic;
fifo_raddr : out std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
fifo_rdata : in std_logic_vector(DWIDTH - 1 downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic
);
end entity;
architecture behave of fifo2zcpsm is
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
signal zcpsm_we : std_logic;
signal zcpsm_re : std_logic;
signal zcpsm_addr : std_logic_vector(3 downto 0);
signal rd_block_en : std_logic;
signal fifo_raddr_reg : std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
constant PORT_IO_ADDR : std_logic_vector(3 downto 0) := X"0"; -- low 4 bits
constant PORT_IO_DATA : std_logic_vector(3 downto 0) := X"1";
constant PORT_QUEUE_STATUS : std_logic_vector(3 downto 0) := X"2";
constant PORT_RD_BLOCK : std_logic_vector(3 downto 0) := X"5";
begin
zcpsm_we <= zcpsm_ce and zcpsm_write_strobe;
zcpsm_re <= zcpsm_ce and zcpsm_read_strobe;
zcpsm_addr <= '0' & zcpsm_port_id(3 downto 1);
zcpsm_in_port <= "000000" & fifo_empty & fifo_full when zcpsm_ce = '1' and zcpsm_addr = PORT_QUEUE_STATUS else (others => 'Z');
u_rd_block : asyncwrite
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rd_block_en,
trigger => '1',
sync_wren => fifo_rd_block,
over => open,
flag => open
);
rd_block_en <= '1' when zcpsm_we = '1' and zcpsm_addr = PORT_RD_BLOCK else '0';
process(zcpsm_clk, reset)
begin
if reset = '1' then
fifo_raddr_reg <= (others => '0');
elsif rising_edge(zcpsm_clk) then
if zcpsm_we = '1' and zcpsm_addr = PORT_IO_ADDR then
fifo_raddr_reg <= zcpsm_out_port(BLOCK_AWIDTH - 1 downto 0);
elsif zcpsm_re = '1' and zcpsm_addr = PORT_IO_DATA then
fifo_raddr_reg <= fifo_raddr_reg + 1;
end if;
end if;
end process;
fifo_raddr <= zcpsm_out_port(BLOCK_AWIDTH - 1 downto 0) when zcpsm_we = '1' and zcpsm_addr = PORT_IO_ADDR else
fifo_raddr_reg + 1 when zcpsm_re = '1' and zcpsm_addr = PORT_IO_DATA else
fifo_raddr_reg;
zcpsm_in_port <= fifo_rdata when zcpsm_ce = '1' and zcpsm_addr = PORT_IO_DATA else (others => 'Z');
end behave;
| gpl-2.0 | 83b4417076d9b9d27d3e2225a1c69eeb | 0.54277 | 2.83815 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_adder.vhd | 3 | 9,048 | -------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_v20_v1_10_d.pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
result_out <= iresult_out;
end architecture implementation;
| bsd-3-clause | b71b5f4d13415b48032ebc8bb36c5b24 | 0.410256 | 5.106095 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_wbmon.vhd | 1 | 22,779 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : z126_01_wbmon.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wbmon.vhd,v $
-- Revision 1.1 2014/03/03 17:49:59 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x06
-- unsupported BTE:
-- only an address increment of 4 is supported by the current wishbone bus and
-- its modules. Other BTEs are unsupported at the moment
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY z126_01_wbmon IS
GENERIC(
wbname : string := "z126_01_wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
bte : IN std_logic_vector(1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp (
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle (
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
);
END z126_01_wbmon;
ARCHITECTURE z126_01_wbmon_arch OF z126_01_wbmon IS
FUNCTION to_string (
constant val : in std_logic_vector
) RETURN string IS
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
BEGIN
FOR i IN reglen DOWNTO 1 LOOP
CASE slv(i) IS
WHEN 'U' => result_str(i) := 'U';
WHEN 'X' => result_str(i) := 'X';
WHEN '0' => result_str(i) := '0';
WHEN '1' => result_str(i) := '1';
WHEN 'Z' => result_str(i) := 'Z';
WHEN 'W' => result_str(i) := 'W';
WHEN 'L' => result_str(i) := 'L';
WHEN 'H' => result_str(i) := 'H';
WHEN '-' => result_str(i) := '-';
WHEN OTHERS => -- an unknown std_logic value was passed
ASSERT FALSE
REPORT "to_string - unknown std_logic_vector value"
SEVERITY ERROR;
END CASE;
END LOOP;
return result_str;
END;
FUNCTION to_hstring
(
CONSTANT bitaccess : IN natural;
CONSTANT val : in std_logic_vector--(7 DOWNTO 0)
) RETURN string is
VARIABLE reglen : natural := 1;
VARIABLE result_str : string(1 to (bitaccess / 4));
VARIABLE slv : std_logic_vector(bitaccess-1 DOWNTO 0);-- := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
slv := val;
IF bitaccess = 8 THEN
reglen := 1;
ELSIF bitaccess = 16 THEN
reglen := 3;
ELSIF bitaccess = 32 THEN
reglen := 7;
ELSIF bitaccess = 64 THEN
reglen := 15;
ELSE
END IF;
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(reglen + 1 - i) := '0';
WHEN "0001" => result_str(reglen + 1 - i) := '1';
WHEN "0010" => result_str(reglen + 1 - i) := '2';
WHEN "0011" => result_str(reglen + 1 - i) := '3';
WHEN "0100" => result_str(reglen + 1 - i) := '4';
WHEN "0101" => result_str(reglen + 1 - i) := '5';
WHEN "0110" => result_str(reglen + 1 - i) := '6';
WHEN "0111" => result_str(reglen + 1 - i) := '7';
WHEN "1000" => result_str(reglen + 1 - i) := '8';
WHEN "1001" => result_str(reglen + 1 - i) := '9';
WHEN "1010" => result_str(reglen + 1 - i) := 'A';
WHEN "1011" => result_str(reglen + 1 - i) := 'B';
WHEN "1100" => result_str(reglen + 1 - i) := 'C';
WHEN "1101" => result_str(reglen + 1 - i) := 'D';
WHEN "1110" => result_str(reglen + 1 - i) := 'E';
WHEN "1111" => result_str(reglen + 1 - i) := 'F';
WHEN others => result_str(reglen + 1 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION data_out (sel : std_logic_vector(3 downto 0); dat : std_logic_vector(31 downto 0)) RETURN string IS
variable byte0 : string(1 to 2);
variable byte1 : string(1 to 2);
variable byte2 : string(1 to 2);
variable byte3 : string(1 to 2);
BEGIN
if sel(0) = '1' then
byte0 := to_hstring(8,dat( 7 downto 0));
else
byte0 := "XX";
end if;
if sel(1) = '1' then
byte1 := to_hstring(8,dat(15 downto 8));
else
byte1 := "XX";
end if;
if sel(2) = '1' then
byte2 := to_hstring(8,dat(23 downto 16));
else
byte2 := "XX";
end if;
if sel(3) = '1' then
byte3 := to_hstring(8,dat(31 downto 24));
else
byte3 := "XX";
end if;
return (byte3 & byte2 & "_" & byte1 & byte0);
end data_out;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 4);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 8);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(31 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (3 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(31 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 4;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
outp(e,c,"Unsupported BTE ("&to_string(bte)&" sb 00)", x"06", enable , ERROR, bte = "00");
IF (cti /= "010" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,"Master Data Out changed during burst cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_b)&")", x"02", enable , ERROR, sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 4;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, bte, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(bte) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"bte is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb = '1' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END z126_01_wbmon_arch; | gpl-3.0 | 121c2fba85eb7b06fa258842b1422fdd | 0.477018 | 3.665755 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd | 2 | 9,190 | -------------------------------------------------------------------------------
-- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate_f.vhd
--
-- Description: OR gates. The width of each OR gate (C_OR_WIDTH)
-- and the number of or gates (C_BUS_WIDTH) are
-- parameterizable.
--
-- Y(j) <= A(j) OR A(C_BUS_WIDTH+j)
-- OR A(2*C_BUS_WIDTH+j)
-- ...
-- OR A((C_OR_WIDTH-1)*C_BUS_WIDTH+j),
--
-- for 0 <= j < C_BUS_WIDTH
--
-- If C_FAMILY is set (or left defaulted) to "nofamily"
-- then the implementation will be by synthesis inference.
-- Otherwise, a structural implementation optimized to
-- C_FAMILY may be generated, depending on whether
-- C_FAMILY supports the needed primtives.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate_f.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2006-12-11
-- ^^^^^^
-- First Version, derived from or_gate by BLT
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v3_00_a;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate_f is
generic (
C_OR_WIDTH : natural := 17;
C_BUS_WIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate_f;
architecture imp of or_gate_f is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity proc_common_v3_00_a.or_muxcy_f
generic map (
C_NUM_BITS => C_OR_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end architecture imp;
| bsd-3-clause | 629ca4e3d97f32472ac6baea4d32f452 | 0.406311 | 5.131212 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/config/eth_config.vhd | 1 | 4,271 | library ieee;
use ieee.std_logic_1164.all;
package eth_config is
constant ETHRX_HEAD_AWIDTH : natural := 6;
constant ETHRX_BUFF_AWIDTH : natural := 12;
constant ETHRX_FIFO_AWIDTH : natural := 2;
constant ETHTX_HEAD_AWIDTH : natural := 6;
constant ETHTX_BUFF_AWIDTH : natural := 5;
constant ETHTX_FIFO_AWIDTH : natural := 0;
constant TASKFIFO_DWIDTH : natural := 8;
constant TX_TASKFIFO_BLOCK_DEPTH : natural := 32;
constant TX_TASKFIFO_BLOCK_AWIDTH : natural := 5;
constant RX_TASKFIFO_BLOCK_DEPTH : natural := 32;
constant RX_TASKFIFO_BLOCK_AWIDTH : natural := 5;
constant TX_TASKFIFO_DEPTH : natural := 64;--16;
constant TX_TASKFIFO_AWIDTH : natural := 6;--4;
constant RX_TASKFIFO_DEPTH : natural := 64;--32;
constant RX_TASKFIFO_AWIDTH : natural := 6;--5;
constant TX_TASKFIFO_RAM_TYPE : string := "BLK_RAM"; -- "DIS_RAM" or "BLK_RAM"
constant RX_TASKFIFO_RAM_TYPE : string := "BLK_RAM"; -- "DIS_RAM" or "BLK_RAM"
-- constant RAM_WR_CYCLE : natural := 8;
-- constant RAM_RD_CYCLE : natural := 8;
-- constant RAM_RD_DELAY : natural := 9;
constant ETHRX_ZCPSM_ID : std_logic_vector(3 downto 0) := X"0";
constant ETHTX_ZCPSM_ID : std_logic_vector(3 downto 0) := X"1";
constant PORTS_ETH_TX : std_logic_vector(3 downto 0) := X"0";
constant PORTS_ETH_TX_TASK : std_logic_vector(3 downto 0) := X"1";
-- constant PORTS_ETH_TX_TIMING : std_logic_vector(3 downto 0) := X"2";
constant PORTS_ETH_RX : std_logic_vector(3 downto 0) := X"1";
constant PORTS_ETH_RXDMA : std_logic_vector(3 downto 0) := X"2";
constant PORTS_ETH_RX_TASK : std_logic_vector(3 downto 0) := X"3";
-- constant PORTS_ETH_RX_TIMING : std_logic_vector(3 downto 0) := X"4";
constant PORTS_DB_TX : std_logic_vector(3 downto 0) := X"0";
constant PORTS_DB_RX : std_logic_vector(3 downto 0) := X"1";
constant PORTS_DB_DEBUG : std_logic_vector(3 downto 0) := X"2";
constant PORTS_DB_TX_TASK : std_logic_vector(3 downto 0) := X"4";
constant PORTS_DB_RX_TASK : std_logic_vector(3 downto 0) := X"5";
constant PORTS_DEBUG_PROG : std_logic_vector(3 downto 0) := X"0";
constant PORT_ETH_TX_HIGHPRI_CE : std_logic_vector(3 downto 0) := X"E";
constant PORT_ETH_TX_HIGHPRI_REQ : std_logic_vector(3 downto 0) := X"0";
constant PORT_ETH_TX_HIGHPRI_ADDR_L : std_logic_vector(3 downto 0) := X"1";
constant PORT_ETH_TX_HIGHPRI_ADDR_H : std_logic_vector(3 downto 0) := X"2";
constant PORT_ETH_TX_HIGHPRI_DATA_L : std_logic_vector(3 downto 0) := X"3";
constant PORT_ETH_TX_HIGHPRI_DATA_H : std_logic_vector(3 downto 0) := X"4";
constant PORT_ETH_TX_HIGHPRI_DESMAC_0 : std_logic_vector(3 downto 0) := X"5";
constant PORT_ETH_TX_HIGHPRI_DESMAC_1 : std_logic_vector(3 downto 0) := X"6";
constant PORT_ETH_TX_HIGHPRI_DESMAC_2 : std_logic_vector(3 downto 0) := X"7";
constant PORT_ETH_TX_HIGHPRI_DESMAC_3 : std_logic_vector(3 downto 0) := X"8";
constant PORT_ETH_TX_HIGHPRI_DESMAC_4 : std_logic_vector(3 downto 0) := X"9";
constant PORT_ETH_TX_HIGHPRI_DESMAC_5 : std_logic_vector(3 downto 0) := X"A";
constant PORT_ETH_LOCAL_ID_0_REQ : std_logic_vector(7 downto 0) := X"F8";
constant PORT_ETH_LOCAL_ID_0_A : std_logic_vector(7 downto 0) := X"F9";
constant PORT_ETH_LOCAL_ID_0_B : std_logic_vector(7 downto 0) := X"FA";
constant PORT_ETH_LOCAL_ID_1 : std_logic_vector(7 downto 0) := X"FB";
constant PORT_ETH_LOCAL_ID_2 : std_logic_vector(7 downto 0) := X"FC";
constant PORT_ETH_LOCAL_ID_3 : std_logic_vector(7 downto 0) := X"FD";
constant PORT_ETH_LOCAL_ID_4 : std_logic_vector(7 downto 0) := X"FE";
constant PORT_ETH_LOCAL_ID_5 : std_logic_vector(7 downto 0) := X"FF";
constant PORT_DB_LOCAL_ID_0_A : std_logic_vector(7 downto 0) := X"F9";
constant PORT_DB_LOCAL_ID_0_B : std_logic_vector(7 downto 0) := X"FA";
constant PORT_DB_LOCAL_ID_1 : std_logic_vector(7 downto 0) := X"FB";
constant PORT_DB_LOCAL_ID_2 : std_logic_vector(7 downto 0) := X"FC";
constant PORT_DB_LOCAL_ID_3 : std_logic_vector(7 downto 0) := X"FD";
constant PORT_DB_LOCAL_ID_4 : std_logic_vector(7 downto 0) := X"FE";
constant PORT_DB_LOCAL_ID_5 : std_logic_vector(7 downto 0) := X"FF";
end package;
| gpl-2.0 | e83a57d1d3979621152a08e1552cd1f5 | 0.64856 | 2.394058 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_bit.vhd | 3 | 6,738 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:26 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| bsd-3-clause | 4d0ae9501d69e95c3c75d4141828a2b9 | 0.387504 | 4.504011 | false | false | false | false |
a4a881d4/zcpsm | src/example/Q7Led/vhd/Q7Led.vhd | 1 | 9,879 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
--Date : Sun Mar 01 22:52:38 2015
--Host : dodo-PC running 64-bit Service Pack 1 (build 7601)
--Command : generate_target Q7Led.bd
--Design : Q7Led
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Q7Led is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
aBus_in_port : in STD_LOGIC_VECTOR ( 7 downto 0 );
aBus_out_port : out STD_LOGIC_VECTOR ( 7 downto 0 );
aBus_port_ce : out STD_LOGIC_VECTOR ( 15 downto 0 );
aBus_port_id : out STD_LOGIC_VECTOR ( 3 downto 0 );
aBus_read_strobe : out STD_LOGIC;
aBus_write_strobe : out STD_LOGIC;
clk : in STD_LOGIC
);
end Q7Led;
architecture STRUCTURE of Q7Led is
component ARM_wrapper is
port (
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end component ARM_wrapper;
component zcpsmISP is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
port_ce : out STD_LOGIC_VECTOR ( 15 downto 0 );
port_id : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_strobe : out STD_LOGIC;
out_port : out STD_LOGIC_VECTOR ( 7 downto 0 );
read_strobe : out STD_LOGIC;
in_port : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_we : in STD_LOGIC;
prog_clk : in STD_LOGIC;
prog_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
end component zcpsmISP;
component zProg2Bram is
port (
BRAM_PORTA_addr : in STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : in STD_LOGIC;
BRAM_PORTA_din : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : in STD_LOGIC;
BRAM_PORTA_rst : in STD_LOGIC;
BRAM_PORTA_we : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_we : out STD_LOGIC;
prog_clk : out STD_LOGIC;
prog_addr : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_din : out STD_LOGIC_VECTOR ( 17 downto 0 )
);
end component zProg2Bram;
signal ARM_wrapper_0_BRAM_PORTA_addr : STD_LOGIC_VECTOR ( 12 downto 0 );
signal ARM_wrapper_0_BRAM_PORTA_clk : STD_LOGIC;
signal ARM_wrapper_0_BRAM_PORTA_din : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ARM_wrapper_0_BRAM_PORTA_en : STD_LOGIC;
signal ARM_wrapper_0_BRAM_PORTA_rst : STD_LOGIC;
signal ARM_wrapper_0_BRAM_PORTA_we : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ARM_wrapper_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal ARM_wrapper_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ARM_wrapper_0_DDR_CAS_N : STD_LOGIC;
signal ARM_wrapper_0_DDR_CKE : STD_LOGIC;
signal ARM_wrapper_0_DDR_CK_N : STD_LOGIC;
signal ARM_wrapper_0_DDR_CK_P : STD_LOGIC;
signal ARM_wrapper_0_DDR_CS_N : STD_LOGIC;
signal ARM_wrapper_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ARM_wrapper_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ARM_wrapper_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ARM_wrapper_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ARM_wrapper_0_DDR_ODT : STD_LOGIC;
signal ARM_wrapper_0_DDR_RAS_N : STD_LOGIC;
signal ARM_wrapper_0_DDR_RESET_N : STD_LOGIC;
signal ARM_wrapper_0_DDR_WE_N : STD_LOGIC;
signal FIXED_IO_1_DDR_VRN : STD_LOGIC;
signal FIXED_IO_1_DDR_VRP : STD_LOGIC;
signal FIXED_IO_1_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal FIXED_IO_1_PS_CLK : STD_LOGIC;
signal FIXED_IO_1_PS_PORB : STD_LOGIC;
signal FIXED_IO_1_PS_SRSTB : STD_LOGIC;
signal clk_1 : STD_LOGIC;
signal zProg2Bram_0_BRAM_PORTA_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal zProg2Bram_0_prog_addr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zProg2Bram_0_prog_clk : STD_LOGIC;
signal zProg2Bram_0_prog_din : STD_LOGIC_VECTOR ( 17 downto 0 );
signal zProg2Bram_0_prog_we : STD_LOGIC;
signal zcpsmISP_0_aBus_in_port : STD_LOGIC_VECTOR ( 7 downto 0 );
signal zcpsmISP_0_aBus_out_port : STD_LOGIC_VECTOR ( 7 downto 0 );
signal zcpsmISP_0_aBus_port_ce : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zcpsmISP_0_aBus_port_id : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zcpsmISP_0_aBus_read_strobe : STD_LOGIC;
signal zcpsmISP_0_aBus_write_strobe : STD_LOGIC;
begin
aBus_out_port(7 downto 0) <= zcpsmISP_0_aBus_out_port(7 downto 0);
aBus_port_ce(15 downto 0) <= zcpsmISP_0_aBus_port_ce(15 downto 0);
aBus_port_id(3 downto 0) <= zcpsmISP_0_aBus_port_id(3 downto 0);
aBus_read_strobe <= zcpsmISP_0_aBus_read_strobe;
aBus_write_strobe <= zcpsmISP_0_aBus_write_strobe;
clk_1 <= clk;
zcpsmISP_0_aBus_in_port(7 downto 0) <= aBus_in_port(7 downto 0);
ARM_wrapper_0: component ARM_wrapper
port map (
BRAM_PORTA_addr(12 downto 0) => ARM_wrapper_0_BRAM_PORTA_addr(12 downto 0),
BRAM_PORTA_clk => ARM_wrapper_0_BRAM_PORTA_clk,
BRAM_PORTA_din(31 downto 0) => ARM_wrapper_0_BRAM_PORTA_din(31 downto 0),
BRAM_PORTA_dout(31 downto 0) => zProg2Bram_0_BRAM_PORTA_dout(31 downto 0),
BRAM_PORTA_en => ARM_wrapper_0_BRAM_PORTA_en,
BRAM_PORTA_rst => ARM_wrapper_0_BRAM_PORTA_rst,
BRAM_PORTA_we(3 downto 0) => ARM_wrapper_0_BRAM_PORTA_we(3 downto 0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
zProg2Bram_0: component zProg2Bram
port map (
BRAM_PORTA_addr(12 downto 0) => ARM_wrapper_0_BRAM_PORTA_addr(12 downto 0),
BRAM_PORTA_clk => ARM_wrapper_0_BRAM_PORTA_clk,
BRAM_PORTA_din(31 downto 0) => ARM_wrapper_0_BRAM_PORTA_din(31 downto 0),
BRAM_PORTA_dout(31 downto 0) => zProg2Bram_0_BRAM_PORTA_dout(31 downto 0),
BRAM_PORTA_en => ARM_wrapper_0_BRAM_PORTA_en,
BRAM_PORTA_rst => ARM_wrapper_0_BRAM_PORTA_rst,
BRAM_PORTA_we(3 downto 0) => ARM_wrapper_0_BRAM_PORTA_we(3 downto 0),
prog_addr(9 downto 0) => zProg2Bram_0_prog_addr(9 downto 0),
prog_clk => zProg2Bram_0_prog_clk,
prog_din(17 downto 0) => zProg2Bram_0_prog_din(17 downto 0),
prog_we => zProg2Bram_0_prog_we
);
zcpsmISP_0: component zcpsmISP
port map (
clk => clk_1,
in_port(7 downto 0) => zcpsmISP_0_aBus_in_port(7 downto 0),
out_port(7 downto 0) => zcpsmISP_0_aBus_out_port(7 downto 0),
port_ce(15 downto 0) => zcpsmISP_0_aBus_port_ce(15 downto 0),
port_id(3 downto 0) => zcpsmISP_0_aBus_port_id(3 downto 0),
prog_addr(9 downto 0) => zProg2Bram_0_prog_addr(9 downto 0),
prog_clk => zProg2Bram_0_prog_clk,
prog_din(17 downto 0) => zProg2Bram_0_prog_din(17 downto 0),
prog_we => zProg2Bram_0_prog_we,
read_strobe => zcpsmISP_0_aBus_read_strobe,
reset => ARM_wrapper_0_BRAM_PORTA_rst,
write_strobe => zcpsmISP_0_aBus_write_strobe
);
end STRUCTURE;
| gpl-2.0 | f05df26e6007055c75bf079146d710c0 | 0.619698 | 3.031298 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/clk_trans_wb2wb.vhd | 1 | 11,730 | ---------------------------------------------------------------
-- Title : Adaption from clk a to clk b
-- Project : A15
---------------------------------------------------------------
-- File : clk_trans_wb2wb.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/03
---------------------------------------------------------------
-- Simulator : Modelsim 5.6
-- Synthesis : Leonardo/Quartus
---------------------------------------------------------------
-- Description :
--
-- This Module transforms the request and acknoledge signals to
-- connect to a a MHz internal bus. Also the data must be
-- transformed in order to fit into the a MHz clk domain.
-- The module supports posted and delayed writes:
-- POSTED_WR=true => acknowledge write access immediately
-- POSTED_WR=false => acknowledge write if access has finished on side b
---------------------------------------------------------------
-- Hierarchy:
--
-- sys_unit
-- clk_trans_wb2wb
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: clk_trans_wb2wb.vhd,v $
-- Revision 1.7 2015/09/08 17:23:00 AGeissler
-- R1: Missing reset for second clock domain
-- M1: Replaced rstn with rst_a and rst_b
--
-- Revision 1.6 2015/06/15 16:40:10 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from clock trans
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.5 2012/09/07 09:59:14 MMiehling
-- added delayed write support by generic switch
--
-- Revision 1.4 2011/05/17 11:16:00 FLenhardt
-- R: Under certain conditions (e.g. when not all cycles of a Wishbone master
-- were connected to CLK_TRANS_WB2WB) a Wishbone access could happen to
-- stuck, because the clock transition was controlled only by the strobe
-- M: A Wishbone access is valid only when also at least one cycle is active
--
-- Revision 1.3 2010/03/12 13:00:27 mmiehling
-- added generic NBR_OF_CYC and NBR_OF_TGA in order to configure the bridge
--
-- Revision 1.2 2007/07/05 13:22:53 FLenhardt
-- Removed an unused signal (due to synthesis warnings)
--
-- Revision 1.1 2005/05/06 12:06:50 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/11/02 11:29:24 mmiehling
-- replaced full => full_a and full_b
--
-- Revision 1.1 2004/07/27 17:15:20 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY clk_trans_wb2wb IS
GENERIC (
POSTED_WR : boolean := TRUE;
NBR_OF_CYC : integer range 1 TO 100 := 1;
NBR_OF_TGA : integer range 1 TO 100 := 6
);
PORT (
-- a MHz domain
rst_a : IN std_logic;
clk_a : IN std_logic;
cyc_a : IN std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_a : IN std_logic; -- request signal from a MHz side
ack_a : OUT std_logic; -- adopted acknoledge signal to b MHz
err_a : OUT std_logic;
we_a : IN std_logic; -- '1' = write, '0' = read
tga_a : IN std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_a : IN std_logic_vector(2 DOWNTO 0); -- transfer type
adr_a : IN std_logic_vector(31 DOWNTO 0); -- adr from a MHz side
sel_a : IN std_logic_vector(3 DOWNTO 0); -- byte enables from a MHz side
dat_i_a : IN std_logic_vector(31 DOWNTO 0); -- data from a MHz side
dat_o_a : OUT std_logic_vector(31 DOWNTO 0); -- data from b MHz side to a MHz side
-- b MHz domain
rst_b : IN std_logic;
clk_b : IN std_logic;
cyc_b : OUT std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_b : OUT std_logic; -- request signal adopted to b MHz
ack_b : IN std_logic; -- acknoledge signal from internal bus
err_b : IN std_logic;
we_b : OUT std_logic; -- '1' = write, '0' = read
tga_b : OUT std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_b : OUT std_logic_vector(2 DOWNTO 0); -- transfer type
adr_b : OUT std_logic_vector(31 DOWNTO 0); -- adr from b MHz side
sel_b : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for b MHz side
dat_i_b : IN std_logic_vector(31 DOWNTO 0); -- data from b MHz side
dat_o_b : OUT std_logic_vector(31 DOWNTO 0) -- data from a MHz side to b MHz side
);
END clk_trans_wb2wb;
ARCHITECTURE clk_trans_wb2wb_arch OF clk_trans_wb2wb IS
COMPONENT fifo_d1
GENERIC (
width : IN integer );
PORT (
rst_a : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
rst_b : IN std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END COMPONENT;
TYPE ct_states IS (idle, waitstate, acknoledge);
SIGNAL ct_state : ct_states;
CONSTANT WR_FIFO_WIDTH : integer:= 69 + NBR_OF_CYC + NBR_OF_TGA; -- cyc + dat + adr + sel + we = 32+32+4+1 = 69
CONSTANT RD_FIFO_WIDTH : integer:= 32; -- dat = 32
SIGNAL ff1_rd : std_logic;
SIGNAL ff1_wr : std_logic;
SIGNAL ff1_full_a : std_logic;
SIGNAL ff1_full_b : std_logic;
SIGNAL ff2_rd : std_logic;
SIGNAL ff2_wr : std_logic;
SIGNAL ff2_full_b : std_logic;
SIGNAL stb_b_int : std_logic;
SIGNAL ff1_dat_a : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ff1_dat_b : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ack_a_int : std_logic;
BEGIN
ack_a <= ack_a_int;
stb_b <= stb_b_int;
err_a <= '0'; -- errors will not reported: error-access will never end!
ff1_dat_a <= tga_a & cyc_a & dat_i_a & adr_a & sel_a & we_a;
tga_b <= ff1_dat_b(68+NBR_OF_CYC+NBR_OF_TGA DOWNTO 69+NBR_OF_CYC);
cyc_b <= ff1_dat_b(68+NBR_OF_CYC DOWNTO 69) WHEN stb_b_int = '1' ELSE (OTHERS => '0');
dat_o_b <= ff1_dat_b(68 DOWNTO 37);
adr_b <= ff1_dat_b(36 DOWNTO 5);
sel_b <= ff1_dat_b(4 DOWNTO 1);
we_b <= ff1_dat_b(0);
cti_b <= (OTHERS => '0');
ff1 : fifo_d1
GENERIC MAP (
width => WR_FIFO_WIDTH
)
PORT MAP (
rst_a => rst_a,
clk_a => clk_a,
wr_a => ff1_wr,
data_a => ff1_dat_a,
full_a => ff1_full_a,
rst_b => rst_b,
clk_b => clk_b,
rd_b => ff1_rd,
data_b => ff1_dat_b,
full_b => ff1_full_b
);
ff2 : fifo_d1
GENERIC MAP (
width => RD_FIFO_WIDTH
)
PORT MAP (
rst_a => rst_b,
clk_a => clk_b,
wr_a => ff2_wr,
data_a => dat_i_b,
rst_b => rst_a,
clk_b => clk_a,
rd_b => ff2_rd,
data_b => dat_o_a,
full_b => ff2_full_b
);
ff1_wr <= '1' WHEN (ct_state = idle AND stb_a = '1' AND unsigned(cyc_a) /= 0 AND ff1_full_a = '0') ELSE '0';
ff2_rd <= '1' WHEN ff2_full_b = '1' ELSE '0'; -- read data from ff when available
proca : PROCESS (clk_a, rst_a)
BEGIN
IF rst_a = '1' THEN
ack_a_int <= '0';
ct_state <= idle;
ELSIF clk_a'EVENT AND clk_a = '1' THEN
CASE ct_state IS
WHEN idle =>
IF (ff1_wr = '1' AND we_a = '1') AND POSTED_WR THEN -- posted write
ct_state <= acknoledge;
ack_a_int <= '1';
ELSIF (ff1_wr = '1' AND we_a = '1') AND NOT POSTED_WR THEN -- delayed write
ct_state <= waitstate;
ack_a_int <= '0';
ELSIF (ff1_wr = '1' AND we_a = '0') THEN -- read
ct_state <= waitstate;
ack_a_int <= '0';
ELSE
ct_state <= idle;
ack_a_int <= '0';
END IF;
WHEN waitstate =>
IF ff2_full_b = '1' THEN
ct_state <= acknoledge;
ack_a_int <= '1';
ELSE
ct_state <= waitstate;
ack_a_int <= '0';
END IF;
WHEN acknoledge =>
ack_a_int <= '0';
ct_state <= idle;
WHEN OTHERS =>
ct_state <= idle;
ack_a_int <= '0';
END CASE;
END IF;
END PROCESS proca;
------------------------------------------------------------------
-- side b: stb_b is not dependent on we_a
------------------------------------------------------------------
-- for read and write equal:
ff1_rd <= '1' WHEN ((ack_b = '0' AND err_b = '0') AND ff1_full_b = '1' AND stb_b_int = '0') OR -- first data phase
((ack_b = '1' OR err_b = '1') AND ff1_full_b = '1' AND stb_b_int = '1') -- within a burst (not the last)
ELSE '0';
ff2_wr <= '1' WHEN stb_b_int = '1' AND (ack_b = '1' OR err_b = '1') AND (NOT POSTED_WR OR (ff1_dat_b(0) = '0' AND POSTED_WR)) ELSE '0'; -- store read-data
-- ack_b stb_b ff1_full stb_b(+1)
-- x 0 1 1
-- x 1 1 1
-- x 0 0 0
-- 1 1 0 0
-- 0 1 0 1
procb : PROCESS (clk_b, rst_b)
BEGIN
IF rst_b = '1' THEN
stb_b_int <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
IF ff1_full_b = '1' THEN
IF stb_b_int = '0' THEN
stb_b_int <= '1'; -- start next data phase
ELSE
-- end of current data phase, start of next
stb_b_int <= '1'; -- or no end of current data phase
END IF;
ELSE
IF stb_b_int = '0' THEN -- no current access and no next access
stb_b_int <= '0';
ELSE
IF ack_b = '1' OR err_b = '1' THEN -- end of current data phase, no next
stb_b_int <= '0';
ELSE
stb_b_int <= '1'; -- no end of current data phase
END IF;
END IF;
END IF;
END IF;
END PROCESS procb;
END clk_trans_wb2wb_arch;
| gpl-3.0 | cc5ac8362291cc2dea7923e54a214fd3 | 0.483546 | 3.52782 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_destroy_2.vhd | 2 | 15,952 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- condattr_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * cond = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_condattr_init( condattr );
when STATE_2 =>
-- Push condattr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_condattr_destroy( condattr );
when STATE_4 =>
-- Push the argument to hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_condattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_condattr_init( condattr );
when STATE_6 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
when STATE_8 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 44ef06b5cd4165bce5148813bc4eecf6 | 0.544383 | 3.824503 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/axi_sync_manager.vhd | 2 | 38,758 | ------------------------------------------------------------------------------
-- axi_sync_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_sync_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Jun 26 14:24:54 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_lite_v1_00_a;
use axi_master_lite_v1_00_a.axi_master_lite;
library axi_sync_manager_v1_00_a;
use axi_sync_manager_v1_00_a.user_logic;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_LITE_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_LITE_DATA_WIDTH -- Master-Intf data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_lite_aclk -- AXI4LITE master: Clock
-- m_axi_lite_aresetn -- AXI4LITE master: Reset
-- md_error -- AXI4LITE master: Error
-- m_axi_lite_arready -- AXI4LITE master: Read address ready
-- m_axi_lite_arvalid -- AXI4LITE master: read address valid
-- m_axi_lite_araddr -- AXI4LITE master: read address protection
-- m_axi_lite_arprot -- AXI4LITE master: Read address protection
-- m_axi_lite_rready -- AXI4LITE master: Read data ready
-- m_axi_lite_rvalid -- AXI4LITE master: Read data valid
-- m_axi_lite_rdata -- AXI4LITE master: Read data
-- m_axi_lite_rresp -- AXI4LITE master: read data response
-- m_axi_lite_awready -- AXI4LITE master: write address ready
-- m_axi_lite_awvalid -- AXI4LITE master: write address valid
-- m_axi_lite_awaddr -- AXI4LITE master: write address valid
-- m_axi_lite_awprot -- AXI4LITE master: write address protection
-- m_axi_lite_wready -- AXI4LITE master: write data ready
-- m_axi_lite_wvalid -- AXI4LITE master: write data valid
-- m_axi_lite_wdata -- AXI4LITE master: write data
-- m_axi_lite_wstrb -- AXI4LITE master: write data strobe
-- m_axi_lite_bready -- AXI4LITE master: read response ready
-- m_axi_lite_bvalid -- AXI4LITE master: read response valid
-- m_axi_lite_bresp -- AXI4LITE master: read response
------------------------------------------------------------------------------
entity axi_sync_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"00FFFFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_M_AXI_LITE_ADDR_WIDTH : integer := 32;
C_M_AXI_LITE_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_lite_aclk : in std_logic;
m_axi_lite_aresetn : in std_logic;
md_error : out std_logic;
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_araddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_arprot : out std_logic_vector(2 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_rdata : in std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_rresp : in std_logic_vector(1 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_awprot : out std_logic_vector(2 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
m_axi_lite_wdata : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_wstrb : out std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
m_axi_lite_bready : out std_logic;
m_axi_lite_bvalid : in std_logic;
m_axi_lite_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_lite_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_lite_aresetn : signal is "10000";
attribute SIGIS of m_axi_lite_aclk : signal is "Clk";
attribute SIGIS of m_axi_lite_aresetn : signal is "Rst";
end entity axi_sync_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_sync_manager is
-------------------------------------------------------------------
-- BEGIN CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - 2 to
C_S_AXI_ADDR_WIDTH - 3) := (others => '1');
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_S_AXI_ADDR_WIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_S_AXI_ADDR_WIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := C_S_AXI_DATA_WIDTH ;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-------------------------------------------------------------------
-- END CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
-- constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
-- constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
--
-- constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- (
-- ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
-- ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
-- ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
-- ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
-- );
-- ------------------------------------------
-- -- Array of desired number of chip enables for each address range
-- ------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG+USER_MST_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
--
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
-- 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
-- 1 => pad_power2(USER_MST_NUM_REG) -- number of ce for user logic master space
-- );
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_M_AXI_LITE_ADDR_WIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_M_AXI_LITE_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_MST_CS_INDEX : integer := 1;
constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1);
signal ipif_ip2bus_mst_be : std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate axi_master_lite
------------------------------------------
AXI_MASTER_LITE_I : entity axi_master_lite_v1_00_a.axi_master_lite
generic map
(
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_lite_aclk => m_axi_lite_aclk,
m_axi_lite_aresetn => m_axi_lite_aresetn,
md_error => md_error,
m_axi_lite_arready => m_axi_lite_arready,
m_axi_lite_arvalid => m_axi_lite_arvalid,
m_axi_lite_araddr => m_axi_lite_araddr,
m_axi_lite_arprot => m_axi_lite_arprot,
m_axi_lite_rready => m_axi_lite_rready,
m_axi_lite_rvalid => m_axi_lite_rvalid,
m_axi_lite_rdata => m_axi_lite_rdata,
m_axi_lite_rresp => m_axi_lite_rresp,
m_axi_lite_awready => m_axi_lite_awready,
m_axi_lite_awvalid => m_axi_lite_awvalid,
m_axi_lite_awaddr => m_axi_lite_awaddr,
m_axi_lite_awprot => m_axi_lite_awprot,
m_axi_lite_wready => m_axi_lite_wready,
m_axi_lite_wvalid => m_axi_lite_wvalid,
m_axi_lite_wdata => m_axi_lite_wdata,
m_axi_lite_wstrb => m_axi_lite_wstrb,
m_axi_lite_bready => m_axi_lite_bready,
m_axi_lite_bvalid => m_axi_lite_bvalid,
m_axi_lite_bresp => m_axi_lite_bresp,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => iBus2IP_Addr,
-- Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
-- Bus2IP_RNW => iBus2IP_RNW,
-- Bus2IP_RdCE => uBus2IP_RdCE,
-- Bus2IP_WrCE => uBus2IP_WrCE,
-- Bus2IP_RdReq => iBus2IP_RdReq,
-- Bus2IP_WrReq => iBus2IP_WrReq,
-- Bus2IP_MstError => iBus2IP_MstError,
-- Bus2IP_MstLastAck => iBus2IP_MstLastAck,
-- Bus2IP_MstRdAck => iBus2IP_MstRdAck,
-- Bus2IP_MstWrAck => iBus2IP_MstWrAck,
-- Bus2IP_MstRetry => iBus2IP_MstRetry,
-- Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
-- IP2Bus_Addr => iIP2Bus_Addr,
-- IP2Bus_MstBE => uIP2Bus_MstBE,
-- IP2Bus_MstBurst => iIP2Bus_MstBurst,
-- IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
-- IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
-- IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
-- IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_WrCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_RdCE(USER_NUM_REG-1 downto USER_NUM_REG-USER_MST_NUM_REG) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
user_Bus2IP_WrCE(USER_NUM_REG-1 downto USER_NUM_REG- USER_MST_NUM_REG) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
end IMP;
| bsd-3-clause | fb52dde842b9796d6ecab02223caedb5 | 0.49969 | 3.774272 | false | false | false | false |
xdsopl/vhdl | quadrature_decoder.vhd | 1 | 1,106 | -- quadrature_decoder - quadrature decoder with synchronizing clock input
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
-- prior debouncing of rotary input is unnecessary
entity quadrature_decoder is
port (
clock : in std_logic;
rotary : in std_logic_vector (1 downto 0);
direction : out std_logic;
pulse : out std_logic
);
end quadrature_decoder;
architecture rtl of quadrature_decoder is
signal a, b, c : std_logic;
signal pul, dir : std_logic;
begin
a <= rotary(0);
b <= rotary(1);
c <= a xor b;
dir <= b when rising_edge(clock) and c = '1' else dir;
pul <= a when rising_edge(clock) and c = '0' else pul;
pulse <= pul;
direction <= dir;
end rtl;
| cc0-1.0 | 355803d91c02c3b31584c21f7f3223e1 | 0.726944 | 3.544872 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_destroy_1.vhd | 2 | 16,175 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_destroy_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_cond_destroy( cond );
when STATE_4 =>
-- Push the argument to hthread_cond_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_cond_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = hthread_cond_init( cond, NULL );
when STATE_6 =>
-- Push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
next_state <= WAIT_STATE;
when STATE_9 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 54853fe8714c58bb1def7453512101bc | 0.543926 | 3.794276 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/condvar_tb.vhd | 9 | 5,092 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:46:38 06/16/2009
-- Design Name:
-- Module Name: /home/jagron/ise_projects/cond_var/proj/condvar_tb.vhd
-- Project Name: proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: condvar
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
ENTITY condvar_tb IS
END condvar_tb;
ARCHITECTURE behavior OF condvar_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT condvar
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
cmd : IN std_logic;
opcode : IN std_logic_vector(0 to 1);
cvar : IN std_logic_vector(0 to 7);
tid : IN std_logic_vector(0 to 7);
ack : OUT std_logic;
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Clock period definitions
constant clock_sig_period : time := 10 ns;
constant C_ENQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(0, 2); -- Opcode for "wait" enqueue
constant C_DEQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant C_DEQALL : std_logic_vector(0 to 2-1) := conv_std_logic_vector(2, 2); -- Opcode for "broadcast" dequeue
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure operation(aopcode : in std_logic_vector(0 to 1); acvar: in integer; atid : in integer) is
begin
-- Send a packet
wait until clock_sig = '0' and ack = '0';
cvar <= conv_std_logic_vector(acvar,8);
tid <= conv_std_logic_vector(atid,8);
cmd <= '1';
opcode <= aopcode;
wait until ack = '1';
cvar <= conv_std_logic_vector(0, 8);
tid <= conv_std_logic_vector(0, 8);
cmd <= '0';
opcode <= "00";
wait until clock_sig = '0';
wait for 4*clock_sig_period;
end procedure operation;
begin
wait for clock_sig_period*10;
-- Reset the core
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for clock_sig_period;
-- Delay
wait for clock_sig_period*2048;
-- ENQ
operation(C_ENQ,0,9);
-- ENQ
operation(C_ENQ,0,7);
-- ENQ
operation(C_ENQ,0,5);
-- ENQ
operation(C_ENQ,0,3);
-- ENQ
operation(C_ENQ,1,10);
-- ENQ
operation(C_ENQ,1,8);
-- ENQ
operation(C_ENQ,1,6);
-- ENQ
operation(C_ENQ,1,4);
-- DEQ
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
-- DEQ-ALL
operation(C_DEQALL,1,0);
-- DEQ-ALL
operation(C_DEQALL,0,0);
wait;
end process;
END;
| bsd-3-clause | 228336d718cd14e63ef9be54e45298d2 | 0.580322 | 3.378898 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_idea.vhd | 2 | 22,187 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
READ_ARGS_4,
READ_ARGS_5,
WHILE_1,
WHILE_2,
WHILE_3,
DO_1,
DO_2,
DO_3,
DO_4,
DO_5,
DO_6,
DONE_1,
DONE_2,
DONE_3,
DONE_4,
MUL_A1,
MUL_A2,
MUL_A3,
MUL_B1,
MUL_B2,
MUL_B3,
MUL_C1,
MUL_C2,
MUL_C3,
MUL_D1,
MUL_D2,
MUL_D3,
MUL_E1,
MUL_E2,
MUL_E3,
MUL_F1,
MUL_F2,
MUL_F3,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant Z16 : std_logic_vector(0 to 15) := (others => '0');
constant ROUNDS: std_logic_vector(0 to 15) := x"0008";
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal inPtr, inPtr_next : std_logic_vector(0 to 31);
signal outPtr, outPtr_next : std_logic_vector(0 to 31);
signal zPtr, zPtr_next : std_logic_vector(0 to 31);
signal origZPtr, origZPtr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
signal t32, t32_next : std_logic_vector(0 to 31);
signal x1, x1_next : std_logic_vector(0 to 15);
signal x2, x2_next : std_logic_vector(0 to 15);
signal x3, x3_next : std_logic_vector(0 to 15);
signal x4, x4_next : std_logic_vector(0 to 15);
signal t1, t1_next : std_logic_vector(0 to 15);
signal t2, t2_next : std_logic_vector(0 to 15);
signal r, r_next : std_logic_vector(0 to 15);
signal a, a_next : std_logic_vector(0 to 15);
signal b, b_next : std_logic_vector(0 to 15);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
inPtr <= inPtr_next;
outPtr <= outPtr_next;
zPtr <= zPtr_next;
origZPtr <= origZPtr_next;
count <= count_next;
t32 <= t32_next;
x1 <= x1_next;
x2 <= x2_next;
x3 <= x3_next;
x4 <= x4_next;
t1 <= t1_next;
t2 <= t2_next;
r <= r_next;
a <= a_next;
b <= b_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
inPtr_next <= inPtr;
outPtr_next <= outPtr;
zPtr_next <= zPtr;
origZPtr_next <= origZPtr;
count_next <= count;
t32_next <= t32;
x1_next <= x1;
x2_next <= x2;
x3_next <= x3;
x4_next <= x4;
t1_next <= t1;
t2_next <= t2;
r_next <= r;
a_next <= a;
b_next <= b;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
inPtr_next <= Z32;
outPtr_next <= Z32;
zPtr_next <= Z32;
origZPtr_next <= Z32;
count_next <= count;
t32_next <= Z32;
x1_next <= Z16;
x2_next <= Z16;
x3_next <= Z16;
x4_next <= Z16;
t1_next <= Z16;
t2_next <= Z16;
r_next <= Z16;
a_next <= Z16;
b_next <= Z16;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Read the inPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
when READ_ARGS_2 =>
inPtr_next <= toUser_value;
-- Read the outPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
when READ_ARGS_3 =>
outPtr_next <= toUser_value;
-- Read count
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
return_state_next <= READ_ARGS_4;
next_state <= WAIT_STATE;
when READ_ARGS_4 =>
count_next <= toUser_value;
-- Read address of z
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
return_state_next <= READ_ARGS_5;
next_state <= WAIT_STATE;
when READ_ARGS_5 =>
origZPtr_next <= toUser_value;
next_state <= WHILE_1;
-- while ( count > 0 ) {
-- Z = origZ;
-- r = ROUNDS;
-- count--;
-- x1 = *inPtr++;
-- x2 = *inPtr++;
when WHILE_1 =>
case count is
when x"00000000" =>
next_state <= EXIT_THREAD;
when others =>
count_next <= count - x"00000001";
r_next <= ROUNDS;
zPtr_next <= origZPtr;
-- Read first 32 bits of inPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inPtr;
-- increment inPtr
inPtr_next <= inPtr + x"00000004";
return_state_next <= WHILE_2;
next_state <= WAIT_STATE;
end case;
-- x3 = *inPtr++;
-- x4 = *inPtr;
when WHILE_2 =>
x1_next <= toUser_value(0 to 15);
x2_next <= toUser_value(16 to 31);
-- Read second 32 bits of inPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inPtr;
-- increment inPtr
inPtr_next <= inPtr + x"00000004";
return_state_next <= WHILE_3;
next_state <= WAIT_STATE;
when WHILE_3 =>
x3_next <= toUser_value(0 to 15);
x4_next <= toUser_value(16 to 31);
next_state <= DO_1;
when DO_1 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_A1;
next_state <= WAIT_STATE;
-- MUL(x1, *Z++)
-- x2 += *Z++
when MUL_A1 =>
a_next <= x1;
b_next <= toUser_value(0 to 15);
x2_next <= x2 + toUser_value(16 to 31);
next_state <= MUL_A2;
when MUL_A2 =>
case a is
when x"0000" =>
x1_next <= x"0001" - b;
next_state <= DO_2;
when others =>
case b is
when x"0000" =>
x1_next <= x"0001" - a;
next_state <= DO_2;
when others =>
t32_next <= a * b;
next_state <= MUL_A3;
end case;
end case;
when MUL_A3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_2;
else
x1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_2;
end if;
-- x3 += *Z++
-- MUL(x4, *Z++ );
when DO_2 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_B1;
next_state <= WAIT_STATE;
when MUL_B1 =>
x3_next <= x3 + toUser_value(0 to 15);
a_next <= x4;
b_next <= toUser_value(16 to 31);
next_state <= MUL_B2;
when MUL_B2 =>
case a is
when x"0000" =>
x4_next <= x"0001" - b;
next_state <= DO_3;
when others =>
case b is
when x"0000" =>
x4_next <= x"0001" - a;
next_state <= DO_3;
when others =>
t32_next <= a * b;
next_state <= MUL_B3;
end case;
end case;
when MUL_B3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x4_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_3;
else
x4_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_3;
end if;
-- t2 = x1^x3;
-- MUL( t2, *Z++ );
-- t1 = t2 + ( x2^x4 );
-- MUL( t1, *Z++ );
when DO_3 =>
t2_next <= x1 xor x3;
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_C1;
next_state <= WAIT_STATE;
when MUL_C1 =>
a_next <= t2;
b_next <= toUser_value(0 to 15);
next_state <= MUL_C2;
when MUL_C2 =>
case a is
when x"0000" =>
t2_next <= x"0001" - b;
next_state <= MUL_D1;
when others =>
case b is
when x"0000" =>
t2_next <= x"0001" - a;
next_state <= MUL_D1;
when others =>
t32_next <= a * b;
next_state <= MUL_C3;
end case;
end case;
when MUL_C3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
t2_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= MUL_D1;
else
t2_next <= t32(16 to 31) - t32(0 to 15);
next_state <= MUL_D1;
end if;
when MUL_D1 =>
a_next <= t2 + (x2 xor x4);
b_next <= toUser_value(16 to 31);
next_state <= MUL_D2;
when MUL_D2 =>
case a is
when x"0000" =>
t1_next <= x"0001" - b;
next_state <= DO_4;
when others =>
case b is
when x"0000" =>
t1_next <= x"0001" - a;
next_state <= DO_4;
when others =>
t32_next <= a * b;
next_state <= MUL_D3;
end case;
end case;
when MUL_D3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
t1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DO_4;
else
t1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DO_4;
end if;
-- t2 = t1+t2;
-- x1 ^= t1;
when DO_4 =>
t2_next <= t1 + t2;
x1_next <= x1 xor t1;
next_state <= DO_5;
-- x4 ^= t2;
-- t2 ^= x2;
when DO_5 =>
x4_next <= x4 xor t2;
t2_next <= t2 xor x2;
next_state <= DO_6;
-- x2 = x3^t1;
-- x3 = t2;
-- while (--r);
when DO_6 =>
x2_next <= x3 xor t1;
x3_next <= t2;
case r is
when x"0001" =>
next_state <= DONE_1;
when others =>
r_next <= r - x"0001";
next_state <= DO_1;
end case;
-- MUL(x1, *Z++);
-- out++ = x1;
-- out++ = x3 + *Z++;
when DONE_1 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
-- Increment zPtr
zPtr_next <= zPtr + x"00000004";
return_state_next <= MUL_E1;
next_state <= WAIT_STATE;
when MUL_E1 =>
a_next <= x1;
b_next <= toUser_value(0 to 15);
next_state <= MUL_E2;
when MUL_E2 =>
case a is
when x"0000" =>
x1_next <= x"0001" - b;
next_state <= DONE_2;
when others =>
case b is
when x"0000" =>
x1_next <= x"0001" - a;
next_state <= DONE_2;
when others =>
t32_next <= a * b;
next_state <= MUL_E3;
end case;
end case;
when MUL_E3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x1_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DONE_2;
else
x1_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DONE_2;
end if;
when DONE_2 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= outPtr;
thrd2intrfc_value <= x1 & (x3 + toUser_value(16 to 31));
outPtr_next <= outPtr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= DONE_3;
-- *out++ = x2 + *Z++;
-- MUL(x4, *Z);
-- *out = x4;
when DONE_3 =>
-- Read the value of zPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= zPtr;
return_state_next <= MUL_F1;
next_state <= WAIT_STATE;
when MUL_F1 =>
a_next <= x4;
b_next <= toUser_value(16 to 31);
next_state <= MUL_F2;
when MUL_F2 =>
case a is
when x"0000" =>
x4_next <= x"0001" - b;
next_state <= DONE_4;
when others =>
case b is
when x"0000" =>
x4_next <= x"0001" - a;
next_state <= DONE_4;
when others =>
t32_next <= a * b;
next_state <= MUL_F3;
end case;
end case;
when MUL_F3 =>
if ( t32(16 to 31) < t32(0 to 15 ) ) then
x4_next <= t32(16 to 31) - t32(0 to 15) + x"0001";
next_state <= DONE_4;
else
x4_next <= t32(16 to 31) - t32(0 to 15);
next_state <= DONE_4;
end if;
when DONE_4 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= outPtr;
thrd2intrfc_value <= (x2 + toUser_value(0 to 15)) & x4;
outPtr_next <= outPtr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= WHILE_1;
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ec3f2a81a59f0c34d005df5ea144d3fb | 0.530987 | 3.315947 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_dpram_select.vhd | 3 | 115,123 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1 2003/03/15 01:05:27 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:27 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| bsd-3-clause | 59514058a2172723e847200bc68285db | 0.368719 | 4.777086 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_adder_bit.vhd | 2 | 11,648 | -------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder_bit.vhd
--
-- Description: Implements 1 bit of the pf_adder
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2001-09-25
-- - Added generic to allow selection of a registered output
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - CHanged the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed call out proc_common to v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v3_00_a;
Use proc_common_v3_00_a.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean := true
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic; -- A operand
Bin : in std_logic; -- B operand
Add_sub_n : in std_logic; -- Function ('1' = add, '0' = A - B)
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_adder_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal lutout_AddSub : std_logic;
signal addsub_result : std_logic;
signal addsub_result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"0069"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lutout_AddSub,
--- xst wrk around I0 => Bin,
--- xst wrk around I1 => Ain,
--- xst wrk around I2 => Add_sub_n,
--- xst wrk around I3 => '0');
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"0069"
)
port map (
O => lutout_AddSub,
I0 => Bin,
I1 => Ain,
I2 => Add_sub_n,
I3 => '0');
MUXCY_I : MUXCY
port map (
DI => Ain,
CI => Carry_In,
S => lutout_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => lutout_AddSub,
CI => Carry_In,
O => addsub_result);
FDRE_I: FDRE
port map (
Q => addsub_result_Reg,
C => Clk,
CE => Clock_Enable,
D => addsub_result,
R => Rst
);
USE_REGISTERED_RESULT : if (C_REGISTERED_RESULT = true) generate
Result <= addsub_result_Reg; -- registered version
end generate USE_REGISTERED_RESULT;
USE_COMBINATIONAL_RESULT : if (C_REGISTERED_RESULT = false) generate
Result <= addsub_result; -- combinational version
end generate USE_COMBINATIONAL_RESULT;
end implementation;
| bsd-3-clause | f04dcd2f939f23d4177f2f7a3464fce8 | 0.412689 | 4.941875 | false | false | false | false |
iocoder/graduation | hardware/cpu/tlb.vhd | 1 | 5,028 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.cpu_pkg.all;
entity tlb is
Port (
CLK : in STD_LOGIC;
-- CPU interface
cpu_iMEME : in STD_LOGIC;
cpu_iRW : in STD_LOGIC;
cpu_iADDR : in STD_LOGIC_VECTOR (19 downto 0);
cpu_dMEME : in STD_LOGIC;
cpu_dRW : in STD_LOGIC;
cpu_dADDR : in STD_LOGIC_VECTOR (19 downto 0);
-- Cache interface:
cache_iMEME : out STD_LOGIC;
cache_iADDR : out STD_LOGIC_VECTOR (19 downto 0);
cache_iCacheable : out STD_LOGIC;
cache_dMEME : out STD_LOGIC;
cache_dADDR : out STD_LOGIC_VECTOR (19 downto 0);
cache_dCacheable : out STD_LOGIC
);
end entity;
architecture Behavioral of tlb is
constant TLB_SIZE : integer := 64;
type frame_t is array (0 to TLB_SIZE-1) of std_logic_vector(19 downto 0);
type page_t is array (0 to TLB_SIZE-1) of std_logic_vector(19 downto 0);
type v_t is array (0 to TLB_SIZE-1) of std_logic;
signal tlb_frame : frame_t;
signal tlb_page : page_t;
signal tlb_v : v_t := (others => '0');
begin
cache_iMEME <= cpu_iMEME;
cache_dMEME <= cpu_dMEME;
cache_iADDR <= "000"&cpu_iADDR(16 downto 0) when
cpu_iADDR(19 downto 17)="100" or
cpu_iADDR(19 downto 17)="101" else
cpu_iADDR;
cache_dADDR <= "000"&cpu_dADDR(16 downto 0) when
cpu_dADDR(19 downto 17)="100" or
cpu_dADDR(19 downto 17)="101" else
cpu_dADDR;
-- process(cpu_iMEME, cpu_iRW, cpu_iADDR, cpu_dMEME, cpu_dRW, cpu_dADDR)
--
-- variable paddr : STD_LOGIC_VECTOR (19 downto 0);
-- variable miss : STD_LOGIC;
-- variable valid : STD_LOGIC;
-- variable dirty : STD_LOGIC;
-- variable cacheable : STD_LOGIC;
-- variable pass_instr : boolean := false;
--
-- procedure translate(vaddr : in STD_LOGIC_VECTOR (19 downto 0);
-- paddr : out STD_LOGIC_VECTOR (19 downto 0);
-- miss : out STD_LOGIC;
-- valid : out STD_LOGIC;
-- dirty : out STD_LOGIC;
-- cacheable : out STD_LOGIC) is
-- variable found : boolean := false;
-- begin
-- if (vaddr(19 downto 17) = "100") then
-- -- kseg0 [0x80000000-0x9FFFFFFF]
-- paddr := "000" & vaddr(16 downto 0);
-- miss := '0';
-- valid := '1';
-- dirty := '1';
-- cacheable := '1';
-- elsif (vaddr(19 downto 17) = "101") then
-- -- kseg1 [0xA0000000-0xBFFFFFFF]
-- paddr := "000" & vaddr(16 downto 0);
-- miss := '0';
-- valid := '1';
-- dirty := '1';
-- cacheable := '0';
-- else
-- -- kuseg [0x00000000-0x7FFFFFFF]
-- -- kseg2 [0xC0000000-0xFFFFFFFF]
-- for i in 0 to TLB_SIZE-1 loop
-- if (tlb_page(i)=cpu_iADDR) then
-- found := true;
-- paddr := tlb_frame(i);
-- miss := '0';
-- valid := tlb_v(i);
-- dirty := '1';
-- cacheable := '1';
-- end if;
-- end loop;
--
-- if (found = false) then
-- paddr := x"00000";
-- miss := '1';
-- valid := '0';
-- dirty := '0';
-- cacheable := '0';
-- end if;
-- end if;
-- end translate;
--
-- begin
--
-- if ( CLK = '0' and CLK'event ) then
-- -----------------------
-- -- data memory cycle --
-- -----------------------
-- if (cpu_dMEME = '1') then
-- -- translate address
-- translate(cpu_dADDR, paddr, miss, valid, dirty, cacheable);
-- if (miss='1' or valid='0') then
-- -- data tlb miss
-- else
-- -- tlb hit
-- cache_dMEME <= '1';
-- cache_dADDR <= paddr;
-- end if;
-- else
-- cache_dMEME <= '0';
-- cache_dADDR <= x"00000";
-- end if;
-- ------------------------------
-- -- instruction memory cycle --
-- ------------------------------
-- if (cpu_iMEME = '1' and not pass_instr) then
-- -- translate address
-- translate(cpu_iADDR, paddr, miss, valid, dirty, cacheable);
-- if (miss='1' or valid='0') then
-- -- instruction tlb miss
-- else
-- -- tlb hit
-- cache_iMEME <= '1';
-- cache_iADDR <= paddr;
-- end if;
-- else
-- cache_iMEME <= '0';
-- cache_iADDR <= x"00000";
-- end if;
-- end if;
--
-- end process;
end Behavioral;
| gpl-3.0 | 94bd5795248f3d0f98bdd776ca38a43a | 0.447295 | 3.568488 | false | false | false | false |
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